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TABLE OF CONTENT

INTRODUCTION ............................................................................................................................................. 3
RESEARCH IDEAS AND CONCEPTS:................................................................................................................ 4
THEORY ......................................................................................................................................................... 7
VHDL: ........................................................................................................................................................ 7
Latch and Flip-Flops: ................................................................................................................................. 8
Flip-Flops ................................................................................................................................................. 10
Data Flip-Flops ........................................................................................................................................ 11
K-Map ...................................................................................................................................................... 12
STATE TRANSITION DIAGRAM OF SEQUENCE DETECTOR 1111 ................................................................ 14
VHDL Program and simulation: ................................................................................................................... 17
PROGRAM FOR RTL: ................................................................................................................................ 17
TEST BENCH CODE FOR SEQUENCES DETECTOR:.................................................................................... 19
SIMULATION RESULT: ............................................................................................................................. 21
CONCLUSIONS: ............................................................................................................................................ 27
References .................................................................................................................................................. 29

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Table of Figure

Figure 1 Implementation of sequential detector.......................................................................................... 6


Figure 2 Structure diagram ........................................................................................................................... 8
Figure 3Circuit Symbol for SR latch ............................................................................................................... 9
Figure 4 SR circuit made up of two NOR gates ............................................................................................. 9
Figure 6 The SR circuit made up of two NAND gates .................................................................................. 10
Figure 7: Logical circuit for S-R flip-flops..................................................................................................... 11
Figure 8: Logical circuit for data flip-flops................................................................................................... 12
Figure 9: A k-map representation for three inputs ..................................................................................... 13
Figure 10: State diagram of sequence 1111 ................................................................................................ 14
Figure 11: Step 1 of State diagram of 1111 ................................................................................................ 14
Figure 12: Step 2 of state diagram .............................................................................................................. 14
Figure 13: Step 3 of state diagram .............................................................................................................. 15
Figure 14: Last step of state diagram .......................................................................................................... 15
Figure 15: circuit diagram as per K- map of sequence 1111 ....................................................................... 17
Figure 16 simulation window ...................................................................................................................... 21
Figure 17 simulation window ...................................................................................................................... 22
Figure 18 Simulation window ..................................................................................................................... 22
Figure 19 Simulation window ..................................................................................................................... 23
Figure 20 Simulation window ..................................................................................................................... 23
Figure 21 Simulation window ..................................................................................................................... 24
Figure 22 Simulation window ..................................................................................................................... 24
Figure 23 Simulation window ..................................................................................................................... 25
Figure 24 Simulation window ..................................................................................................................... 25
Figure 25 Simulation window ..................................................................................................................... 26
Figure 26 Simulation window ..................................................................................................................... 26
Figure 27: Entity .......................................................................................................................................... 27
Figure 28: Architecture ............................................................................................................................... 27

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INTRODUCTION
Digital systems are a subdivision of electronics engineering where the systems work on only two
voltage level. This two voltage level is represented in binary numbers 1 and 0 and is recognized
as high or low according to the voltage. A digital circuit is one that is made with devices with two
well-defined conditions. Such circuits can operation information denoted in binary form. Systems
built on digital circuits touch all features our present-day lives. The present-day home products
together with electronic games and appliances, communication and office automation goods,
computers with an extensive series of capabilities, and industrial instrumentation and control
systems, electromedical equipment, and defence and aerospace systems are severely reliant on
digital circuits. Many fields that developed later to digital electronics have peaked and smoothed
off, but the application of digital ideas appears to be still rising exponentially. This extraordinary
growth is powered by the semiconductor technology, which allows the introduction of more and
composite integrated circuits. The complexity of an integrated circuit is restrained in terms of the
number of transistors that can be combined into a single unit. The number of transistors in a single
integrated circuit has been doubling each eighteen month (Moore Law) for numerous decades and
touched the number of nearly one billion transistors per chip. This allowed the circuit engineers to
deliver more and more complex functions in a single unit.

In this assignment, the focus is to design a sequence detector in VHDL. A sequence detector is a
determinate state machine and a finite state machine is a machine which has got fixed number of
states which each state can be triggered by some kind of action. Sequential circuits work on a clock
cycle which may be synchronous or asynchronous. Sequential circuits use current inputs and
previous inputs by saving the information and putting back into the circuit on the next clock cycle.

Combinational Logic Circuits are completed up from basic logic NAND, NOR or NOT gates
that are combined or linked together to yield more complex switching circuits. These logic gates
are the building blocks of combinational logic circuits. An example of a combinational circuit is a
decoder, which changes the binary code data present at its input into a number of diverse output
lines, one at a time making an equivalent decimal code at its output.

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Mooreys law states that processor speeds, or complete processing power for computers will
double every two years. A rapid check between specialists in dissimilar computer companies
shows that the term is not very popular but the rule is still accepted. Now a chip consists of
hundreds of million gates and we can have a wireless-PDA-MP3-player camera-GPS-cell-phone
gadget very soon. Transistor geometry Chips double its density (number of transistor) in every
18 months Devices become smaller, faster and cheaper

VHDL is acronym for VHSIC Hardware Description Language and VHSIC is acronym for Very
High Speed Integrated Circuit. VHDL is used to program electronic automatons like field
programmable gate array, parallel program executors, etc.

The learning outcomes of this assignment are:

The student can learn implement sequence detectors in VHDL.


The student can implement designs in VHDL
The student can explain what FSM is.
The student can explain what sequence detectors are.
The student can explain the basics of digital systems

This project deals with the theoretical and research details about sequence detectors, state
transition diagram of sequence detectors and VHDL code for sequence detectors.

RESEARCH IDEAS AND CONCEPTS:


A sequence detector is a determinate state machine and a finite state machine is a machine which
has got fixed number of states which each state can be triggered by some kind of action. Sequential
circuits work on a clock cycle which may be synchronous or asynchronous.

Few examples of sequence detectors applications in the real world are:

T.V remote where every command from remote is digital sequence transmitted through IR
transmitter. The sequence is noticed by sequence detector and channels are tuned
consequently.
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Remote garage openers where the remote sends a sequence of pulse to the control unit of
garage
Communication pairing between two communication modules, each communication
module starts with a sequence and conveys data. The sequence detector detects the opening
pairing sequence and continues communication between the modules. By this method
communication modules stay connected even if the noise is too high.

There are various technologies which are used to design several sequence detectors few of them
are complex to implement and some are easy. The technologies used to implement sequence
detectors are tabulated in table below;

CODING
TECHNOLOGY EASE OF COST OF
REQUIRED OR
USED IMPLEMENTATION IMPLEMENTATION
NOT
Difficult and long
Basic gates used No Low
procedure
Complex
VHDL Code
Programmable Logic Easy and short procedure Very High
required
Device
Programmable Logic VHDL Code
Easy and short procedure High
Array required
Field Programmable VHDL Code
Easy and short procedure Medium
Gate Array required
Table 1: Comparison of various technologies used to implement sequence detector

From the above table, it is detected that the best choice is FPGA since the cost is relatively medium
and difficulty to implement the circuit is really low. There are various researches undergoing on
the topic of sequence detectors just as;

In the theory, Design and Implementation of Sequence Detection Algorithms for


Dynamic Spectrum Access Networks by Zhanwei Sun, describes how sequence detector
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can be utilized as security appliances for defending people using from spectrum of
perceptive radio system. Every consumer transmits their own sequence and the sequence
detector notices this sequence and further assigns the spectrum to the user.
A Verilog Model of Universal Scalable Binary Sequence Detector by P.V Sansaka, Y.V
Ramana Rao and A.L Siridhara, advertised using FGPA and Verilog for designing the
sequence detector, in this research paper it has been suggested that Verilog is better than
VHDL. The paper also suggests ways to use DSP processor for sequence detector.
Deterministic Algorithm for Alpha-Numeric Sequence Comparison with Application to
Protein Sequence Detection by N Brahmi, says behaviors to perceive pattern in DNA.
Firstly, DNA are distorted into binary data and is verified to an earlier set sequence using
sequence detector.

From the above research papers, it is observed that sequence detector has touched in its maturity
and is used for progressive applications. Above research papers are the few of the currently
undergoing researches about sequence detectors. It is being noticed that sequence detectors are
widely used for security measures and for pairing of communication devices from the research
paper.

A sequence detector is a single input sequential circuit which accepts a stream of bits and generate
an output I whenever a specified sequence is detected. There are two basic types of sequence
detectors, overlap sequence (electors and no overlap sequence detectors. In overlap sequence
detectors, the final bits of one sequence can be the starting of another sequence.

Figure 1 Implementation of sequential detector

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A state machine is a system that can be used to describe the system in terms of set of states that
the system goes through. In this type of system, memory capability of system is a must. Also, the
state machine must have a set of inputs and outputs.

THEORY
The basic objective of the assignment is to design a sequence detector using VHDL. A sequence
detector is a single input sequential circuit which accepts a stream of bits and generate an output I
whenever a specified sequence is detected. It involves some basic concepts like, of flip-flops, state
transition diagram, K-map and VHDL are explained further.

VHDL:
VHDL is acronym for VHSIC Hardware Descriptive Language and VHSIC stands for Very
High Speed Integrated Circuit is a programming language developed by US air force to program
automatons or finite state machines. Well VHDL is a hardware description language used to
escribe digital and mixed signals and also used for programming programmings. It is a
programming language used to model a digital system by dataflow, behavioral and structural style
of modeling. VHDL allows models to be developed at a very high level of abstraction. Initially
VHDL was developed by US department in order to document behavior of the ASICs. This
hardware description is used to configure a programmable logic device (PLD), such as a field
programmable gate array (FPGA), with a custom logic design. The general format of a VHDL
program is built around the concept of BLOCKS which are the basic building units of a VHDL
design. Within these design blocks a logic circuit of function can be easily described.

In VHDL an entity is used to describe a hardware module. An entity can be described using,

Entity declaration

Architecture

Configuration

Package declaration

Package body
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ENTITY
PACKAGE
(INTERFACE DISCRIPTION)
DECLARATION
ARCHITECTURE
PACKAGE
BODY (FUNCTIONALITY)

CONFIGURATION

CONNECTION ENTITY<-
>ARCHTITECTURE

Figure 2 Structure diagram


VHDL allows you to specify:

The components of a circuit.


Their interconnection.
The behavior of the components in terms of their input and output signals.

Latch and Flip-Flops:


Latch
A latch is an example of a bistable multivibrator, that is, a device with exactly two stable states.
These states are high-output and low-output. It holds a single bit and is known as the simplest
memory circuit unit. This latch is called SR-latch, which stands for set and reset. Latch circuits
can be either active-high or active-low. The difference is determined by whether the operation of
the latch circuit is triggered by HIGH or LOW signals on the inputs. The SR-latch works
independently of control signals and relies only on the state of the S and R inputs. SR latch can be
created by two NOR or even can be made by two NAND gates, referred as SR.

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The circuit symbol for SR latch:

Figure 3Circuit Symbol for SR latch

The SR circuit made up of two NOR gates:

Figure 4 SR circuit made up of two NOR gates

The truth table for the desired circuit:

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The SR circuit made up of two NAND gates:

Figure 5 The SR circuit made up of two NAND gates

The truth table for the desired circuit:

Flip-Flops
A flip-flop is a synchronous version of the latch. To complicate the situation even more, there are
several fundamental types of flip-flops. These are simple memory holding digital circuits with can
hold one bit of memory in each flip-flop. Flip-flops can be divided into common types:
the SR ("set-reset"), D ("data" or "delay"), T ("toggle"), and JK. A flip-flop, on the other hand,
is edge-triggered and only changes state when a control signal goes from high to low or low to

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high.Flip-Flops contain three inputs and two outputs, three input pins are SET, RESET and
CLOCK and two outputs are data and inverted data

Figure 6: Logical circuit for S-R flip-flops

The above figure illustrates logical circuit for S-R flip-flops which are the basic flip-flops
available, the circuit of clocked SR flip flop using NOR gates is shown above. The S represents

SET pin, CK represents CLOCK pin, R represents RESET pin, Q represent data pin and Q
represent inverted data pin.

CLOCK EDGE S R Q Q
0 0 Previous Data Previous Data
1 0 1 0
0 1 0 1
1 1 Invalid Condition Invalid Condition
Table 2: Truth table for S-R flip-flops

Data Flip-Flops
The D Flip Flop is by far the most important of the clocked flip-flops as it ensures that ensures
that inputs S and R are never equal to one at the same time. The D-type flip flop are constructed
from a gated SR flip-flop with an inverter added between the S and the R inputs to allow for a
single D (data) input.

Then this single data input, labelled D, is used in place of the set signal, and the inverter is used
to generate the complementary reset input thereby making a level-sensitive D-type flip-flop from
a level-sensitive RS-latch as now S = D and R = not D as shown.

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Figure 7: Logical circuit for data flip-flops

The above figure showcases logical circuit for D flip-flops showing D pin which is the data pin
and Q and Q which are data holding pin and inverted data holding pin.

CLOCK EDGE D Q Q
0 0 1
1 1 0
Table 3: Truth table for data flip-flops

The above table shows truth table for D flip-flops, it is clear that the output is exactly same as the
input bit.

K-Map
Karnaugh map is a graphical method to minimize Boolean algebra. K-map is a truth table
expressed in another way in which certain particular operations are done such that the Boolean
expression can be reduced to implement the circuit. There are two type of K-map expression sum
of products commonly known as sop and product of sums which is commonly known as pos. In
sum of product form 1s are considered for expression and on product of sum form 0s are considered
for expression.

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Figure 8: A k-map representation for three inputs

According to the above figure, the expression for k-map according to sum of product form is

Output = BC + AC + AB

The expression for output according k-map in product of sum form is;

Output = (B+C) (A+B)

Synchronous sequential system

Behaviour depends on the inputs and outputs at discrete instants of time.


Flip-flops, registers, and latches that are enabled/controlled with a signal derived from
clock form a synchronous sequential system.
Asynchronous sequential system.

Behaviour depends on inputs at any instant of time.


Latches without control signals behave in an asynchronous manner.
The state machines discussed in this chapter will be synchronous sequential systems
This allows us to form timed Boolean functions.

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STATE TRANSITION DIAGRAM OF SEQUENCE DETECTOR 1111


In this assignment, the sequence detector has to detect the sequence of 1111. So, for detecting this
sequence there is a requirement of 4 states

Figure 9: State diagram of sequence 1111


This state diagram is drawn by going the various steps which is described below by following the
all 4 steps:

Step 1: State a.

Figure 10: Step 1 of State diagram of 1111

Step 2: State b.

Figure 11: Step 2 of state diagram

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Step 3: State c.

Figure 12: Step 3 of state diagram

Step 4: State d.

Figure 13: Last step of state diagram


Now the next step is to draw the state transition table:
So, firstly assign the binary value to each state and the value of each is mentioned below:
a = 00, b = 01, c = 10, d = 11
The state table is shown below in table 4
Table 4: State Transition Table
Present state Input Next state output FF inputs

A B X An+1 Bn+1 Y DA DB

a 0 0 0 0 0 0 0 0

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a 0 0 1 0 1 0 0 1

b 0 1 0 0 0 0 0 0

b 0 1 1 1 0 0 1 0

c 1 0 0 0 0 0 0 0

c 1 0 1 1 1 0 1 1

d 1 1 0 0 0 1 0 0

d 1 1 1 1 1 1 1 1

Now the next step is to draw the k- map and write the Boolean expression for sequence obtained
in DA, DB and output (Y).

K- Map for DA

Logic Expression => DA = BX + AX


= (A + B) X
K- Map for DB

Logic Expression => DB = AX + BX


= (A + B) X

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K- Map for Y

Logic Expression => Y= AB

So, last step is to draw the circuit diagram of the sequence 1111 as per result observed with the
help of k map. Circuit diagram is shown below:

Figure 14: circuit diagram as per K- map of sequence 1111

VHDL Program and simulation:


The VHDL code for implementing the sequence detector of sequence 1111

PROGRAM FOR RTL:


library IEEE;
use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity sequence_detector is
port (
clk: in STD_LOGIC;
rst: in STD_LOGIC;
x: in STD_LOGIC;
z: out STD_LOGIC);
end sequence_detector;
architecture sequence_detector_arch of sequence_detector is % define the architecture
type seq_detect_type is (
S1, S2, S3, S4
);
signal seq_detect: seq_detect_type;
begin
seq_detect_machine: process (clk)
begin
if clk'event and clk = '1' then
if rst='1' then
seq_detect <= S1;
else
case seq_detect is
when S1 =>
if x = '1' then
seq_detect <= S2;
elsif x = '0' then
seq_detect <= S1;
end if;
when S2 =>
if x = '1' then
seq_detect <= S3;
elsif x = '0' then
seq_detect <= S1;
end if;
when S3 =>
if x = '1' then
seq_detect <= S4;
elsif x = '0' then
seq_detect <= S1;
end if;
when S4 =>
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if x = '1' then
seq_detect <= S4;
elsif x = '0' then
seq_detect <= S1;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
z_assignment:
z <= '0' when (seq_detect = S1 and x = '1') else
'0' when (seq_detect = S1 and (x = '0' and not (x = '1'))) else
'0' when (seq_detect = S2 and x = '1') else
'0' when (seq_detect = S2 and (x = '0' and not (x = '1'))) else
'0' when (seq_detect = S3 and x = '1') else
'0' when (seq_detect = S3 and (x = '0' and not (x = '1'))) else
'1' when (seq_detect = S4 and x = '1') else
'0' when (seq_detect = S4 and (x = '0' and not (x = '1'))) else
'0';
end sequence_detector_arch;

TEST BENCH CODE FOR SEQUENCES DETECTOR:


library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sequence_detector_tb is
end sequence_detector_tb;
architecture TB_ARCHITECTURE of sequence_detector_tb is
component sequence_detector
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
x : in STD_LOGIC;
z : out STD_LOGIC );
end component;
signal clk : STD_LOGIC;
signal rst : STD_LOGIC;
signal x : STD_LOGIC;
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signal z : STD_LOGIC;
begin
UUT : sequence_detector
port map (
clk => clk,
rst => rst,
x => x,
z => z
);
clk_process : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
sti_process: process
begin
x <= '1';
wait for 10 ns;
x <= '0';
wait for 10 ns;
x <= '1';
wait for 10 ns
x <= '0';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '0';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '0';
wait for 10 ns;
x <= '1';
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wait for 10 ns;


x <= '0';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '0';
wait for 10 ns
end process; % end the task
end TB_ARCHITECTURE; %end of the architecture
configuration TESTBENCH_FOR_sequence_detector of sequence_detector_tb is
for TB_ARCHITECTURE
for UUT : sequence_detector
use entity work.sequence_detector(sequence_detector_arch);
end for;
end for;
end TESTBENCH_FOR_sequence_detector; % end of the testbench

SIMULATION RESULT:

Figure 15 simulation window

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Figure 16 simulation window

Figure 17 Simulation window

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Figure 18 Simulation window

Figure 19 Simulation window

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Figure 20 Simulation window

Figure 21 Simulation window

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Figure 22 Simulation window

Figure 23 Simulation window

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Figure 24 Simulation window

Figure 25 Simulation window

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RESULT: -

Figure 26: Entity

Figure 27: Architecture

CONCLUSIONS:
The sequence detector for detecting the sequence 1111 is designed and implemented using
VHDL in Xilinx software. The procedure to implement a sequence detector is described in detail
with step by step. There are several procedures to implement sequence detectors are state transition
diagram, truth table, excitation table, k-map, etc. which all are solved with an example in the theory
part. In research ideas and concepts sub-topic various latest researches on sequence detector is
reviewed and real life of applications of sequence detector are mentioned. With the help of VHDL
programming sequence detector is implemented using behavioral modelling. The above figure and

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simulated figure are exactly same so the result has got zero error. After completing this assignment
number of concepts and implementation techniques are achieved.

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References
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Agarwal, T. (2017). Know about the Difference Between Latches and Flip Flops.
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Apr. 2017].
Basic Electronics Tutorials. (2017). Sequential Logic Circuits and the SR Flip-flop.
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Brighthub Engineering. (2017). Types of flip-flop circuits explained - RS, JK, D & T.
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Daenotes.com. (2017). Flip Flops, R-S, J-K, Clocked R-S, D, T, Master Slave. [online]
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types-applications-woking [Accessed 10 Apr. 2017].
Ee.surrey.ac.uk. (2017). Introduction to Sequential Circuits. [online] Available at:
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Electronicsteacher.com. (2017). Latches and flip-flops - Digital Circuits. [online]
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Engineering.com. (2017). What is latch in electronic circuits?. [online] Available at:
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Facstaff.bucknell.edu. (2017). Digital Logic - Flip-Flops. [online] Available at:
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[Accessed 10 Apr. 2017].
Renesas Electronics America. (2017). Tutorial: Digital Circuits-Sequential Logic,
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us/support/technical-resources/engineer-school/digital-circuits-03-sequential-
logic.html [Accessed 10 Apr. 2017].
WhatIs.com. (2017). What is flip flops (bistable gates)? - Definition from WhatIs.com.
[online] Available at: http://whatis.techtarget.com/definition/flip-flops-bistable-
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