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MANIPAL INSTITUE OF TECHNOLOGY

A Constituent Institute of Manipal University


MANIPAL- 576104, KARNATAKA, INDIA.

VLSI LAB MANUAL


For
Vth Semester B. Tech E&C ENGG.

SUBJECT CODE: ECE 311

DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING

Prepared by Approved by

Lab Coordinator Head of Department


Dept. of E&C Engg., MIT VLSI LAB

ECE 311 VLSI LAB [0-0-3-1]

Total number of Lab Sessions: 12

Course Objectives:
At the end of this course, the students will be able to:

CO1:Write VHDL codes for combinational and sequential circuits and simulate.

CO2: Analyze the coding in different modeling styles using VHDL.

CO3: Synthesize combinational and sequential circuits in Xilinx environment.

CO4: Implement digital circuits using the FPGA/CPLD.

CO5: Generate layouts for simple logic circuits using layout editor and analyze
to do post layout simulation.

CO6: Perform timing analysis with constraints and map it to the design.

CO7: Write test benches using VHDL codes for the given program.

CO8: Write VHDL code and implement circuits for some typical applications.

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Procedure for the evaluation of the Lab

Marks for internal evaluation: 60


Marks for end- sem exam: 40
Total marks: 100
Procedure for the evaluation of Internal marks:
Weekly Evaluation: 10 Marks
Marks Distribution:
Conduction and debugging of program: 4 Marks
Conduction of the unsolved exercises = 03 Marks
Observation book = 03 Marks

Procedure for the evaluation of External marks:

Marks for write-up- 12


Marks for execution- 12
Marks for Results- 8
Marks for Viva voice- 8

Total =40

Total marks for 10 experiments: 100 Marks


60% of the marks obtained is the internal marks

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Important Instructions to the Students

1. You should first study the solved problems and then try to solve
all the exercise problems of the experiment in the lab.

2. Maintaining an observation copy is compulsory, where in the


VHDL code of all the problems solved in the lab should be
properly noted down after the completion.

3. Show your results and observation copies to the concerned staff

3. You should maintain a folder of all the programs in the lab


computer and save it by your name/roll no. You are also advised
to keep a back-up of it.

4. Use of external storage media is not allowed.

5. Maintain the timings and discipline of the lab.

6. You will be evaluated in every lab you attend, based on your


performance, observation copy and behavior in the lab.

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References:

1. M.J.S.Smith, Application Specific ICs, Pearson 1997.

2. C.H.Roth, Digital System Design using VHDL, PWS,1998.

3. Ashenden Peter J, Designer's Guide to VHDL, Morgan Kaufmann


Publishers, 3rd Edition.

4. J.Bhaskar VHDL Primer, Prentice Hall India,3rd edition.

5. Anand Kumar, Fundamentals of Digital Circuits, Prentice Hall of India.

6. Morris M. Mano, Digital Design, Pearson Education.

7. Ronald J. Tocci, Digital Systems, Pearson Education.

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CONTENTS

Page No.
Sl. No. Title of the Experiment

01 INTRODUCTION TO MODELSIM 6

INTRODUCTION TO DATA FLOW AND BEHAVIORAL


02 11
MODELS

INTRODUCTION TO SEQUENTIAL, BEHAVIORAL AND


03 13
MIXED-MODE MODELS

INTRODUCTION TO BEHAVIORAL MODELING OF


04 17
SEQUENTIAL CIRCUITS

INTRODUCTION TO STRUCTURAL MODELING OF


05 21
LOGIC CIRCUITS

06 INTRODUCTION TO SUBPROGRAMS IN VHDL 26

07 INTRODUCTION TO XILINX ISE TOOL 29


SYNTHESIS AND EXECUTION OF LOGIC CIRCUITS IN
08 40
XILINX SPARTAN 3 CHIP USING VHDL

SYNTHESIS AND EXECUTION OF STAIRCASE, RAMP


09 AND TRAINGULAR WAVEFORMS IN SPARTAN 3 CHIP 43
USING VHDL

IMPLEMENTING STEPPER MOTOR CONTROL USING


10 46
XILINX SPARTAN 3 CHIP

INTRODUCTION TO MICROWIND SOFTWARE FOR


11 48
LAYOUT GENERATION

INTRODUCTION TO PIN LAYOUT OF XILINX SPARTAN


12 60
3 CHIP XC3S400-TQ144

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EXPERIMENT NO. 01
INTRODUCTION TO MODELSIM

I. Starting ModelSim
1. Start ModelSim

Start Programs ModelSim ModelSim


2. After starting ModelSim, you should see the Welcome to ModelSim 10 dialog. If the
dialog does not show up, you can display by selecting Help Welcome Menu from the
Main window.

3. The first thing to do is to create a project. Projects ease the interaction with ModelSim and
are
useful for organizing files and simulation settings.

4. Create a new project by clicking on Jumpstart on the Welcome to ModelSim


dialog, and then on Create a Project. You can also create a new project without the help of
the dialog window by selecting: File New Project from the Main window.

5. A Create Project window pops up (See Figure 1). Select a suitable name for your project;
set the Project Location to D:/Name_reg_no, and leave the Default Library Name to work.
Hit Ok.

Figure 1. Create Project dialog.

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6. After hitting OK, an Add items to the Project dialog pops out (See Figure 2).

Figure 2. Add items to the Project dialog.

II. Creating a VHDL File from Scratch


1. From the Add items to the Project dialog click on Create a new file.

If you have closed the Add items to the Project dialog, then select File Add to Project

New File.

2. A Create Project File dialog pops out. Select an appropriate file name for the file you want
to

add; choose VHDL as the add file as type option and Top level as the Folder option (See

Figure 3).

Figure 3. Add items to the Project dialog


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3. On the workspace section of the Main Window (See Figure 4), double-click on the file you

have just created (DFF.vhd in our case).

Figure 4: ModelSims Main Window

4. Type in your code in the new window. For our tutorial, we will use a simple D flip-flop
code

from the textbook you referred.

5. Save your code (File Save) and use compile compile option.

III. Simulating the Design


This section covers the basics for simulating a design using ModelSim.

1. Click on the Library tab of the main window and then click on the (+) sign next to the
work

library. You should see the name of the entity of the code that we have just compiled DFF.

(See Figure 5).

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Figure 5: ModelSims Main Window

2. Double-click on DFF to load the file. This should open a third tab sim in the main
window.

3. Now select view All Windows from the main window to open all ModelSim windows.

4. Locate the signals window and select the signals that you want to monitor for simulation

purposes. For this tutorial, select all signals as shown in figure 6.

Figure 6: The Signals Window

5. Drag the above signals using the left button of the mouse into the wave window. You can

also use: add wave Selected signals.

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6. Do the same as in step 5 with the list window (i.e. drag selected signals into the list
window,

or use add list Selected signals).

7. Now, select the wave window, and click on zoom full (see below). Your simulation
should
look as follows. Add binary values i.e 1 or 0 by selecting force value option by right-
clicking on the required signals.

Figure 7: the Wave window

Exercise problems
1. Repeat the same for combinational circuits.

2. Repeat the same for sequential circuits.

3. Create your own snapshots for the same.

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EXPERIMENT NO. 02
INTRODUCTION TO DATA FLOW AND BEHAVIORAL
MODELS
I. Solved Examples
1. Data flow model for all 2-i/p basic gate and universal operations.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gates is
Port ( Ain : in std_logic;---- First Input
Bin : in std_logic; ---- Second Input
Op_not : out std_logic;
Op_or : out std_logic;
Op_and : out std_logic;
Op_nor : out std_logic;
Op_nand : out std_logic;
Op_xor : out std_logic;
Op_xnor : out std_logic);
end gates;

architecture Behavioral of gates is


begin
Op_not <= not Ain;
Op_or <= Ain or Bin;
Op_and <= Ain and Bin;
Op_nor <= Ain nor Bin;
Op_nand <= Ain nand Bin;
Op_xor <= Ain xor Bin;
Op_xnor <= Ain xnor Bin;
end Behavioral;

2. Behavioral VHDL code for 1-bit full subtractor

library ieee;

use ieee.std_logic_1164.all;

entity full_sub is

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port(a,b,c:in std_logic; diff,borr:out std_logic);


end full_sub;

architecture behavioral of full_sub is


begin

process(a,b,c) is
variable temp1,temp2,temp3:std_logic;

begin
diff<= a xor b xor c;
temp1:= not(a) and b;
temp2:= not(a) and c;
temp3:= b and c;
borr<= temp1 or temp2 or temp3;
end process;
end behavioural;

II. Exercise problems


A. Write the data-flow model for following blocks. Simulate and synthesize the same.

1. Three input majority function.


2. Three input minority function.
3. Tri-state buffer with propagation delay of 10ns (try using when.else statement)
4. Three-input ex-nor gate
5. 1-bit comparator
6. Bit-level equality detector.

B. Write the behavioral model for following blocks/functions. Simulate and synthesize
the same.

1. Four-input AOI gate.


2. 1-bit comparator (use ifthenelse..)
3. Half-adder
4. Half-substractor
5. Full-adder
6. F(a,b,c,d)= m(0,4,9,15)

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EXPERIMENT NO. 03
INTRODUCTION TO SEQUENTIAL, BEHAVIORAL AND
MIXED-MODE MODELS

I. Solved Examples
1. Write a sequential VHDL code for mod-6 binary counter with positive edge triggered
clock and active-low clear.

entity mod6 is
port (clk: in std_logic;
signal s:std_logic_vector (2 downto 0);
c: out std_logic_vector(2 downto 0));
end mod6;

architecture modcount of mod6 is


begin
process(clk,s)
begin
if s=000 then
if clkevent and clk =1 then
c<=001;
end if;
end if;
if s=001 then
if clkevent and clk =1 then
c<=010;
end if;
end if;
if s=010 then
if clkevent and clk =1 then
c<=011;
end if;
end if;
if s=011 then
if clkevent and clk =1 then
c<=100;

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end if;
end if;
if s=100 then
if clkevent and clk =1 then
c<=101;
end if;
end if;
if s=101 then
if clkevent and clk =1 then
c<=000;
end if;
end if;
s<=0;
end process;
end modcount;

2. Sequential Model for Combinational Arithmetic Logic Unit

a_input
output
b_input

alu_ctrl

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity asyn_alu is
generic(data_width : integer := 8);
port
( a_input,b_input : in std_logic_vector(data_width-1 downto 0);
asyn_output: out std_logic_vector(data_width-1 downto 0);
alu_ctrl : in std_logic_vector(1 downto 0)
);
end asyn_alu;

architecture behavior of asyn_alu is

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begin

process(alu_ctrl,a_input, b_input)
begin
case alu_ctrl is
when "00" =>
asyn_output <= a_input and b_input;

when "01" =>


asyn_output <= a_input or b_input;

when "10" =>


asyn_output <= a_input + b_input;

when "11" =>


asyn_output <= a_input - b_input;

when others =>


asyn_output <= "00000000";
end case;
end process;
end behavior;

II. Exercise problems

A. Write the data flow model for following blocks.

1. 3-to-8 decoder with enable input and active-high output (Using concurrent signal
assignment statements).

2. 3-to-8 decoder with enable input and active high output (Using With..select.)

3. Seven segment display (Using Withselect.)

B. Write the sequential model for following blocks/functions.

1. F(a,b,c,d)=MM(1,2,13,15)

2. 4-bit even/odd parity indicator


3. 3-to-8 decoder with enable input and active high output (Using case statement)

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4. 3-to-8 decoder with enable input and active high output (Using If..then..else)
5. 8:1 Mux (Using case statement)
6. Clocked negative edge triggered 8:3 encoder with asynchronous reset facility (Using case
statement)
7.1:4 Demux with active-low inputs (Using case statement)
8.8-to-3 priority encoder with active high enable input and active high output (Using
If..then..else )
9.Mod-100 integer counter with a positive edge triggered clock , active high clear , parallel
load, up/down feature.
10. Write the mixed style VHDL model for full subtractor block. Model the difference and
borrow using data flow (behavioral) and structural style respectively.
11. 8-bit binary to gray and gray to binary code converter
12. Computing 1s complement and 2s complement of given 8-bit binary number
13.2-bit BCD to Excess-3 code converter
14.8-bit binary to 8-bit BCD code converter
15. To simulate the cosine of a real number.

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EXPERIMENT NO. 04
INTRODUCTION TO BEHAVIORAL MODELING OF
SEQUENTIAL CIRCUITS
I. Solved Examples
1. Write a sequential VHDL code for Ring Counter.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ring_counter is
port (
DAT_O : out unsigned(3 downto 0);
RST_I : in std_logic;
CLK_I : in std_logic
);
end ring_counter;

architecture Behavioral of ring_counter is

signal temp : unsigned(3 downto 0):=(others => '0');


begin

DAT_O <= temp;

process(CLK_I)
begin
if( rising_edge(CLK_I) ) then
if (RST_I = '1') then
temp <= (0=> '1', others => '0');
else
temp(1) <= temp(0);
temp(2) <= temp(1);
temp(3) <= temp(2);
temp(0) <= temp(3);
end if;
end if;
end process;
end Behavioral;

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2. Write a sequential VHDL code for Sequential Arithmetic Logic Unit and Counter.

a_input
output
b_input

alu_ctrl
clock

reset
4
counter

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity syn_alu is
generic(data_width : integer := 8);
port
( clock,reset : in std_logic;
a_input,b_input : in std_logic_vector(data_width-1 downto 0);
output : out std_logic_vector(data_width-1 downto 0);
counter_out: out std_logic_vector(data_width-1 downto 0);
alu_ctrl : in std_logic_vector(1 downto 0)
);
end syn_alu;

architecture behavior of syn_alu is

signal counter,counter_plus_4 : std_logic_vector(data_width-1 downto 0);

begin

counter_out <= counter;


counter_plus_4 <= counter +4;

process(clock)
begin
if rising_edge(clock) then
if reset = '1' then

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counter <= conv_std_logic_vector(0,data_width);


else
counter <= counter_plus_4;
end if;
end if;
end process;

process(clock)
begin
if rising_edge(clock) then
case alu_ctrl is
when "00" =>
output <= a_input and b_input;

when "01" =>


output <= a_input or b_input;

when "10" =>


output <= a_input + b_input;

when "11" =>


output <= a_input - b_input;

when others =>


output <= "00000000";
end case;
end if;
end process;

end behavior;

II. Exercise problems


Write the sequential VHDL code for following sequential circuits.

1. Negative edge triggered D Flip Flop


2. Negative edge triggered T Flip Flop
3. Negative edge triggered SR Flip Flop with propagation delay 10ns
4. Positive edge triggered Master Slave Flip Flop
5. Write the sequential VHDL code for negative edge triggered 4-bit Gray code counter with
active high reset input. Simulate and synthesize the same.

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6. Write the sequential VHDL code for a Mealy synchronous sequential circuit for detection
10110 serial input sequences. The3 circuit has to produce a high on the output Q, whenever it
detects 10110 sequence on its serial input. The overlapping sequence must be detected.

Example
x 0 1 1 0 1 1 0 1 1 0 0
Q 0 0 0 0 0 0 1 0 0 1 0

7. Write the sequential VHDL code for a Mealy synchronous sequential circuit for detection
11011 serial input sequences. The3 circuit has to produce a high on the output Q, whenever
it detects 11011 sequence on its serial input. The overlapping sequence must be detected.
Simulate and synthesize the same.
Example
x 0 1 1 1 0 1 1 0 1 1
Q 0 0 0 0 0 0 1 0 0 1

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EXPERIMENT NO. 05
INTRODUCTION TO STRUCTURAL MODELING OF LOGIC
CIRCUITS

I. Solved Examples
1. Structural model of Full Adder using only NAND gates.

library ieee;
use ieee.std_logic_1164.all;
entity nand1 is
port(x: in std_logic; y: in std_logic; z: out std_logic);
end nand1;
architecture nand1 of nand1 is
begin
z<=x nand y;
end nand1;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_adder is
port( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end full_adder;

architecture Behavioral of full_adder is

component nand1
port(x: in std_logic; y :in std_logic; z:out std_logic);
end component;

signal d,e,f,g,h,i,j: std_logic;


begin
U1: nand1 port map(a,b,d);
U2: nand1 port map(a,d,e);
U3: nand1 port map(b,d,f);

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U4: nand1 port map(e,f,g);


U5: nand1 port map(g,cin,h);
U6: nand1 port map(g,h,i);
U7: nand1 port map(h,cin,j);
U8: nand1 port map(i,j,sum);
U9: nand1 port map(h,d,cout);
end Behavioral;

2. Structural model of D latch using only NOR gates.


library ieee;
use ieee.std_logic_1164.all;

entity nor1 is
port(x,y: in std_logic; z:out std_logic);
end nor1;

architecture nor1 of nor1 is


begin
z<= x nor y;
end nor1;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity d_latch is
Port ( d : in STD_LOGIC; clk: in std_logic;
q : inout STD_LOGIC;
qbar : inout STD_LOGIC);
end d_latch;

architecture Behavioral of d_latch is

component nor1
port(x,y: in std_logic; z: out std_logic);
end component;

signal dbar,e,f:std_logic;

begin

U1: nor1 port map(d,clk,e);


U2: nor1 port map(dbar,clk,f);
U3: nor1 port map(e,q,q);

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U4: nor1 port map(f,qbar,qbar);

end Behavioral;

3. Structural model of EVEN/ODD PARITY INDICATOR/CHECKER CIRCUIT

library ieee;
use ieee.std_logic_1164.all;

entity xor1 is
port(u,v: in std_logic; w:out std_logic);
end xor1;

architecture xor1 of xor1 is


begin
w<=u xor v;
end xor1;

library ieee;
use ieee.std_logic_1164.all;

entity not1 is
port(x: in std_logic; y: out std_logic);
end not1;

architecture not1 of not1 is


begin
y<=not(x);
end not1;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity parity is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
odd : buffer STD_LOGIC;
even : out STD_LOGIC);
end parity;

architecture Behavioral of parity is

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component xor1
port(u,v: in std_logic; w: out std_logic);
end component;

component not1
port(x: in std_logic; y: out std_logic);
end component;

signal e,f: std_logic;

begin

U1: xor1 port map(a,b,e);


U2: xor1 port map(c,d,f);
U3: xor1 port map(e,f,odd);
U4: not1 port map(odd,even);
end Behavioral;

II. Exercise problems

Write the structural VHDL code for the following digital blocks. Simulate and synthesize the
same.

1. Full subtractor using only NAND gates.


2.4:1 mux using only NOR gates
3.1:4 demux using only NAND gates
4.1 out- of- 8 decoder with enable input and active high outputs using only NOR gates.
5. SR latch using only NAND gates.
6.4 bit magnitude comparator
7.8 bit equality detector
8.4 bit priority encoder
9.4 bit SIPO shift register.

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EXPERIMENT NO. 06
INTRODUCTION TO SUBPROGRAMS IN VHDL

I. Solved Examples
1. Write a function for byte reversal in VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity byt is
port(
din:in std_logic_vector(3 downto 0);
dout:out std_logic_vector(3 downto 0));
end byt;
architecture byt of byt is

function byte_reversal(din:std_logic_vector) return std_logic_vector is

variable res:std_logic_vector(din'reverse_range);
begin

for j in din'range loop


res(j):=din(j);
end loop;
return res;
end byte_reversal;
begin

process(din)
begin

dout<=byte_reversal(din);
end process;
end byt;

2. Write a package to implement sum of Full adder.

Program for Package


library ieee;
use ieee.std_logic_1164.all;

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use ieee.std_logic_unsigned.all;

package mymux is
function MUX(signal in1,in2,sel:in std_logic) return std_logic;
end myMUX;

package body mymux is


function MUX(signal in1,in2,sel:in std_logic) return std_logic is
begin
return ((in1 and (not sel)) or (in2 and sel));
end MUX;
end myMUX;

--Use of package
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use work.mymux.all;

entity FullAdd is
Port ( A,b,Ci : in std_logic;
sum, carry : out std_logic);
end FullAdd;

architecture Behavioral of FullAdd is


signal x,y,cbar:std_logic;
begin
cbar<= not ci;
m1: x<=MUX (ci,cbar,b);
m2: y<=MUX (cbar,ci,b);
m3: sum<=MUX (x,y,a);
end Behavioral;

3. Write a VHDL program for full adder using half adder (Procedure) and OR gate
(Component).

library ieee;
use ieee.std_logic_1164.all;
entity or_2c is
port(in1,in2:in std_logic;
out1:out std_logic);

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end or_2c;
architecture dataflow of or_2c is
begin
out1<= in1 or in2;
end dataflow;

library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port(a,b,cin:in std_logic;
sum, carry:out std_logic);
end fulladder;
architecture FA of fulladder is
procedure HA (signal in1,in2:in std_logic; signal sum1,carry1:out std_logic)
is
begin
sum1<=(in1 xor in2);
carry1<=(in1 and in2);
end HA;

signal s1,c1,c2:std_logic;
begin
u1: ha(a,b,s1,c1);
u2: ha(s1,cin,sum,c2);
u3: entity or_2c port map (in1=>c1 ,in2=>c2, out1=>carry);
end fa;

II. Exercise problems

A. Write the behavioral VHDL code for the following generic blocks:

1. N-bit NOR gate


2. N-bit NAND gate
3. N-bit magnitude comparator

B. Write the structural VHDL code for following generic blocks:

1. N-bit magnitude comparator


2. Mod-20 ripple counter using negative edge triggered JK FF component
3. N-bit SISO/SIPO right-shift register using negative edge triggered D FF

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4. N-bit carry-ripple adder

C. Write the behavioral VHDL code for following circuits using function and procedure
1. 4-bit gray code counter
2. To find cos2(x), where Cos(x) = 1 (x2/2!) + (x4/4!)-(x6/6!)+. Considering
first five terms.

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EXPERIMENT NO. 07
INTRODUCTION TO XILINX ISE TOOL
Getting Started
To start ISE, double-click the desktop icon,

or start ISE from the Start menu by selecting:

Start All Programs Xilinx ISE 10.1 Project Navigator Note:


Your start-up path is set during the installation process and may differ from the one above.

Accessing Help
At any time during the tutorial, you can access online help for additional information about
the ISE software and related tools.
To open Help, do either of the following:
Press F1 to view Help for the specific tool or function that you have selected or
highlighted.
Launch the ISE Help Contents from the Help menu. It contains information about
creating and maintaining your complete design flow in ISE.

Create a New Project


Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit
demo board.
To create a new project:
1. Select File > New Project... The New Project Wizard appears.
2. Type tutorial in the Project Name field.
3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory
is created automatically.
4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.
6. Fill in the properties in the table as shown below:

Product Category: All


Family: Spartan3
Device: XC2s400
Package: TQ144
Speed Grade: -5
Top-Level Source Type: HDL

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Synthesis Tool: XST (VHDL/Verilog)


Simulator: ISE Simulator (VHDL/Verilog)
Preferred Language: Verilog (or VHDL)
Verify that Enable Enhanced Design Summary is selected. Leave the
default values in the remaining fields.

When the table is complete, your project properties will look like the following AS SHOWN
IN FIG 1:

FIG.1. Schematic of current POP-UP window.

7. Click Next to proceed to the Create New Source window in the New Project Wizard. At
the end of the next section, your new project will be complete.

Create an HDL Source

In this section, you will create the top-level HDL file for your design. Determine the
language that you wish to use for the tutorial. Then, continue either to the "Creating a VHDL
Source" section below, or skip to the "Creating a Verilog Source" section.

Creating a VHDL Source


Create a VHDL source file for the project as follows:
1. Click the New Source button in the New Project Wizard.
2. Select VHDL Module as the source type.
3. Type in the file name counter.

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4. Verify that the Add to project checkbox is selected.


5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown below:

FIG.2. Schematic of current POP-UP window

7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete
the new source file template.

8. Click Next, then Next, then Finish.

The source file containing the entity/architecture pair displays in the Workspace, and the
counter displays in the Source tab, as shown below in figure 3:

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FIG.3.

Schematic of current POP-UP window

Final Editing of the VHDL Source


1. Add the following signal declaration to handle the feedback of the counter output
below the architecture declaration and above the first begin statement:
signal count_int : std_logic_vector(3 downto 0) := "0000";

2. Customize the source file for the counter design by replacing the port and signal name
placeholders with the actual ones as follows:
replace all occurrences of <clock> with CLOCK
replace all occurrences of <count_direction> with DIRECTION
replace all occurrences of <count> with count_int

3. Add the following line below the end process; statement:


COUNT_OUT <= count_int;

4. Save the file by selecting File Save.


When you are finished, the counter source file will look like the following:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is

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Port ( CLOCK : in STD_LOGIC;


DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
signal count_int : std_logic_vector(3 downto 0) := "0000";
begin
process (CLOCK)
begin
if CLOCK='1' and CLOCK'event then
if DIRECTION='1' then
count_int <= count_int + 1;
else
count_int <= count_int - 1;
end if;
end if;
end process;
COUNT_OUT <= count_int;
end Behavioral;

You have now created the VHDL source for the tutorial project. Skip past the Verilog
sections below, and proceed to the Checking the Syntax of the New Counter
Modulesection.

Checking the Syntax of the New Counter Module


When the source files are complete, check the syntax of the design to find errors and typos.
1. Verify that Implementation is selected from the drop-down list in the Sources
window.
2. Select the counter design source in the Sources window to display the related
processes in the Processes window.
3. Click the + next to the Synthesize-XST process to expand the process group.
4. Double-click the Check Syntax process.
Note: You must correct any errors found in your source files. You can check for errors in the
Console tab of the Transcript window. If you continue without valid syntax, you will not be
able to
simulate or synthesize your design.
5. Close the HDL file.
Design Simulation
Verifying Functionality using Behavioral Simulation
Create a test bench waveform containing input stimulus you can use to verify the
functionality of the counter module. The test bench waveform is a graphical view of a test
bench.

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Create the test bench waveform as follows:


1. Select the counter HDL file in the Sources window.
2. Create a new test bench source by selecting Project New Source.
3. In the New Source Wizard, select Test Bench WaveForm as the source type, and type
counter_tbw in the File Name field.
4. Click Next.
5. The Associated Source page shows that you are associating the test bench waveform with
the source file counter. Click Next.
6. The Summary page shows that the source will be added to the project, and it displays the
source directory, type, and name. Click Finish.
7. You need to set the clock frequency, setup time and output delay times in the Initialize
Timing dialog box before the test bench waveform editing window opens.
The requirements for this design are the following:
The counter must operate correctly with an input clock frequency = 25 MHz.
The DIRECTION input will be valid 10 ns before the rising edge of CLOCK.
The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK. The
design requirements correspond with the values below.
Fill in the fields in the Initialize Timing dialog box with the following information:
Clock High Time: 20 ns.
Clock Low Time: 20 ns.
Input Setup Time: 10 ns.
Output Valid Delay: 10 ns.
Offset: 0 ns.
Global Signals: GSR (FPGA)
Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically.
Initial Length of Test Bench: 1500 ns

FIG.4. Schematic of current POP-UP window

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8. Click Finish to complete the timing initialization.


9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input
Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define the
input stimulus for the counter design as follows:
Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the
counter will count up.
Click on the blue cell at approximately the 900 ns to assert DIRECTION low so that the
counter will count down.

FIG.5. Schematic of current POP-UP window


Simulating Design Functionality

Verify that the counter design functions as you expect by performing behavior simulation
as follows:
1. Verify that Behavioral Simulation and counter_tbw are selected in the Sources
window.
2. In the Processes tab, click the + to expand the Xilinx ISE Simulator process and
double-click the Simulate Behavioral Model process.
The ISE Simulator opens and runs the simulation to the end of the test bench.
3. To view your simulation results, select the Simulation tab and zoom in on the
transitions.
The simulation waveform results will look like the following:

FIG.6. Schematic of current POP-UP window

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Note: You can ignore any rows that start with TX.
4. Verify that the counter is counting up and down as expected.
5. Close the simulation view. If you are prompted with the following message, You have
an active simulation open. Are you sure you want to close it?, click Yes to continue.
You have now completed simulation of your design using the ISE Simulator.

Implement Design and Verify Constraints

Implement the design and verify that it meets the timing constraints specified in the
previous section.
1. Select the counter source file in the Sources window.
2. Open the Design Summary by double-clicking the View Design Summary process in the
Processes tab.
3. Double-click the Implement Design process in the Processes tab.
4. Notice that after Implementation is complete, the Implementation processes have a
green check mark next to them indicating that they completed successfully without
Errors or Warnings.

FIG.7. Schematic of current POP-UP window

5. Locate the Performance Summary table near the bottom of the Design Summary.
6. Click the All Constraints Met link in the Timing Constraints field to view the Timing
Constraints report. Verify that the design meets the specified timing requirements.

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FIG.8. Schematic of current POP-UP window


7. Close the Design Summary.

Assigning Pin Location Constraints

Specify the pin locations for the ports of the design so that they are connected correctly on
the board shown in fig 8.
To constrain the design ports to package pins, do the following:
1. Verify that counter is selected in the Sources window.
2. Double-click the Floorplan Area/IO/Logic - Post Synthesis process found in the
User Constraints process group. The Xilinx Pinout and Area Constraints Editor
(PACE) opens.
3. Select the Package View tab.
4. In the Design Object List window, enter a pin location for each pin in the Loc column
using the following information:
CLOCK input port connects to FPGA pin P80 (GCK0 signal on board)
COUNT_OUT<0> output port connects to FPGA pin P30 (LD0 signal on board)
COUNT_OUT<1> output port connects to FPGA pin P31 (LD1 signal on board)
COUNT_OUT<2> output port connects to FPGA pin P44 (LD2 signal on board)
COUNT_OUT<3> output port connects to FPGA pin P45 (LD3 signal on board)
DIRECTION input port connects to FPGA pin P3 (SW signal on board)

5. Select File Save. You are prompted to select the bus delimiter type based on the
synthesis tool you are using. Select XST Default <> and click OK.

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6. Close PACE.
Notice that the Implement Design processes have an orange question mark next to them,
indicating they are out-of-date with one or more of the design files. This is because the UCF
file has been modified.

FIG.9. Schematic of current POP-UP window

DOWNLOAD DESIGN TO THE BOARD


This is the last step in the design verification process. This section provides simple
instructions for downloading the counter design to the Kit board.
1. Connect the 5V DC power cable to the power input on the board.
2. Connect the download cable between the PC and Board.

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3. Select Implementation from the drop-down list in the Sources window.


4. Select counter in the Sources window.
5. In the Process window, double-click the Configure Target Device process.
6. The Xilinx WebTalk Dialog box may open during this process. Click Decline.
iMPACT opens and the Configure Devices dialog box is displayed.

7. In the Welcome dialog box, select Configure devices using Boundary-Scan OR configure
device & select using slave serial mode.
8. Verify that Automatically connect to a cable.
9. Click Finish.
10. one window generate ,select counter.bit file
11. The Assign New Configuration File dialog box appears. To assign a configuration file to
the xc2s50 device in the JTAG chain, select the counter.bit file and click Open.
12. If you get a Warning message, click OK.
13. Select Bypass to skip any remaining devices.
14. Right-click on the xc3s400 device image, and select Program... The Programming
Properties dialog box opens

15. Click OK to program the device.


When programming is complete, the Program Succeeded message is displayed.
On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running.
16. Close iMPACT without saving.

FIG.10. Schematic of current POP-UP window

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EXPERIMENT NO. 08

SYNTHESIS AND EXECUTION OF LOGIC CIRCUITS FOR XILINX


SPARTAN 3 CHIP USING VHDL

I. Solved Examples
1. Simulate and synthesize 1-bit comparator using XILINX SPARTAN 3 chip.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comparator is
Generic (N: integer := 3);--- Generalizing the Inputs
Port( A,B: in STD_LOGIC_VECTOR(N downto 0);
ALB,AGB,AEB: out STD_LOGIC);
end comparator;

architecture Comparator_arc of comparator is


begin

process(A,B)
begin
if ( A < B ) then ALB <= '1';
else ALB <= '0';
end if;
if ( A > B ) then AGB <= '1';
else AGB <= '0';
end if;
if ( A = B ) then AEB <= '1';
else AEB <= '0';
end if;
end process;
end Comparator_arc;

UCF For Comparator


NET "A<0>" LOC = "p74" ;
NET "A<1>" LOC = "p76" ;
NET "A<2>" LOC = "p77" ;
NET "A<3>" LOC = "p79" ;
NET "AEB" LOC = "p84" ;
NET "AGB" LOC = "p85" ;
NET "ALB" LOC = "p86" ;

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NET "B<0>" LOC = "p78" ;


2. Simulate and synthesize 4:1 DEMUX using XILINX SPARTAN 3 chip.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity exp2e_Demux1_4 is
port (
d_in: in STD_LOGIC; --Input For Demultiplexer
sel: in STD_LOGIC_VECTOR (1 downto 0); --Select Line of Demux
d_out: out STD_LOGIC_VECTOR (3 downto 0)); --Output Lines of Demux
end exp2e_Demux1_4;

architecture demux1_4_arch of Demux1_4 is


begin
process(d_in,sel)
begin
d_out<="0000";
case sel is
when "00"
=> d_out(0)<=d_in;
when "01"
=> d_out(1)<=d_in;
when "10"
=> d_out(2)<=d_in;
when others => d_out(3)<=d_in;
end case;
end process;
end demux1_4_arch;

UCF For DEMUX

NET "a" LOC = "p79" ;


NET "en" LOC = "p74" ;
NET "sel[0]" LOC = "p77" ;
NET "sel[1]" LOC = "p76" ;
NET "y[0]" LOC = "p87" ;
NET "y[1]" LOC = "p86" ;
NET "y[2]" LOC = "p85" ;
NET "y[3]" LOC = "p84" ;

II. Exercise problems

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Exercise problems on synthesis and downloading the circuit description to XILINX


SPARTAN 3 chip using universal VLSI Trainer kit

A. Write the behavioral VHDL code for realizing following counters, capable of
counting following counts repeatedly with a 1 sec delay at given OUTPUT LEDs (by
assigning proper pin numbers in the edit constraint file);

(i) 4 bit binary counter ie. 0000-0001-0010-1110-1111

(ii) 4-bit gray code counter 0000-0001-0011-0010-1001-1000

Use the available system clock of frequency 4 MHz and include an asynchronous active-high
reset input.

B. Write a behavioral VHDL code for generating a single digit counter, capable of
counting following counts repeatedly with a 1 sec delay at one of its seven segment
display digits(by assigning a proper pin number to display control in the trainer):

(i) Hex digit display 0-1-2-F-0

(ii) Hex digit display; even counters say 0-2-4-E-0

(iii) Hex digit display; odd counts say1-3-5-F-1

(iv) Decimal digit display; 0-1-2 -9-0

Use the available system clock of frequency 4 MHz and include an asynchronous active-high
reset input.

C. Write the behavioral VHDL code for a Mealy synchronous sequential circuit for
detecting 10110 serial input sequences. The circuit has to produce a high on the output
q, whenever it detects 10110 sequence on its serial input x. the overlapping sequence
must be detected.

Example:

Serial input x 01101101100

Output q 00000010010

Synthesize the code and download the description on the SPARTAN 3 chip and demonstrate
the sequence detector action.

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EXPERIMENT NO. 09
SYNTHESIS AND EXECUTION OF STAIRCASE, RAMP AND
TRAINGULAR WAVEFORM IN SPARTAN 3 CHIP USING VHDL

I. Solved Examples
1. Synthesize and display the staircase waveform in CRO using SPARTAN 3 CHIP.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity staircase is
Port ( clk : in STD_LOGIC;
divider : inout STD_LOGIC_VECTOR(7 downto 0):="00000000");
end staircase;

architecture Behavioral of staircase is


signal count:std_logic_vector(3 downto 0);
signal clk1:std_logic;
begin

process(clk)
begin
if clk' event and clk='1' then
count<=count +1;
end if;
end process;
clk1<=count(3);
process(clk1,divider)
begin
if clk1' event and clk1='1' then
divider<=divider + 25;
end if;
end process;
end Behavioral;

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2. Synthesize and display the ramp waveform in CRO using SPARTAN 3 CHIP.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RAMPWAVE is
Port ( clk : in STD_LOGIC;
divider : inout STD_LOGIC_VECTOR(7 downto 0):="00000000");
end RAMPWAVE;

architecture Behavioral of RAMPWAVE is


signal count: std_logic_vector (8 downto 0);
signal clk1:std_logic;

begin
process(clk)
begin
if clk' event and clk='1' then
count<=count +1;
end if;
end process;
clk1<=count(8);
process(clk1,divider)
begin
if clk1' event and clk1='1' then
divider<=divider + 1;
end if;
end process;
end Behavioral;

3. Synthesize and display the traingular waveform in CRO using SPARTAN 3 CHIP.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity traingle is

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Port ( clk : in STD_LOGIC;


divider : inout STD_LOGIC_VECTOR(7 downto 0):="00000000");

end traingle;

architecture Behavioral of traingle is


signal counter:std_logic_vector(8 downto 0);
signal temp:std_logic_vector(3 downto 0);
signal en:std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp<=temp+1;
end if;
end process;

process(temp(3))
begin

if rising_edge(temp(3)) then
counter<=counter +1;
if counter(8)= '1' then
divider<=counter(7 downto 0);
else
divider<=not(counter(7 downto 0));
end if;
end if;
end process;
end Behavioral;

II. Exercise problems

1. Synthesize and display the ramp waveform with delay of 0.25 us.

2. Write a VHDL code to generate sine waveforms using DAC.

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EXPERIMENT NO. 10
IMPLEMENTING STEPPER MOTOR CONTROL USING XILINX
SPARTAN 3 CHIP

I. SOLVED EXAMPLES
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity stepper is
port (clk, anticlk, slow, med, high1: in STD_LOGIC;
stepout: out STD_LOGIC_VECTOR (3 downto 0));
end stepper;

architecture Behavioral of stepper is


signal clk1: std_logic;
signal divider: std_logic_vector(20 downto 0);
signal count: std_logic_vector(1 downto 0);

begin
process(clk)
begin
if rising_edge(clk) then
divider<=divider+1;
end if;
end process;
process(slow, med, high1)
begin
if slow=1 then clk1<=divider(20);
elsif med=1 then clk1<=divider(18);
elsif high=1 then clk1<=divider(15);
else clk1<=0;
end if;

end process;
process(anticlk, clk1)
begin
if rising_edge(clk1) then
if antclk=1 then
count<=count-1;
else

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count<=count+1;
end if;
end if;
end process;
process(count)
begin
case count is
when 00=>stepout<=1100;
when 01=>stepout<=0110;
when 10=>stepout<=0011;
when 11=>stepout<=1001;
when others=>null;
end case;
end process;
end Behavioral;

II. Exercise problems

1.Write a program to run the motor in the clockwise direction with a frequency of 10Hz.
2.Write a program to run the motor in the anti-clockwise direction with a frequency of 4MHz.
3.Write a program to run the motor in steps of 2 and 4 in one clock cycle (assume suitable
clock frequency).

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EXPERIMENT NO. 11
INTRODUCTION TO MICROWIND SOFTWARE FOR LAYOUT
GENERATION

Microwind is a tool for designing and simulating circuits at layout level. The tool features
full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics,
2D cross section, 3D process viewer), and an analog simulator.

Fig: 1. Schematic of editor

When we open the file microwind, a window with grids and a palette consisting of different
fabrication materials will pop out as in the fig1.

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On the tool bar we can find the following tools

: Delete tool, Erases some layout included in the given area or pointed by the mouse.

: Copy and paste tool, Copies the layout included in the given area.

: Stretch and move tool, Changes the size of one box, or moves the layout included in
the given area.

: Electrical node, Verifies the electrical net connections.

: Run simulation, used to simulate the layout

: Measure the distance

: Design rule checker, used to check the size constraints.

: Show palette

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MOS Layout Design Rules:

Rule number Description L-Rule

R1 Minimum active area width 3


R2 Minimum active area spacing 3

R3 Minimum poly width 2


R4 Minimum poly spacing 2
R5 Minimum gate extension of poly over active 2
R6 Minimum poly-active edge spacing 1
(poly outside active area)
R7 Minimum poly-active edge spacing 3
(poly inside active area)

R8 Minimum metal width 3


R9 Minimum metal spacing 3

R10 Poly contact size 2


R11 Minimum poly contact spacing 2
R12 Minimum poly contact to poly edge spacing 1
R13 Minimum poly contact to metal edge spacing 1
R14 Minimum poly contact to active edge spacing 3

R15 Active contact size 2


R16 Minimum active contact spacing 2
(on the same active region)
R17 Minimum active contact to active edge spacing 1
R18 Minimum active contact to metal edge spacing 1
R19 Minimum active contact to poly edge spacing 3
R20 Minimum active contact spacing 6
(on different active regions)

To Draw the Layout

Example: cmos inverter

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Fig: 2. Select N well.

Step 1:

To create a pMOS transistor: Select N well from the palette. Click on the grid and
drag it to draw a box as shown in the fig2.

The width of the N well should not be less than 10

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Fig: 3. Select P+diffusion

Step 2:

Select P+diffusion, and draw the box inside the N well as can be seen in fig 3.

The spacing between p+diffusion and the N well boundaries should not be less than 6

Fig: 4.Select polysilicon.

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Step 3:
Now select polysilicon from the palette and draw the polysilicon gate as shown in the
fig 4.

The box width should not be less than 2, which is the minimum width of the polysilicon
box. And the extra polysilicon surrounding the p+diffusion should not be less than 3

Fig: 5.Select contact P+diffusion/metal1.

Step 4:
To define the source and drain contacts: To build an electrical connection, a physical
contact is needed. The corresponding layer is called "contact".
Click on Metal 1 in the palette and then create the required rectangle on both the ends
of p diffusion.
Make the contacts between metal 1 and p+ diffusion by placing the contact
P+diffusion/metal1 from the palette on the layout as shown in the fig 5.

The distance between polysilicon and the metal should be at least 1 .

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Fig: 6. select contact N+diffusion/metal1

Step 5:

Similarly draw the nmos below the pmos by using N+diffusion, define the polysilicon
gate, source, drain and the contacts.

To define the contacts between metal and N+diffusion, select contact


N+diffusion/metal1 fom the palette and place it wherever there are metal and
N+diffusion contacts

The spacing between two metals should not be less than 4

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Fig: 7.Go for design rule checker.

Step 6:

Once the design is over check the size constraints using the design rule checker.

If there are any changes to be made in the dimension of the layout, it will display the
errors as shown in fig 7.

It can be resized by clicking on the edges of the layout and dragging it.

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Fig: 8. Connect the drains of each transistors

Step 7:

Once the pmos and nmos transistors are drawn, connections between them is to be
done.

Connect two gates of pmos and nmos by the polysilicon.

And connect the drains of each transistors with the metal 1 as it is show in fig 8.

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Fig: 9.Insert metal-to-polysilicon contact.

Step 8:
As polysilicon is a poor conductor, metal is preferred to interconnect signals and
supplies.
Consequently, the input connection of the inverter is made with metal.
Metal and polysilicon are separated by an oxide which prevents electrical
connections.
Therefore, a box of metal drawn across a box of polysilicon does not allow an
electrical connection.
You may insert a metal-to-polysilicon contact in the layout using an icon situated in
the palette.

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Fig: 10.Apply Vdd and Vss.

Step 9:
To define the inputs, outputs, ground and supply, select clock or pulse, a visible node,
ground and vdd supply respectively from the palette and place it on the appropriate
places of layout. (Fig 10).
Adding the VDD polarization in the n-well region is a very strict rule.
It is possible to define the rise time, fall time, time high and time low for the input
clock.

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Fig: 11. Output wave form.

Step: 8
Once the design is over we can simulate it by clicking on the run simulation. The
timing diagrams of the cMOS device appears, as shown in fig 11
Depending on the input sequences assigned at the input the output is observed in the
simulation. The power value is also given.

II. Exercise problems

1. Draw layout of all 2-input basic gates.

2. Draw layout of 2:1 MUX.

3. Draw layout of D-FF using switch logic.

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Dept. of E&C Engg., MIT VLSI LAB

EXPERIMENT NO. 12
INTRODUCTION TO PIN LAYOUT OF XILINX SPARTAN 3 CHIP

XC3S400-TQ144

I. FPGA DESIGN FLOW

Fig.1. Typical FPGA Design flow

II. SPARTAN 3 CHIP LAYOUT.

Fig.2. SPARTAN 3 chip layout.

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Dept. of E&C Engg., MIT VLSI LAB

Fig.3. SPARTAN 3 BGA package marking.

Fig.4. SPARTAN 3 packaging.

INTRODUCTION TO VERILOG PROGRAMMING

1. DATA- FLOW MODEL FOR HALFADDER

module ha(a, b, sum, carry);


input a;
input b;
output sum;
output carry;
assign carry=a&b; This is same as and(carry,a,b)
assign sum=a^b; This is same as xor(sum,a,b)
endmodule

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Dept. of E&C Engg., MIT VLSI LAB

2. SEQUENTIAL MODEL FOR 4:1 MUX

module mux4_1 (out, in, sel) ;


output out ;
input [3:0] in ;
input [1:0] sel ;
reg out ;
always @(sel or in) begin
case(sel)
2d0: out = in[0] ;
2d1: out = in[1] ;
2d2: out = in[2] ;
2d3: out = in[3] ;
default: 1bx ;
endcase
end
endmodule

II.EXERCISE PROBLEM- WRITE VERILOG CODE FOR

A. DATA FLOW MODELLING OF FOLLOWING

1. Three input majority function.


2. Three input minority function.
3. Three-input ex-nor gate
4. Bit-level equality detector.

B. SEQUENTIAL MODELLING OF FOLLOWING

1. Four-input AOI gate.


2. 1-bit comparator (use ifthenelse..)
3. Half-substractor
4. Full-adder
5. F(a,b,c,d)= m(0,4,9,15)

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