DC Lab

RAGHU INSTITUTE OF TECHNOLOGY
Dakamarri (v), Bheemunipatnam (M)

Visakhapatnam Dist, Andhra Pradesh, PIN-531162
(Approved by AICTE, New Delhi, and Affiliated to Jawaharlal Nehru Technological University: Kakinada (AP)
2015-2016
III B.Tech ECE: II- Semester
LABORATORY MANUAL
For
DIGITAL COMMUNICATIONS LABORATORY

[Student Manual]
Prepared by
Mrs.M.Kalpana
Assosciate Professor
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
RAGHU INSTITUTE OF TECCHNOLOGY
Dakamarri (v), Bheemunipatnam (M)
Visakhapatnam Dist, Andhra Pradesh, PIN-531162
(Approved by AICTE, New Delhi, and Affiliated to Jawaharlal Nehru Technological University: Kakinada (AP)
CERTIFICATE
Name of the Laboratory : Digital Communication Laboratory
Name of the Faculty : Mrs. M. Kalpana
Department : Electronics and Communication Engineering
Program : B.Tech
Year : III Year
Semester : II Semester
IQAC Members:
Name
Signature(s) :
HOD - ECE
C O NT E N T S
S.No Description Page No
1 Course Description i
2 General Instructions vi
3 Additional Instructions viii
5 University Syllabus ix
6 List of Experiments xi
7 Cycle-Wise List of Experiment xii

8 Time Division Multiplexing. 1
9 Pulse Code Modulation. 9
10 Differential Pulse Code Modulation. 16
11 Delta Modulation. 24
12 Frequency Shift Keying. 34
13 Binary Phase Shift Keying. 42
14 Differential Phase Shift Keying. 49

15 Companding 57
16 Image Compression Using Huffman Coding 64
17 Linear Block Code-Encoder and Decoder 71

18 Binary Cyclic Code - Encoder and Decoder 79
19 Convolution Code - Encoder and Decoder 91
20 Adaptive Delta Modulation 101
21 Minimum Shift keying 113
Appendix 123
References 135
Department of Electronics & Communications Engineering DC LAB
COURSE DESCRIPTION
Course Context and Overview:

The course consists of laboratory tasks dealing with various modulation and de-modulation,
source coding and decoding and multiplexing techniques.
Course Prerequisites:
Probability Theory and stochastic process, Signals and systems, Analog Communications.
Literature
Student Manual
Books Recommended:
Text Books:
Digital Communications-Simon Haykin,John Wiley,2005
Principles of Communication Systems-H.Taub and D.Schilling TMH,2003.
Reference Books:
1.Digital and Analog Communication Systems-Sam Shanmugam, John Wiley,2005
2.Digital Communications-John Proakis, TMH,1983.
3.Modern Analog and Digital Communication B.P.Lathi,Oxford reprint,3rd edition ,2004.
Additional Resources:
1. www.ece.ucf.edu
Programme Educational Objectives
PEO No. Programme Educational Objectives
PEO 1 To have the knowledge and technical skills required to be and to remain productive
To apply technical knowledge and skills as electronics and communication
PEO 2 engineers to provide effective solutions in industrial and governmental
organizations
To achieve success with awareness of entrepreneurship skills and have the ability for
PEO 3 lifelong learning by pursuing professional development to meet the emerging and
evolving demands to have a successful career.
Raghu Institute of Technology, Dakamarri, Visakhapatnam i

Programme Outcomes
PO No. Programme Outcomes
a an ability to apply knowledge of mathematics, science and engineering
b an ability to design and conduct experiments, as well as to analyze and interpret data
c an ability to design a system, component, or process to meet desired needs within realistic
constraints such as economic, environmental, social, political, ethical, health and safety,
d manufacturability,
an andonsustainability
ability to function multidisciplinary teams
e an ability to identify, formulate, and solve engineering problems
f an ability to understanding of professional and ethical responsibility
g an ability to communicate effectively
h the broad education necessary to understand the impact of engineering solutions in a global,
economic, environmental, and societal context
i a recognition of the need for, and an ability to engage in life-long learning
j a knowledge of contemporary issues
k an ability to use the techniques, skills, and modern engineering tools necessary for
engineering practice
l an ability to implement MATLAB, Embedded systems design for electronics and
communications engineering applications.
Course Objectives:
1.To study 4 channel analog Multiplexing and Demultiplexing technique.
2. To study pcm and dpcm technique
3. To study delta modulation and demodulation technique.
4. To generate and demodulate the FSK signals.
5. To study binary and differential phase shift keying.
6. Implementation of -law companding and expansion of signal.
7 Image compression using Huffman coding.
8. To study Linear Block encoding and decoding.
9.To study Cyclic Redundancy code encoding and decoding.
10.To Study Convolution Encoding And Hard Decision Viterbi Decoding For K= 7 And Rate
=1/2.
Raghu Institute of Technology, Dakamarri, Visakhapatnam ii

Course Outcomes:
S.No Course Outcomes
Students will be able to identify and describe different techniques in modern digital
1 communications, in particular in source coding, modulation and detection, carrier modulation,
and channel coding.
Students will be able to analyze digital modulation techniques by using signal processing
2
tools.
Mapping of Course Outcomes to Programme Outcomes and Programme Educational

Objectives
Programme
Programme
S.No Course Outcomes Educational
Outcomes
Objectives
Students will be able to identify and describe different
techniques in modern digital communications, in particular
1 C,K PEO 2
in source coding, modulation and detection, carrier
modulation, and channel coding.
Students will be able to analyze digital modulation
2 E PEO 2
techniques by using signal processing tools.
Assessment Strategy
A variety of learning strategies are used throughout the course.
S.No Teaching Learning and Assessment Strategy
1 Classroom Demonstration by Faculty In charge through different Teaching

Methodologies
2 Extra Laboratory Session
3 Student- Faculty In charge Discussion
4 Collaborative and Co-operative learn
5 Independent student study and Practice
Raghu Institute of Technology, Dakamarri, Visakhapatnam iii

Evaluation of Marks for the Laboratory Exam

Internal Marks - 25
For Laboratory courses there should be continuous evaluation during the semester for 25
Internal Marks. The distribution of Internal Marks is given below.
Serial No Criteria Marks

1 Day to Day Work 10
2 Internal Examination 10
3 Record 5
Total Marks 25
External Lab Exam - 50

Each semester end lab Examination shall be evaluated by an External Examiner along with an
Internal Examiner.

1 Pre practical 20
2 Practical 10
3 Post practical 10
4 Viva 10
Total Marks 50
Total Lab Exam Marks - 75

Each semester Total Final lab Examination marks is the sum of marks obtained in both
internal and external Exams.

1 Internal 25
2 External 50
Total Marks 75
Raghu Institute of Technology, Dakamarri, Visakhapatnam iv

GENERAL INSTRUCTIONS
SAFETY:
1. You are doing experiments with the help of electrical power. You have to be very careful.
You must clearly know the supply system to your worktable in particular and the entire
laboratory in general.
2. In case of any wrong observation, you have to immediately switch off supply to the
worktable.
3. You have to tuck in your shirts and you have to wear an overcoat.
4. Wearing loose garments inside the lab is strictly prohibited.
5. You have to wear shoes compulsorily.
ATTENDANCE:
1. Every time you come to the laboratory class, you have to come with your record note
book, observation notebook, calculators etc.
2. You have to give your attendance, you have to submit your records, you have to show the
day's experiment's circuit diagram and get it signed. You have to occupy the respective
worktable of the equipment. Collect required kits etc as per indent slip.
DOING EXPERIMENTS:
1. Start the experiment as per the procedure.
2. If any of the things are wrong, then switch off and modify the connections. Inform to the
staff and then START.
OBSERVATION:
1. Enter all readings in the tabulation.
CALCULATION:
Calculate all required quantities and enter in the tabulation. Units are very, very important.
Draw the necessary graphs. Write the result. Show it to the staff for getting Signature.
RECORD:
1. As the name Implies, it is a record: permanent record for reference. Write neatly; Draw
circuit diagrams neatly and label correctly.
2. Enter readings in the tabulation.
Raghu Institute of Technology, Dakamarri, Visakhapatnam v

3. UNITS are to be written for various quantities.

4. Draw Graph. Complete the record before you come for next lab class.
5. Bring the record for submission during next lab class
ADDITIONAL INSTRUCTIONS
1. Before entering into the laboratory class, you must be well prepared for the experiment
that you are going to do on that day.
2. You must bring the related textbook, which may deal with the relevant experiment.
3. Get the circuit diagram approved.
4. Get the reading verified. Then inform the technician so that supply to the worktable can be
switched off.
5. You must get the observation note corrected within two days from the date of completion
of experiment.
6. Write the answer for all the discussion questions in the observation note. If not, marks for
concerned observation will be proportionately reduced.
7. If you miss any practical class due to unavoidable reasons, intimate the staff in charge and
do the missed experiment in the repetition class.
8. Such of those students who fail to put in a minimum of 75% attendance in the laboratory
class will run the risk of not being allowed for the University Practical Examination. They
will have to repeat the lab course in subsequent semester after paying prescribed fee.
9. Girls should put their plait inside their overcoat.
10. Acquire a good knowledge of the surrounding of your worktable. Know where the various
live points are situated in your table.
11. In case of any unwanted things happening, immediately switch off the mains in the
worktable. The same must be done when there is a power break during the experiment
being carried out.
12. Avoid carrying too many instruments at the same time.
13. Avoid using water hydrant for electrical fires.
14. Avoid wearing any loose metallic rings, straps or bangles, as they are likely to prove
dangerous at times.
Raghu Institute of Technology, Dakamarri, Visakhapatnam vi

LIST OF EXPERIMENTS RECOMMENDED BY JNTU KAKINADA

Note: Any 10 of the following experiments are to be conducted:
1. Time Division Multiplexing.

2. Pulse Code Modulation.
3. Differential Pulse Code Modulation.
4. Delta Modulation.
5. Frequency Shift Keying.
6. Binary Phase Shift Keying.
7. Differential Phase Shift Keying.
8. Companding
9. Source Code-Encoder and Decoder
10. Linear Block Code-Encoder and Decoder
11. Binary Cyclic Code - Encoder and Decoder
12. Convolution Code - Encoder and Decoder
Raghu Institute of Technology, Dakamarri, Visakhapatnam vii

LIST OF SELECTED EXPERIMENTS FROM JNTUK RECOMMENDED
1. Time Division Multiplexing.

2. Pulse Code Modulation.
3. Differential Pulse Code Modulation.
4. Delta Modulation.
5. Frequency Shift Keying.
6. Binary Phase Shift Keying.
7. Differential Phase Shift Keying.
8. Companding
9. Source Code-Encoder and Decoder
10. Linear Block Code-Encoder and Decoder
11. Binary Cyclic Code - Encoder and Decoder
12. Convolution Code - Encoder and Decoder
LIST OF ADDITIONAL EXPERIMENTS DESIGNED
1. Adaptive Delta Modulation

2. Minimum Shift keying
Raghu Institute of Technology, Dakamarri, Visakhapatnam viii

CYCLE-WISE LIST OF EXPERIMENTS FINALISED

Cycle-1
Expt-1 Time Division Multiplexing.
Expt-2 Pulse Code Modulation.
Expt-3 Differential Pulse Code Modulation.
Expt-4 Delta Modulation.
Expt-5 Frequency Shift Keying.
Expt-6 Binary Phase Shift Keying.
Expt-7 Differential Phase Shift Keying.
Cycle-2
Expt-8 Companding
Expt-9 Image Compression Using Huffman Coding
Expt-10 Linear Block Code-Encoder and Decoder
Expt-11 Binary Cyclic Code - Encoder and Decoder
Expt-12 Convolution Code - Encoder and Decoder
Expt-13 Adaptive Delta Modulation
Expt-14 Minimum Shift keying
Raghu Institute of Technology, Dakamarri, Visakhapatnam ix

Department of Electronics & Communication Engineering DC LAB
EXPERIMENT:1
TIME DIVISION MULTIPLEXING
AIM:
1. Study of 4 channel analog Multiplexing and Demultiplexing technique.
2. Study of effect of sampling frequency variation on the output.
3. Study of input signal amplitude and variation of duty cycle on the output.
EQUIPMENT:
1. Time Division Multiplexing and Demultiplexing Trainer kit.

2. Oscilloscope-30MHz dual channel.
3. Patch chords.
4. Power supply.
THEORY:
The TDM is used for transmitting several analog message signals over a
communication channel by dividing the time frame into slots, one slot for each message signal.
The four input signals, all band limited by the input filters are sequentially sampled, the output of
which is a PAM waveform containing samples of the input signals periodically interlaced in
time. The samples from adjacent input message channels are separated by Ts/M, where M is
number of input channels. A set of M pulses consisting of one sample from each of the input M-
input channels is called a frame.
At the receiver the samples from individual channels are separated by carefully
synchronizing and is critical part of TDM. The samples from each channel are filtered to
reproduce the original message signal. There are two levels of synchronization. Frame
synchronization is necessary to establish when each group of samples begin and word
synchronization is necessary to properly separate samples within each frame. Besides the space
diversity & frequency diversity there is a method of sending multiple analog signals on a channel
using TIME DIVISION MULTIPLEXING & DEMULTIPLEXING technique.
Raghu Institute of Technology,Dakamarri,Visakhapatnam 1


CIRCUIT DESCRIPTION:
Function Generator:
A 4.096 MHz clock is used to derive the modulating signal, which is generated by an comprising
circuit a 4.096MHz crystal and three 74HC04 (U4) inverter gates. This 4.096MHz clock is then
divided down in frequency by a factor 4096, by binary counter 74HC4040(U3), to produce 50%
duty cycle, 64 KHz square wave on pin no.1 of U4,and 32 kHz square wave on pin no.4.32KHz
square wave is given to pin no.2 of IC NE555(U7) which act as a monostable multivibrator.
Potentiometer P5 adjust the pulse width.64KHz square wave is fed to the four bit binary
counter(U4 first half of 74HC393) on pin no.1 to produce 4KHz square wave at pin no.6. This
signal goes to pin no.13. This signal clocks to the second half of the counter to produce square
wave at following frequencies.
Counter output frequency
2QD 250Hz
2QC 500Hz
2QB 1KHz
2QA 2KHz
Each of these square wave outputs is then fed to its own low pass filter circuits
TL072 (U8,U9). Which generators corresponding sine wave outputs. The amplitude of this sine
wave can be varied by potentiometers P1,P2,P3,P4 respectively. These sine wave outputs are
available at TP1(250Hz),TP2(500Hz),TP3(1KHz),TP4(2KHz) respectively and have amplitudes
upto 10V max.( variable amplitudes)
Transmitter:
Each modulating signal is applied to IC TL074(U6) (pin nos. 3,5,10,12 respectively).

This IC buffers the applied signal and is fed to pin nos.3,14,11,6 respectively of IC DG211(U5).
The pulse input (32KHz(clock)) is applied to pin nos. 1,16,9,8 of U5. Corresponding PAM
outputs are available at test points TP5,TP6,TP7,TP8 respectively. These each PAM outputs are
applied to IC 4052(U1) which act as multiplexer.

4 Channel multiplexer:
CD4052 is a channel analog multiplexer which can accept analog signal in the range
from 0 to +/- 5V p-p. The channel selection is done by the signals A&B. these outputs are
available at TP10, TP11( 4 to1) decoder decodes these two signals and controls the switch
position. The common output (TDM analog output) is available at pin 13 of IC U1 and at TP9.
4 Channel demultiplexer:
The multiplexed PAM signal is given to the 4 channel Demultiplexer input at pin
3(TP12). The A&B timing wave forms selects the channel and accordingly connects the same to
the output. This at the PAM signal of each channel is separated. These separated demultiplexed
outputs are monitored at test points 13, 14, 15, 16 respectively.
Low pass filter:
Each separated PAM outputs are being connected to corresponding channels butter
th
worth Low Pass Filter. This is 4 order filter having roll of rate of 24 dB/octave(40dB/decade)
and cut-off frequency of 250Hz, 500Hz, 1KHz, 2KHz respectively. The output of these filters
goes to corresponding sockets termed as CH1, CH2, CH3, CH4. The reconstructed signal can be
monitored at test points 17, 18, 19, 20 respectively. These outputs are at lower amplitude.

MODEL GRAPHS:

PROCEDURE:
Multiplexing:
1. Connect the circuit as shown in diagram.

2. Switch ON the power supply.
3. Set the amplitude of each modulating signal as 5Vp-p.
4. Monitor the outputs at test points 5, 6, 7, 8. These are natural sampling PAM outputs.
5. Observe the outputs by varying the duty cycle pot(P5). The PAM outputs will varying
with 10% to 50% duty cycle.
6. Try varying the amplitude of modulating signal corresponding each channel by using
amplitude pots P1, P2, P3, P4. Observe the effect on all outputs.
7. Observe the TDM output at pin no. 13(at TP9) of 4052. All the multiplexer channels are
observed during the full period of the clock (1/32 KHz).
Demultiplexing & low pass filter:
1. Connect the circuit as shown in diagram.

2. Observe the demultiplexed outputs at test points 13, 14, 15, 16 respectively.
3. Observe the effect on the outputs by varying the duty cycle pot P5.
4. Observe the low pass filter outputs for each channel at test points 17, 18, 19, 20 and at
sockets channels CH1, CH2, CH3, CH4. These signals are true replica of the inputs.
These signals have lower amplitude.

OBSERVATIONS:
S NO Amplitude(Vp-p) Frequency Time Period

Message signals:
CH1
CH2
CH3
CH4
TDM signal
Demultiplexed signal
CH1
CH2
CH3
CH4
PRECAUTIONS:
1. Connect power supply with proper polarity.

2. Do not make any interconnections when power supply is ON.
RESULT:

VIVA QUESTIONS
1) What are the major types of multiplexing techniques?

2) What is the use of multiplexing?
3) What are the advantages of digital communication?
4) What are the disadvantages of digital communication?
5) What is the interference seen in TDM?
6) What is TDM?
7) What is the time space between successive samples from any input?
8) What is a frame?
9) What is the time spacing between two samples for a multiplexer with N channels.
10) What is signaling rate?
11) What is the minimum transmission bandwidth of TDM channel?
12) Is there need for transmitter and receiver to be synchronized?
13) What is crosstalk and how can it be reduced?
14) What is guard time?
15) What is the expression for guard time and where is it particularly important?

EXPERIMENT:2
PULSE CODE MODULATION
AIM:
To study 2-channel Time division multiplexing and sampling of analog signal, and its pulse code
modulation in none parity mode in the transmitter section and to study the demultiplexing and
the reconstruction of the analog signal in the receiver section
EQUIPMENT REQUIRED:
1. Pulse code modulation and demodulation trainer kit.

2. Connecting chords.
3. Power supply.
4.30 MHz Dual Storage Oscilloscope.
THEORY:
The sine waves (analog signal) of frequency 500Hz and 1 KHz and DC signal DC1 and DC2
whose amplitude can be varied accordingly are generated on board on DCL-03.these signals are
fed to the input of the sampling logic CH0 &CH1 and their samples are multiplexed by
interleaving them properly in their time slots.
The crystal oscillator generates a clock of 6.4 MHz from which all the transmitter data and
timing signals are derived for fast mode operation the transmitter clock is 240 KHz, and
sampling clock is 16KHz.for slow mode operation depending on jumper position the transmitter
clock is 1.23Hz or 0.6Hz and sampling clock is 0.088Hzor 0.044 i.e. the sampling rate per
channel is 11 or 22 seconds and serial data transmission rate is 813 milliseconds or 1.6 seconds.
The multiplexed data is pulse code modulated before transmission .At the receiver after the
pulse code modulation, the recovered multiplexed data is sent to de-multiplexing logic .The two
demultiplexed samples are fed to reconstruction unit .which consists of 4th order low pass butter-
worth filter, where frequency components are filtered out to recover the original base band signal
at the receiver output CH0and CH1.


CIRCUIT DESCRIPTION
Function generator
Transmitter timing logic two different frequencies say 16 KHz &8 KHz are taken. This signal is
fed to parallel shift register U25,U27(IC 74HC164),which generates the sine wave ,by serial shift
operations .The serial to parallel shift register (IC74HC164) has resistive ladder network at the
output. For 16 shifts of the register, one stair case sine wave is produced .So if a 16 KHz clock is
fed to the shift register, 1KHz sine wave is generated and similarly 500Hz sine waveform with
amplitude variable form 0-5volts.Two amplitude variable DC levels are also generated which are
used as analog information signals for both FAST and SLOW mode operations.
Clock generator
This block consists of crystal Oscillator, which generates a 6.4 MHz clock, from IC 74LS04 and
supplied to U2(IClS390) decade counter from which all the transmitter data and timing signals
are derived.
Transmitter timing logic
This logic generates the various timing signals for the transmitter two synchronized amplitude
variable sine waves are generated which are used as analog information signals for fast mode
operations. The 6,4MHz crystal oscillators generate a 7.4Mhz clock .It is divided by 2-decade
counter U2(IC74LS30)and ripple counter U3(IC 74LS393) to get the 32KHz,16KHZ,8KHzand
4KHz frequencies. This logic also generates 240 KHz transmitter clock with the help of two
input mux U6(IC74LS157) and JK flip-flop U11(IC74LS74)16KHz sampling clock for FAST
mode operations ,and 1.23Hz&0.6Hz Transmitter clock and 0.088hz& 0.044Hz sampling clock
for SLOW mode operations. A frame sync signal is also generated By U3,U10 and U11 this
logic for synchronization purposes


Sample and hold logic
This logic samples the two information signals from the signals from the two analog input, using
(IC4016)U30.
Multiplexer logic
Two signals available at CH0 IN &CH1IN are multiplexed their samples by interleaving them
properly in their assigned time slots controlled by timing signals TM1and TM-2 generated from
U9(IC74LS74).The capacitor is provided at the output of the third buffer to provide a sample and
hold mode to U30,which is a sampling switch CD4016.
Analog to digital converter
The analog to digital converter converts the analog samples to digital bits. This device performs
both quantizing and encoding operations. The analog to digital converter IC, AD673 forms the
heart of this logic .AD673 is used for the analog to digital conversion of the multiplexed data.
The timing of the A/D conversion is controlled by the convert pulse, which is generated in the
transmitter timing logics. As soon as the data is ready, the AD673 gives a data ready (DR Active
low) output. The data latch is used for latching the valid outputs A/D converter. The timing and
latching interval of data latch is controlled by the latch enable signal U22 (74HCT374).Each
sample is coded to a 7 bit data by the AD673.
Quantising And Encoding
The signal level of the input signal assumed to vary from 0volts to 4.96 volts. The entire level is
dividing to 128 uniform steps .Each step corresponds to 4.96V/128=40mV
The quantizing level is chosen to be midway of steps .If the signal level falls below the
quantizing level, and then the signal is rounded off to lower level. If signal level falls above the
quantizing level, and then, the signal is rounded off to the upper level. This type of quantizing is
called uniform quantizing, where the step levels are uniform. Then the corresponding to the
level chosen, code words are assigned to the samples. The code words vary from 0000000 to
1111111 for the 0 to 4.96V.Thus analog to digital converter assigns the code words for all the
samples

PROCEDURE:
1) Connect power supply in proper polarity to the kits DCL-03and DCL-04 and switch it on.
2) Connect sine wave of frequency 500Hz and 1KHz to the input CH0 and CH1 of the sample
and hold logic
3) Connect OUT0 to CH0 IN &CH IN.
4) Set the speed selection switch SW1to FAST mode.
5) Select parity selection switch to NONE mode on both the kit DCL-03 and DCL-04 as shown
in switch setting diagram.
6) Connect TXDATA, TXCLK and TXSYNC of the transmitter section DCL -03 to the
corresponding RX DATA,RXCLK and RXSYNC of the receiver section DCL-04.
7) Connect DACOUT to IN post of demultiplexer section in DCL-04.
8) Ensure that FAULT SWITCH SF1 as shown in switch setting diagram introduces no fault.
9) Take the observations as mentioned below.
10) Repeat the above experiment with DC signal at the inputs of the channel CH0 andCH1
11) Connect the ground points of both the kits with the help of connecting chord provided
during all experiments
OBSERVATIONS:
SNO Amplitude Frequency Time Period

Modulating output
Sampler output
D/A converter output
Demodulation output
PRECAUTIONS
1) Connect the power supply with proper polarity.
2) Do not make any interconnections when the power supply is on.
3) Keep all the switch faults in off position.
RESULT:

VIVA QUESTIONS
1) What are the advantages of digital representation of analog signals?
2) What is the length of the code word?
3) What is quantization?
4) What is pulse code modulation?
5) What is the purpose of low pass filter in PCM?
6) What is the nature of output of sample and hold circuit?
7) What is quantization error?
8) What is the maximum quantization error?
9) What is uniform quantization?
10) What is nonuniform quantization?
11) What is signaling rate?
12) What is the bandwidth needed for PCM transmission?
13) What circuits form A/D converter in PCM?
14) How can the quantization error be reduced?
15) What is the effect of increasing the no of bits per sample in PCM?
16) What is the process in PCM receiver?
17) Is it possible to reconstruct the original signal?
18) What are the disadvantages of PCM?
19) What is the probability of error?

EXPERIMENT-3
DIFFERENTIAL PULSE CODE MODULATION
AIM:
To Study differential pulse code modulation & demodulation technique.
EQUIPMENT REQUIRED:
1. Differential pulse code modulation trainer kit (FALCON ADCL-07)
2. Connecting chords.
3. Power supply.
4.20MHz Dual Trace Oscilloscope
THEORY:
DPCM is a good way to reduce the bit rate for voice transmission .However it causes some
other problems that deals with voice quality .DPCM quantizes and encodes the difference
between a previous sample input signal and a sample input signal .DPCM quantizes the
difference signal using uniform quantization. uniform quantization generates an SNR that is
small for small input sample signals and large for large input sample signals .Therefore, the
voice quality is better at higher signals.
DPCM MODULATOR
Clock Generator
The crystal oscillator generates a 2.048MHz clock.1.024MHz clock is generated by dividing
the 2.048MHz clock. 512KHz,256KHz,128KHz and 64KHz clocks are generated using
U(74HCT393) a 4-bit binary counter.
Timing Logic
This logic generates the various timing signals for the transmitter. The operation of ADC673 is
controlled by two inputs: CONVERT and/DATA ENABLE. The transmited clock is fed to a 4-
bit binary counter(IC74LS393) whose output is ANDED using(IC74HC08). A pulse(plrst) is
generated which is further fed to D flipflop to generate the CONVERT pulse and the /DATA
ENABLE signal.


Sine Wave Generator

8 KHz frequency is fed to serial to parallel shift register (IC74HC164) which generates the
sine wave, by serial shift operations. The serial to parallel shift register (IC74HC164) has
resistive ladder network at the output. For 8 shifts of register, one staircase sine wave is
generated. So if 8KHz clock is fed to the shift register,500Hz sine wave is generated with
amplitude variable from 0 to 4Vpp.
Sample and Hold Logic
This logic samples the information signal with the clock frequency of 16KHz,(IC4016) is used
for sampling. It is a quad bilateral switch intended for the transmission or multiplexing of
analog or digital signals.
Analog to Digital Converter
The analog to digital converter converts the analog samples to digital bits. This device performs
both the quantizing and encoding operations. The analog to digital converter IC,AD673 forms
the heart of this logic. The timing of the A/D conversion is controlled by the convert pulse,
which is generated in the timing logics. As soon as the data is ready, the AD673 gives a data
ready(DR active low) output.The data latch is used for latching the valid outputs of the A/D
converter. The timing and latching interval of the data latch is controlled by the latch enable
signal(74HCT374). Each sample is coded to a 8 bit data by AD673. These coded data is fed to
a parallel to serial shift register, which gives a serial 8-bit quantized data.
Quantising
The signal level of the input signal assumed to vary from 0 volt to 4.96 volts. The entire level is
dividing to 126 uniform steps. Each step corresponds to 4.96/128=40mv
The quantizing level is chosen to be the midway of the steps. If the signal level falls below the
quantizing level, and then the signal level is rounded off to the upper level. This type of quantizing is
called uniform quantizing, where the step levels are uniform. Then corresponding to the level
choosen, code words are assigned to the samples. The code words vary from 0000000 to 1111111 for
the 0 to 4.96V. Thus the analog to digital converter assigns the code

MODEL WAVEFORMS:

Linear Predictor
D flip-flops (74HCT74) are used as delay elements to give two bit delays in the quantized data.
The two delayed datas are ORED using (IC74HC32).The ORED data is fed to the integrator
circuit, which is built around(ICTL084)
Comparator
The comparator circuit is built around (ICLM311). This circuit compares the two inputs and the
differenced output is fed to the quantizer.
DPCM DEMODULATOR
Linear Predictor
D flip-flops(74HCT74) are used as delay elements to give two bit delays.The received data and
the delayed is ORED using(74HC32).The delay element is placed in feedback loop with the OR
circuit.
Integrator
The integrator is built around (ICTL084). Integrator output is the integration of the input signal
applied.
Butterworth Filter
The butterworth low pass filter is built around (ICTL084),which filters out the sampling
frequency components from the demodulation out
PROCEDURE:
1. Connect the circuit as per the block diagram and switch settings.
2. Connect power supply in proper polarity to the kit ADCL-07 and switch it ON.
3. Keep the clock frequency at 512KHz, by changing the jumper position of JP1 in the clock
generator section.
4. Keep the amplitude of the onboard sine wave, of frequency 500Hz to 1Vpp.
DPCM modulation:
5. Connect the 500Hz sine wave to the IN post of analog buffer.
6. Connect OUT post of analog buffer to IN post of DPCM modulator section.
7. Observe the sample output at the given test point. The input signal is sampled at clock
frequency of 16KHz.
8. Observe the linear predicted output at the PREDICTED OUT post of the linear predictor in
the DPCM modulator section.

9. Observe the differential pulse code modulated data (DPCM) at the DPCM OUT post of
DPCM modulator section.
10. Observe the DPCM data at DPCM OUT post by varying input signal from 0 to 2 volts
DPCM demodulation:
11. Connect the DPCM modulated data from the DPCM OUT post of the DPCm modulator to
the IN post of the DPCM demodulator.
12. Observe the demodulated data at the output of summation block.
13. Observe the integrated demodulated data at the DEMOD OUT post of the DPCM
demodulator.
14. Connect the demodulated data from the DEMOD OUT post of the DPCM demodulator to the
IN post of low-pass filter.
15. Observe the reconstructed signal at the OUT post of the filter .use RST switch for clear
observation of the output.
16. Now, simultaneously reduce the clock frequencies from 512KHz to 256KHz,and 128KHz by
changing the jumper position of JP1 and observe the difference in the DPCM modulated and
demodulated data. As the frequency of clock decreases, DPCM demodulated data at DEMOD
OUT becomes distorted.
17. Observe various waveforms for different frequencies.
OBSERVATIONS:
DPCM->At 64 KHZ
Parameter DATA Sinusoidal Predicted DPCM Summation Demodulated Filter

CLK output output output output output output
Time
Frequency
Vpp
V amp

PRECAUTIONS:
3) Keep all the switch faults in of position.
RESULT:

VIVA QUESTIONS
1) What is DPCM?
2) What is the principle of working of DPCM?
3) How do you reduce the no of bits transmitted in DPCM?
4) What is the BW requirement compared to DPCM?
5) Does feedback exist?
6) What are the no of bits transmitted?
7) Are the levels fixed or variable?

EXPERIMENT:4
DELTA MODULATION
AIM :
To Study delta modulation and demodulation technique.
EQUIPMENT REQUIRED:
1. Delta modulation and demodulation trainer kit. (DCL-07)
2. Connection chords
3. Power supply
4. 50MHz Digital Storage oscilloscope
THEORY:
Delta Modulation
Delta modulation is the differential pulse code modulation scheme in which the difference signal
is encoded into just a single bit. In digital modulation system ,the analog signal is sampled and
digitally coded. This code represents the sampled amplitude of the analog signal. The digital
signal is sent to the receiver through any channel in serial form. At the receiver the digital signal
is decoded and filtered to get reconstructed analog signal. Sufficient number of samples is
required to allow the analog signal to be reconstructed accurately. Delta modulation is a process
of converting analog signal into one bit code, means only one bit is sent per sample. This bit
indicates whether the signal is larger or smaller than the previous samples. The advantage of
DM is that the modulator and demodulator circuits are much simpler than those used in
traditional PCM.
Delta modulation is an encoding process where the logic levels of the transmitted pulses indicate
whether the decoded output should rise or fall at each pulse. This is a true digital encoding
process as compare to PAM,PWM and PPM.
If signal amplitude has increased in DM then modulated output is a logic level 1. If the signal
amplitude has decreased the modulator output is logic level 0. Thus the output from the
modulator is a series of zeroes and the ones to indicate rise or fall of the waveform from the
previous value.


The block diagram of Delta Modulator illustrates the components at the transmitter end. It
consists of Digital Sampler and the Integrator at the feedback path of Digital sampler . Let
assume that the base band signal a(t) and its quantized approximation i(t) are applied as inputs to
the comparator. A comparator as its name suggests simply makes a comparison between inputs.
The comparator has one fixed output c(t) when a(t) >i(t) and the different output when a(t)<i(t)
the comparator output is then latched in to a D-flip/flop which is clocked by the selected
transmitted clock. Thus the output of D-flip/flop is latched 1 or 0 clocked by the selected
transmitted clock. Thus the output of D-flip/flop is latched 1 or 0 synchronous with the clock
edge. This binary data stream is transmitted to the receiver and is also fed to the input of the
integrator. This integrator output is then connected to the negative terminal of voltage
comparator, thus completing the modulator circuit.
Delta Demodulator
The Delta Demodulator consists of a D-flip/flop, followed by an integrator and a 2nd and
4th order low pass buttonworh filter. The Delta Demodulator receives the data stream from
D-flip/flop of Delta Demodulator. It latches this data at every rising edge of the receiver
clock. This data stream is then fed to integrator ; its output tries to follow the analog signal
in ramp fashion and hence is a good approximation of the signal itself. The integrator output
contains sharp edges, which is smoothened out by the 2nd order, and 4th order low pass
Butterworth filter whose cut-off frequency is just above the audio band.
The practical use of Delta Modulation is limited due to following drawbacks:
1) NOISE: A noise is defined, as any unwanted random waveform accompanying the
information signal. When the signal is received at the receiver irrespective of any channel it
is always accompanied by noise.
2) DISTORTION: Distortion means that the receiver output is not the true copy of the analog
signal at the transmitter. In Delta modulation, when the analog signal is greater than the integrator
output the integrator ramps up to meet the analog signal. The ramping rate of integrator is
constant. Therefore if the rate of change of analog input is faster than the ramping rate, the
modulator is unable to catch up with the input signal. This cause a large disparity between the
information signal and it's quantized approximation. This error phenomenon is

known as slope over loading and causes the loss of rapidly changing information. The slope
overloading waveform is as shown in the figure. The problem of slope overload can be solved by
increasing the ramping rate of the integrator. But as it can be seen from the figure the effect of
the large step size is to add large sharp edges at the integrator output and hence it adds no noise.
3) Another problem of Delta modulation is that it is unable to pass DC information.
This is not a serious limitation oif speech communication.
Clock Generator
This section provides five different sampling frequencies. All these frequencies are generated
from main clock of 2.048MHz crystal. The 2.048MHz crystal oscillator generates a 2.048MHz
clock. It is divided by 2 ripple counters U2(74LS393) to get five different sampling frequencies
of 8KHz, 16KHz, 32KHz, 64KHz, and 128KHz. The different clocks for sampling in
modulation techniques can be selected with the help of U3 (GAL 16V8-25LC), driving circuit
for the U3 is setup by U5(74LS393) and U4(74LS74 - D flip flop ) through switch S1. LED
indications are provided for each selected sampling frequency using U3(GAL 16V8-25LC).
Sine wave generation
This section basically provides four amplitude variable ( 0-4 Vpp) synchronized sine waves each
of 250Hz, 500Hz, 1KHz and 2KHz. The 32KHz, 16KHz, 8KHz and 4KHz frequencies are fed to
serial to parallel shift register (74LS164), which generates the stare case sine wave, by serial
shift operation. The serial to parallel shift register has a resistive ladder network at the output.
For 16 shifts of the register, one stare case sine wave is produced. So if a 16Hz clock is fed to the
shift register, 1KHz stare case sine wave is generated. Thus by using the 32KHz, 16KHz, 8KHz
and 4KHz, stare case sine wave of 2KHz, 1KHz, 500Hz and 250Hz are generated respectively by
U10, U9, U8, U7. The active filter at output (LM324) suppresses the ripple and also takes care of
the impedance matching. After filtering we will get smooth sine waves. Amplitude of the signal
is varied using respective potentiometers.
DC Generator
In this section Zener diode D7 (5V1) will regulate VCC to 5 volts. Amplitude varied by
using potentiometer P5.
Input Buffer
This is a non-inverting unity gain amplifier built around U12(LM324).


Digital Sampler
Digital sampler consists of two stages. First stage is of different amplifier U13(LM311) and
second stage is D flip-flop U14(4013). Differential amplifier gives output by comparing voltage
levels at input terminals. Output is equal to signal IN2 subtracted from signal IN1. D flip flop
sends this output at every rising edge of the clock applied to it.
Integrator-1
Integrator is built around U15(IC LF353). Integrator output is integration of the input
signal applied.
Integrator-2
Integrator is built around U16 (IC LF353). Integrator output is integration of the input
signal applied. In this integrator switch S3 is provided to select low or high time constant
for integration operation. Pot P6 is provided to control the gain of integrator.
Delta or Sigma Delta Selection
Switch S2 is provided for selection. In case of Delta modulation signal is bypassed through
capacitor, DC signal is blocked. In case of Sigma Delta modulation DC signal is also send
to integrator inputs.
Integrator-3
for integration operation.
Demodulator
Demodulator is simple D flip-flop using U14 (4013). Output is available at rising edge of clock
applied to it.
2nd Order Butterworth Filter
2th order Buffer worth Low Pass Filter is built around U23(IC LM324), which filters out the
sampling frequency components from the Demodulation output of each modulation techniques
and recovers the originals signals.


4th Order Butterworth Filter

sampling frequency components from the Demodulation output of each modulation
techniques and recovers the originals signals.
PROCEDURE:
1) Connect the circuit as per the block diagram.
2) Connect the power supply with the proper polarity to the Kit DCL -07 and switch it ON.
3) Select sine waves input 250Hz of 0V through pot P1 and connect post 250Hz to post IN
of input buffer.
4) Connect output of buffer post OUT to digital sampler input post IN1.
5) Then select clock rate of 8 KHz by pressing switch S1 selected clock is indicated by
LED glow.
6)Keep switch S2 in delta position.
7) Connect output of digital sampler post OUT to input post IN of integrator 1.
8) Connect output of integrator 1 post OUT to input post IN2 of digital sampler.
9) Then observe the Delta modulated output at output of digital sampler post OUT and
compare it with the clock rate selected. It is half the frequency of clock rate selected.
10) Observe the integrator output test point . It can be observed that as the clock rate is
increased amplitude of triangular waveform decreases. This is called minimum step size. These
waveforms are as shown. Then increase the amplitude of 250Hz sine wave up to 0.5V. Signal
approximating 250Hz is available at the integrator output resulting from delta modulation.
11) Then go on increasing the amplitude of selected signal through the respective pot from 0
to 2V. It can be observed that the digital high makes the integrator output to go downwards.
Observe that the integrator output follow the input signal. The waveforms are as shown in the
figure. Observe the waveforms at various test-points in the Delta modulator section.
12) Increase the amplitude of 250Hz sine wave through pot P1 further high and observe that the
integrator output cannot follow the input signal. State the reason.
13) Repeat the above mentioned procedures with different signal sources and selecting
the different clock rates and observe the response of Delta Modulator.
14) Connect Delta modulated output post OUT of digital sampler to the input of Delta

Demodulator section post IN of Demodulator.

15) Connect output of Demodulator post OUT to the input of integrator 3 posy IN.
16)Connect output of Integrator 3 post OUT to the input of output buffer post
IN.17)Connect output of buffer post OUT to the input of 2nd order filter post IN.
17)Connect output of 2nd order filter post OUT to the input of 4th order filter post
IN. 18)Keep Switch S4 in HIGH position.
19)Then observe various tests points in Delta Demodulator section and observethe
reconstructed through 2nd order filter and 4th order filter. Observe the waveforms.
OBSERVATIONS
Signal Amplitude Frequency Timeperiod
Sine wave
Clock Signal
Integrator-1
Digital sample
Integrator -3
LPF
PRECAUTIONS:

RESULT:

VIVA QUESTIONS
1) What is delta modulation?

2) What are the advantages of DM?
3) Why is it called linear DM?
4) What is disadvantage of DM?
5) What is slope over load noise?
6 )How do you reduce slope over load noise?
7) Why do slope over load noise arise?
8) When does granular noise occur? What is granular noise?
10) What happens when the input signal to DM is almost flat?
11) How do you reduce the granular noise?

EXPERIMENT NO:5
FREQUENCY SHIFT KEYING
AIM:-
1. To generate FSK Modulation,
2. To Demodulate the FSK signals.
EQUIPMENT REQUIRED:-
1. FSK Modulation & Demodulation trainer kit.
2. 30 MHz dual channel storage oscilloscope.
3. Patch cords.
THEORY:-
Binary FSK is a form of constant-amplitude angle modulation and the modulating
signal is a binary pulse stream that varies between two discrete voltage levels
but not continuous changing analog signal. In FSK, the carrier amplitude(Vc) remains
constant with modulation and the carrier radian frequency(Wc) shifts by an amount equal
to w/2. The frequency shift (w/2) is proportional to the amplitude and polarity of the
input binary signal. For example, a binary 1 could be +1 volt and a binary zero could be
-1 volt producing frequency shifts of +w/2 and -w/2 respectively. The rate at which the
carrier frequency shifts is equal to the rate of change of the binary input signal V m(t)(that is
the input bit rate). Thus the output carrier frequency deviates(shifts) between Wc+w/2 and
Wc -w/2 at the rate equal to fm.

Data Formatting:-
A modulation code is defined as a rule by which a serial train of binary data (comprising
ones and zeroes) is converted to a signal suitable for transmission.
Non-return to zero(NRZ):-
This is a level type code and is one that is widely used in serial data transmission . A `0` is
low level and a `1` is a high level.
CIRCUIT DESCRIPTION:-
Data Clock Generator:-
The Bit clock Generator is designed around the IC 555(U1) operated in Astable
mode. The 100K preset P1 in conjunction with 0.0047f capacitor in the timing circuit


facilitates the frequency to be set and at any chosen value from 300Hz to 1KHz. This
output is available at TP1.
Data Selection:-
The 8 Bit parallel Load Serial shift IC 74165(U2) is used to generate the
required word pattern. A DIP switch (DATA SELECTION) is used to set ONE & ZERO
pattern. The Bit Pattern set by the switch is parallely loaded by controlling the logic level
at pin 1(DATA ON-OFF).The last stage output Q7 is coupled to the first stage input D0
in the Shift Register. The Serial Shift Clock is given at Pin 2. The 8 bit data set by the
switch and loaded with the register parallely is now shifted serially

right(Q0 Q1,Q1 Q2) and circulated repetitively. Thus the 8 Bit Word pattern is
generated cyclically which is used as modulating signal in the FSK modulator. It is
available at TP12.
NRZ(L) Output:-
The Q output(pin 2) of Flip-Flop IC U3(74HC 175) is applied to the data
input ID pin 2 of flip flop IC U5(74HC74 dual D type flip flop). This flip flop clocked at
its clock input 1 CLK IC U5 pin 3 by the original DATA CLOCK signal. The device
which is positive edge triggered gives the NRZ(L) output at its 1 Q output Pin 5(TP 2) .
The generation of the NRZ(L) signal is shown in Timing Diagram each bit represented
by the NRZ(L) waveform is delayed by one half cycle of the DATA CLOCK signal,
with respect to the data selection at TP 12.The output shown at TP 2.
FSK MODULATION:-
The XR-2206 can be operated with two separate timing resistors, R24 and R25,
connected to the timing pin 7&8, respectively. Depending on the polarity of the logic signal at
Pin 9, either one or the other of these timing resistors is activated. If pin 9 is open circuited or
connected to a bias voltage 2V, only R24 is activated. Similarly, if the voltage level at Pin 9 is
1V, only R25 is activated. Thus, the output frequency can be keyed between two levels, F1 and
F2. F1 = 1/R24C9 and F2 = 1/R25C9. In our circuit R24=3.9k, R25= 6.8k, C9=100nF.For split-
supply operation, the keying voltage at pin 9 is referenced to V. The FSK output can be
monitored at TP 8.

MODEL WAVEFORMS:

DEMODULATION:-
Square Wave Converter:-
The incoming FSK modulated signal can be monitored at TP9. This signal is
then attenuated by resistor network R43,R44 then AC coupled via capacitor C12 to remove
any dc component in the signal. The signal is connected to SIGN Input (pin 14) of the U12
(74HC 4046 Phase comparator). The signal is first squared up by an inbuilt comparator and
is connected to one of the input of a chip 2 Input EX-OR gate. The other 5 input of the
gate is connected to the COMPIN Input (pin 3) of IC U12.The output is monitored at
TP10.
PLL Detector:-
A very useful application of the 565 PLL is as a FSK demodulator. In the 565
PLL the frequency shift is usually accomplished by driving a VCO with the binary data
signal so that the two resulting frequencies correspond to the logic 0 and logic 1states of
the binary data signal. The frequencies corresponding to logic 1 and logic 0 states are called the
mark and space frequencies.
Capacitive coupling is used at the input to remove a dc level. As the signal
appears at the input of the 565 , the loop locks to the input frequency and tracks it
between the two frequencies with a corresponding dc shift at the output. Preset P2 and
capacitor C15 determine the free-running frequency of the VCO.A three-stage RC ladder(low-
pass) filter is used to remove the carrier component from the output. The high cut off
frequency ( fH = 1/2RC ) of the ladder filter is chosen to be approximately halfway between
the maximum keying rate and twice the input frequency. This output signal can be made logic
compatible by connecting voltage comparator (U11)(LM 311) between the output of ladder
filter and pin 6 of PLL (LM 565)(U16).
Phase Adjustment Circuit:-
U17 , U18 (NE 555) used as Phase Adjustment Circuit. The output of voltage
comparator (pin 7 of U11) is fed to pin 2 of U17 which is connected as monostable mode.
And the output of U17(pin 3) is again fed to U18(pin 2).The output is available at pin 3 of
U18 and can be monitored at TP11.This is serial data of output.
Raghu Institute of 38
Technology,Dakamarri,Visakhapatnam
PROCEDURE:-
Modulation:-
1. Switch ON the power supply.
2. Set the Data selection switch (`DATA SELECTION`) to the desired code(say
11001100)
3. Set the switch (DATA ON-OFF) ON position. Observe the 8 Bit Word pattern at TP 12.
4. Observe the Data Clock at TP1 and also observe the NRZ (L) at TP2.
5. Connect the patch cord as per block diagram. Observe the corresponding FSK output at
(when Data is logic `1`,the frequency is high and Data is logic `0` the frequency is
low)TP8.
6. Now change the Data selection and repeat the above steps 3 to 6 and observe the
corresponding FSK outputs.
7. Connect the patch cord as per block diagram. Observe the corresponding FSK output at
(when Data is logic `1`,the frequency is high and Data is logic `0` the frequency is
low)TP8.
8. Now change the Data selection and repeat the above steps 3 to 6 and observe the
corresponding FSK outputs.
Demodulation:-
1. Connect the circuit according to the circuit diagram.
2. The incoming FSK input is observed at TP 9.
3. The output of `Square wave converter` is available at TP 10. The serial Data output is
available at TP11.
4. Repeat the above steps 1,2,3 for other serial data inputs and observe the corresponding
serial data outputs. These outputs are true replica of the original inputs.

OBSERVATIONS:-
Signal Amplitude Frequency
Data Clock
NRZ Data
Carrier signal
Modulated output
Demodulated Data
PRECAUTIONS:-
1. Do not make any inter connections on the board while the power supply is ON.
2. Whenever the input data is changed, Switch OFF and ON the Data Select switch.
3. Connect the power supply with proper polarity.
RESULT:-

VIVA QUESTIONS
1) What is BFSK?
2) What is the bandwidth required?
3) What are the advantages of BFSK?
4) What are the disadvantages of BFSK?
5) What is the symbol duration?
6) What is the bandwidth of Mary FSK?
7) What is the probability of error of FSK?
8) What is the method of detection?

EXPERIMENT 6
BINARY PHASE SHIFT KEYING
AIM :
To Study of Carrier Modulation & Demodulation Techniques by binary phase shift

keying method.
EQUIPMENT REQUIRED :
1. BPSK Modulation & Demodulation Trainer kit ADCL-01.
2. Connecting Chords.
3. Power supply.
4. 20MHz Digital Storage Oscilloscope.
THEORY :
In Binary Phase Shift keying (BPSK) modulation technique, the modulated output switches
between in-phase and out-of phase component of the carrier for every one to zero
transitions of modulating signal. The carrier frequency chosen for BPSK modulation are 500
KHz (0 Degree) and 500KHz (180 Degree).
CARRIER GENERATOR block on ADCL-01 generates the carrier waves 500 KHz (0 Degree )
and 500 KHz (180 Degree), which are available at SIN 1 and 2 posts. The BPSK modulator is
also built around the 2 to 1 Analog Multiplexer, which switches between the 500 KHz (0
Degree) and 500 KHz (180 Degree) signals for all one to zero transitions occurring in
the transmitted data stream.
The phase detector works in the prnciple of squaring loops. First step in BPSK detection is the
sine to square wave conversion using a Schmitt trigger. This enables the BPSK detector to be
built around digital ICs. The Bi-phase splitter basically doubles the frequency component of
the modulated data and also ensures that the out of phase compnent of the modulation signal
does not reach the PLL. The PLL recovers the carrier frequency from the output of the phase
splitter, but the frequency of the recovered carrier is twice that of the transmitted carrier.So a
Divide by 2 counters is used to divide the frequency of the PLL output by 2, thus recovering the
reference carrier. The delay flip-flop is used to compare the phase of the incoming data and the
reference carrier thereby recovering the data.


CIRCUIT DESCRIPTION
Clock And Data Generator
This block generates data of a variable pattern depending on positions of eight bit switch SW1
also Reference clock of frequency 250 KHz (CLOCK) is generated . The crystal oscillator
generates a 2MHz clock ,from which a 250 KHz clock is recovered by using U4 (74HCT393) 4-
bit binary counter. For data generation output of SW1 is given to Parallel to serial shift register
U6(IC 74LS165).Output of shift register is taken as reference data .This reference data then
given to NRZ-L coder to generate the NRZ-L data,which is then used as basic modulating
signal for all modulation techniques.
Carrier Generator
The SIN 1 (500 KHz 0 deg.) signal is generated from U4 (74HCT393). The signal shaper
circuits and LC filters components are used to get a pure sine wave .SIN 2 (500 KHz 180
deg),which is 180 deg out of phase with SIN 1 obtained by feeding SIN 1 to inverting buffering
U3 (IC TL084) .
Carrier Modulation
The carrier modulator section consists of U17 (IC 4053) which is a dual channel analog
Multiplexer. At the output of the modulator analog buffer U3(TL084) is connected to avoid
loading.To obtain BPSK signal, SIN Carriers 1 and 2 are fed to inputs of modulator i/p 1 and
i/p2. Connect NRZ-L data to the control input C1 of the modulator.
The BPSK Modulated signal will get at the output of U3.
BPSK Demodulation Section
The PHASE DETECTION SECTION works on the principle of squaring loops. First step in
BPSK detection is the sine to square wave conversion using a Schmitt trigger U8 (IC 74HCT14).
This enables the BPSK detector to be built around digital Ics. The biphase splitter
basically doubles the frequency component of the modulated date and also ensures that the out
of phase component of the modulate signal does not reach the PLL. This is achieved by using
U11 (IC74LS123). The PLL recovers the carrier frequency from the output of the phase splitter,

MODEL GRAPHS:


but the frequency of the recovered carrier is twice that the of the transmitted carier. So a D flip-
flop is used as a divide by 2 counters to divide the frequency of the PLL output by 2, thus
recovering the reference carrier. The D flip-flop is used to compare the phase of the incoming
data and the reference carrier thereby recovering the data.
PROCEDURE:
1) Connect the circuit as per the block diagram and switch settings .
2) Connect power supply in proper polarity to the kit ADCL-01 and switch it on.
3) Select Data pattern of simulated data using switch SW1.
4) Connect SDATA generated to DATA IN of NRZ-L CODER .
5) Connect the NRZ-L DATA ouput to the control input C1 of the Carrier Modulator logic.
6) Connect carrier component SIN1 to IN 1 and SIN 2 to IN 2 of the Carrier Modulator logic.
7) Connect BPSK modulated signal MOD OUT on ADCL -01 to the MOD IN of the
BPSK DEMODULATOR.
8) Observe the BPSK DEMODULATED data at the output of the BPSK DEMODULATOR
at b(t) OUT.
9) Observe output waveforms at various output terminals.Use RESET switch for clear
observation of data output, if recovered data mismatches with respect to transmitter data.
OBSERVATIONS:
Signal Amplitude Frequency Time Period

Carrier signal
Data input
Modulated output
Demodulated output
PRECAUTIONS:-
1) Do not make any inter connections on the board while the power supply is ON.
2) Whenever the input data is changed, Switch OFF and ON the Data Select switch.
RESULT:

VIVA QUESTIONS
1)What are distortions in PSK?
2) What is the bandwidth required?
3) What is coherent (synchronous) detection?
4) What is noncoherent detection and what is its advantage?
5) What are the requirements that any digital modulation scheme should satisfy?
6) What is the probability of error of BPSK?
7) What is interchannel interference in BPSK?
8) What is intersymbol interference?
9) How is intersymbol interference reduced?

EXPERIMENT:7
DIFFERNETIAL PHASE SHIFT KEYING
AIM :
To Study of Carrier Modulation & Demodulation Techniques by Differential phase
shift keying (DPSK) method.
EQUIPMENT REQUIRED :
1. DPSK Trainer kit ADCL-01
2. Connecting Chords
3. Power supply
4. 20MHz Digital Storage Oscilloscope
THEORY :
In BPSK communication system, the demodulation is made by comparing the instant phase of
the BPSK signal to an absolute reference phase locally generated in the receiver. The modulation
is called in this case BPSK absolute .The greatest difficulty of these systems lies in the need to
keep the phase of the regenerated carrier always constant. This problem is solved with the PSK
differential modulation, as the information is not contained in the absolute phase of the
modulated carrier but in the phase difference between two next modulation intervals.
The block diagram shows DPSK modulation and demodulation system .The coding is obtained
by comparing the output of an EX-OR ,delay of a bit interval ,with the current data bits.As total
result of operation , the DPSK signal across the output of the modulator contains 180 deg.phase
variation at each data bit 1 .The demodulation is made by a normal BPSK demodulator,
followed by a decision device supplying a bit 1 each time there is a variation of the logic level
across its input.
The DPSK system has a clear advantage over the BPSK system in that the former avoids the
need for complicated circuitry used to gemerate a local carrier at the receiver .To see the relative
disadvantage of DPSK in comparison with PSK ,consider that during some bit interval the
received signal is so contaminated by noise that in a PSK system an error would be made in the
determination of whether the transmitted bit was a 1 or 0. In DPSKa bit determination is made


on the basis of the signal received in two successive bit intervals .Hence noise in one bit interval
may cause errors to two-bit matter of fact , there is a tendencyfor bit errors to occurs in pairs .It is
not inevitable however that error occur in pairs. Single errors are still possible.
CIRCUIT DESCRIPTION
Clock And Data Generator
This block generates data of a variable pattern depending on positions of eight bit switch SW1
also Reference clock of frequency 250 KHz (CLOCK) is generated . The crystal oscillator
generates a 2MHz clock ,from which a 250 KHz clock is recovered by using U4 (74HCT393) 4-
bit binary counter. For data generation output of SW1 is given to Parallel to serial shift register
U6(IC 74LS165).Output of shift register is taken as reference data .This reference data then
given to NRZ-L coder to generate the NRZ-L data,which is then used as basic modulating
signal for all modulation techniques.
Carrier Generator
The SIN 1 (500 KHz 0 deg.) signal is generated from U4 (74HCT393). The signal shaper
circuits and LC filters components are used to get a pure sine wave .SIN 2 (500 KHz 180
deg),which is 180 deg out of phase with SIN 1 obtained by feeding SIN 1 to inverting buffering
U3 (IC TL084) .
Carrier Modulation
The carrier modulator section consists of U17 (IC 4053) which is a dual channel analog
Multiplexer. At the output of the modulator analog buffer U3(TL084) is connected to avoid
loading.To obtain BPSK signal, SIN Carriers 1 and 2 are fed to inputs of modulator i/p 1 and
i/p2. Connect NRZ-L data to the control input C1 of the modulator.
The BPSK Modulated signal will get at the output of U3.


BPSK Demodulation Section
The PHASE DETECTION SECTION works on the principle of squaring loops. First step in
BPSK detection is the sine to square wave conversion using a Schmitt trigger U8 (IC 74HCT
14). This enables the BPSK detector to be built around digital ICs. The biphase splitter
basically doubles the frequency component of the modulated date and also ensures that the out
of phase component of the modulate signal does not reach the PLL. This is achieved by using
U11 (IC74LS123). The PLL recovers the carrier frequency from the output of the phase splitter,
but the frequency of the recovered carrier is twice that the of the transmitted carier. So a D flip-
flop is used as a divide by 2 counters to divide the frequency of the PLL output by 2, thus
recovering the reference carrier. The D flip-flop is used to compare the phase of the incoming
data and the reference carrier thereby recovering the data.
Delay Section
Delay section is used to delay the input data by one bit.It is done by using U16 (74HCT74).
Decoding Logic
DPSK Decoder
Since the NRZ-L data is differentially encoded before being applied to the carrier modulator at
the transmitter, it is therefore necessary to decode the data at the receiver. The DPSK decoder
consists of a decision device U 18 (74 HC85). The output of the BPSK receiver (say b (t) is
passed through the delay section U18 (74HCT74) to provide one bit delay (say (b (t-Tb)) to the
received data.This b (t) and b (t-Tb) are the inputs of the decision device. The output of the
decision device is then passed through the digital logic.The output of the digital logic is
recovered data.
PROCEDURE:
1) Carry out the connections as per the block diagram and switch settings .
3) Select Data pattern of simulated data using switch SW1.

OBSERVATIONS:
Signal Amplitude Frequency Time period

Input Data
Differentially encoded data
DPSK modulated output
Demodulated output

4) Connect DATA generated to DATA IN of NRZ-L CODER .

5) Connect the NRZ-L DATA ouput to the DATA IN of the DIFFERENTIAL ENCODER.
6) Connect the clock generated SCLOCK to CLK IN of the DIFFERENTIAL ENCODER.
7) Connect differentially encode data to control input C1 of CARRIER MODULATOR.
8) Connect carrier component SIN 1 to IN 1 and SIN 2 to IN 2 of the carrier modulator logic.
9) Connect DPSK modulated signal MOD OUT to MOD IN of the BPSK Demodulator.
10) Connect output of BPSK demodulator b(t) OUT to input of DELAY SECTION b(t) IN
and one input b(t) IN of decision device.
11) Connect the output of delay section b(t-Tb) OUT to the input b(t-Tb) IN of decision
device .
12) Compare the DPSk decoded data at DATA OUT with respect to input SDATA.
13) Observe various waveforms as mentioned below (Fig.3.3), If recovered data mismatches
with respect to the transmitter data , then use RESET switch for clear observation of data output
PRECAUTIONS:-
1. Do not make any inter connections on the board while the power supply is ON.
2. Whenever the input data is changed, Switch OFF and ON the Data Select switch.
3. Connect the power supply with proper polarity.
RESULT:

VIVA QUESTIONS
1)What do DPSK does not need a synchronous carrier at the Demodulator?
2) What is the bandwidth required? What is the method of detection?
3) What are the advantages over BPSK?
4) What are the disvantages of DPSK?
6) Why do error occur in pairs in DPSK?
7) What is the bandwidth of Mary PSK?
8) What is the phase shift in Mary PSK?
9) What is the symbol phase angle?

EXPERIMENT:8
COMPANDING
AIM:
Implementation of -law companding and expansion of signal.
EQUIPMENT:
DSP Processing kit.

THEORY:
The united states and Japan support m-law companding. Limiting sample values to 13 magnitude
bits, m-law compression can be defined mathematically by the following continuous equation:
F(x)=sgn(x) ln(1 + m lxl ) / ln( 1+ m ) -formula(1)
Where m is the compression parameter (m=22510 for the U.S and japan ), and x is the
normalized integer to be compressed. Following figure illustrates a piece-wise linear
approximation to this compression equation.
The least significant bits of large amplitude values are discarded during compression. The
number of deleted bits is encoded into a field of the of the encoded word, called the segment.
Each segment of this piece- wise linear approximation is equally divided into quantization levels.
The segment size between adjacent codewords is doubled for each succeeding segment.
Moreover, the most significant bit of the codeword contains the sign of the original integer. An
8-bit m-255 codeword is comprised of one sign bit, concatenated with a 3-bit segment,

concatenated with a 3- bit segment, concatenated with a 4-bit quantization value. Prior to
transmission, all the bits are inverted so a positive value will have a sign bit 1 (one). Prior to
segment determination, sign of the original integer is set aside and a bias of 3310 is added to the
absolute value (magnitude) of the integer. The bias limits the maximum allowable input to
815910, and reduces the minimum step size to 2/815910. The bias simplifies the calculation by
making the endpoints of each segment powers of two. Locatings the segment is determined by
detecting the most significant 1 of the biased magnitude, while the quantization value is
comprised of the four bits following it. The translation from linear to m-law compression is
illustrated in following table of the compressed codeword, bits 0-3 represent the quantization and
bits 4-6 represent the segment. The sign of the compressed codeword is left out for simplicity.
The entire m-law codeword is inverted prior to transmission. The inversion is performed because
low amplitude signals occur more frequently than large amplitude signals. Consequently,
inverting the bits increases the positive pulse density on the transmission line, which improves
system performance. m-law expansion can be defined mathematically by the folloeing
continuous equation:
-1
F (y) = sgn(y) (1/m) [(1+m) lyl -1] -formula(2)
Prior to expansion, the m-law codeword is inverted again during expansion, the least significant
bits discarded but are approximated by the median interval, to reduce the loss in accuracy. For
example, if five of the least significant bits of the original integer were discarded during

compression, 100002 will approximate them during expansion. The translation from m-law to
linear expansion is illustrated in following table. Again, the sign bits are left out for simplicity.
After decoding the m-law codeword, the bias is removed and the bit is applied to obtain the final
linear value.
PROCEDURE:
1. Open code composer studio, make sure that DSP kit is turned ON.
2. Load program in the following location.
PATH: DSP320PROGRAMS \ mu-law
3. Then run program from debug.
OUTPUT:
Here we generated a sample 1KHz sine wave from sin function available in C.
When you run program, it will ask to enter amplitude level. Enter amplitude level say
5V.so generated sine wave have amplitude from -5v to +5v
To view original signal
Graph settings & graph




VIVA QUESTIONS
1) What is companding?
2) How do you obtain compression and expansion.?
3) What compression is used for speech and music signal?
4) What is the expression for companding?
5) What is the necessity of nonuniform quantization for speech signal?

EXPERIMENT 9:
IMAGE COMPRESSION USING HUFFMAN CODING

AIM:
Image compression using Huffman coding.
THEORY:
Huffman coding
Huffman encoding , an algorithm for the lossless compression of files based on the
frequency of occurrence of a symbol in the file that is being compressed. The Huffman
algorithm is based on statistical coding , which means that the probability of a symbol has a
direct bearing on the length of its representation .The more probable the occurrence of a symbol
is, the shorter will be its bit-size representation. In any file, certain characters are used more
than others. Using binary representation , the number of bits required to represent each
character depends upon the number of characters that have to be represented. Using one
bit we can represent two characters , i.e, 0 represents the first character and 1 represents
the second character. Using two bits we can represent four characters , and so on.
Unlike ASCII code, which is a fixed-length code using seven bits per character ,
Huffman compression is a variable-length coding system that assigns smaller codes for most
frequently used characters and larger codes for less frequently used characters in order to
reduce the size of files being compressed and transferred.
The basic idea in Huffman coding is to assign short code word to those input blocks
with high probabilities and long codeword to those with low probabilities. This concept is
similar to that of the Morse code.
A Huffman code is designed by merging together the two least probable characters,
and repeating this process until there is only one character remaining. A code tree is thus
generated and the Huffman code is obtained from the labeling of the code tree . An example
of how this is done is shown below.

Example:
It does not matter how the characters are arranged. I have arranged it above so that
the final code tree looks nice and neat.
It does not matter how the final code tree are labeled (with 0s and 1s). I choose to
label the upper branches with 0s and lower branches with 1s.
There may be cases where there is a tie for the two least probable characters. In
such cases, any tie-breaking procedure is acceptable.
Huffman codes are not unique.
Huffman codes are optimal in the sense that no other lossless fixed-to-variable
length code has a lower average rate.
The rate of the above code is 2.94 bits/character.
The entropy lower bound is 2.88 bits/character.
PROCEDURE:
Open code compressor Studio, make sure the DSP kit is turned on.

Load program using `File load_program`. Which is in Program, CD-ROM at
following location.
PATH:PROGRAMS \ HUFFMAN_CODING \ Debug \ HUFFMAN_CODING.out

Then run program from debug Run .
RESULT:
Here we have generated pixels value from MATLAB for image of lena.
Then we calculate frequency of same pixel value & a sine new values from 0 to 256 as
per occurrence.
To view original image

Select Tool Image Analyzer.


After completing property go on image right click refresh in image.
To view compressed image Select

Tool Image Analyzer.


After completing property go on image right click refresh.
Program:
#include<stdio.h>
#include<math.h>
#define N 64
#include "coe.h"
char image_in[N][N];
char image_out[N][N];
void main()

int out[N][N];
int temp[256],hist[256],a;
int i,j,count,value,b=0,k=0;
for(value=0;value<256;value++)
{
count=0;
for(i=0;i<N;i++)
{
for(j=0;j<N;j++)
{
if(in[i][j]==value)
count++;
}
}
if(count!=0)
{
temp[b]=value;
b++;
}
for(k=0; k<b; k++)

{

for(i=0; i<N; i++)

{
for(j=0; j<N; j++)
{
if(temp[k]==in[i][j])
out[i][j]=k;
}
}
}
for(i=0;i<N;i++)
for(j=0;j<N;j++)
{
image in[i][j]=in[i][j];
image out[i][j]=out[i][j];
}
}

VIVA QUESTIONS
1) What is the amount of information?
2) What is the amount of information carried by equally likely and independent messages?
3) What is information rate?
4) What is channel capacity?
5) What does Shannons theorem state?
6) What is Shannon Hartley theorem for Gaussion channel?.

EXPERIMENT: 10
LINEAR BLOCK CODE ENCODER AND DECODER
AIM:
Hamming Coding (Linear Block Coder and Decoder )
EQUIPMENT REQUIRED:
1) Experimental kits DCL-03 & DCL-04
2) Connecting chords
3) Power supply
4)50 MHz Digital Storage Oscilloscope
THEORY:
Linear Block Coding Technique
When the data is transmitted in the channel, bit errors may be introduced by noise and other
factors existing in the channel. Error control coding techniques are used for detecting and
correcting the errors. They can be used for controlling single bit, two bit, and three bit errors.
Even Parity Codes, Odd Parity Codes, Hamming Codes are the normal error control coding
techniques, used for the detection and correction of all single bit errors that occur in the
transmission of data.
Hamming Codes
Hamming codes are the most effective single error detecting and correcting codes, used in
practice. The hamming distance for such a code is 3, ensuring an effective correction of all single
bit errors occurring in transmission:
The general format for Hamming Codes is as follows:
If N is the length of the coded sequence and n is number of error check
n
bits Then, N=2 1 (Where n = 0,1,2,3)
n
Bit position of the check bits = 2


The typical size of some of Hamming Code normally used in practice is given below:
Size of the coded sequence Size of Data Size of Error Check bits
7 4 3
15 11 4
31 26 5
63 57 6
Thus depending upon the size of the coded sequence, hamming parity bits are generated. At the
receiver the parity check is done and error bit is located and is corrected by bit reversal. Thus all
single bit errors occurring in data transmission can be detected and corrected by this error check
option.
The (7, 3) Hamming code, which is illustrated in DCL - 03 and DCL - 04 has:
Bit length of the coded sequence = 7
Number of error check bits = 3
Number of data bit = 4
In the coded sequence:
Let K1, K2, K3 be the error check bits.
L4, L5, L6, L7 be the data bits.
Now K1, K2, K3 are chosen in such a manner that
K1 - Even parity for the data bits L4, L5, and L7
K2 - Even parity for the data bits L4, L6, and L7.
K3 - Even parity for the data bits L5, L6, and L7.
The K1, K2, K3 hamming bits and L4, L5, L6, and L7 are the data bits where L7 is the most
significant data bit. Thus the coded sequence will be transmitted following format:
K1, K2, K3, L4, L5, L6, L7
L7 is shifted out first and K1 is the last.


Truth table for (7, 3) Hamming Code is given below:
Data(In decimal) Bit position
K1 K2 K3 L4 L5 L6 L7
0 0 0 0 0 0 0 0
1 1 1 0 1 0 0 0
2 1 0 1 0 1 0 0
3 0 1 1 1 1 0 0
4 0 1 1 0 0 1 0
5 1 0 1 1 0 1 0
6 1 1 0 0 1 1 0
7 0 0 0 1 1 1 0
8 1 1 1 0 0 0 1
9 0 0 1 1 0 0 1
10 0 1 0 0 1 0 1
11 1 0 0 1 1 0 1
12 1 0 0 0 0 1 1
13 0 1 0 1 0 1 1
14 0 0 1 0 1 1 1
15 1 1 1 1 1 1 1
At the Receiver to detect and correct the error occurred during transmission, EVEN Parity Check
is done at bit positions.
Let K1*, K2*, K3* be the even parity check for the following bit of the coded
sequence: K1*: Even parity check bit for K1, L4, L5, and L7 of the coded sequence
K2*: Even parity check bit for K2, L4, L6, and L7 of the coded sequence
K3*: Even parity check bit for K3, L5, L6, and L7 of the coded sequence
From the recovered K1*, K2*, and K3* the error bits are located and corrected.

Truth Table for error bit location is given below:
Error in data bit K3* K2* K1*

No error 0 0 0
Error in data bit L4 0 1 1
Once the error bits are located the error is corrected by bit reversal.
PROCEDURE
Hamming Parity Mode
1) Carry out the following connections as per the block diagram.

2) Connect power supply in proper polarity to the kits DCL-03 and DCL-04 and switch it on.
3) Connect DC input signal DC 1 to the input CH 0 and CH 1 of the Sample and Hold logic.
4) Set the speed selection switch SW1 to FAST mode.
5) Select parity selection switch to HAMMING mode on both the kit DCL-03 and DCL-04 as
shown in switch setting diagram (Fig. A).
6) Connect TXDATA, TXCLK and TXSYNC of the transmitter section DCL-03 to the
corresponding RXDATA, RXCLK, and RXSYNC of the receiver section DCL-04.
7) Vary the amplitude of input DC signal from 0V to 4.96V and observe the variation on LED
on the transmitter and receiver as mention below.
8) Create a single bit fault in any one of the 4 MSB data bit by putting switch in below
position of SF 1 and observe the status of PARITY ERROR.
9) You will receive the data at the receiver side with the single bit error corrected and with the
indicator as to which of the 4 data bits had the error.
10) This proves that Hamming Code can not only detect single bit error but also correct the
error.

OBSERVATION TABLE
A/D Parity coded Error Code Data latch D/A Error
Converter data generator Converter Detection/correction
PRECAUTIONS
RESULT

VIVA QUESTIONS
1) What is code word?
2) What is block length?
3) What is the code rate?
4) What is channel data rate?
5) What is the hamming distance?
6) What is the minimum distance?
7) What is code efficiency?
8) What is a linear code?

EXPERIMENT: 11
BINARY CYCLIC CODE ENCODER AND DECODER
AIM:
To study Cyclic Redundancy code encoding and decoding.
EQUIPMENT REQUIRED:
1) Cyclic Redundancy code encoding and decoding trainer kit.

2) 50 MHz Digital Storage Oscilloscope
3) Power supply
4) Patch cords
THEORY:
A cyclic redundancy check (CRC) or polynomial code checksum is a non-secure hash function
designed to detect accidental changes to raw computer data, and is commonly used in digital
networks and storage devices such as hard disk drives. A CRC-enabled device calculates a short,
fixed-length binary sequence, known as the CRC code or just CRC, for each block of data and
sends or stores them both together. When a block is read or received the device repeats the
calculation; if the new CRC does not match the one calculated earlier, then the block contains a
data error and the device may take corrective action such as rereading or requesting the block be
sent again.
CRCs are so called because the check (data verification) code is a redundancy (it adds zero
information) and the algorithm is based on cyclic codes. The term CRC may refer to the check
code or to the function that calculates it, which accepts data streams of any length as input but
always outputs a fixed-length code. CRCs are popular because they are simple to implement in
binary hardware, are easy to analyze mathematically, and are particularly good at detecting
common errors caused by noise in transmission channels


Operation
The theory of a CRC calculation is straight forward. The data is treated by the CRC algorithm as
a binary number. This number is divided by another binary number called the polynomial. The
rest of the division is the CRC checksum, which is appended to the transmitted message. The
receiver divides the message (including the calculated CRC), by the same polynomial the
transmitter used. If the result of this division is zero, then the transmission was successful.
However, if the result is not equal to zero, an error occurred during the
transmission. The CRC-16 polynomial is shown in Equation 1.below
16 15 2
P(x) = x +x +x +1 -- Equation 1
Example Calculation
In this example calculation, the message is two bytes long. In general, the message can have any
length in bytes. Before we can start calculating the CRC value 1, the message has to be
augmented by n-bits, where n is the length of the polynomial. The CRC-16 polynomial has a
length of 16-bits; therefore, 16-bits have to be augmented to the original message. In this
example calculation, the polynomial has a length of 3-bits; therefore, the message has to be
extended by three zeros at the end. An example calculation for a CRC is shown below.
Calculation For Generating A CRC
Checking a Message For A CRC Error

CRC Hardware Implementation
The CRC calculation is realized with a shift register and XOR gates. Figure shows a CRC
generator for the CRC-16 polynomial. Each bit of the data is shifted into the CRC shift register
(Flip-Flops) after being XORed with the CRCs most significant bit.
Hardware of CRC-16 generator
PROCEDURE:
1) Do the Connections as per block diagram shown in figure.

2) Connect the power supply to the kit and switch it ON.
3) Set the data pattern as shown in block diagram using SW1.Observe the 8 bit serial data at
SERIAL DATA post.
4) Connect SERIAL DATA to DATA IN post of CRC GENERATOR.
5) Observe CRC encoded signal at DATA OUT post of CRC GENERATOR.

6) Connect DATA OUT to DATA IN post of CRC ERROR ADDER block to introduce 2
bit manual error. Introduce error by switch SW2.
7) To decode the signal Connect DATA OUT to IN post of CRC DECODER block.
8) Observe CRC decoded and corrected signal at OUT post of CRC DECODER. Calculated
CRC at receiver end is displayed on led B1 to B4.
OBSERVATIONS:
4 3
In ADCL-08 kit the generator polynomial for CRC is X + X + 1 i. e. (11001).
Select data pattern as 11100100. Internally 4 zeros are appended after actual 8 bit data for
transmitting 4 bit CRC. Thus data will be 111001000000.
To Calculate the CRC divide the input data by generator polynomial as shown
below. 11100100 0000 11001 111001000000 | 11111 11001 0010110 11001
011110 11001 0011100 11001 0010100 11001
01101 -------- Remainder is nothing but CRC.

Thus generated CRC for the data pattern is 1101. And final transmitted data will be (Data +
CRC) 111001001101.
In receiver side the same generator polynomial is used to calculate the CRC of the received data.
If remainder is zero then received data has no error. CRC can correct single bit error.
In ADCL-08 two errors can be introduced in data at 5th and 8th position using switch SW2. at
receiver CRC is being calculated is shown below for data without any errors.
111001001101 11001
111001001101 | 11111
11001

0010110
11001
011110
11001
0011111
11001
0011001
11001
00000 ------------ Remainder is zero indicated received data has zero Errors.
If one error is introduced to data using SW2 (left side switch) in 5th position of data then data
with error will be received at receiver side. The receiver calculates CRC using same polynomial.
If there is some remainder then using look up table the bit with error are found out and simply
invert that bit to correct the data.
Data without error at receiver = 111001001101
Data with error in 5th position =
111011001101 CRC calculation is as shown
below; 111011001101 11001 111011001101
| 11111 11001 0010010 11001 010110 11001
011111 11001 0011010 11001 000111
Remainder in this case is 111. The corresponding LED indication is observed on B2, B3, and B4
at CRC DECODER section. The value 111 corresponds to Bit position 5 in look up table and that
particular bit is inverted and corrected data at receiver is available which is 11001001101.

Similarly for another error bit which is in 8th position, the remainder will be 1001 which is
indicated on B1 and B4 at CRC DECODER section.
CAPUTERED WAVEFORMS:
1) CH-1: SERIAL DATA

CH-2: DATA OUT OF CRC GENERATOR
2) CH-1: DATA OUT OF CRC GENERATOR

CH-2: DATA OUT OF CRC ERROR ADDER WITHOUT ANY ERROR.


CH-2: DATA OUT OF CRC ERROR ADDER WITH SW2 FIRST BIT ON.

CH-2: DATA OUT OF CRC ERROR ADDER WITH SW2 SECOND BIT ON.


CH-2: DATA OUT OF CRC ERROR ADDER WITH SW2 BOTH BIT ON

CH-2: OUT OF CRC DECODER WITHOUT ANY ERROR ADDED.

7)CH-1: DATA OUT OF CRC GENERATOR

CH-2:OUTOFCRCDECODERWITHONEBIT ERRORADDED.

CH-2: OUT OF CRC DECODER WITH ANOTHER ONE BIT ERROR ADDED.


CH-2: OUT OF CRC DECODER WITH TWO BIT ERROR ADDED.
PRECAUTIONS:

RESULT:

VIVA QUESTIONS
1) What is a cyclic code?
2) What are the advantages of cyclic codes?
3) What are the disadvantages of cyclic codes?

EXPERIMENT: 12
CONVOLUTION CODE ENCODER AND DECODER
AIM:
To Study Convolution Encoding And Hard Decision Viterbi Decoding For K= 7 And Rate =1/2.
EQUIPMENTS:
1) Convolution Encoding and Decoding Experimental Kit ADCL-06.
2) Patch Chords.
3) Power supply.
4) 16 Channel Logic Analyzer
THEORY
A convolutional code works by adding some structured redundant information to the user's data
and then correcting errors using this information. A convolutional encoder is a linear system. A
binary convolutional encoder can be represented as a shift register. The outputs of the encoder
are modulo 2 sums of the values in the certain register's cells. The input to the encoder is either
the unencoded sequence (for non-recursive codes) or the unencoded sequence added with the
values of some register's cells (for recursive codes).
The convolution encoder used in ADCL-06 supports INTELSAT standard. As per the standard
the generator polynomials
For K = 7, R = 1/2 are
2 3 5 6 2 3 6
G0(x) = 1+x +x +x +x G1(x) = 1+x+x +x +x
Fig (a)


i.e. G0(x) = 133(octal) & G1(x) = 171(octal). The implementation depicted below and is used in
conjunction with an R=1/2, K=7 Hard Decision Viterbi Decoder. The intent of this experiment is
to help clarify the terms used to define the convolutional encoding and Viterbi decoding as well
as to explain how convolutional encoding and Hard decision Viterbi decoding takes place
theoretically and to observe and verify the results practically. We can approach the encoder in
terms of its impulse response i.e. the response of the encoder to a single one bit that moves
through it. Consider the contents of the register in Fig (a)
Branch Word
Register Contents
U1 U2
1000000 1 1
0100000 0 1
0010000 1 1
0001000 1 1
0000100 0 0
0000010 1 0
0000001 1 1
Fig (b)
Input sequence: 1000000
Output sequence: 11 01 11 11 00 10 11
The output sequence for the input one is called the impulse response of the encoder. Then for
the input sequence m = 1 1 1 1 1 1 1, the output may be found by the superposition or the linear
addition of the time shifted input impulses as follows:

Fig (c)
Observe that this is the same output obtained in Fig (d), demonstrating that convolutional codes
are linear. It is from this property of generating the output by the linear addition of time shifted
impulses, or the convolution of the input sequence with the impulse response of the encoder, that
we derive the name convolutional encoder.



Fig (d)

PROCEDURE:
1) Carry out the connections as per the block diagram and switch settings.
3) Keep the Data clk select switch SW2 towards slow position.
4) Select data pattern using select switch SW1 in the Data Generator block.
5) Connect SERIAL DATA generated on board to DATA IN ofCONVOLUTION
ENCODER.
6) Observe RDY1 pin, convolutionally encoded data will be observed at OUT1 and
OUT2 post. The convolutionally encoded data are valid from the instant when RDY1
goes high.
7) Connect OUT1 and OUT2 post of Convolution Encoder block IN1 and IN2 of Hard
Decision Viterbi Decoder block.
8) Observe the decoded data at the DATA OUT1 post of Hard Decision Viterbi Decoder
block.
9) Repeat the procedure by keeping the data clk select switch towards fast position.
Note1: The reason for the provision of data clock with high and low frequency, using data clk
select switch is to observe the encoded and decoded data in a slow as well as fast mode.
Note2: It is advised to observe the decoded data i.e. output of the Hard decision Viterbi Decoder
in fast mode because it takes approximately four minutes by the Viterbi decoder to decode the
data since the operating frequency is very low.
OBSERVATIONS:
Input data:
Encoded data:
OUT1:
OUT2:
Decoded data:

PRECAUTIONS:
RESULT:

VIVA QUESTIONS
1) What is a convolution code?

2) What is constraint length?
3) What are the advantages of convolutional codes?
4) What are the disadvantages of convolutional codes?

EXPERIMENT13
ADAPTIVE DELTA MODULATION
AIM: Study of Adaptive Delta modulation and Demodulation with Continuously Variable
Slope Delta Modulator(CVSD).
EQUIPMENT REQUIRED:
1) Adaptive delta modulation trainer kit(DCL-07)
2) Connecting chords
3) Power supply
4) 20MHz Dual trace oscilloscope
THEORY:-
Delta modulation system is unable to chase the rapidly changing information of the analog
signal, which gives rise to distortion and poor quality reception. The problem can be overcome
by increasing the integrator gain. Adaptive delta modulation is a variation of Delta modulation,
which offers relief from disadvantage of DM by adopting the step size to accommodate changing
signal conditions. If the input signal is large, step is cause to increase, here by reducing slope
overload effects. The block diagram of ADM is as shown in figure. It is same as Delta
modulation expect the variable gain circuit and step size controller. The controller keeps sensing
the slope condition of the message conveyed. If the slope is large the controller output causes the
variable gain circuit to have large gain. If the slope is small, the controller output causes a small
gain. In certain cases Adaptive delta modulation do not change step size on a pulse-to- pulse
basis, but changes are made much more slowly, such slow control is referred to as syllabic. The
usual implementation involves a continuously variable slope delta(CVSD).
The CVSD is the simple alternative to more complex conventional conversion techniques in
system requiring digital communication of analog signals. The CVSD A/D is well suited for the
requirements of digital communications. A Delta modulator consists of a comparator in the
forward path and an integrator in the feedback path of a simple control loop. The input to the
comparator is the simple analog signal and the integrator output. That sign bit is the digital
output and also control the direction of ramp in the integrator.The output of comparator is fed to
the sampler. Then the sampler output is fed to the slope magnitude control followed by slope


polarity switch.the output slope polarity the slope polarity switch and level detect algorithm. The
level detect algorithm is again fed to a switch is fed to the integrator in the control loop. With no
input at transmitter a continuous 1 and 0alternation are transmitted. The outstanding
characteristic is its ability to transmit the intelligible voice out at relatively low data rate.
Companded PCM for telephone quality transmission requires about 64 kbits/sec. data
rate/channel. CVSD produces equal quality at 32Kbit/sec. In CVSD Decoder CVSD mod outout
is fed to the input of comparator.
The comparator output is fed to the internal shift register. Then the output of internal shift
register is fed to the digital logic followed by slope polarity switch and integrator. The output of
integrator is fed to the low pass filters for the reconstruction of original signal.
Clock Generator
This section provides five different sampling frequencies. All these frequencies are generated from
main clock of 2.048MHz crystal. The 2.048MHz crystal oscillator generates a 2.048MHz clock. It is
divided by 2 ripple counters U2(74LS393) to get five different sampling frequencies of 8KHz,
16KHz, 32KHz, 64KHz, and 128KHz. The different clocks for sampling in modulation techniques
can be selected with the help of U3 (GAL 16V8-25LC), driving circuit for the U3 is setup by
U5(74LS393) and U4(74LS74 - D flip flop ) through switch S1. LED indications are

provided for each selected sampling frequency using U3 (GAL 16V8-25LC).

Sine wave generation
This section basically provides four amplitude variable (0-4 Vpp) synchronized sine waves each
of 250Hz, 500Hz, 1KHz and 2KHz. The 32 KHz, 16KHz, 8KHz and 4KHz frequencies are fed
to serial to parallel shift register (74LS164), which generates the stair case sine wave, by serial
shift operation. The serial to parallel shift register has a resistive ladder network at the output.
For 16 shifts of the register, one stair case sine wave is produced. So if a 16Hz clock is fed to
the shift register, 1 KHz stair case sine wave is generated. Thus by using the 32 KHz, 16 KHz, 8
KHz and 4KHz, stair case sine wave of 2 KHz, 1 KHz, 500 Hz and 250 Hz are generated
respectively by U10, U9, U8, and U7. The active filter at output (LM324) suppresses the ripple
and also takes care of the impedance matching. After filtering we will get smooth sine waves.
Amplitude of the signal is varied using respective potentiometers.
DC Generation
In this section Zener diode D7 (5V1) will regulate VCC to 5 volts. Amplitude varied by
using potentiometer P5.
Input Buffer
.This is a non-inverting unity gain amplifier built around U12 (LM324).
Digital Sampler
Digital sampler consists of two stages. First stage is of different amplifier U13 (LM311) and
second stage is D flip-flop U14(4013). Differential amplifier gives output by comparing voltage
levels at input terminals. Output is equal to signal IN2 subtracted from signal IN1. D flip flop
sends this output at every rising edge of the clock applied it.
Integrator-1
signal applied.
Integrator-2
Integrator is built around U16 (IC LF353). Integrator output is integration of the input signal


applied. In this integrator switch S3 is provided to select low or high time constant
for integration operation. Pot P6 is provided to control the gain of integrator.
Delta or Sigma Delta Selection
Switch S2 is provided for selection. In case of Delta modulation signal is bypassed through
capacitor, DC signal is blocked. In case of Sigma Delta modulation DC signal is also send
to integrator inputs.
Integrator-3
for integration operation.
Demodulator
Demodulator is simple D flip-flop using U14 (4013). Output is available at rising edge of
clock applied to it.
Compressor
Compressor is log amplifier built around U18 (LF353). For low amplitude signal output is linear
and for high amplitude signal output is logarithmic.
Expander
Expander is Antilog amplifier built around U19 (LF353). For low amplitude signal output
is linear and for high amplitude signal output is logarithmic.
CVSD Modulator
The CVSD is built around U20 (IC MC3418). The CVSD is the simple alternative to more complex
conventional conversion techniques, in systems requiring digital communication of analog signals.
The CVSD A/D is well suited for the requirements of digital communications. A Delta modulator
consists of a comparator in the forward path and the integrator in the feedback path of a simple
control loop. The input to the comparator is the simple analog signal and the integrator output. The
comparator output is the difference between the input voltage and the integrator output. The sign bit
is the digital and also controls the direction of ramp in the integrator. The output of comparator is
fed to the sampler. Then the sampler output is fed to the slope polarity switch. The output slope
polarity switch is fed to the integrator in the control loop. With no input at the transmitter a
continuous 1 and 0 alterations are transmitted. The outstanding characteristic is its ability to transmit
the intelligence voice out at relatively about 64Kbits/sec

data rate per channel. CVSD produce equal quality at 32Kbit/sec

CVSD Demodulator
The CVSD Demodulator is built around U21 (IC MC 3418). I n CVSD Decoder CVSD mod
output fed to the input of comparator. The comparator output is fed to the internal shift
register is fed to the digital logic followed by slope polarity switch and integrator . The output
of integrator is fed to low pass filters for the reconstruction of original signal
Output buffer
This is a non-inverting unity gain amplifier built around U12 (LM324).
2nd 2Order Butterworth Filter
sampling frequency components from the Demodulation output of each modulation techniques
and recovers the originals signals.
4th Order Butterworth Filter
sampling frequency components from the Demodulation output of each modulation
techniques and recovers the originals signals.
PROCEDURE:
Adaptive Delta modulation
1) Make the connections as per the block diagram.
2) Connect the power supply with the proper polarity to the kit DCL-07 and switch it ON.
3) Select sine wave input 500Hz of 2V or above through pot P2 and connect post 1KHz to
post IN of input buffer.
4) Connect output of buffer post OUT to Digital Sampler input post IN.
5)Then select clock rate of 32KHz by pressing switch clock is S1 selected clock is indicated by
LED glow.
6) Keep Switch S2 in (Delta) position.
7) Connect output of Digital sampler post OUT to input post IN of Integrator 2.
8) Connect output of Integrator 2 post OUT to input post IN2 of Digital Sampler.
9) Keep Switch S3 in LOW position.
10) Connect Delta modulated output post OUT of Digital Sampler to the input of
Delta Demodulator section post IN of Demodulator.

11) Connect output of Demodulator post OUT to the input of Integrator3 post IN.
12) Connect output of Integrator 3 post OUT to the input of output buffer post IN.
nd
14) Connect output of output buffer post OUT to the input of 2 order filter post IN.
nd nd
15) Connect output of 2 order filter post OUT to the input of 4 order filter post IN.
16) Keep Switch S4 in LOW position.
nd
17) Observe the output of filter at post OUT of 4 order filter.
18) Repeat the above mention procedures with different signal sources and selecting the
different clock rates and observe the response of Adaptive delta modulation. This follows input
signal even if amplitude & frequency of input signal increases. Adaptive delta modulator
matches the slope of the input signal due to low time constant.
19) We will get better recovery of signal as we go on increasing the clock rates.
Continuously Variable Slope Delta Modulator(CVSD).
1) Make the connections as per the block diagram.
2) Connect the power supply with proper polarity to the Kit DCL-07 and switch it ON.
3) Select sine wave input 1 KHz of 2V or above through pot P3 and connect post 1 KHz to
post IN of input buffer.
4) Connect output of buffer post OUT to the CVSD modulator input post IN.
5) Select the clock rate of 32 KHz by pressing the S1.
6) Observe the CVSD output.
7) Connect the output of CVSD modulator post OUT to the input of CVSD Demodulator
post IN.
8) Connect CVSD Demodulated output post OUT to the input of output buffer post IN.
nd
9)Connect output of output buffer post OUT to the input of 2 order filter post IN.
nd nd
10) Connect output of 2 order filter post OUT to the input of 4 order filter post IN.
11) Repeat the above mentioned procedures with different signal sources and selecting
the different clock rates and observe the response of CVSD modulator and demodulator.
12) Observe all signals on dual channel through oscilloscope probes. We will get clear
reception at high clock rates (e.g.128KHz).

9)


OBSERVATIONS:
Adaptive Delta modulation

Input
Clock
Integrator2
Digital Sampler output
Demodulator output
Integrator3
nd
2 order filter output
nd
OBSERVATIONS:
Continuously Variable Slope Delta Modulator(CVSD).

Input
Clock
CVSD modulator output
CVSD demodulator output
nd
nd
PRECAUTIONS:
2. Do not make any interconnections when power supply is ON
RESULT:

VIVA QUESTIONS
1) What is adaptive Delta modulation?
2) How many bits are used to encode one sample?
3) What are the areas of application of ADM?
4) How is the signal to noise ratio in ADM compared to DM?
5) What is the error present in ADM?
6) What is the sampling rate and bit rate in ADM for voice encoding?

EXPERIMENT14
MINIMUM SHIFT KEYING
AIM:-
A) To study minimum shift keying modulation and demodulation.
B) To study the constellation diagram of MSK.
EQUIPMENT REQUIRED:-
1) MSK modulation and demodulation trainer kit(ADCL-08).
2) Power supply.
3) Patch chords.
4) Digital storage oscilloscope.
THEORY:-
Minimum shift keying ,MSK is a form of FSK (frequency shift or phase shift
keying(PSK).MSK uses changes in phase to represent 0s and 1s with the phase shift used
depending on the previous phase value. MSK acts like FSK with minimum difference between
the frequencies of the two FSK signals, resulting in a power spectral density that falls of much
faster than QPSK. Minimum frequency shift keying or minimum shift keying is a particularly
spectrally efficient form of coherent FSK. In MSK the difference between the higher and lower
frequency is identical to half the bit rate. Consequently ,the waveforms used to represent a 0 and
1 bit differ by exactly half a carrier period. This is the smallest FSK modulation index that can
be chose n such that the waveforms for 0 and 1 are orthogonal.In ADCL -08 the carrier is
transmitted according to symbols given in following table.
S.NO Symbols Carriers

0
1 00 HIGH FREQ(180 )
0
2 01 LOW FREQ (180 )
0
3 10 LOW FREQ (0 )
0
4 11 HIGH FREQ (0 )
Frequency of the high frequency carrier =384.6 KHz.
Frequency of the low frequency carrier =256.4 KHz.
High frequency (384.6 KHz) is 1.5 times the low frequency (256.4 KHz).


PROCEDURE:-
A) Minimum shift keying modulation and demodulation.
1) Make connections as per the block diagram shown in the figure.
2) Connect the power supply to the kit and switch it On.
3) Set the data pattern as shown in block diagram using SW1. Observe the 8 bit serial data
at SERIAL DATA post.
4) Observe the carrier used for modulation at SIN1 and SIN2 posts.
2) Connect the power supply to the kit and switch it On.
3) Set the data pattern as shown in block diagram using SW1. Observe the 8 bit serial data
4) Observe the carrier used for modulation at SIN1 and SIN2 posts.5) Connect SERIAL
DATA to DATA IN post of DIBIT CODER.
6) Observe EVEN and ODD data with respect to their clocks.
7) Observe MSK modulated signal at MOD OUT post of CARRIER MODULATOR.
8) To demodulate the MSK signal connect MOD OUT to IN post of MSK
DEMODULATOR section.
9) Observe the demodulated EVEN and ODD signal at MSK DEMODULATOR and compare
it with dibit coder.
10) Observe the demodulated signal at OUT post of MSK DEMODULATOR and compare
it with original signal i.e with signal at SERIAL DATA.
B) Constellation diagram for MSK
1)Make the connections as per the block diagram shown in figure.
2) Connect the power supply to the kit and switch it on.
3) Set the data pattern as shown in block diagram using SW1.Observe the 8 bit serial data
4) Observe the carrier used for modulation at SIN1 and SIN2 posts.


5) Connect SERIAL DATA to DATA IN post of DIBIT CODER.

6) Observe EVEN and ODD data with respect to their clocks.
7) Observe MSK modulated signal at MOD OUT post of CARRIER MODULATOR.
8) To demodulate the MSK signal connect MOD OUT to IN post of MSK
DEMODULATOR section.
9) Observe the demodulated EVEN and ODD signal at MSK DEMODULATOR and compare
it with dibit coder.
10) Observe the demodulated signal at OUT post of MSK DEMODULATOR and compare
it with original signal i.e with signal at SERIAL DATA.
11)To observe the constellation diagram connect X to X channel and Y to Y channel of
CRO. Put oscilloscope display mode on X-Y.





OBSERVATIONS:

Serial data(0001 1011)
Even clock signal of Dibit coder
Odd clock signal of Dibit coder
MSK modulator output
MSK demodulator output(0001 1011)
PRECAUTIONS:

2. Do not make any interconnections when power supply is ON
RESULT:

VIVA QUESTIONS
1) What is MSK?
2) What is bandwidth efficiency of MSK?
3) What is the symbol-error probability of MSK?
4) In MSK, what is the frequency difference between two signals that can possible
be transmitted?
5) In MSK, what is the phase change in each bit interval?
6) What is the dimension of the signal space of an MSK signal?
7) What is the in-phase component during the interval T t T, in MSK.
8) How does the PSD of MSK vary?












REFERENCES
1. Digital communications - Simon Haykin, John Wiley, 2005
2. Principles of Communication Systems H. Taub and D. Schilling, TMH, 2003
3. Digital and Analog Communication Systems - Sam Shanmugam, John Wiley, 2005.
4. Digital Communications John Proakis, TMH, 1983. Communication Systems Analog

& Digital Singh &Sapre, TMH, 2004.
5. Modern Analog and Digital Communication B.P.Lathi, Oxford reprint, 3rd edition, 2004.


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RAGHU INSTITUTE OF TECHNOLOGY

Dakamarri (v), Bheemunipatnam (M)

III B.Tech ECE: II- Semester

DIGITAL COMMUNICATIONS LABORATORY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Name of the Laboratory : Digital Communication Laboratory

Name of the Faculty : Mrs. M. Kalpana

Department : Electronics and Communication Engineering

Year : III Year

3 Additional Instructions viii

7 Cycle-Wise List of Experiment xii

13 Binary Phase Shift Keying. 42

14 Differential Phase Shift Keying. 49

17 Linear Block Code-Encoder and Decoder 71

Course Context and Overview:

Programme Educational Objectives

PEO No. Programme Educational Objectives

Raghu Institute of Technology, Dakamarri, Visakhapatnam i

Raghu Institute of Technology, Dakamarri, Visakhapatnam ii

Mapping of Course Outcomes to Programme Outcomes and Programme Educational

S.No Teaching Learning and Assessment Strategy

1 Classroom Demonstration by Faculty In charge through different Teaching

Raghu Institute of Technology, Dakamarri, Visakhapatnam iii

Evaluation of Marks for the Laboratory Exam

Serial No Criteria Marks

External Lab Exam - 50

Serial No Criteria Marks

Total Lab Exam Marks - 75

Serial No Criteria Marks

Raghu Institute of Technology, Dakamarri, Visakhapatnam iv

Raghu Institute of Technology, Dakamarri, Visakhapatnam v

3. UNITS are to be written for various quantities.

Raghu Institute of Technology, Dakamarri, Visakhapatnam vi

LIST OF EXPERIMENTS RECOMMENDED BY JNTU KAKINADA

1. Time Division Multiplexing.

Raghu Institute of Technology, Dakamarri, Visakhapatnam vii

LIST OF SELECTED EXPERIMENTS FROM JNTUK RECOMMENDED

1. Time Division Multiplexing.

LIST OF ADDITIONAL EXPERIMENTS DESIGNED

1. Adaptive Delta Modulation

Raghu Institute of Technology, Dakamarri, Visakhapatnam viii

CYCLE-WISE LIST OF EXPERIMENTS FINALISED

Expt-1 Time Division Multiplexing.

Expt-2 Pulse Code Modulation.

Expt-3 Differential Pulse Code Modulation.

Expt-4 Delta Modulation.

Expt-5 Frequency Shift Keying.

Expt-6 Binary Phase Shift Keying.

Expt-7 Differential Phase Shift Keying.

Expt-9 Image Compression Using Huffman Coding

Expt-10 Linear Block Code-Encoder and Decoder

Expt-11 Binary Cyclic Code - Encoder and Decoder

Expt-12 Convolution Code - Encoder and Decoder

Expt-13 Adaptive Delta Modulation

Expt-14 Minimum Shift keying

Raghu Institute of Technology, Dakamarri, Visakhapatnam ix

1. Time Division Multiplexing and Demultiplexing Trainer kit.

Raghu Institute of Technology,Dakamarri,Visakhapatnam 1

Raghu Institute of Technology,Dakamarri,Visakhapatnam 2

Each modulating signal is applied to IC TL074(U6) (pin nos. 3,5,10,12 respectively).

Raghu Institute of Technology,Dakamarri,Visakhapatnam 3

Low pass filter:

Raghu Institute of Technology,Dakamarri,Visakhapatnam 4