Digital Integrated

Circuits
A Design Perspective
Semiconductor Memories
Reference: Digital Integrated Circuits,
2nd edition, Jan M. Rabaey, Anantha
Chandrakasan and Borivoje Nikolic
Disclaimer: slides adapted for
INE5442/EEL7312 by Jos L. Gntzel
from the books companion slides made
available by the authors.
 Lecture Summary

Memory Classification

Memory Architectures

The Memory Core (ROM Memories)

Digital Integrated Circuits2nd Slide 2 Semiconductor Memories

 Memory Timing: Definitions
Read cycle

READ

Write cycle
Read access Read access
WRITE

Write access
Data valid

DATA

Data written

Digital Integrated Circuits2nd Slide 3 Semiconductor Memories

Semiconductor Memory Classification

Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory

Random Non-Random EPROM Mask-Programmed

Access Access
2
E PROM Programmable (PROM)

SRAM FIFO FLASH

DRAM LIFO
Shift Register
CAM

Digital Integrated Circuits2nd Slide 4 Semiconductor Memories

 Memory Architecture: Decoders
M bits M bits

S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage Storage
Word 2 A1 Word 2
cell cell
wo r d s

A K 1
N

De c o d e r

SN 2
Word N 2 2 Word N 2 2
SN 1
Word N 2 1 Word N 2 1
K = log2N

Input-Output Input-Output
(M bits) (M bits)

Intuitive architecture for N x M memory Decoder reduces the number of select signals
Too many select signals:
N words == N select signals
K = log2N

Digital Integrated Circuits2nd Slide 5 Semiconductor Memories

 Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH

2L 2 K Bit line
Storage cell
AK

Row Decoder
A K 1+ 1 Word line

A L 2 1

M.2K

Sense amplifiers / Drivers Amplify swing to

rail-to-rail amplitude

A0
Column decoder Selects appropriate
A K 2 1 word

Input-Output
(M bits)

Digital Integrated Circuits2nd Slide 6 Semiconductor Memories

 Hierarchical Memory Architecture
Block 0 Block i Block P 2 1

Row
address

Column
address
Block
address

Global data bus

Control Block selector Global
circuitry amplifier/driver

Advantages: I/O

1. Shorter wires within blocks

2. Block address activates only 1 block => power savings

Digital Integrated Circuits2nd Slide 7 Semiconductor Memories

 Block Diagram of 4 Mbit SRAM
32 128-bit
Clock Z-address X-address
generator buffer buffer blocks
Predecoder and block selector
Bit line load
rA
o
lca
yB
k0
K
1
2
8

Global row
u
b
g
o
lS
a
rd
w
e
c

decoder
S
u
b
g
o
la
d
rw
e
c

o
G
lb
a
d
rw
e
c

0
kc3
B
o
l

1
kc3
B
o
l

o
lcB
k1

Sub-global
row decoder

Transfer gate
Column decoder L
o
cra
d
w
le

Local row decoder

Sense amplifier and write driver

CS, WE I/O x1/x4 Y-address X-address

buffer buffer controller buffer buffer
[Hirose90]

Digital Integrated Circuits2nd Slide 8 Semiconductor Memories

 Contents-Addressable Memory
Data (64 bits)

I/O Buffers

Commands
I / O B u f f e r s

I / O B u f f e r s

Comparand

C o m m a n d s
C o m m a n d s

Mask

Address Decoder

Priority Encoder
2 Validity Bits
CAM Array
Control Logic R/W Address (9 bits) 9
2 words x3 64 bits
Va l i d i t y B i t s

9
2

P r i o r i t y E n c o d e r

Va l i d i t y B i t s

Ad d r e s s De c o d e r

P r i o r i t y E n c o d e r

Ad d r e s s De c o d e r

Digital Integrated Circuits2nd Slide 9 Semiconductor Memories

 Memory Timing: Approaches
DRAM Timing SRAM Timing
Multiplexed Addressing Self-timed

Address
bus Row Address Column Address

RAS Address
Bus Address
Address transition
CAS initiates memory operation

RAS-CAS timing

DRAM external timing signals: SRAM: no external timing signals!

RAS= Row Address Strobe
CAS=Column Address Strobe

Digital Integrated Circuits2nd Slide 10 Semiconductor Memories

 Read-Only Memory Cells
BL BL BL
VDD
WL
WL WL
1

BL BL BL

WL WL
WL
0
GND

Diode ROM MOS ROM 1 MOS ROM 2

MOS ROM1: BL must be resistively clamped to ground

MOS ROM2: BL must be resistively clamped to Vdd
Digital Integrated Circuits2nd Slide 11 Semiconductor Memories
 MOS OR ROM
BL[0] BL[1] BL[2] BL[3] Data read

WL[0]
V DD To reduce area
WL[1] overhead,
supply voltage
lines are shared
WL[2] between
adjacent rows
V DD

WL[3]

V bias

Pull-down loads

Digital Integrated Circuits2nd Slide 12 Semiconductor Memories

 MOS NOR ROM
V DD
Pull-up devices

WL[0]

GND
WL [1]

WL [2]

GND
WL [3]

BL [0] BL [1] BL [2] BL [3] Data read

Each row is a pseudo-NMOS (WLs are the inputs)!

Digital Integrated Circuits2nd Slide 13 Semiconductor Memories
 MOS NOR ROM Layout
Cell (9.5 x 7)
WL[0]

GND] Programmming using the

Active Layer Only
WL[1]

WL[2]
Polysilicon
GND] Metal1
WL[3] Diffusion

Metal1 on Diffusion

Digital Integrated Circuits2nd Slide 14 Semiconductor Memories

MOS NOR ROM Layout
Cell (11 x 7)

WL[0]
Programmming using
GND] the Contact Layer Only
WL[1]

WL[2] Polysilicon

GND] Metal1

WL[3]
Diffusion

Metal1 on Diffusion

Digital Integrated Circuits2nd Slide 15 Semiconductor Memories

 MOS NAND ROM
V DD
Pull-up devices

BL [0] BL [1] BL [2] BL [3]

WL [0]

WL [1]

WL [2]

WL [3]

All word lines high by default with exception of selected row

Digital Integrated Circuits2nd Slide 16 Semiconductor Memories

 MOS NAND ROM Layout
Cell (8 x 7)

Programmming using
the Metal-1 Layer Only

No contact to VDD or GND necessary;

drastically reduced cell size
Loss in performance compared to NOR ROM

Polysilicon

Diffusion

Metal1 on Diffusion

Digital Integrated Circuits2nd Slide 17 Semiconductor Memories

 NAND ROM Layout
Cell (5 x 6)

Programmming using
Implants Only

Polysilicon

Threshold-altering
implant
Metal1 on Diffusion

Digital Integrated Circuits2nd Slide 18 Semiconductor Memories

 Equivalent Transient Model for MOS NOR ROM
Model for NOR ROM V DD

BL
rword
WL Cbit

cword

Word line parasitics

 Wire capacitance and gate capacitance
 Wire resistance (polysilicon)

Bit line parasitics
 Resistance not dominant (metal)
 Drain and Gate-Drain capacitance

Digital Integrated Circuits2nd Slide 19 Semiconductor Memories

 Equivalent Transient Model for MOS NAND ROM

V DD
Model for NAND ROM
BL

CL
r bit

cbit
r word
WL

cword

Word line parasitics

 Similar to NOR ROM

Bit line parasitics
 Resistance of cascaded transistors dominates
 Drain/Source and complete gate capacitance

Digital Integrated Circuits2nd Slide 20 Semiconductor Memories

 Decreasing Word Line Delay
Driver
WL Polysilicon word line

Metal word line

(a) Driving the word line from both sides

Metal bypass

WL K cells Polysilicon word line

(b) Using a metal bypass

(c) Use silicides

Digital Integrated Circuits2nd Slide 21 Semiconductor Memories

 Precharged MOS NOR ROM
f V DD
pre

Precharge devices

WL [0]

GND
WL [1]

WL [2]
GND
WL [3]

BL [0] BL [1] BL [2] BL [3]

PMOS precharge device can be made as large as necessary,

but clock driver becomes harder to design.

Digital Integrated Circuits2nd Slide 22 Semiconductor Memories