----------------------------------------------------------------------------------

-- Company:
-- Engineer:
--
-- Create Date: 11:14:48 04/03/2017
-- Design Name:
-- Module Name: EX_ENCODER_4_2_USING_IF - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity EX_ENCODER_4_2_USING_IF is
PORT (
R : IN STD_LOGIC_VECTOR ;
CODE : OUT STD_LOGIC_VECTOR;
ACTIVE : OUT STD_LOGIC
);

end EX_ENCODER_4_2_USING_IF;

architecture Behavioral of EX_ENCODER_4_2_USING_IF is

begin
PROCESS (R)
BEGIN
IF R(3) = '1' THEN
CODE <= "11" ;
ELSIF R(2) ='1' THEN
CODE <= "10" ;
ELSIF R(1) = '1' THEN
CODE <= "01" ;
ELSE
CODE <= "00";
END IF;
END PROCESS;
ACTIVE <=R(3) OR R(2) OR R(1) OR R(0);
end Behavioral;

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:54:10 03/30/2017
-- Design Name:
-- Module Name: ALU_32_BITS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU_32_BITS is
 Port ( SRC0, SRC1 : in STD_LOGIC_VECTOR (31 downto 0);
CTRL : in STD_LOGIC_VECTOR (1 downto 0);
E, S : in STD_LOGIC;
RESULT : out STD_LOGIC_VECTOR (31 downto 0));
end ALU_32_BITS;

architecture Behavioral of ALU_32_BITS is

SIGNAL SIG0, SIG1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SRC0_I, SRC1_I : INTEGER;
SIGNAL SUM_I, DIFF_I, MODD_I, DIV_I : INTEGER;
SIGNAL SUM, DIFF, MODD, DIV : STD_LOGIC_VECTOR(31 DOWNTO 0);
begin
SRC0_I <= TO_INTEGER(UNSIGNED(SRC0));
SRC1_I <= TO_INTEGER(UNSIGNED(SRC1));
SUM_I <= SRC0_I + SRC1_I;
DIFF_I <= SRC0_I - SRC1_I;
MODD_I <= SRC0_I MOD SRC1_I;
DIV_I <= SRC0_I / SRC1_I;

SUM <= STD_LOGIC_VECTOR(TO_UNSIGNED(SUM_I, 32));

DIFF <= STD_LOGIC_VECTOR(TO_UNSIGNED(DIFF_I, 32));
MODD <= STD_LOGIC_VECTOR(TO_UNSIGNED(MODD_I, 32));
DIV <= STD_LOGIC_VECTOR(TO_UNSIGNED(DIV_I, 32));

SIG0 <= (OTHERS=>'1') WHEN S = '1' ELSE

(OTHERS=>'0');

WITH CTRL SELECT

SIG1 <= SUM WHEN "00",
DIFF WHEN "01",
 MODD WHEN "10",
DIV WHEN OTHERS;
RESULT <= SIG0 WHEN E = '0' ELSE
SIG1;
end Behavioral;

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:54:10 03/30/2017
-- Design Name:
-- Module Name: ALU_32_BITS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU_32_BITS is
Port ( SRC0, SRC1 : in STD_LOGIC_VECTOR (31 downto 0);
CTRL : in STD_LOGIC_VECTOR (1 downto 0);
E, S : in STD_LOGIC;
RESULT : out STD_LOGIC_VECTOR (31 downto 0));
end ALU_32_BITS;

architecture Behavioral of ALU_32_BITS is

SIGNAL SIG0, SIG1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SRC0_I, SRC1_I : INTEGER;
SIGNAL SUM_I, DIFF_I, MODD_I, DIV_I, MUL_I : INTEGER;
SIGNAL SUM, DIFF, MODD, DIV, MIN, NANDL, MUL : STD_LOGIC_VECTOR(31
DOWNTO 0);
begin
-- SRC0_I <= TO_INTEGER(UNSIGNED(SRC0));
-- SRC1_I <= TO_INTEGER(UNSIGNED(SRC1));
-- SUM_I <= SRC0_I + SRC1_I;
-- DIFF_I <= SRC0_I - SRC1_I;
-- MODD_I <= SRC0_I MOD SRC1_I;
-- DIV_I <= SRC0_I / SRC1_I;
-- MUL_I <= SRC0_I * SRC1_I;
--
-- SUM <= STD_LOGIC_VECTOR(TO_UNSIGNED(SUM_I, 32));
-- DIFF <= STD_LOGIC_VECTOR(TO_UNSIGNED(DIFF_I, 32));
-- MODD <= STD_LOGIC_VECTOR(TO_UNSIGNED(MODD_I, 32));
-- DIV <= STD_LOGIC_VECTOR(TO_UNSIGNED(DIV_I, 32));
-- MUL <= STD_LOGIC_VECTOR(TO_UNSIGNED(MUL_I, 32));
-- MIN <= SRC0 WHEN SRC0 < SRC1 ELSE
-- SRC1;
-- NANDL <= SRC0 NAND SRC1;
--
PROCESS(SRC0, SRC1, CTRL)
BEGIN
SRC0_I <= TO_INTEGER(UNSIGNED(SRC0));
SRC1_I <= TO_INTEGER(UNSIGNED(SRC1));
SUM_I <= SRC0_I + SRC1_I;
DIFF_I <= SRC0_I - SRC1_I;
MODD_I <= SRC0_I MOD SRC1_I;
DIV_I <= SRC0_I / SRC1_I;
MUL_I <= SRC0_I * SRC1_I;

SUM <= STD_LOGIC_VECTOR(TO_UNSIGNED(SUM_I, 32));

DIFF <= STD_LOGIC_VECTOR(TO_UNSIGNED(DIFF_I, 32));
MODD <= STD_LOGIC_VECTOR(TO_UNSIGNED(MODD_I, 32));
DIV <= STD_LOGIC_VECTOR(TO_UNSIGNED(DIV_I, 32));
MUL <= STD_LOGIC_VECTOR(TO_UNSIGNED(MUL_I, 32));
MIN <= SRC0 WHEN SRC0 < SRC1 ELSE
SRC1;
NANDL <= SRC0 NAND SRC1;
IF CTRL(4) = '1' THEN
RESULT <= SUM;
ELSIF CTRL(3) = '1' THEN
 RESULT <= DIFF;
ELSIF CTRL(2) = '1' THEN
RESULT <= MODD;
ELSIF CTRL(1 DOWNTO 0) = "00" THEN
RESULT <= DIV;
ELSIF CTRL(1 DOWNTO 0) = "01" THEN
RESULT <= MUL;
ELSIF CTRL(1 DOWNTO 0) = "10" THEN
RESULT <= MIN;
ELSE
RESULT <= NANDL;
END IF;
END PROCESS;
end Behavioral;

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:41:57 03/30/2017
-- Design Name:
-- Module Name: MUX_4_TO_1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MUX_4_TO_1 is
Port ( A, B, C, D : in STD_LOGIC;
S : in STD_LOGIC_VECTOR(1 DOWNTO 0);
Y : out STD_LOGIC);
end MUX_4_TO_1;

architecture Behavioral of MUX_4_TO_1 is

begin
PROCESS(A, B, C, D, S)
BEGIN
IF S = "00" THEN
Y <= A;
 ELSIF S = "01" THEN
Y <= B;
ELSIF S = "10" THEN
Y <= C;
ELSE
Y <= D;
END IF;
END PROCESS;

end Behavioral;

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:28 03/27/2017
-- Design Name:
-- Module Name: ENCODER_4_TO_2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ENCODER_4_TO_2 is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
CODE : out STD_LOGIC_VECTOR (1 downto 0);
ACTIVE : out STD_LOGIC);
end ENCODER_4_TO_2;

architecture Behavioral of ENCODER_4_TO_2 is

begin
PROCESS(I)
BEGIN
IF I(3) = '1' THEN
CODE <= "11";
ELSIF I(2) = '1' THEN
CODE <= "10";
ELSIF I(1) = '1' THEN
CODE <= "01";
 ELSIF I(0) = '1' THEN
CODE <= "00";
ELSE
CODE <= "00";
END IF;
ACTIVE <= I(3) OR I(2) OR I(1) OR I(0);
END PROCESS;

end Behavioral;