Code VHDL - [expand]

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--Program for HAMMING CODE TRANSMISSION & RECEPTION .
-- ( generating Hamming code parellely , ssending it serially &
-- receiving it parallely for error detecttion & correction.)
--(IMPORTANT:- ASSIGN THAT PIN OF THE CPLDD TO THE CLK I/P BY WHICH YOU CAN TOGG
LE THE
-- CLOCK WITH A SWITCH PROVIDED ON THE CPLLD BOARD.)

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity hammgen is
port (
d: in STD_LOGIC_VECTOR (3 downto 0); -- i/p message bits
clk:in STD_LOGIC; -- Clock i/p
ten:in STD_LOGIC; -- transmitter-enable(Mux enable)
err:in STD_LOGIC; -- error introducing i/p
ren:in STD_LOGIC; -- receiver-enable(Demux enable)
dh: out STD_LOGIC_VECTOR (7 downto 1); --Detected & corrected Hamming code.
error:out STD_LOGIC_VECTOR (6 downto 0) -- 7-segment o/p for displaying error.
);
end hammgen;
architecture hammgen_arch of hammgen is
signal h: STD_LOGIC_VECTOR (7 downto 1);
signal mh :STD_LOGIC;
signal dmh:STD_LOGIC_VECTOR(7 downto 1);
signal sipoh: STD_LOGIC_VECTOR (7 downto 1);
signal ripoh: STD_LOGIC_VECTOR (7 downto 1);
signal sum1 : STD_LOGIC;
signal sum2 : STD_LOGIC;
signal sum4 : STD_LOGIC;
signal p1 : STD_LOGIC;
signal p2: STD_LOGIC;
signal p4 : STD_LOGIC;
signal en: STD_LOGIC_VECTOR (7 downto 1);
signal sum5: STD_LOGIC;
signal sum6: STD_LOGIC;
signal sum8: STD_LOGIC;
signal y: STD_LOGIC_VECTOR (7 downto 0);
signal countx:STD_LOGIC_VECTOR (2 downto 0);
signal countr:STD_LOGIC_VECTOR (2 downto 0);

begin
-- Program module for HAMMING CODE GENERATTION .
process (sum1,sum2,sum4,p1,p2,p4,d)
begin
sum1<=d(0) xor d(1) xor d(3); -- Parity bits are found here.
sum2<=d(0) xor d(2) xor d(3);
sum4<=d(1) xor d(2) xor d(3);
if sum1='0' then
p1<='0';
else
p1<='1';
end if;
if sum2='0' then
p2<='0';
else
p2<='1';
end if;
if sum4='0' then
p4<='0';
else
p4<='1';
end if;
end process;
h(1)<=p1; --The parity bits found out in the above process block
h(2)<=p2; -- are put in a register 'h'(declared as signal).
h(3)<=d(0);
h(4)<=p4;
h(5)<=d(1);
h(6)<=d(2);
h(7)<=d(3);
-- Program module for Mux & xmit count & iintroducing error.
process (clk,countx,ten) -- A 3-bit up counter o/p (countx) is connected
begin -- to the Select lines of the Mux which will
if clk 'event and clk='1' then -- increment the ststus of the Select line
s
if ten='1' then -- automatically .
if (countx <"111"or countx="111") then
countx<=countx+1;
else
countx<="000";
end if;
else
countx<="ZZZ";
end if;
end if;
end process;
process(countx,clk,h,err,mh) -- In this part the Hamming code bits are sent
begin -- thro' the Mux . If the err i/p is =1 error
if clk'event and clk='1' then -- is introduced in the hamming code bit
(means
case countx is -- that bit is complemented.)
when "000"=> -- mh is Mux o/p.
if err='0' then
mh<=h(7);
else
mh<=not h(7);
end if;
when "001"=>mh<=h(6);
if err='0' then
mh<=h(6);
else
mh<=not h(6);
end if;
when "010"=>mh<=h(5);
if err='0' then
mh<=h(5);
else
mh<=not h(5);
end if;
when "011"=>mh<=h(4);
if err='0' then
mh<=h(4);
else
mh<=not h(4);
end if;
when "100"=>mh<=h(3);
if err='0' then
mh<=h(3);
else
mh<=not h(3);
end if;
when "101"=>mh<=h(2);
if err='0' then
mh<=h(2);
else
mh<=not h(2);
end if;
when "110"=>mh<=h(1);
if err='0' then
mh<=h(1);
 else
mh<=not h(1);
end if;
when others=>Null;
end case;
end if;
end process;
-- Program module for De-mux & rec. count .
process(ren,clk,countr,mh) --process(r,clk,ren,ch,countr)
begin
if clk 'event and clk='1' then -- A 3 bit counter o/p
if ren='1' then -- similar to the mux,
if ( countr<"111"or countr="111" ) then -- is given to the select
countr<=countr+1; -- lines.
dmh<=mh&dmh(7 downto 2) ; -- Here serial to parellel
else -- conversion of the received
countr<="000"; -- serial hamming code from the
-- mux(i.e. mh signal), is made.
end if; --(Shift register concept)
else
countr<="ZZZ";
dmh<="ZZZZZZZ";
end if;
end if;
end process;
sipoh<=dmh; -- When the serial data (mh) is shifted to make it parallel
-- the MSB goes into the LSB position. So the shifted bits
-- of dmh(Demux o/p) which are stored in ssipoh register
ripoh(7)<=sipoh(1); -- (declared as signal) are put into the ripoh register
ripoh(6)<=sipoh(2); -- (declared as signal) in reverse order.
ripoh(5)<=sipoh(3);
ripoh(4)<=sipoh(4);
ripoh(3)<=sipoh(5);
ripoh(2)<=sipoh(6);
ripoh(1)<=sipoh(7);
-- Program for HAMMING CODE DETECTION .
sum5<=ripoh(1) xor ripoh(3) xor ripoh(5) xor ripoh(7); -- Error detection part
sum6<=ripoh(2) xor ripoh(3) xor ripoh(6) xor ripoh(7);
sum8<=ripoh(4) xor ripoh(5) xor ripoh(6) xor ripoh(7);

y(0)<=not sum8 and not sum6 and not sum5; -- Decoder is used to decode
y(1)<=not sum8 and not sum6 and sum5; -- the position of the bit in error.
y(2)<=not sum8 and sum6 and not sum5;
y(3)<=not sum8 and sum6 and sum5;
y(4)<= sum8 and not sum6 and not sum5;
y(5)<= sum8 and not sum6 and sum5;
y(6)<= sum8 and sum6 and not sum5;
y(7)<= sum8 and sum6 and sum5;

en(1)<=y(1); -- The decoder o/p lines are given to the

en(2)<=y(2); -- enable (en, which is declared as a signal) i/p
en(3)<=y(3); -- of an inverter so as to complement the bit in
en(4)<=y(4); -- in error. Complementing is done in the next
en(5)<=y(5); -- process block .
en(6)<=y(6);
en(7)<=y(7);
process( en,ripoh)
begin
case en is
-- 7654321
when "0000001"=>dh<=ripoh(7 downto 2)& not ripoh(1); -- Only the bit in error is
complemented
when "0000010"=>dh<=ripoh(7 downto 3)& not ripoh(2)& ripoh(1); -- Rest are kept
unchanged.
when "0000100"=>dh<=ripoh(7 downto 4)& not ripoh(3)& ripoh(2 downto 1);
when "0001000"=>dh<=ripoh(7 downto 5)& not ripoh(4)&ripoh(3 downto 1);
when "0010000"=>dh<=ripoh(7 downto 6 )& not ripoh(5)& ripoh(4 downto 1);
when "0100000"=>dh<=ripoh(7)& not ripoh(6)& ripoh(5 downto 1) ;
when "1000000"=>dh<=not ripoh(7)&ripoh(6 downto 1);
when "0000000"=>dh<=ripoh;
when others=>Null;
end case;
end process;