DSA2AE0000121

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
October 1995
– PRELIMINARY –
Edition 1.0
PRODUCT PROFILE SHEET
MB8118165A-60/-70
CMOS 1M X 16BIT HYPER PAGE MODE DYNAMIC RAM
CMOS 1,048,576 x 16BIT Hyper Page Mode Dynamic RAM
The Fujitsu MB8118165A is a fully decoded CMOS Dynamic RAM (DRAM) that contains
16,777,216 memory cells accessible in 16-bit increments. The MB8118165A features a ”hyper
page” mode of operation whereby high-speed random access of up to 1,024-bits of data within
the same row can be selected. The MB8118165A DRAM is ideally suited for mainframe,
buffers, hand-held computers video imaging equipment, and other memory applications where
very low power dissipation and high bandwidth are basic requirements of the design. Since the
standby current of the MB8118165A is very small, the device can be used as a non-volatile
memory in equipment that uses batteries for primary and/or auxiliary power.
The MB8118165A is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer
polysilicon and two-layer aluminum process. This process, coupled with advanced stacked
capacitor memory cells, reduces the possibility of soft errors and extends the time interval
between memory refreshes. Clock timing requirements for the MB8118165A are not critical
and all inputs are TTL compatible.
Plastic SOJ Package

PRODUCT LINE & FEATURES (LCC-42P-M01)
Parameter MB8118165A–60 MB8118165A–70
RAS Access Time 60ns max. 70ns max.

Random Cycle Time 104ns min. 124ns min.
Address Access Time 30ns max. 35ns max.
CAS Access Time 15ns max. 17ns max.
Hyper Page Mode Cycle Time 25ns min. 30ns min.
Low Pow- Operating current 880mW max. 825mW max.

er
Dissipation Standby current 11mW max. (TTL level) / 5.5mW max. (CMOS level)
• 1,048,576 words × 16 bit organization • Early write or OE controlled write capability

• Silicon gate, CMOS, Advanced stacked • RAS only, CAS-before-RAS, or Hidden Plastic TSOP Packages
Capacitor Cell Refresh (FPT-50P-M06)
• All input and output are TTL compatible • Hyper page mode, Read-Modify-Write (Normal Bend)
• 1,024 refresh cycles every 16.4ms capability
• Self refresh function • On chip substrate bias generator for high
performance
ABSOLUTE MAXIMUM RATINGS (see NOTE)

Parameter Symbol Value Unit Package and Ordering Information
Voltage at any pin relative to VSS VIN, VOUT –0.5 to + 7.0 V
 42-pin plastic (400mil) SOJ,
order as MB8118165A-××PJ
Voltage of VCC supply relative to VSS VCC –0.5 to + 7.0 V
 50-pin plastic (400mil) TSOP-II
Power Dissipation PD 1.0 W with normal bend leads,
order as MB8118165A-××PFTN
Short Circuit Output Current IOUT –50 to + 50 mA
Operating Temperature TOPE 0 to 70 °C
Storage Temperature TSTG –55 to +125 °C
This device contains circuitry to protect the inputs against
NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings damage due to high static voltages or electric fields. However,
are exceeded. Functional operation should be restricted to the conditions as it is advised that normal precautions be taken to avoid
detailed in the operational sections of this data sheet. Exposure to absolute application of any voltage higher than maximum rated voltages
maximum rating conditions for extended periods may affect device reliability. to this high impedance circuit.
Copyright 1995 by FUJITSU LIMITED

1
– PRELIMINARY –
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Edition 1.0
MB8118165A-60
MB8118165A-70
Fig. 1 – MB8118165A DYNAMIC RAM – BLOCK DIAGRAM
RAS
UCAS Clock
Gen #1
LCAS
Write
Clock WE
Gen
Mode
Control
Clock
Gen #2
Data In
A0 Buffer
A1
A2 Column
Decoder
A3 DQ1 to
DQ16
Address Sense Amp &
A4
Buffer I/O Gate
&
A5
Pre-
Decoder
A6
A7 Row 16,777,216 Bit

Decoder Storage Data Out
A8 Cell Buffer
A9
OE
Refresh
Address Substrate
Counter Bias Gen VCC
VSS
CAPACITANCE (TA = 25°C, f = 1MHz)

Parameter Symbol Max Unit
Input Capacitance, A0 to A9 CIN1 5 pF
Input Capacitance, RAS, LCAS, UCAS, WE, OE CIN2 5 pF
Input/Output Capacitance, DQ1 to DQ16 CDQ 7 pF
2
– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
PIN ASSIGNMENTS AND DESCRIPTIONS
42-Pin SOJ
(TOP VIEW)
VCC 1 42 VSS
DQ1 2 41 DQ16 Designator Function
DQ2
3 1 Pin Index 40 DQ15
DQ3 DQ14 A0 to A9 Address inputs
4 39
row : A0 to A9
DQ4 5 38 DQ13
column : A0 to A9
VCC 6 37 VSS
refresh : A0 to A9
DQ5 7 36 DQ12
DQ6
8 35 DQ11 RAS Row address strobe
DQ7 9 34 DQ10
DQ8 10 33 DQ9 LCAS Lower column address strobe
NC. 11 32 NC.
NC. LCAS UCAS Upper column address strobe
12 31
WE 13 30 UCAS
WE Write enable
RAS 14 29 OE
N.C. 15 28 A9 OE Output enable
N.C. 16 27 A8
A0 17 26 A7 DQ1 to DQ16 Data Input/Output
A1 18 25 A6
A2 A5 VCC +5.0 volt power supply
19 24
A3 A4
20 23 Circuit ground
VSS
VCC 21 22 VSS
N.C. No connection
50-Pin TSOP
(TOP VIEW)
VCC 1 50 VSS
DQ1 2 49 DQ16
DQ2
3 1 Pin Index 48 DQ15
DQ3 4 47 DQ14
DQ4 5 46 DQ13
VCC 6 45 VSS
DQ5 7 44 DQ12
DQ6 DQ11
8 43
DQ7 9 42 DQ10
DQ8 10 41 DQ9
NC. 11 40 NC.
NC. NC.
15 36
NC. LCAS
16 35
WE 17 34 UCAS
RAS 18 33 OE
N.C. 19 32 A9
N.C. A8
20 31
A0 A7
21 30
A1 22 29 A6
A2 23 28 A5
A3 24 27 A4
VCC 25 26 VSS
3
– PRELIMINARY –
MB8118165A-60
MB8118165A-70
RECOMMENDED OPERATING CONDITIONS

Parameter Notes Symbol Min Typ Max Unit Ambient
Operating Temp.
VCC 4.5 5.0 5.5

Supply Voltage 1 V
VSS 0 0 0
0°C to +70°C
Input High Voltage, all inputs 1 VIH 2.4  6.5 V
Input High Voltage, all inputs/outputs∗ 1 VIL –0.3  0.8 V
∗ : Undershoots of up to –2.0 volts with a pulse width not exceeding 20ns are acceptable.
FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty input bits are required to decode any sixteen of 16,777,216 cell addresses in the memory matrix. Since only ten address bits (A0 to A9) are
available, the column and row inputs are separately strobed by LCAS or UCAS and RAS as shown in Figure 1. First, ten row address bits are input on
pins A0–through–A9 and latched with the row address strobe (RAS) then, ten column address bits are input and latched with the column address
strobe (LCAS or UCAS). Both row and column addresses must be stable on or before the falling edges of RAS and LCAS or UCAS, respectively.
The address latches are of the flow-through type; thus, address information appearing after tRAH (min) + tT is automatically treated as the column ad-
dress.
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated; when WE is High, a read cycle is se-
lected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of three basic ways : an early write cycle, an OE (delayed) write cycle, and a read-modify-write cycle. The
falling edge of WE or LCAS / UCAS, whichever is later, serves as the input data-latch strobe. In an early write cycle, the input data of DQ1-DQ8 is
strobed by LCAS and DQ9-DQ16 is strobed by UCAS and the setup/hold times are referenced to each LCAS and UCAS because WE goes Low be-
fore LCAS / UCAS. in a delayed write or a read-modify-write cycle, WE goes Low after LCAS / UCAS; thus, input data is strobed by WE and all setup/
hold times are referenced to the write-enable signal.
DATA OUTPUT
The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical to that of the input; the output buffers
remain in the high-impedance state until the column address strobe goes Low. When a read or read-modify-write cycle is executed, valid outputs
and High-Z state are obtained under the following conditions:
tRAC : from the falling edge of RAS when tRCD (max) is satisfied.
tCAC : from the falling edge of LCAS (for DQ1–DQ8) UCAS (for DQ9–DQ16) when tRCD is greater than tRCD (max).
tAA : from column address input when tRAD is greater than tRAD (max), and tRCD (max.) is satisfied.
tOEA : from the falling edge of OE when OE is brought Low after tRAC, tCAC, or tAA.
tOEZ : from OE inactive.
tOFF : from CAS inactive while RAS inactive.
tOFR : from RAS inactive while CAS inactive.
tWEZ : from WE active while CAS inactive.
The data remains valid after either OE is inactive, or both RAS and LCAS (and/or UCAS) are inactive, or CAS is reactived. When an early write is ex-
ecuted, the output buffers remain in a high-impedance state during the entire cycle.
HYPER PAGE MODE OPERATION

The hyper page mode operation provides faster memory access and lower power dissipation. The hyper page mode is implemented by keeping the
same row address and strobing in successive column addresses. To satisfy these conditions, RAS is held Low for all contiguous memory cycles in
which row addresses are common. For each page of memory (within column address locations), any of 1,024x16-bits can be accessed and, when
multiple MB8118165As are used, CAS is decoded to select the desired memory page. Hyper page mode operations need not be addressed se-
quentially and combinations of read, write, and/or read-modify-write cycles are permitted. Hyper page mode features that output remains valid when
CAS is inactive until CAS is reactivated.
4
– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted) Notes 3
Value
Parameter Notes Symbol Conditions Unit
Min Typ Max
Output high voltage 1 VOH IOH = –5.0mA 2.4  
V
Output low voltage 1 VOL IOL = +4.2mA   0.4
0V ≤ VIN ≤ VCC;
Input leakage current (any input) II(L) 4.5V ≤ VCC ≤ 5.5V; –10  10
VSS = 0V; All other pins
not under test = 0V µA
Output leakage current IDO(L) 0V ≤ VOUT ≤ VCC; –10  10

Data out disabled
Operating current MB8118165A-60 160

RAS & LCAS, UCAS cycling;
(Average power ICC1 tRC = min   mA
supply current) 2 MB8118165A-70 150
Standby current TTL level RAS = LCAS = UCAS = VIH 2.0

(Power supply ICC2   mA
current) CMOS level RAS = LCAS = UCAS ≥ VCC–0.2V 1.0
Refresh current #1 MB8118165A-60 160

LCAS = UCAS = VIH, RAS cycling;
(Average power ICC3 tRC = min   mA
supply current) 2 MB8118165A-70 150
MB8118165A-60 100
Hyper Page Mode RAS = VIL, LCAS = UCAS cycling;
Current ICC4 tHPC = min   mA
2 MB8118165A-70 90
Refresh current #2 MB8118165A-60 RAS cycling; 160

(Average power ICC5 CAS-before-RAS;   mA
supply current) 2 MB8118165A-70 tRC = min 150
Refresh current #3 MB8118165A-60

RAS = VIL, CAS = VIL
(Average power I CC9 Self refresh ;   1000 µA
supply current) tRASS = min.
MB8118165A-70
5
– PRELIMINARY –
MB8118165A-60
MB8118165A-70
AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Notes 3,4,5
MB8118165A-60 MB8118165A-70
No. Parameter Notes Symbol Unit
Min Max Min Max
1 Time Between Refresh tREF  16.4  16.4 ms
2 Random Read/Write Cycle Time tRC 104  124  ns
3 Read-Modify-Write Cycle Time tRWC 138  162  ns
4 Access Time from RAS 6,9 tRAC  60  70 ns
5 Access Time from CAS 7,9 tCAC  15  17 ns
6 Column Address Access Time 8,9 tAA  30  35 ns
7 Output Hold Time tOH 3  3  ns
8 Output Hold Time from CAS tOHC 5  5  ns
9 Output Buffer Turn On Delay Time tON 0  0  ns
10 Output Buffer Turn Off Delay Time 10 tOFF  15  17 ns

11 Output Buffer Turn Off Delay Time from RAS 10 tOFR  15  17 ns
12 Output Buffer Turn Off Delay Time from WE 10 tWEZ  15  17 ns
13 Transition Time tT 1 50 1 50 ns
14 RAS Precharge Time tRP 40  50  ns
15 RAS Pulse Width tRAS 60 100000 70 100000 ns
16 RAS Hold Time tRSH 15  17  ns
17 CAS to RAS Precharge Time 21 tCRP 5  5  ns
18 RAS to CAS Delay Time 11,12,22 tRCD 14 45 14 53 ns
19 CAS Pulse Width tCAS 10  13  ns
20 CAS Hold Time tCSH 40  50  ns
21 CAS Precharge Time (Normal) 19 tCPN 10  10  ns
22 Row Address Set Up Time tASR 0  0  ns
23 Row Address Hold Time tRAH 10  10  ns
24 Column Address Set Up Time tASC 0  0  ns
25 Column Address Hold Time tCAH 10  10  ns
26 Column Address Hold Time from RAS tAR 24  24  ns
27 RAS to Column Address Delay Time 13 tRAD 12 30 12 35 ns
28 Column Address to RAS Lead Time tRAL 30  35  ns
29 Column Address to CAS Lead Time tCAL 23  28  ns
30 Read Command Set Up Time tRCS 0  0  ns

Read Command Hold Time
31 Referenced to RAS
14 tRRH 0  0  ns
Read Command Hold Time

32 Referenced to CAS
14 tRCH 0  0  ns
33 Write Command Set Up Time 15, 20 tWCS 0  0  ns
34 Write Command Hold Time tWCH 10  10  ns
35 Write Hold Time from RAS tWCR 24  24  ns
6
– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
AC CHARACTERISTICS (Continued)
(At recommended operating conditions unless otherwise noted.) Notes 3,4,5
MB8118165A-60 MB8118165A-70
No. Parameter Notes Symbol Unit
Min Max Min Max
36 WE Pulse Width tWP 10  10  ns
37 Write Command to RAS Lead Time tRWL 15  17  ns
38 Write Command to CAS Lead Time tCWL 10  13  ns
39 DIN Set Up Time tDS 0  0  ns
40 DIN Hold Time tDH 10  10  ns
41 Data Hold Time from RAS tDHR 24  24  ns
42 RAS to WE Delay Time 20 tRWD 77  89  ns
43 CAS to WE Delay Time 20 tCWD 32  36  ns
44 Column Address to WE Delay Time 20 tAWD 47  54  ns

RAS Precharge Time to CAS
45 Active Time (Refresh cycles)
tRPC 5  5  ns
CAS Set Up Time for CAS-before-

46 RAS Refresh
tCSR 0  0  ns
CAS Hold Time for CAS-before-

47 RAS Refresh
tCHR 10  12  ns
48 Access Time from OE 9 tOEA  15  17 ns

Output Buffer Turn Off Delay
49 from OE
10 tOEZ  15  17 ns
50 OE to RAS Lead Time for Valid Data tOEL 10  10  ns
51 OE to CAS Lead Time tCOL 5  5  ns
52 OE Hold Time Referenced to WE 16 tOEH 5  5  ns

53 OE to Data In Delay Time tOED 15  17  ns
54 RAS to Data In Delay Time tRDD 15  17  ns
55 CAS to Data In Delay Time tCDD 15  17  ns
56 DIN to CAS Delay Time 17 tDZC 0  0  ns
57 DIN to OE Delay Time 17 tDZO 0  0  ns
58 OE Precharge Time tOEP 8  8  ns

59 OE Hold Time Referenced to CAS tOECH 10  10  ns
60 WE Precharge Time tWPZ 8  8  ns
61 WE to Data In Delay Time tWED 15  17  ns
62 Hyper Page Mode RAS Pulse Width tRASP  100000  100000 ns
Hyper Page Mode Read/Write
63 Cycle Time
tHPC 25  30  ns
Hyper Page Mode Read-Modify-Write

64 Cycle Time
tHPRWC 69  79  ns
65 Access Time from CAS Precharge 9,18 tCPA  35  40 ns
66 Hyper Page Mode CAS Precharge Time tCP 10  10  ns

Hyper Page Mode RAS Hold Time
67 from CAS Precharge
tRHCP 35  40  ns
Hyper Page Mode CAS Precharge

68
to WE Delay Time
20 tCPWD 52  59  ns
7
– PRELIMINARY –
MB8118165A-60
MB8118165A-70
Notes:
1. Referenced to VSS. 12. tRCD (min) = tRAH (min) + 2tT + tASC (min).
2. ICC depends on the output load conditions and cycle rates; The 13. Operation within the tRAD (max) limit ensures that tRAC (max)
specified values are obtained with the output open. can be met. tRAD (max) is specified as a reference point only;
ICC depends on the number of address change as RAS = VIL if tRAD is greater than the specified tRAD (max) limit, access
UCAS=VIH, LCAS=VIH and VIL > –0.3V. tome is controlled exclusively by tCAC or tAA.
ICC1, ICC3 ICC4 and ICC5 are specified at one time of address 14. Either tRRH or tRCH must be satisfied for a read cycle.
change during RAS = VIL and UCAS = VIH, LCAS = VIH. 15. tWCS is specified as a reference point only. If tWCS ≥ tWCS (min)
ICC2 is specified during RAS = VIH and VIL > –0.3V. the data output pin will remain High-Z state through entire
3. An initial pause (RAS = CAS = VIH) of 200µs is required after cycle.
power-up followed by any eight RAS–only cycles before proper 16. Assumes that tWCS < tWCS (min).
device operation is achieved. In case of using internal refresh 17. Either tDZC or tDZO must be satisfied.
counter, a minimum of eight CAS-before-RAS initialization 18. tCPA is access time from the selection of a new column address
cycles instead of 8 RAS cycles are required. (that is caused by changing both UCAS and LCAS from ”L” to
4. AC characteristics assume tT = 2ns. ”H”). Therefore, if tCP is long, tCPA is longer than tCPA (max).
5. VIH (min) and VIL (max) are reference levels for measuring tim- 19. Assumes that CAS-before-RAS refresh.
ing of input signals. Also transition times are measured be- 20. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating
tween VIH (min) and VIL (max). parameters. They are included in the data sheet as an electrical
6. Assumes that tRCD ≤ tRCD (max), tRAD ≤ tRAD (max). If tRCD is characteristic only. If tWCS ≥ tWCS (min), the cycle is an early
greater than the maximum recommended value shown in this write cycle and DOUT pin will maintain high impedance state
table, tRAC will be increased by the amount that tRCD exceeds through out the entire cycle. If tCWD ≥ tCWD (min), tRWD ≥ tRWD
the value shown. Refer to Fig.2 and 3. (min), tAWD ≥ tAWD (min) and tCPWD ≥ tCPWD (min) the cycle is a
7. If tRCD ≥ tRCD (max), tRAD ≥ tRAD (max), and tASC ≥ tAA read-modify-write cycle and data from the selected cell will
–tCAC– tT, access time is tCAC. appear at the DOUT pin.
8. If tRAD ≥ tRAD (max) and tASC ≤ tAA –tCAC– tT, access time is tAA. If neither of the above conditions is satisfied, the cycle is a
9. Measured with a load equivalent to two TTL loads and 50pF. delayed write cycle and invalid data will appear the DOUT pin,
10. tOFF, tOFR, tWEZ and tOEZ are specified that output buffer change and write operation can be executed by satisfying tRWL, tCWL,
to high mpedance state. and tRAL specifications.
11. Operation within the tRCD (max) limit ensures that tRAC (max) 21. The last CAS rising edge.
can be met. tRCD (max) is specified as a reference point only; 22. The first CAS falling edge.
if tRCD is greater than the specified tRCD (max) limit, access time
is controlled exclusively by tCAC or tAA.
8
– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
Fig. 2 – tRAC vs. tRCD Fig. 3 – tRAC vs. tRAD Fig. 4 – tCPA vs. tCP
tRAC (ns) tCPA (ns)
tRAC (ns)
90 70
120
80 60
100
70ns version
80 70 50
70ns version
60ns version 70ns version
60ns version
60 60 40
60ns version
40 50 30
0 20 40 60 80 100 0 10 20 30 40 50 60 0 10 20 30 40 50
tRCD (ns) tRAD (ns) tCP (ns)
FUNCTIONAL TRUTH TABLE

Clock Input Address Input/Output Data
Operation Mode DQ1 to DQ8 DQ9 to DQ16 Refresh Note
RAS LCAS UCAS WE OE Row Column
Input Output Input Output
Standby H H H X X – – – High-Z – High-Z –
L H Valid High-Z
Read Cycle L H L H L Valid Valid – High-Z – Valid Yes∗ tRCS ≥ tRCS
L L Valid Valid (min)
L H Valid –
Write Cycle
(Early Write)
L H L L X Valid Valid – High-Z Valid High-Z Yes∗ tWCS ≥ tWCS
L L Valid Valid (min)
Read-Modify- L H Valid Valid – High-Z

Write Cycle L H L H L L H Valid Valid – High-Z Valid Valid Yes∗
L L Valid Valid Valid Valid
RAS-only Yes
L H H X X Valid – – High-Z – High-Z
Refresh Cycle
CAS-before-RAS
Refresh L L L X X – – – High-Z – High-Z Yes tCSR ≥ tCSR
Cycle (min)
L H Valid High-Z Previous data
Hidden Refresh – Yes
H L H L H X L – – – High-Z Valid is kept
Cycle
L L Valid Valid
X; ”H” or ”L”
∗; It is impossible in Hyper Page Mode.
9
– PRELIMINARY –
MB8118165A-60
MB8118165A-70
Fig. 5 – READ CYCLE
tRC
tRAS
VIH tAR
RAS
VIL
tCRP
tCSH tRP
tRCD tRSH
LCAS VIH tCAS

or
VIL tRAD
UCAS
tCDD
tRAL
tRAH tCAL
tASR tASC tCAH tOEL
tRDD
tCOL
VIH
A0 to A9 ROW ADD COLUMN ADD
VIL
tRRH
tRCS
tRCH tWPZ
VIH
WE tAA
VIL
tCAC tWED
tOH tWEZ
tRAC
tOFF
DQ VOH
HIGH-Z
(Output) V
OL
tDZC tON
tOEZ
VIH tOEA
DQ
(Input) HIGH-Z
VIL
tOH
tDZO tON
tOED
VIH
OE
VIL
”H” or ”L”
Valid Data
DESCRIPTION
To implement a read operation, a valid address is latched by the RAS and LCAS or UCAS address strobes and with WE set to a High level and
OE set to a low level, the output is valid once the memory access time has elapsed. DQ8–DQ16 pins is valid when RAS and CAS are High or
until OE goes High. The access time is determined by RAS(tRAC), LCAS/UCAS(tCAC), OE(tOEA) or column addresses (tAA) under the follow-
ing conditions:
If tRCD > tRCD(max), access time = tCAC.

If tRAD > tRAD(max), access time = tAA
If OE is brought Low after tRAC, tCAC, or tAA(whichever occurs later), access time = tOEA.
However, if either LCAS/UCAS or OE goes High, the output returns to a high-impedance state after tOH is satisfied.
10
– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
Fig. 6 – EARLY WRITE CYCLE
tRC
tRAS
VIH
RAS
VIL
tCRP
tCSH tRP
tRCD tRSH
tCAS
LCAS VIH
or
VIL
UCAS
tAR
tASR tRAH tASC tCAH
VIH
A0 to A9 ROW ADD COLUMN ADD
VIL
tWCR
tWCS
tWCH
VIH
WE
VIL
tDHR
tDS tDH
DQ VIH
VALID DATA IN
(Input) VIL
DQ VOH
HIGH-Z
(Output) V
OL
”H” or ”L”
DESCRIPTION
A write cycle is similar to a read cycle except WE is set to a Low state and OE is an ”H” or ”L” signal. A write cycle can be implemented in either
of three ways – early write, delayed write, or read-modify-write. During all write cycles, timing parameters tRWL, tCWL, tRAL and tCAL must be
satisfied. In the early write cycle shown above tWCS satisfied, data on the DQ pins are latched with the falling edge of LCAS or UCAS and writ-
ten into memory.
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MB8118165A-60
MB8118165A-70
Fig. 7 – DELAYED WRITE CYCLE (OE CONTROLLED)
tRC
tRAS
VIH tAR
RAS
VIL
tRP
tCSH
tCRP tRCD tCAS
tRSH
LCAS VIH
or
VIL
UCAS
tASR tRAH tASC tCAH
VIH ROW COL

A0 to A9 ADD ADD
VIL
tRCS tCWL
tWCH
tRWL
tWP
VIH
WE
VIL
tDS
tDZC tDH
DQ VIH VALID
HIGH-Z
(Input) VIL DATA IN
tOED
tON
DQ VOH
HIGH-Z HIGH-Z
(Output) V
OL
tDZO tON tOEH
tOEZ
VIH
OE
VIL
”H” or ”L”
Invalid Data
DESCRIPTION
In the delayed write cycle, tWCS is not satisfied; thus, the data on the DQ pins is latched with the falling edge of WE and written into memory.
The Output Enable (OE) signal must be changed from Low to High before WE goes Low (tOED + tT + tDS).
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– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
Fig. 8 – READ-MODIFY-WRITE-CYCLE
tRWC
tRAS
VIH
RAS
VIL
tAR tRP
tCRP
tRCD
LCAS VIH
or
VIL tRAD
UCAS
tASR tRAH tASC
tCAH
VIH ROW COL

A0 to A9 ADD ADD
VIL
tRWD tCWL
tRCS tAWD tRWL
tCWD
VIH
WE
VIL
tDS tWP
tDZC tDH
DQ VIH HIGH-Z VALID

(Input) tOED DATA IN
VIL
tCAC tOEH
tAA
tRAC
VOH
DQ HIGH-Z HIGH-Z
VALID
(Output) VOL
tON
tOEA
tDZO tON
tOEZ
VIH
OE
VIL
tOH
”H” or ”L”
DESCRIPTION
The read-modify-write cycle is executed by changing WE from High to Low after the data appears on the DQ pins. In the read-modify-write
cycle, OE must be changed from Low to High after the memory access time.
13
– PRELIMINARY –
MB8118165A-60
MB8118165A-70
Fig. 9 – HYPER PAGE MODE READ CYCLE
tRASP
tRCD
tRHCP
VIH
RAS
VIL
tRAD tHPC tRP
tCRP tRSH
tCSH tCP
tCAS tCAS
tCAS
LCAS VIH
or tRDD
VIL
UCAS tCAH tRRH
tASR tAR tASC tCAH
tASC tASC
tRAH
tCAH tRAL
VIH ROW COL COL COL

A0 to A9 ADD ADD ADD ADD
VIL
tRCS tRCH
tRCS tRCH tRCS tRCH
VIH
WE
VIL
tCPA tCPA tOH
tDZC
tCDD
tOHC
DQ VIH
HIGH-Z
(Input)
VIL tDZO tOFR
tCAC tCAC tON tOFF
tOHC tOH
tON tON
tRAC tOFF
DQ VOH
HIGH-Z
(Output) VOL
tAA
tAA tOH
tOEZ
tOED
VIH
OE
VIL
During one cycle is achieved, the input/output timing apply the same manner as the former cycle.
”H” or ”L”
Valid Data
DESCRIPTION
The hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address.
This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level during all successive
memory cycles in which the row address is latched. The address time is determined by tCAC, tAA, tCPA, or tOEA, whichever one is the latest in
occurring.
14
– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
Fig. 10 – HYPER PAGE MODE READ CYCLE (OE = ”H” or ”L”)
tRASP
tRCD
tRHCP
VIH
RAS
VIL
tRAD tAR tHPC tRP
tCRP tRSH
tCSH tCP tCP
tCAS tCAS tRRH
tCAS
LCAS VIH
or
VIL
UCAS tCAH
tASR tCAL tASC tCAH
tASC tASC tCDD
tRAH
tCAH tRAL
VIH ROW COL COL COL

VIL
tRDD
tRCS tRCH
VIH
WE
VIL
tOH
tDZC
tOHC tOFR
tOH
DQ VIH HIGH-Z HIGH-Z
(Input)
VIL
tCPA tCPA
tRAC tAA tAA tOFF
tAA tCAC
ÍÍ
tCAC tCAC
ÍÍ
DQ VOH
HIGH-Z
ÍÍ
(Output) V
OL
tOH tOECH tOH
tON tON
tOEZ
tOEZ tOH tOED
tDZO tOEP tOEA
VIH tOEA tCOL
OE
VIL tOEA
tOEZ
During one cycle is achieved, the input/output timing apply the same manner as the former cycle. ”H” or ”L”
Valid Data
DESCRIPTION
occurring.
15
– PRELIMINARY –
MB8118165A-60
MB8118165A-70
Fig. 11 – HYPER PAGE MODE READ CYCLE (WE = ”H” or ”L”)
tRASP
tRHCP
VIH
RAS
VIL
tRCD tHPC tRP
tCRP tRSH
tCSH
tCAS tCAS
tCAS
LCAS VIH
or tRAD
VIL
UCAS
tASR tCAL tRAL
tASC tCSH tRDD
tASC tASC tOFR
tRAH tCSH
tCAH
VIH ROW COL COL COL

VIL
tRCS tOH
tRCS tRCH tRCH tRCS tRCH
tWPZ
tWPZ tWPZ
VIH
WE
VIL
tCDD
tDZC tWED
tOH
DQ VIH
HIGH-Z HIGH-Z
(Input) VIL
tRAC tAA tAA tOFF

tAA tCAC tCAC
tWEZ tWEZ
tCAC
tWEZ
tON tON
DQ VOH
HIGH-Z
(Output) V
OL
tOH
tON
tOEZ
tDZO tOED
tON
VIH tOEA
OE
VIL
During one cycle is achieved, the input/output timing apply the same manner as the former cycle. ”H” or ”L”
Valid Data
DESCRIPTION
occurring.
16
– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
Fig. 12 – HYPER PAGE MODE EARLY WRITE CYCLE
tRASP
VIH
tRHCP
RAS
VIL
tCRP tHPC tRP

tCSH tRSH
tCP
tRCD tCAS tCAS tCAS
LCAS VIH
or
VIL
UCAS
tAR tCAH tCAH
tCAH
tRAH tASC
tASC tRAL
tASR tASC
VIH ROW COL COL COL

VIL
tWCH
tWCR tWCH tWCS
tWCS
tWCS tWCH tCWL
tCWL tCWL tRWL
VIH
WE
VIL
tDHR tDS
tDH tDS tDH tDH
tDS
DQ VIH VALID VALID VALID

(Input) DATA DATA DATA
VIL
DQ VOH
HIGH-Z
(Output) V
OL
During one cycle is achieved, the input/output timing apply the same manner as the former cycle.
”H” or ”L”
DESCRIPTION
The hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except the states of WE and OE
are reversed. Data appearing on the DQ1 to DQ8 is latched on the falling edge of LCAS and one appearing on the DQ9 to DQ16 is latched on
the falling edge of UCAS and the data is written into the memory. During the hyper page mode early write cycle, including the delayed (OE)
write and read-modify-write cycles, tCWL must be satisfied.
17
– PRELIMINARY –
MB8118165A-60
MB8118165A-70
Fig. 13 – HYPER PAGE MODE DELAYED WRITE CYCLE
V IH t RASP
RAS
V IL
t CRP t CSH t HPC t RP
t RCD t t RSH
t CAS CP
LCAS V IH t CAS
or
V IL t AR
UCAS t ASC
t RAH t ASC t CAH t CAH t CWL
t ASR
V IH ROW COL COL
A 0 to A 9 ADD ADD
ADD
V IL
t CWL t RWL
t RCS t WCH t WCH
t WP t WP
V IH
WE
V IL t DS t DS
t DZC t DH
t DH
V IH
DQ VALID VALID
(Input) DATA IN DATA IN
V IL t OED
t ON t ON t OED
t OEH
V OH
DQ HIGH–Z
(Output) V OL t ON t OEH
t ON
t OEZ
t DZO t OEZ
V IH
OE V IL
“H” or “L”
Invalid Data
DESCRIPTION
The hyper page mode delayed write cycle is executed in the same manner as the hyper page mode early write cycle except for the states of
WE and OE. Input data on the DQ pins are latched on the falling edge of WE and written into memory. In the hyper page mode delayed write
cycle, OE must be changed from Low to High before WE goes Low (tOED + tT + tDS).
18
– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
Fig. 14 – HYPER PAGE MODE READ/WRITE MIXED CYCLE
V IH t RASP
RAS t RHCP
V IL
t RP
t CRP t RCD t HPC t RSH
t CSH t CP
t CAS t CAS
LCAS V IH t CAS
or t RAD
V IL
UCAS
t ASC t CAL
t RAH t ASC t
t ASR t CAH t CAH t ASC t CAHRAL
V IH ROW COL COL COL

A 0 to A 9 ADD
ADD ADD ADD
V IL
t RCS t RCH
V IH t WCS t WCH
WE V IL
t DZC t WED t DH
t DS
V IH
DQ HIGH–Z VALID
(Input) V IL DATA IN
t CPA
t RAC
t AA
t AA t WEZ
t OHC t CAC
t CAC
V OH
DQ HIGH–Z HIGH–Z
(Output) V OL t ON
t DZO t OEZ
t ON t OED
V IH
OE t OEA
V IL
“H” or “L”
ÉÉ
ÉÉ
Valid Data
DESCRIPTION
The hyper page mode performs read/write operations repetitively during one RAS cycle. At this time, tHPC (min.) is invalid.
19
– PRELIMINARY –
MB8118165A-60
MB8118165A-70
Fig. 15 – HYPER PAGE MODE READ MODIFY WRITE CYCLE
V IH t RASP
RAS
V IL
t RP
t CRP t RWL
t RCD t HPRWC
LCAS
V IH t CWD t
or CP
t CWD
UCAS V IL t RAD t ASC
t t CAH
t RAH ASC
t ASR t CAH
V IH ROW COL COL
A 0 to A 9 ADD ADD
ADD
V IL
t AWD t CPWD
t CWL
t RCS t CWL t RCS
t WP t WP
V IH
WE
V IL
t DS
t RWD
t DS
t DZC t DH t DH
V IH
DQ
VALID VALID
(Input) V IL t OED t OED
t CAC t CAC
ÉÉ ÉÉ
t AA t AA
V OH t ON
ÉÉ ÉÉ
t ON
DQ HIGH–Z
(Output) V OL t ON
t ON t OEH
t RAC t OEZ
t OEA t OEH
t DZO t OEZ
V IH
OE
V IL
t OEA t CPA
“H” or “L”
ÉÉ
ÉÉ
Valid Data
DESCRIPTION
During the hyper page mode of operation, the read-modify-write cycle can be executed by switching WE from High to Low after input data
appears at the DQ pins during a normal cycle.
20
– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
Fig. 16 – RAS-ONLY REFRESH (WE = OE = ”H”or ”L”)
tRC
VIH tRAS
RAS VIL
tRP
tASR
tRAH tRPC
VIH
A0 to A9 ROW ADDRESS
VIL
tCRP tCRP
LCAS
VIH
or VIL tOFF
UCAS
tOH
DQ VOH
(Output) VOL HIGH–Z
”H” or ”L”
DESCRIPTION
Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 1,024 row addresses ev-
ery 16.4–milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden refresh.
RAS-only refresh is performed by keeping RAS Low and LCAS and UCAS High throughout the cycle; the row address to be refreshed is
latched on the falling edge of RAS. During RAS-only refresh, DQ pins are kept in a high-impedance state.
Fig. 17 – CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = ”H”or ”L”)
tRC
tRP
tRAS
VIH
RAS VIL
tCPN tCSR tCHR tRPC tCSR
tCPN
LCAS VIH
or VIL
UCAS tOFF
tOH
DQ VOH
(Output) VOL HIGH–Z
”H” or ”L”
DESCRIPTION
CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If LCAS or UCAS is held
Low for the specified setup time (tCSR) before RAS goes Low, the on-chip refresh control clock generators and refresh address counter are
enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the
next CAS-before-RAS refresh operation.
21
– PRELIMINARY –
MB8118165A-60
MB8118165A-70
Fig. 18 – HIDDEN REFRESH CYCLE
tRC tRC
tRAS tRP tRAS
VIH tOEL
RAS
VIL
tRP
tRCD tRSH tCRP
tRAD tCHR
LCAS VIH
or tRAH
UCAS VIL
tASR
tRAL
tASC
tAR
tCAH
VIH
A0 to A9 ROW COLUMN
VIL ADDRESS ADDRESS
tRCS tRRH
VIH
WE
VIL tAA
tRAC
tCDD
tDZC tCAC
DQ VIH
HIGH-Z
(Input) tOFF
VIL
tON tOFR
tOH
tOH
DQ VOH
HIGH-Z VALID DATA OUT
(Output) V
OL
tOEZ
tDZO tOEA
tOED
VIH
OE
VIL
”H” or ”L”
DESCRIPTION
A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of LCAS or UCAS
and cycling RAS. The refresh row address is provided by the on-chip refresh address counter. This eliminates the need for the external row
address that is required by DRAMs that do not have CAS-before-RAS refresh capability.
22
– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
Fig. 19 – CAS–BEFORE–RAS REFRESH COUNTER TEST CYCLE
VIH
RAS VIL
tCHR tCP tFRSH tRP
tCSR tFCAS
LCAS VIH
or
VIL
UCAS
tFCAH
tASC
VIH
A0 to A9 COLUMN ADDRESSES
VIL
tCWL
tRCS tFCWD tRWL
VIH
WE VIL
tDZC
tWP
tDS
tDH
DQ VIH
(Input) VIL HIGH–Z VALID DATA IN
tOED
tFCAC
DQ VOH
HIGH–Z HIGH–Z
(Output) VOL tON
tOEH
tDZO tOEA
tOEZ
VIH
OE VIL
”H” or ”L”
Valid Data
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function of
CAS-before-RAS refresh circuitry. If a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is held Low, read
and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A0 through A9 are defined by the on-chip refresh counter.
Column Addresses: Bits A0 through A7 are defined by latching levels on A0–A7 at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows;

1) Initialize the internal refresh address counter by using 8 RAS only refresh cycles.
2) Use the same column address throughout the test.
3) Write ”0” to all 1,024 row addresses at the same column address by using normal write cycles.
4) Read ”0” written in procedure 3) and check; simultaneously write ”1” to the same addresses by using CAS-before-RAS
refresh counter test (read-modify-write cycles). Repeat this procedure 1,024 times with addresses generated by the
internal refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 1,024 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
(At recommended operating conditions unless otherwise noted.)
MB8118165A-60 MB8118165A-70
No. Parameter Symbol Unit
Min Max Min Max
69 Access Time from CAS tFCAC  50  55 ns
70 Column Address Hold Time tFCAH 35  35  ns
71 CAS to WE Delay Time tFCWD 70  77  ns
72 CAS Pulse width tFCAS 90  99  ns
73 RAS Hold Time tFRSH 90  99  ns

Note: Assumes that CAS-before-RAS refresh counter test cycle only.
23
– PRELIMINARY –
MB8118165A-60
MB8118165A-70
Fig. 17 – SELF REFRESH CYCLE (A0–A11 = WE = OE = ”H” or ”L”)
t RASS t RPS
RAS V IH
V IL
t CSR t RPC
t CPN
t CHS
LCAS
or V IH
t OFF
V IL
UCAS
t OH
DQ V OH HIGH–Z
(Output) V OL
“H” or “L”
A0 to A9, WE, OE = ”H” or ”L”
(At recommended operating conditions unless otherwise noted.)

MB8118165A-60 MB8118165A-70
No. Parameter Symbol Unit
Min Max Min Max
74 RAS pulse Width t RASS 100 — 100 — µs

75 RAS precharge Time t RPS 104 — 124 — ns
76 CAS Hold Time t CHS –50 — –50 — ns
Note . Assumes self refresh cycle only.

DESCRIPTION
The self refresh cycle provides a refresh operation without external clock and external Address. Self refresh control circuit on chip is operated
in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter and timing generator.
If CAS goes to ”L” before RAS goes to ”L” (CBR) and the condition of CAS ”L” and RAS ”L” is kept for term of tRASS (more than 100µs), the
device can enter the self refresh cycle. Following that, refresh operation is automatically executed at fixed intervals using internal refresh
address counter during RAS=L” and ”CAS=L”.
Exit from self refresh cycle is performed by toggling /RAS and /CAS to ”H” with specified tCHS min.. In this time, RAS must be kept ”H” with
specified tRPS min..
Using self refresh mode, data can be retained without external CAS signal during system is in standby.
Restriction for Self Refresh operation ;

For self refresh operation, the notice below must be considered.
1) In the case that distributed CBR refresh are operated between read/write cycles
Self refresh cycles can be executed without special rule if 4,096 cycles of distributed CBR refresh are executed within tREF
max..
2) In the case that burst CBR refresh or distributed/burst /RAS only refresh are operated between read/write cycles
1,024 times of burst CBR refresh or 1,024 times of burst /RAS only refresh must be executed before and after Self refresh
cycles.
Read/Write operation Self Refresh operation Read/Write operation

t RASS
RAS V IH
V IL
t NS < 1ms t SN < 1ms

1,024 burst refresh cycle 1,024 burst refresh cycle
* read/write operation can be performed non refresh time within tNS or tSN
24
– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
PACKAGE DIMENSIONS
(Suffix: -PJ)
42-LEAD PLASTIC LEADED CHIP CARRIER

(CASE No.: LCC-42P-M01)
+.014 +0.35
.134 (3.40 )
–.008 –0.20
∗1.075±.005 .108(2.75)NOM.
42 (27.30±0.13) .025(0.64)MIN.
22
R.032(0.81)TYP.
.432±.005
(10.97±0.13) .370±.020
.400(10.16) (9.40±0.51)
NOM.
INDEX
+.002
1
.050±.005 21
.008
–.001
(1.27±0.13) +0.05
LEAD (0.20 )
1.000(25.40)REF. –0.02
No.
“A”
Details of “A” part
.032(0.81)
.098(2.50) MAX
NOM
.004(0.10)
.017±.004
(0.43±0.10)
∗: This dimension exclude resin protrusion. (Each side:.006(0.15)MAX.) Dimensions in

1994 FUJITSU LIMITED C42001S–2C(W) inches (millimeters)
25
– PRELIMINARY –
MB8118165A-60
MB8118165A-70
PACKAGE DIMENSIONS (Continued)

(Suffix: -PFTN)
50-LEAD PLASTIC FLAT PACKAGE

(CASE No.: FPT-50P-M06)
50 40 36 26 Details of “A” part
.006(0.15)
.010(0.25)
“A” .006(0.15)MAX
INDEX
.016(0.40)MAX
LEAD No. 1 11 15 25
∗.825±.004 .463±.008
+.004 +0.10 (11.76±0.20)
(20.95±0.10) .043 –.002(1.10 –0.05 )
.012±.004 (MOUNTING HEIGHT) .400±.004
(0.30±0.10)
.005(0.13) M
(10.16±0.10) .005±.002
(0.125±0.05)
.004(0.10) .020±.004 .424±.008

.031(0.80) 0(0) MIN (0.50±0.10) (10.76±0.20)
TYP (STAND OFF
.756(19.20)REF HEIGHT)
*: This dimension exclude resin protrusion.(Each side : .006(0.15) MAX) Dimensions in

1994 FUJITSU LIMITED F50006S-1C(W) inches (millimeters)
26
– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical
semiconductor applications. Complete information sufficient for construction purposes
is not necessarily given.
The information contained in this document has been carefully checked and is believed
to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The information contained in this document does not convey any license under the
copyrights, patent rights or trademarks claimed and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications without notice.
No part of this publication may be copied or reproduced in any form or by any means, or
transferred to any third party without prior written consent of Fujitsu.
The products described in this document are not intended for use in equipment requiring
high reliability, such as marine relays and medical life–support systems. For such appli-
cations, contact your Fujitsu sales representative.
If the products and technologies described in this document are controlled by the For-
eign Exchange and Foreign Trade Control Act established in Japan, their export is sub-
ject to prior approval based on the said act.
27
– PRELIMINARY –
Edition 1.0
MB8118165A-60
MB8118165A-70
For further information please contact:
Japan
FUJITSU LIMITED
Application &Sales Engineering Dept.
1015,Kamikodanaka Nakahara–ku,
Kawasaki 211, Japan
Tel: (044)754–3283
FAX: (044)754–3343
North and South America

FUJITSU MICROELECTRONICS, INC.
3545 North First Street
San Jose, CA 95134–1804, USA.
Tel: 408–922–9000
FAX: 408–432–9044, 9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6–10,
63303 Dreieich-Buchschlag,
Germany
Tel: (06103) 690–0
Telex: 411963
FAX: (06103) 690–122
Asia
FUJITSU MICROELECTRONICS ASIA PTE LIMITED
#06–04 to #06–07
Plaza By The Park
No.51 Bras Basah Road
Singapore 0718
Tel: 336–1600
Telex: 55573
FAX: 336–1609
FUJITSU LIMITED 1995 Printed in Japan
28

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ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

Plastic SOJ Package

RAS Access Time 60ns max. 70ns max.

Low Pow- Operating current 880mW max. 825mW max.

• 1,048,576 words × 16 bit organization • Early write or OE controlled write capability

ABSOLUTE MAXIMUM RATINGS (see NOTE)

Copyright 1995 by FUJITSU LIMITED

Fig. 1 – MB8118165A DYNAMIC RAM – BLOCK DIAGRAM

A7 Row 16,777,216 Bit

CAPACITANCE (TA = 25°C, f = 1MHz)

Input Capacitance, A0 to A9 CIN1 5 pF

Input Capacitance, RAS, LCAS, UCAS, WE, OE CIN2 5 pF

Input/Output Capacitance, DQ1 to DQ16 CDQ 7 pF

PIN ASSIGNMENTS AND DESCRIPTIONS

RECOMMENDED OPERATING CONDITIONS

VCC 4.5 5.0 5.5

Input High Voltage, all inputs/outputs∗ 1 VIL –0.3  0.8 V

HYPER PAGE MODE OPERATION

Output leakage current IDO(L) 0V ≤ VOUT ≤ VCC; –10  10

Operating current MB8118165A-60 160

Standby current TTL level RAS = LCAS = UCAS = VIH 2.0

Refresh current #1 MB8118165A-60 160

Refresh current #2 MB8118165A-60 RAS cycling; 160

Refresh current #3 MB8118165A-60

2 Random Read/Write Cycle Time tRC 104  124  ns

3 Read-Modify-Write Cycle Time tRWC 138  162  ns

4 Access Time from RAS 6,9 tRAC  60  70 ns

5 Access Time from CAS 7,9 tCAC  15  17 ns

6 Column Address Access Time 8,9 tAA  30  35 ns

7 Output Hold Time tOH 3  3  ns

8 Output Hold Time from CAS tOHC 5  5  ns

9 Output Buffer Turn On Delay Time tON 0  0  ns

10 Output Buffer Turn Off Delay Time 10 tOFF  15  17 ns

12 Output Buffer Turn Off Delay Time from WE 10 tWEZ  15  17 ns

14 RAS Precharge Time tRP 40  50  ns

15 RAS Pulse Width tRAS 60 100000 70 100000 ns

16 RAS Hold Time tRSH 15  17  ns

17 CAS to RAS Precharge Time 21 tCRP 5  5  ns

18 RAS to CAS Delay Time 11,12,22 tRCD 14 45 14 53 ns

19 CAS Pulse Width tCAS 10  13  ns

20 CAS Hold Time tCSH 40  50  ns

21 CAS Precharge Time (Normal) 19 tCPN 10  10  ns

22 Row Address Set Up Time tASR 0  0  ns

23 Row Address Hold Time tRAH 10  10  ns

24 Column Address Set Up Time tASC 0  0  ns

25 Column Address Hold Time tCAH 10  10  ns

26 Column Address Hold Time from RAS tAR 24  24  ns

27 RAS to Column Address Delay Time 13 tRAD 12 30 12 35 ns

28 Column Address to RAS Lead Time tRAL 30  35  ns

29 Column Address to CAS Lead Time tCAL 23  28  ns

30 Read Command Set Up Time tRCS 0  0  ns

Read Command Hold Time

33 Write Command Set Up Time 15, 20 tWCS 0  0  ns

34 Write Command Hold Time tWCH 10  10  ns

35 Write Hold Time from RAS tWCR 24  24  ns

37 Write Command to RAS Lead Time tRWL 15  17  ns

38 Write Command to CAS Lead Time tCWL 10  13  ns

39 DIN Set Up Time tDS 0  0  ns

40 DIN Hold Time tDH 10  10  ns

41 Data Hold Time from RAS tDHR 24  24  ns

42 RAS to WE Delay Time 20 tRWD 77  89  ns

43 CAS to WE Delay Time 20 tCWD 32  36  ns

44 Column Address to WE Delay Time 20 tAWD 47  54  ns

CAS Set Up Time for CAS-before-