ClRCUIT THEORY AND APPLICATION, VO1..

15, 61-69 (1987)

SUCCESSIVE APPROXIMATION LOGARITHMIC A/D

CONVERSION USING CHARGE REDISTRIBUTION TECHNIQUES
C . C. LEFAS
Nuclear Reseurch Center Dernocritos, 153.41 A. Puraskevi, Attiki, Greece

SUMMARY
The present papei describes a logarithmic A/D converter (LADC) working with the charge redistribution principle.
The LADC uses a serial and a parallel capacitive attenuator and is suitable for manufacturing o n a single chip.
Formulae for the values of the capacitors are given in terms of the base of logarithm used. This LADC uses
logarithmically spaced voltage comparison levels and therefore eliminates the use of logarithmic analogue signal
conditioning circuits.

INTRODUCTION
Logarithmic A/D converters (LADC) have attracted considerable attention both on their design aspects
as well as on their applications. In particular LADCs offer a wider dynamic range than linear ADCs for
the same number of bits per word, constant relative error etc. On the digital system side logarithmic
arithmetic has been used successfully in controller^,^ calculations4 and signal processors.s36
The interface of such systems to the analogue world requires the use of a logarithmic A/D conversion
scheme.
In the past, several approaches to the design of LADCs have been taken. Analogue logarithmic
amplifiers have been cascaded in front of linear ADCs to condition the analogue signal logarithmically
before it is fed into a linear ADC. Another approach exploits the exponential law of the
capacitor-resistor combination.a11 Several other approaches use operational amplifiers whose feedback
path consists of digitally controlled logarithmically weighted resistor
All the above methods have in common the fact that they separate the logarithmic conversion process
into a linear A D C and a logarithmic analogue signal conditioning circuit cascaded in front of the ADC.
This, however, inherits all problems associated with the design and manufacture of stable and reliable
logarithmic amplifiers. An alternative is to use an ADC with logarithmically spaced, rather than linearly
spaced, voltage comparison levels. In this way the digital word corresponds directly to the logarithm of
the input and the use of a logarithmic analogue amplifier is avoided. An approach described in
reference 14 achieves this by using a series of resistive attenuators that are switched on and off. The
greater disadvantage of this method is that it requires the use of several high precision resistors, which are
difficult to manufacture on a chip.
Recent advances in VLSI technology have made the manufacture of single-chip ADCs not only
technically feasible but also economically attractive. This development has changed the design philosophy
of ADCs, which now uses capacitors and charge, rather than resistors and current, as the working media,
The manufacture of capacitors on the wafer is easier than the manufacture of resistors, and therefore
charge redistribution ADCs are gaining ground
Linear charge redistribution ADCs use the same architecture as the ADCs using resistive attenuators.
For a logarithmic ADC, however, the adaptation of the switched attenuator a r c h i t e c t ~ r e is~ not
straightforward, since the equivalent of switching an attenuator on and off would be the possibility to
return to earlier charge distributions, after these have been altered. This, however, presents difficulties and
requires the use of precision amplifiers to charge capacitors back to their previous state. The approach
taken, therefore, is to realize digitally an approximation to the logarithmic

0098-9886/87/010061-09$05.00 Received I 0 May 1985

0 1987 by John Wiley & Sons, Ltd. Revised 23 June I986
62 C . C. LEFAS

T h e present paper describes a new charge redistribution successive approximation LADC, which
provides directly the logarithm of the input signal. The LADC uses a serial and a parallel capacitive
attenuator to overcome the attenuator switch-off pr0b1em.l~Finally, a scaled prototype is built to verify
the method proposed.

MACHINE REPRESENTATION OF NUMBERS USING LOGARITHMS

Real numbers are represented in the logarithmic lumber system by their sign and the logarithm of their
absolute value, i.e. the real number A is represented by the pair S A , LA defined by

L A = log(TA) (2)
where r is a scaling parameter.
Since LA is a real number it is represented approximately in the machine by rounding L A to its nearest
number represented in the machine K A .K A is mathematically defined as
KA = [0*5 f LA2N]2N (3)
where an N-bit digital word is assumed and [ X I denotes the largest integer that is not greater than X
(ENTIER or FLOOR function).
The 0.5 constant is introduced in equation (3) to cause rounding, rather than mere truncation, to take
place.
As the base of the logarithm any real number can be chosen. The number 2 is a logical choice.2
Alternatively a number D < 1 has been used for control application^.^ The latter approach is taken here.
To simplify matters, it is assumed that D is never raised to a power greater than unity and, consequently,
only the numbers in the - 1, + 1 range are represented. This, however, does not create any problems,
since the scaling parameter T can be used in equation ( 2 ) to cover any real number range desired.
The choice of D influences directly the range of numbers represented. The largest number is always 1
and the smallest is, assuming an ( N + 1)-bit format, D2N-'.Define the dynamic range as the ratio of the
biggest to the smallest number represented (in absolute values). Then the dynamic range is represented
by the number S defined as
6 = D2-l - (+pJ-I) = 2D2N-I
(4)
The relative error eL for a number KA in the machine is the maximum error done by approximating the
real number by KA divided by K A .K A represents all real numbers A in the range
<
J D ~ ~ + ~ D A
~ K < JDZK-'D2", i.e. D ~ " \ ~<DA c D ' " / ~ D
Since KA represents exactly the real number D Z Kthe relative error is
EL = ( D ~ " / J D- 02")/02"
= ( ~ / J D )- 1 (5)
Combining equations (4) and (5):
b = 2(&L + 1)2-ZN
From equation (6) it is seen that, for a fixed number of bits N, the goals of small relative error and large
dynamic range are conflicting. This is so, since small relative error requires closer spacing of the numbers
represented digitally, whereas large dynamic range requires the opposite. The dynamic range has,
therefore, to be traded off against relative error for each application. Figure 1 shows equation (6) with N
as parameter. It can be clearly seen that to achieve lower values of 6 (larger dynamic range), higher values
of eLhave to be used.
 SUCCESSIVE APPROXIMATION LOGARITHMIC AID CONVERSION 63

Figure 1. eL plotted against 6. The number of bits per word is the parameter 1

THE SUCCESSIVE APPROXIMATION CONVERSION PROCEDURE

Assume ( N + 1)-bit word format. N bits are used for the logarithm and one bit is used for the sign. A
digital word bN-,, . . . ,bl, bo represents the number
x= ...
~ b f , - 1 2 f , - ~ ~ b ~ - 2 2~ ~b -1 ~2 ~ D b 0 2 ~

Bits 6, are determined in successive steps starting from b N - ,and ending at bo. To do that, the input is
compared first to D Z N - ' -if it is smaller bN-, is 1. if it is larger bN-, is zero. To determine!fl7z, the input is
compared to D
2N-1 D2N-'2
, ifbN-,is 1,or to DZN-',ifbN-,is 0 . Note that D2N-2= D Z N - l / D . This process
is repeated until bo is determined.
The key in the above algorithm is that for the kth step, determining b,+]-k, the comparison level is
2N-I-k 2N-1-k
either V D , if bN-kis 1, or v / D ,if bN-k iS 0,where v is the comparison level of the k - 1 Step.
Figure 2 summarizes the above procedure.
The problem with the realization of the above algorithm is that the factor D is lower than 1 and
2N-1-k .
therefore division by D implies a voltage multiplication operation. To get round this problem in
Reference 14 a series of attenuators is used and the multiplication operation takes place by switching the
attenuators off. In a charge redistribution scheme this means that that earlier charge distributions must be
recovered, which is no simple task. An alternative is therefore proposed in the next section using a
parallel and a serial capacitive attenuator.

THE SUCCESSIVE APPROXIMATION LADC

System design
Figure 3 shows the diagram of the successive approximation LADC. The main blocks of the circuit are
a comparator, a shift register, a serial capacitive attenuator and a parallel attenuator. The capacitors of
the serial attenuator are calculated so that when the attenuator is charged from OV to V the voltages (1,
64 C . C . LEFAS

et V=V

Figure 2. Conversion algorithm. The loop is repeated N - 1 times

D , D ~. ., . , D Z N - ' )appear at its taps. The capacitors of the parallel attenuator are calculated so that when
its k th capacitor is discharged and is connected in parallel to the serial attenuator, the voltage across the
latter drops to D Z kof its initial value.
T h e conversion process starts with charging the serial attenuator to J D V r e fThe . voltages \iD D 2 N - 1 V r e f ,
\iD D 2 N - 2 V r e. f. . exist at its tappings by chosing its capacitors suitably. First, the input voltage is
compared t o \iD D Z N - l V r eifr ;it is larger, b N - ,= 0 and the input is compared with \iD D2N-2Vref, which is
available on the serial attenuator; if it is smaller, b N - ,= 0 and the input is compared with
JD ~ 2 N - 1 ~ 2 N Vref
- 2 in the next step. This voltage is obtained by discharging the serial attenuator to DZN-'
of its former value. This is achieved by connecting momentarily the ( N - 1)th capacitor of the parallel
attenuator in parallel to the serial attenuator.

L__---------------J

Figure 3. Architecture of the successive approximation LADC

 SUCCESSIVE APPROXIMATION LOGARITHMIC A/D CONVERSION 65

The conversion process is summarized in the following steps:

1. Start by discharging all capacitors.
2. Charge the serial attenuator to the reference voltage V,.
3. Start f o r k = 0.
4. Compare the input voltage V,, with V,N-k(refer to Figure 3)
bN-k = 0, if v,n '' S N - k
bN-k = 1, if v,"< 'SN-k

- ~connecting c,,,-,in parallel to the serial attenuator. DO nothing

5. If b N - k is 1 reduce V, to v , D * ~ by
if bN-kis zero.
6. Repeat steps 4, 5 until bo is reached.
The operational algorithm for the LADC is shown in Figure 4. The steps described in Figure 2 are
implemented as a series of switch operations. A t the end the contents of the shift register are the required
digital word. Note here that the parallel attenuator does not have to provide attenuation D since this is
provided directly by the serial attenuator.

S t a r t
C J
discharge all
capacitors.

tches. Close SN+

Shift SR 1 step

of Conversi

Figure 4. Conversion procedure

66 C. C . LEFAS

Calculation of the serial and parallel attenuators

First the serial attenuator is calculated. Only the capacitor ratios are of interest, not the absolute values,
and, consequently, capacitor values are given in terms of capacitor Co. When the attenuator is charging or
discharging the same current flows through all capacitors since they are connected in series. The voltage
across each o n e is then:
'1

Vc1 = j i dt/C, (7)

'0

therefore

Equation (8) is used together with Figure 3 to determine the capacitor ratios of the serial attenuator:

The total capacitance of the serial attenuator is

C , = Cso(l - D )
The capacitors of the parallel attenuator are calculated as follows:
If a discharged capacitor Cplis connected in parallel to the serial attenuator charged at voltage V , then
the voltage across the serial attenuator drops due to charge redistribution to

For C , the desirable ratio is D2', and therefore

The design of the serial attenuator, as is shown in Figure 3, does not take into account the parasitic
capacitances which exist between the earth and the capacitor plates. For a Capacitor C, the bottom plate
parasitic capacitance may be 0.1 C -+ 20 per cent and the top plate parasitic capacitance may be
0.01 C 2 20 per cent. Consequently a more realistic model of the serial attenuator is shown in Figure 5 ,

parasitics j
! Ic50 ::

Figure 5. The serial attenuator with the parasitics shown

 SUCCESSIVE APPROXIMATION LOGARITHMIC AID CONVERSION 67

where the parasitic capacitances are shown. The parasitics interfere with the serial attenuator accuracy
but, in principle, do not change its functionality. If, for example, the parasitic capacitances were exactly
known, the serial attenuator capacitors could be scaled down to preserve the desired voltage levels.
Assume, for the moment, that the parasitic capacitances are exactly known, and are a fraction A of the
actual capacitor. Then:
C,, =A C,, 15i IN -1
The i t h voltage level is preserved if the total capacitance of the i + 1 5 j 5 N - 1 capacitors remains
constant, i.e. all capacitors must be scaled down to counter the effect of the parasitic capacitor. Denote by
Cl, the total capacitance of the part of the serial attenuator that includes capacitors C,, C,,+],. . .

The parasitic capacitance parallel to C, is

Therefore CIImust be scaled down to CT,, so that

c:I + c,, = Cl,
Combining equations ( l l b ) , (12) and (13):
CTl = ( 1 - A B l ) C l ,
B , = D2,-'/(1 - D Z f - ' )
To achieve the desired CT, all C,, Cs,+letc., must be scaled down according to equation (14), which,
however, offsets the effect of C,, only. To offset all parasitic capacitors, C,I must be scaled down to
c:l = S,C, (16)

S, = n
j = 1
(1 - A B , ) (17)

From equations (14) and (17) it is seen that the most significant term in equation (17) is (1 - A B , ) ,since
B1 = D/(1 - D )
Since the parasitic capacitances are not accurately known, D is chosen so that
BlsF (18)
where F is a design parameter. Then
D 5 1 -A/(A + 1 -F) (19)
The factor F is chosen in accordance with the accuracy with which the ratio of parasitic to actual
capacitance is known. Equation (19) puts a severe limit on the range of D . Equation (19) shows that the
effect of the parasitic capacitances is smaller for smaller D . Hence, the LADC presented here is suitable
for short word, large dynamic range applications. For example, for F = 0.5, A = 0.1
D 5 0.8333
which limits the LADC resolution to 5-6 bits, assuming a dynamic range of four to five decades.

DESIGN OF A SCALED PROTOTYPE

A scaled prototype has been made to show the feasibility of the method. The word length is 8 bits, one
sign bit and seven data bits, i.e. N = 7 in this case. The dynamic range has been selected to be four
decades, i.e. the scale is from 0.0001 to 1. For this purpose D must be equal to 0.93045 and, for this value
68 C. C. LEFAS

o u t p u t Vin C m CLK EOC

Figure 6 . Block diagram of the prototype LADC

of N , E , , is 3.7 per cent. Figure 6 shows the diagram of the scaled prototype. It has been built with discrete
components and a value for Cu = 1000 pF. The values of the other capacitors have been calculated
according t o equations (9) and (11). The CLEAR signal resets the LADC and the conversion process
starts when CLEAR becomes LOW. The end of the conversion process is marked by the E O C line, which
goes HIGH, disabling the clock at the same time.

CONCLUSIONS
A successive approximation LADC has been designed using the charge redistribution principle. The
design has been implemented successfully in a scaled prototype using discrete components. The structure
of the LADC make this design suitable for manufacture on a single chip. This design is not immune to
parasitic capacitances and the present LADC is suitable for short word, large dynamic range applications.
Typical values are 5-6 bits resolution and 4-5 decades input range.

REFERENCES
1. J. N. Mitchel, Computer multiplication and division using binary logarithms, IRE Trans., EC-11, 512-517 (1962).
2. A. D. Edgar and S. C. Lee, FOCUS microcomputer number system, Comm. ACM, 22, 166-177 (1979).
3 . J. Lang, On the design of a special purpose digital control processor, IEEE Trans. Automatic Control, AC-29, 195-201
( 1984).
4. E. E. Swartzlander and A. G. Alexopoulos, The sign/logarithm number system, IEEE Trans. Computers, C-24, 1238-1242
(1975).
5. N. G . Kingsbury and P. J . W. Rayner, Digital filtering using logarithmic arithmetic, Electronic Letters, 7 , 56-58 (1971).
6. E. E. Swartzlander, D. V. Satish-Chandra, H. Troy-Nagle and S. A. Starks, Sign/logarithm arithmetic for FFT
implementation, I E E E 7rans. Computers, C-32, 526-534 (1983).
7. S. Cantarano, G. Pallotino, Logarithmic analog to digital converters. A survey, I E E E Trans. Instrumentation and
Measurements, 1M-22, 201-2 13 (1973).
8. C. H. Burton, K. G. Weir and G. J. Bowden, Linear and nonlinear A/D, D/A and A/A conversions using the dual slope
principle, I E E E Trans. Instrumentation and Measurement, IM-24, 201-205 (1975).
 SUCCESSIVE APPROXIMATION LOGARITHMIC A/D CONVERSION 69

9. W. L. Patterson, Multiplication and logarithmic conversion by operational amplifier-transistor circuits, Rev. Sci. Instr., 34,
1311-1316 (1963).
10. S. Ben-Yaakov and 3 . Chen, An RC logarithmic converter-digitizer, I E E E Trans. Instrument and Measurements, 1M-27,
24-26 (1978).
11. E. J. Duke, RC logarithmic analog to digital conversion, I E E E Trans. Instrumentation and Measurements, IM-20, 74-76
(1971).
12. J. F. Gibbons and H. S . Horn, A circuit with logarithmic transfer response over 9 decades, f E E E Trans. Circuir Theory,
CT-11, 378-384 (1964).
13. Y. Parker, A binary floating point resistor, IEEE Trans. Computers, C-20, 7-11 (1971).
14. B. Gottshalk, Logarithmic analog to digital conversion using switched attenuators, Rev. Sci. Instr., 49, 200-204 (1 978).
15. C. W. Barbour, Simplified PCM analog to digital converters using capacitive charge transfer, Proc. 1971 Telemerering
Conference, 4.1-4.1 1.
16. J. L. McGreary and P. M. Gray, All-MOS charge redistribution analog to digital conversion techniques. Pt 1. I E E E J . Solid
Stale Circuits, SSC-10, 371-379 (1975).
17. R. E. Suarez, P. M. Gray and D. A. Hodges, All-MOS charge redistribution analog to digital conversion techniques. Pt. 2,
I E E E J . Solid State Circuits, SSC-10, 379-385 (1975).
18. Y . S . Lee, L. M. Terman, L. G. Heller, A two stage weighted capacitor network for D/A-A/D conversion, I E E E J . Solid S/mr
Circuits, SSC-14, 778-781 (1979).
19. Y. R. Tsividis e t a / . , All-MOS companded voice encoder, Digest of ISSCC, Philadelphia PA, 1976, pp. 380-385.
20. A. R. Hamade, A single chip all-MOS 8 bit A/D converter, I E E E J . Solid Stare Circuits. SSC-13, 785-791 (1978).
21. K. B. Ohri and M. J. Callahan, Integrated PCM codec, IEEE J . Solid State Circuits, SSC-14, 38-46 (1979).
22. M. E. Hoff, J. Huggins and B. M. Warren, An NMOS telephone codec for transmission and switching applications, ZEEE J .
Solid State Circuits, SSC-14, 47-53 (1979).
23. J. T. Caves, C. H. Chan, S. D. Rosenbaum, L. P. Sellars and J. P. Terry, A PCM voice codec with on-chip filters, I E E E J .
Solid State Circuits, SSC-14, 65-73 (1979).
24. Y. A. Haque, R. Gregorian, R. W. Blasco, R. A. Mao and W. E. Nicholson, A two chip PCM codec with filters, IEEE .I .
Solid
State Circuits, SSC-14, 961-969 (1979).