Verification of DRAM Controller for DDR2,DDR3,LPDDR1, LPDDR2,WIDEIO memory

models
SOMA files creation for different memory models
Creation of register sequences and testcases
Creation of hardware configuration file for generating RTLs for different configurations
supported by the IP
Coverage implementation for the features to be verified
Implementing the sampling of the coverage using the memory call back of the memory IP
Writing assertion for the critical functionality of the module
Regression support and primary verification debug
Coverage analysis and closure by adding test cases for uncovered functionality or code and
by adding exclusions

HVL : Systemverilog,
TB Methodology : UVM;

Tools : Incisive Metrics Centre10.2,

Incisive Enterprise simulator10.2,
PureView11.3(MMAV3.3.014),
Simvision waveform viewer10.2,
APB Systemveilog VIP11.3,
OCP Systemverilog VIP11.3,
AXI Systemverilog VIP11.3,
DDR2,DDR3,LPDDR2,WIDEIO memory models11.3(Denali3.3013),
DFI,
SVN Repository tool1.7.0

M.TECH Major Project:

Title:
Algorithmic Design for Real Time Retinex Image Processing

Abstract:
A programmable class of Retinex-like filters, based on the separation of the illumination and
reflectance components is proposed. The dynamic range of the input image is controlled by
applying a suitable non-linear function to the illumination, while the details are enhanced by
processing the reflectance. An innovative spatially recursive rational filter is used to estimate
the illumination. Further, to improve the visual quality results of two-branch Retinex
operators when applied to videos, a three-branch technique can be used which exploits both
spatial and temporal filtering. Real-time implementation can be obtained by designing an
Application Specific Instruction-set Processor (ASIP)

Specialties:GATE 2008 Percentile: 97.68

VLSI Domain Skills:

HDL: Verilog

HVL: SystemVerilog, SVA and PSL

Verificatin Methodolodies: Coverage Driven Verification

Assertion Based Verification

TB Methodology: UVM

Scripting Languages: Perl