Course SS 0501 SDH Principle

Issue 2.0

Section 7 Timing and Synchronization

3Objectives:
Master the synchronization mode of digital networks.
Master the characteristics of the three work modes of node slave clock in master/slave synchronization
mode.
Understand the demands of SDH introduction for network synchronization.
Learn the master/slave synchronization clock types of SDH network.

In a digital network, network synchronization is the first problem to be solved. For it is

required that the transmitting end shall put the pulse in a specific time position (i.e. a
specific timeslot) when sending digital pulse signals, and the receiving end shall be
able to extract and interpret the pulse in the specific time position, so as to ensure
normal communication between the two ends. Timing clocks at the two ends shoulder,
their task to ensure correct information extraction/sending in a specific time position by
the receiver/transmitter. So, network synchronization aims to limit the clock frequencies
and phases of all nodes in the network within a preset error tolerance range, so as to
avoid transmission performance deterioration (error codes, and jitter) resulted from
incorrect positioning of receiving/sending in the digital transmission system.

7.1 Synchronization Mode

Digital network synchronization can be achieved in two modes:
pseudo-synchronization and master/slave synchronization. Pseudo-synchronization
means that all digital exchanges in the digital switching network have independent
clocks which are not related with one another, while all the clocks have high accuracy
and stability, and usually they are cesium atom clocks. Since the clocks are highly
precise, though clocks in all exchanges in the network are not fully identical (in
frequency and phase), the error is so small that they are almost synchronous. Such
type of synchronization is called pseudo-synchronization. Master/slave
synchronization means that in the network a clock host exchange configured with a
high-precision clock is set, and all exchanges in the network are under control of this
host exchange (i.e. they trace the host exchange clock and use it as their timing
reference), while such control is exerted on the exchanges below level by level till the
terminal NE in the network----terminal exchange.
Usually, pseudo-synchronization mode is applied in international digital networks, i.e.
between digital networks of different countries. For example, the international
exchanges in China and in USA each has a cesium clock, and pseudo-synchronization
mode is applied between the two exchanges. Master/slave synchronization mode is
usually used for digital networks in a country or region. It features that the country or
region only has one host exchange clock, and other NEs on the network use the host
exchange clock as reference for timing of themselves. Principles of master/slave
synchronization and pseudo-synchronization are shown in Figure 7-1.

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To overseas international exchange

Pseudo- MS Master/slave synchronization

International exchange International exchange

MS MS MS
MS Domestic MS
Local exchange Domestic exchange exchagne Domestic exchange Domestic exchange

MS MS MS MS MS
Local exchange Local transit Local transit Local transit
Local transit exchange
exchange
MS exchange exchange
MS
MS MS
Terminal xchange Terminal xchange Terminal exchange Terminal exchange

Figure 7-1 Principle diagram of pseudo-synchronization and master/slave synchronization

To improve reliability of the master/slave timing system, an auxiliary clock can be set in
the network, with hierarchical master/slave control mode used. Both the two clocks are
cesium clocks, in normal time the master clock serves as the network timing reference,
while the auxiliary clock also takes the master clock as the reference. When the master
clock is faulty, the auxiliary clock provides timing reference for the network. When the
master clock recovers, it is switched back again and provides timing reference for the
network.
At present, China adopts hierarchical master/slave synchronization mode, with the
master clock in Beijing and the auxiliary clock in Wuhan. In master/slave
synchronization, timing signals of the upper-level NE are transmitted to the lower-level
NE via specific routes----synchronization link or by attaching to line signals. NE at this
level extracts the clock signals, traces and locks the clock via its own phase lock
oscillator, and generates local clock signals used by itself with the clock as reference.
Meanwhile it transmits the clock signals to NE at the lower level for it to trace and lock
via synchronization link or transmission line (i.e. transmitting clock information by
attaching it to line signals). If the station does not receive the reference clock sent by
the upper-level NE, it provides the local clock used by the NE via its own built-in phase
lock oscillator and sends clock signals to the lower-level NE.
Besides pseudo-synchronization and master/slave synchronization, synchronization
modes for digital networks such as mutual synchronization, external reference injection
and asynchronous synchronization (i.e. low-precision quasi-synchronization) are also
available. In the following, external reference injection synchronization mode is
introduced.
External reference injection mode backs up important node clocks on the network, in
order to avoid such case as the master clock reference of the important node on the
network is lost, while the nodes built-in clock quality is poor, thus NE normal work is
widely affected. This mode is to install GPS (Global Positioning System) receivers in
important node exchanges of NE to provide high-precision timing and form LPR (Local
Primary Reference). Other lower-level NEs in this area still use master/slave
synchronization mode to trace the primary reference clock provided by the GPS after
the master clock reference is lost.

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7.2 Slave Clock Work Modes in Master/Slave Synchronization

network
In the digital network of master/slave synchronization, clocks in slave stations
(lower-level stations) usually work in three modes.

Normal work mode----tracing and locking the upper-level clock

The clock reference traced and locked by the slave station is the one sent from the
upper-level station, it may be the master clock in the network, or the clock sent by the
built-in clock source of the upper-level NE, or GPS clock in the area.
In comparison with the other two work modes of slave clocks, this work mode of the
slave clock has the highest precision.

Holding mode

When all timing references are lost, the slave clock enters into holding mode, and the
slave station clock source works with the last frequency information saved before
timing reference signals are lost as its timing reference. In other words, the slave clock
has memory function, through which it provides timing signals comparatively
consistent with the original timing reference, so as to ensure a very small frequency
difference between the slave clock frequency and the primary reference clock
frequency for a long time. However, this type of work mode can not provide
comparatively high-precision clock for very long time because the inherent oscillation
frequency of the oscillator may wander slowly. Clock precision in this mode is only
inferior to that in normal work mode. Free run mode----free oscillation mode
When the slave clock loses all the external timing references, and the timing reference
memory is also lost or it is in holding mode for too long time, the oscillator inside the
slave clock will work in free oscillation mode. Clock precision in this mode is the lowest,
and is not used unless absolutely necessary.

7.3 Demands of SDH Introduction for Network

Synchronization
The synchronization performance of digital networks is crucial for normal working of the
networks, and the introduction of SDH network raises higher demands for network
synchronization. When the network works in normal mode, all NEs are synchronized to
a primary reference clock, only phase difference but not frequency difference exists
between NE node clocks, so pointer justification event only occurs occasionally
(pointer justification seldom occurs when the network is synchronized.).When a
specific NE node loses the synchronization primary reference clock and enters into
holding mode or free oscillation mode, frequency difference will occur between the NE
node local clock and the network clock, resulting in continuous pointer justification and,
affecting normal transmission of network services.
SDH network can co-exist with PDH network for a long time, and jitter and wander
occurring at the boundary between SDH and PDH mainly results from pointer
justification and payload mapping.
The frequency of pointer justification on SDH/PDH boundary node is closely related to
the synchronization performance of such gateway node. If the SDH input gateway

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implementing asynchronous mapping function is out of synchronization, then

frequency deviation and frequency shift of the node clock will cause constant pointer
justification of the whole SDH network, and deteriorate the synchronization
performance. If the last network unit connected with SDH network loses
synchronization, then in SDH network output there is still pointer justification which will
affect the synchronization performance. If the intermediate network node loses
synchronization, then as long as the input gateway is still synchronized to PRC, the
network unit or output gateway still in synchronous status and closely following the
faulty node can correct the pointer movement of the intermediate network node. In this
way, net pointer movement wont occur at the last output gateway, and synchronization
performance wont be affected.

7.4 Synchronization Mode of SDH Network

7.4.1 Synchronization Principles of SDH Network

The digital synchronization network in China adopts hierarchical synchronization mode.

In other words, a single PRC is used to control synchronization in the whole network
through synchronization links in the synchronization distribution network, a series of
hierarchical clocks are used in the network, and the clock at each level is synchronized
to the upper-level clock or clock at the same level.
The master/slave synchronization clock of SDH network can be divided into four types
(levels), corresponding to different using ranges: master clock as timing reference of
the whole network, slave clock of transit exchange, slave clock of terminal exchange
(local exchange), clock of SDH equipment (i.e. built-in clock of SDH equipment). ITU-T
has standardized the clocks of various levels (standardize the accuracy of clocks at
various levels), and the clock quality level is shown from high to low as follows:

y Master PRCconforming to G.811 specifications.

y Transit exchange clockconforming to G.812 specifications (transit clocks of

intermediate exchanges).

y Terminal exchange clockconforming to G.812 specifications (local exchange

clocks).

y SDH network unit clockconforming to G.813 specifications (SDH NE built-in

clocks).
In normal work mode, performance of various clocks sent to corresponding exchanges
mainly depends on the performance of the synchronous transmission link and the
timing extraction circuit. When NE works in protection mode or free run mode,
performance of various clocks used by NE mainly depends on the performance of the
clock sources that generate various clocks (clock sources are located in different NE
nodes accordingly), so high-level clocks should use high-performance clock sources.
Several points need to be noted when transmitting clock reference in the digital
network:
1) During transmission of synchronization clock, loops should be avoided.
For example, as Figure 7-2 shows,

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NE1

NE2 NE3

Figure 7-2 Network diagram

If NE2 traces NE1 clock, NE3 traces NE2, NE1 traces NE3 clock, then the
synchronization clock transmission link forms a loop, and deterioration of any NE clock
may cause chain deterioration of NE synchronization performance on the whole loop.
2) The timing transmission link should be as short as possible, for too long a link may
affect the clock signal quality in transmission.
3) Clock in slave station should obtain reference from the equipment at the upper level
or at the same level.
4) Active/standby clock references should be obtained from decentralized routes, in
case that clock reference is lost after the active clock transmission link is disconnected.
5) Transmission system of high availability should be selected to transmit clock
reference.

7.4.2 Types of SDH NE Clock Sources

y External clock source---- the input interface is provided by SETPI functional block.
y Line clock source----extracted by SPI functional block from STM-N line signals.
y Tributary clock source----extracted by PPI functional block from PDH tributary
signals. Usually this clock is not used, because pointer justification at SDH/PDH
boundary may affect the clock quality.
y Equipments built-in clock source----provided by SETS functional block.
Meanwhile, SDH NE provides external clock source output interface via SETPI
functional block.

7.4.3 Common Timing Modes in SDH Network

SDH network is a part of the whole digital network, and its timing reference should be
the unified timing reference in the digital network. Usually, SDH network in a specific
area uses the transit clock of the high-level exchange in the area as the primary timing
source. This primary reference clock may be the network master clock traced by the
exchange, local primary reference (LPR) provided by GPS, or even the clock provided
by the built-in clock source of local exchange (in holding mode or free run mode). Then
how does SDH network trace the primary reference clock and keep the network
synchronized? First, there should exist a SDH NE clock master station in the SDH
network. Here, the NE clock master station refers to the clock maser station of the SDH
network, clocks of other NEs on the network use this NE clock as reference, i.e. other
NEs trace the clock of the master NE. But where does the clock of the master station
come from? Since SDH network is a part of the digital network, its synchronization
clock should be the primary reference clock of this area. The master station on the SDH
network usually is set in the exchange with a high-level clock in the area, and the clock
used by SDH master station is just this transit exchange clock. When equipment logic
composition is talked about, the equipments SETPI functional block has been

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mentioned, and this block provides input/output interfaces for the equipment clock.
SETS functional block of the master station SDH NE extracts transit exchange clock via
the clock input interface, and uses it as the timing reference for the local station and
SDH network. If the exchange clock does not enter SDH master station NE via the
clock input interface provided by SETPI functional block, then SDH NE can extract
clock information (through function of PPI functional block) from PDH service that is
added/dropped at the local exchange as the timing reference of the SDH network.

Precaution:

The latter mode is seldom used, because at SDH/PDH network boundary (i.e. where PDHSDH), both
pointer justification and signal jitter are great, and clock signal quality will be affected.

How do other SDH NEs on the SDH network trace the master station SDH network
clock? Two modes are available, one is to output the NE clock to other SDH NEs via the
clock output interface provided by SETPI. Since SETPI provides PDH interface, this
mode usually is not used (there are many pointer justification events). The common
method is to put the SDH master station clock in STM-N signals transmitted on SDH
network, other SDH NEs extract clock information in STM-N signals through the
equipments SPI functional block, trace and lock it, which is consistent with
master/slave synchronization mode. In the following, several typical examples are used
to describe this type of clock tracing mode.

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See Figure 7-3.

STM-N
A B C D
w w e w e w
TM ADM ADM ADM

Master station External clock

Figure 7-3 Network diagram

The above diagram shows the topology of a chain network, station B is the clock
master station of the SDH network, and the external clock (exchange clock) of NE B is
the timing reference for the station and the SDH network. When NE B multiplexes
services into STM-N frame, the clock information is attached onto STM-N signals
naturally. At this time, NE A can extract timing clock from received STM-N signals at W
side port of the line (through SPI) and use it as its local clock. Similarly, NE C can
extract NE B clock information from received signals at the west line port, and use it as
its local clock, while attaching the clock information onto STM-N signals and
transmitting to NE at lower level. NE D synchronizes to NE B by extracting clock
information from received STM-N signals at the west line port. Thus through the
master/slave synchronization mode level by level, synchronization of all NEs in the
SDH network is realized.
After slave stations NEs A, C and D have lost the clock reference coming from the
upper-level NE, they enter into the holding mode. After a period of time, they enter into
the free run mode, and NE clock performance on the network deteriorates.

Precaution:

Synchronization performance deterioration of NE A does not affect NE C and NE D, but synchronization

performance deterioration of NE C affects NE D, for NE C is the upper-level NE traced by NE D clock. In
other words, NE C is the master station of NE D.

No matter what work mode the upper-level NE is in, the lower level NE is usually in
normal work mode, tracing the clock attached by the upper-level NE in STM-N signals.
So, deterioration of NE B clock performance can cause chain action of performances of
the whole SDH network clocks, with synchronization performance of all NEs on the
network deteriorating (with regard to the whole digital network, slave station NEs on the
SDH network are still in clock tracing status).
If the chain is very long, the master station NE clock may have to be transferred for
many times and transmitted a long distance before reaching the slave station NE. At
this time to ensure satisfactory clock signal quality received by slave station, two
master stations can be set on the SDH network, to provide two timing references on the
network. Each reference is traced by part of NEs on the network, so as to reduce
transmission distance and transfer times of clock signals. But it should be noted that
the two clock references should be kept synchronous and with same quality level.

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Technical details:
Several reference clock sources can be input into SDH master station in case external reference clock
source of SDH master station is lost. These clock sources are classified into different levels according to
the quality. SDH master station in normal status traces external high-level clock, and turns to trace
low-level external primary reference clock if the high-level one is lost, thus improving the reliability of
system synchronization performance.

Then how is the clock in ring network traced? See Figure 7-4.

External clock source

e
w
NE1 w
NE6
e e

NE2
w STM-N w
NE5
e e

NE3 w w
e
NE4

Figure 7-4 Ring network diagram

NE1 in the ring is the clcok master station, it uses the external clock source as clock
reference for local station and the SDH network, and other NEs trace the clock
reference and use it as local clock reference. The tracing mode of slave station clock is
similar to that of chain network, except that the slave station here can extract clock
information from received STM-N signals at both west and east line ports (ADM has
two line ports). However, in consideration of transit times and transmission distance
influence on clock signals, the slave station NE should extract from the port direction
with shortest route and least transit times. For example, it is suitable for NE5 to trace
the clock at west line port and NE3 to trace the clock at east line port.
See Figure 7-5:

NE1
External clock

STM-M
NE2 STM-N NE4 NE5

NE3 Note

Figure 7-5 Network diagram

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In the figure, NE5 is the clock master station, it uses external clock source (exchange
clock) as timing reference for itself and all other NEs on the SDH network. NE5 is a
chain attached to the ring, and this chain is attached to the low-speed tributary of NE4.
NE1, NE2 and NE3 trace and lock NE4 clock through east/west line ports, while NE4
clock traces the clock (in STM-M signals) sent from the master station NE5. How does
the tracing go? NE4 extracts through SPI module on the tributary optical board the
clock information in STM-N signals sent by NE5 via the chain, and synchronizes
lower-level NEs (slave stations) on the ring.

7.5 S1 Byte and SDH Network Clock Protection Switching

Principle

1 Working principle of S1 byte

With the development and wide application of SDH optical synchronous transmission
system, more and more people are keenly interested in ITU-T defined principle about
synchronous clock S1 byte and the application. Introduced here are the working
principle of S1 byte and the control protocol realizing synchronous clock protection
switching by using S1 byte. Meanwhile, an example is taken to show the application of
S1 byte.
In SDH network, each NE traces the same clock reference source level by level via a
specific clock synchronization path, thus synchronizing the whole network. Usually, an
NE may obtain synchronous clock source through more than one path. In other words,
there may be multiple clock reference sources available for an NE at the same time.
They may come from the same master clock source or from reference clock sources of
different qualities. In the synchronization network, it is very important to keep respective
NE clocks synchronous. To prevent the interruption of one clock synchronization path
from causing loss of the whole network synchronization, it is necessary to consider the
automatic protection switching of the synchronous clock. That is to say, when the
synchronous clock reference source that an NE is tracing is lost, this NE should be able
to switch to trace another clock reference source automatically. The latter clock
reference source may be the same clock source as the lost clock reference source, and
it may also be a clock source worse than the lost one. Obviously, it is necessary to know
the quality information of respective clock reference sources to complete the above
functions.
S1 byte defined by ITU-T is used to transmit quality information of clock source. Here,
the high four bits of the section overhead byte S1 byte are used to indicate 16 kinds of
synchronous source quality information.
Table 7-1 lists ITU-T defined synchronization status information codes. Using this
information and following a specific switching protocol, it is possible to implement
automatic protection switching function of synchronous clock in synchronization
network.

Table 7-1 Synchronous status information codes

S1 (b5-b8)
( S1 byte Description of SDH
synchronization quality level
0000 0x00 Synchronization quality unknown
(only for the existing
synchronization network)

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0001 0x01 Reserved

0010 0x02 G.811 clock signal
0011 0x03 Reserved
0100 0x04 G.812 transit exchange clock signal
0101 0x04 Reserved
0110 0x06 Reserved
0111 0x07 Reserved
1000 0x08 G.812 local exchange clock signal
1001 0x09 Reserved
1010 0x0A Reserved
1011 0x0B Synchronous equipment timing
source (SETS) signal
1100 0x0C Reserved
1101 0x0D Reserved
1110 0x0E Reserved
1111 0x0F Should not be used for
synchronization

In SDH optical synchronization transmission system, clock automatic protection

switching follows the protocol below:
Quality threshold of a synchronization clock source should be specified. NE first selects
a clock source of the highest level from the clock reference sources reaching the quality
threshold as the synchronous source, and transmits quality information (i.e. S1 byte) of
the synchronous source to a downstream NE.
If there is no clock reference source reaching the quality threshold, then select a clock
source of the highest level from the currently available clock sources as the
synchronous source, and transmit its quality information (i.e. S1 byte) to NE in the
downstream.
If the clock synchronization source currently traced by NE B is clock of NE A, then NE B
clock is unavailable synchronous source for NE A.

2 Examples

An example is given below to show how to implement automatic protection switching of

synchronization clock.
In the transmission network shown in Figure 7-6, BITS clock signals are accessed
through external clock access interfaces of NE1 and NE4.The two external BITS clocks
are active/standby to each other, satisfying quality requirements of G812 local clock
reference source. When working normally, clocks of the whole transmission network
are synchronous with external BITS clock reference source of NE1.

BITS

E W E W
NE1 NE6
W E
NE2 BITS NE5
E W
NE3 NE4
W E W E

Figure 7-6 Clock tracing in normal status

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The quality threshold of synchronous source clock should be set to not poorer than
G812 local clock. Configuration of synchronous source and clock source levels of
respective NEs is shown in Table 7-2.

Table 7-2 Configuration of synchronous source and clock source levels of respective NEs

NE Synchronous source Clock source level

NE1 External clock source External clock source, west clock
source, east clock source and
built-in clock source.
NE2 West clock source West clock source, east clock
source and built-in clock source.
NE3 West clock source West clock source, east clock
source and built-in clock source.
NE4 West clock source West clock source, east clock
source, external clock source and
built-in clock source.
NE5 East clock source East clock source, west clock
source and built-in clock source.
NE6 East clock source East clock source, west clock
source and built-in clock source.

In addition, NE1 and NE4 should also be set with the timeslot (given by BITS provider)
where S1 byte of external BITS clock is located.
In normal working, disconnection of the optical fiber between NE2 and NE3 will trigger
automatic protection switching of synchronization clock. In compliance with the above
switching protocol, since NE4 traces clock of NE3, the clock quality information sent by
NE4 to NE3 is Clock source unavailable, i.e. S1 byte is 0XFF.Thus, when NE3 detects
that the west synchronous clock source is lost, NE3 can not use the east clock source
as synchronous source of local station. It can only use the built-in clock source of local
station as its clock reference source, and transmit this information through S1 byte to
NE4, i.e. NE3 transmits S1 byte 0X0B to NE4, indicating Clock signal of synchronous
equipment timing source (SETS). NE4 receives this information and finds that the
synchronous source quality traced deteriorates (originally it is G812 local exchange
clock, i.e. S1 byte is 0X08), not up to the set synchronous source quality threshold.
Then NE4 needs to reselect the clock reference source satisfying quality requirement.
Four clock sources are available for NE4: west clock source, east clock source, built-in
clock source and external BITS clock source. O bviously, now only the east clock
source and external BITS clock source reach the quality threshold. Because the level of
the east clock source configured in NE4 is higher than that of the external BITS clock
source, NE4 finally selects east clock source as synchronous source of the local station.
After the synchronous source traced by NE4 is switched from west to east, the east
clock source of NE3 becomes available. Now the quality of the east clock source meets
quality threshold, and is of highest level, so NE3 will select the east clock source as the
synchronous source of the local station. Finally, the clock tracing status of the whole
transmission network is as Figure 7-7 shows.

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BITS

E W E W
NE1 NE6
W E
NE2 BITS NE5
W
NE3 NE4
E W E

Figure 7-7 Clock tracing when the optical fiber between NE2 and NE3 is damaged

In normal working status, if external BITS clock of NE1 is faulty, then according to the
switching protocol and analyzed in the above said method, the final clock tracing status
of the transmission network is shown in Figure 7-8.

E W E W
NE1 NE6
W E
NE2 BITS NE5
E W
NE3 NE4
W E W E

Figure 7-8 Clock tracing when the external BITS of NE1 is invalid

If external BITS clocks of both NE1 and NE4 are faulty, then at this time all the available
clock sources of each NE fail to meet the quality threshold of the reference source. In
this case, according to the switching protocol, respective NEs will select the clock
source of the highest level from the available clock sources as their synchronous
source. Suppose clocks of all NEs in the network are synchronous to NE4 clock before
fault occurs to all the BITS, then after the two BITS clocks get faulty, it can be seen
through analysis that the clocks of respective NEs in the network will still be
synchronized to NE4 clock, as shown in Figure 7-9.But at this time, the synchronous
source clock quality of the whole transmission network is degraded from G812 local
clock to the timing source clock of the synchronous equipment. But the whole network
is still synchronized to the same clock reference source.

E W E W
NE1 NE6
W E
NE2 NE5
E Built-in clock W
NE3 NE4
W E W E

Figure 7-9 Clock tracing when both the two external BITS are invalid

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Here, it can be seen that both reliability and synchronization performance of

synchronization network are improved greatly thanks to the implementation of clock
automatic protection switching.

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? Questions:
What have been talked about in this section?
1. Network synchronization modes----master/slave synchronization and pseudo-synchronization.
2. The three work modes of node clock in synchronization network.
3. Requirements for network synchronization by SDH network, and quality level classification of
master/slave synchronization clock in SDH network.
4. Modes to realize master/slave synchronization in SDH network.
Here, point 4 is the focus of this section, have you mastered it?

Summary
This section mainly describes common synchronization modes of SDH synchronization
network, and usual clock tracing modes of different kinds of equipment.

Exercises
1. Common synchronization modes of digital network are , .

2. Clock sources available for an SDH NE are ________, ________, ________,

________. , , , .

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