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Features
Triple Voltage Regulator
Output Voltage 5 V with 450 mA Current Capability
Two tracked Outputs for 50 mA and 100 mA
Enable Function for main and tracked Output(s)
Reset with adjustable Threshold
Undervoltage- and Power On-Reset
Watchdog
Independent Watchdog- and Reset delay
Wide Temperature Range
Overtemperature Protection
Overvoltage Protection
Reverse Polarity Proof
Green Product (RoHS compliant)
AEC Qualified
Functional Description
The TLE 4471 is a monolithic integrated very low-drop triple voltage regulator. The main
output supplies loads up to 450 mA and the additional tracked outputs can provide up to
50 mA and 100 mA. In addition the device includes a watchdog for microcontroller-
supervision, an undervoltage reset, a power on reset and extended enabling features.
The watchdog and reset timing can be chosen independently of each other. The
TLE 4471 is available in a Power PG-DSO-20 package. It is designed to supply
microprocessor systems under the severe condition of automotive applications and
therefore it is equipped with additional protection against overload, short circuit and
overtemperature. Of course the TLE 4471 can be used in other applications as well.
The TLE 4471 operates in the temperature range of Tj = -40 to 150 C.
Type Package
TLE 4471 G Power PG-DSO-20
E1 Main
1 Regulator 5 V 2%, 450 mA
E2 Q1
E3
Tracker 1
100 mA, 0.5% Tracking Q2
Reference Voltage REF2
Tracker 2
50 mA, 0.5% Tracking
EN Q3
Reference Voltage
REF3
Reset
Generator
Reset
DR Delay
R
Reset
RADJ Level
Adjust
W
Watchdog
DW TLE 4471
AES02864
GND 1 20 GND
E1 2 19 DW
I 3 18 W
Q2 4 17 Q3
REF2 5 16 E3
R 6 15 REF3
DR 7 14 EN
E2 8 13 N.C.
Q1 9 12 RADJ
GND 10 11 GND
AEP02865
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Note: In the operating range, the functions given in the circuit description are fulfilled.
Table 4 Characteristics
VI = 13.5 V; Tj = -40 C < Tj < 125 C
Parameter Symbol Limit Values Unit Measuring Condition
Min. Typ. Max.
Main Output Q1
Output voltage VQ1 4.9 5.0 5.1 V 10 mA < IQ1 < 450 mA;
5.5 V < VI < 19 V
Output voltage VQ1 4.8 5.0 5.2 V 10 mA < IQ1 < 300 mA;
5.5 V < VI < 28 V
Output voltage VQ1 4.8 5.0 5.2 V 10 mA < IQ1 < 200 mA;
5.5 V < VI < 40 V
Output current limit IQ1 550 1500 mA VQ1 = 0.1 V
Output voltage drop VDR 0.25 0.55 V IQ1 = 450 mA1)
Line regulation VQ1 -25 25 mV 8 V VI 16 V;
IQ1 = 10 mA
Load regulation VQ1 -25 25 mV 10 mA < IQ1 < 450 mA;
VI = 7 V
Power Supply Ripple PSRR 30 dB CQ1 = 22 F;
Rejection 20 Hz < fr < 20 kHz;
VPP = 0.5 V2)
Output capacitor CQ1 22 F 2)
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 C and
the given supply voltage.
II IQ1
VI I Q1 VQ1
IE1 22 F
VE1 E1 IQ2
IE2 Q2 VQ2
VE2 E2 10 F
IE3 IREF2
TLE 4471
VE3 E3
VREF2
REF2
IEN
VEN EN
IQ3
IDR, dis
Q3 VQ3
CDR DR 10 F
IRADJ 100 nF IDR, ch
VRADJ RADJ IREF3
IW REF3 VREF3
VW W
IR
CDW DW R VR
IDW, ch GND
100 nF
IGND
AES02866
Application Information
Q2 Sensor /
Peripheral
I Tracking
VBAT KL. 30 Output 2
REF2
optional
Main Q1 AD
DR RADJ
Watchdog /
Reset
R
DW
W Controller
E1
Ignition KL. 15 Enable E2
E3 Logic
Enable-Signal
EN AD
REF3
Tracking
Output 3
Q3 Sensor /
Peripheral
AES02867
Input
With an input voltage between 5.5 V < VI < 40 V the regulator works in its normal
operating range. If the input voltage exceeds the 40 V up to 60 V for less than 400 ms,
e.g. caused by a load dump, the active components are switched off.
For compensating line influences and to avoid steep input edges above 1 V/s an input
capacitor is needed. Using a resistor of approx. 1 in series to the input capacitor, the
oscillating circuit consisting of input inductance and input capacitor is damped.
Output Voltage
To obtain an output voltage of VQ1 = 5 V with an accuracy of 2% at the main output Q1
an input voltage in the range of 5.5 V < VI < 40 V is needed. The main output Q1 supplies
5 V with 450 mA current capability. For stability it requires an output capacitor of at least
22 F and a maximum ESR of 3 . The two outputs Q2 and Q3 are tracked to Q1 and
can supply currents of 100 mA and 50 mA. So any undervoltage condition or shutdown
of Q1 will cause the same effect to Q2 and Q3. For Stability both outputs require an
output capacitor of at least 10 F with ESR < 3 each. Q2 is switched on and off
simultaneously with Q1, while the tracked output Q3 can be enabled or disabled
individually.
Two reference outputs REF2, REF3 with voltages of VREF2 = VQ2/2 and VREF3 = VQ3/2 are
also available. In case of an overvoltage at the tracker outputs, the voltage references
are limited internally to 4.5 V.
Output Current
The output current is a function of the input voltage. For high input voltages above 22 V,
the output current is reduced linear. This is designed into the regulator for protection.
Above 42 V the regulator is switched off. The thermal shutdown switches the regulator
off, if it exceeds the thermal threshold of 160 C typical. It is switched on again, as soon
as the regulator is cooled down by typical 10 K (thermal hysteresis). Please note the
device should not be operated above a junction temperature of 150 C for long term
reliability.
Enable Function
The TLE 4471 includes the possibility of enabling the main and tracked outputs.
Three ORed enable inputs E1, E2, E3 are used to control the main output Q1 and the
tracked output Q2. E1 and E3 can be supplied from the battery line or ignition key with
input voltages up to 16 V. The enable inputs should be protected by a series resistor and
a capacitor, e.g. RE1 = RE3 = 22 k, CE1 = CE3 = 2.2 nF. E2 is intended for connection to
the microcontroller. A logic HIGH at any enable input will switch on the related regulator
and/or tracker.
A separate enabling pin EN is available to switch on and off the second tracked output
Q3 separately by the microcontroller.
Reset
The power on reset feature is necessary for a defined start of the microprocessor during
power up. When the output voltage of the main regulator has reached the reset threshold
voltage the reset delay capacitor CDR is charged. After a certain time, the reset delay time
tdr, the voltage at the capacitor equals the upper reset timing threshold and the reset
output goes HIGH.
The reset delay time tdr is defined by the reset delay capacitor CDR at pin DR and can be
calculated as follows:
VDR ,dt
t rd = C DR --------------
- (1)
I DR ,ch
Definitions:
CDR = reset delay capacitor
tdr = reset delay time required by the application
VDR, dt = typical 1.8 V for power up reset
IDR, ch = charge current typical 4 A
For a delay capacitor CDR = 100 nF the typical power up reset delay time is 45 ms.
The undervoltage reset circuitry supervises the output voltage. In case VQ1 falls below
the reset threshold the reset output is set LOW after the reset reaction time trr (discharge
of the reset delay capacitor). The reset LOW signal is held down to an output voltage VQ1
of 1 V. Both, the reset reaction time and the reset delay time are defined by the capacitor
value.
The reset reaction time trr is the time it takes the voltage regulator to set its reset output
LOW after the output voltage has dropped below the reset threshold. The reset reaction
time can be calculated using the following equation:
V DR ,dt V DR ,st
t rr = C DR -----------------------------------
- (2)
I DR ,dis
t
VQ < t rr
V Q, rth
t
VD
VDR, dt
VDR, st
t rr t
t dr
V RO
t
Power-on-Reset Thermal Voltage Dip Undervoltage Secondary Overload
Shutdown at Input Spike at Output AED03045
TLE 4471
I Q
Bandgap
Reference
RRTH1
1.36 V
R
Vrth,ref
RADJ
RRTH2
AES02877
RRTH1
V Q, rthext = V rth ,ref 1 + --------------
- (3)
RRTH2
Watchdog
The reset and watchdog timing can be defined independently of each other by two delay
capacitors CDR and CDW at pins DR and DW.
The watchdog function supervises the microcontroller including time base failures. If
there is no positive edge within a certain pulse repetition time twp or the trigger pulse is
too short a reset is generated. Programming of the max. repetition time is done by a
delay capacitor CDW at pin DW.
The frequency of the watchdog pulses generated by the microcontroller has to be higher
than the minimum pulse sequence twp set by the external reset delay capacitor CDW. The
pulse repetition time can be calculated as follows:
V DW ,dt V DW ,st
t wp = C DW -------------------------------------
- (4)
I DW ,ch
VI
t
VQ1
t
t > 10 s t > 25 s
VW
t
tWP
VDW VDW,dt
VDW,st
t
VDR
VDR,dt
VDR,st
tdr trr t
VR
t
Missing edge Watchdog pulses
at Watchdog too short
AET03000
Power Supply Ripple Rejection PSRR of Power Supply Ripple Rejection PSRR of
Main Output Q1 versus Frequency f Output Q2 versus Frequency f
AED02996
AED02995 80
80
dB CQ1 = 22 F dB CQ2 = 10 F
PSRR PSRR
I Q1 = 10 mA
70 70
I Q1 = 450 mA
IQ2 = 1 mA
60 60
50 50
IQ2 = 100 mA
40 40
30 0 30 0
1 2 3 4 5 10 101 102 103 Hz 105
10 10 10 10 10 Hz 10
f f
70
IQ3 = 1 mA
60
50
40
IQ3 = 50 mA
30 0
10 101 102 103 Hz 105
f
Enable Currents IE1, IE3 and Output Enable Currents IE2, IEN and Output
Voltage VQ1 versus Enable Voltages Voltage VQ3 versus Enable Voltages
VE1, VE3 VE2, VEN
AED02998 AED02999
5 7.5 250 7.5
A V A V
IE1, IE3 VQ1 IE2, IEN VQ3
4 6 200 6
2 3 100 3
1 1.5 50 1.5
0 0 0 0
0 1 2 3 4 V 5 0 0.5 1 1.5 2 V 2.5
VE1, VE3 VE2, VEN
Package Outlines
11 0.15 1)
3.5 MAX.
B
3.25 0.1
+0.07
2.8
-0.02
1.1 0.1
0 +0.1
0.25
5 3
1.3
15.74 0.1
6.3
1.27 (Heatslug) 0.1 Heatslug
(Mold)
0.95 0.15
0.4 +0.13
0.25 M A 20x 14.2 0.3
0.25 B
Bottom View
(Metal)
(Metal)
5.9 0.1
3.2 0.1
20 11 11 20
Index Marking
1 1 Heatslug
10 10
1 x 45 13.7 -0.2
15.9 0.15 1) (Metal)
A
(Mold)
1)
Does not include plastic or metal protrusion of 0.15 max. per side
GPS05791
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Revision History
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
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