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5 4 3 2 1

Block Diagram Rev. B


STMP35XX Reference Schematics
Revision History MAIN MEMORY Page 9 or 10 DISPLAY Page 11
REV. A - 3/3/03 Liquid
NAND FLASH Crystal Voltage
Original Release
Display Generation
D D
REV. B - 8/20/03 (LCD) Capacitors
Added Switched USB Jack 3500 page SD/MMC Connector
Backlight
Added 35XX 1-Channel Buck page LED
Edited boot mode tables.
Updated the Buck mode Play/Pswitch circuit to prevent excessive
current being injected into the Pswitch pin. BUTTONS Page 12 OPTIONAL Page 15
Added Optional Line-In circuit to Optional Circuits Page. CIRCUITS
Removed TEA5757 FM Tuner. FM TUNER Page 13 or 14 STMP35XX Button Matrix Misc. Circuits
Removed 35XX 144QFP information.
FM Tuner
Added Panasonic BTF-03 FM Tuner page.
Removed C115 and C116, optional ESD caps on USB D+ and D-.
STMP35XX Page 5, 6, 7, or 8 USB & MICROPHONE Page 2
Removed R139, NOPOP resistor shorting VDDIO to VDDIO_P.
Boot Mode Universal Serial Bus
Changed LED drive to match 3410 Rev. G schematics (and Host Computer
C Select Connector C
keep the same polarity as 3410 SDK LEDs).
Changed the value of resistors to PSwitch from 47K to 20K. DCDC
Battery Microphone
Added pull-up resistors on MMC socket pins 8 and 9. Converter
Components
Added optional 16-bit NAND support.
Updated Boot Mode tables.
AUDIO Page 3 or 4
Removed SmartMedia circuit.
Headphone
Changed default TEA5767 FM Tuner connections as follows: 24.000MHz crystal Connector Headphones
FM_DATA changed from GPIO_19 to I2C_DATA
FM_CLOCK changed from GPIO_18 to I2C_CLK
SWP1 changed from I2C_CLK to GPIO_33
Added SW24 (Reset Button) option to STMP35XX pages.
To use these schematics to create a design:
Removed 1K pull-up to VDDIO on the Hold Switch.
B 1) Select USB and Microphone options on "USB & MICROPHONE" page B

2) Select one of the audio pages: 100QFP STMP35XX Audio Options


144BGA STMP35XX Audio Options

3) Select one of the STMP35XX pages: STMP35XX 100-TQFP Boost Mode


STMP35XX 100-TQFP Single Channel Buck Mode
STMP35XX 144-BGA Dual Channel Buck Mode
STMP35XX USB Shared Jack Boost Mode

4) Select one of the "Memory" pages: NAND flash only


MMC + NAND flash SigmaTel, Inc.
3815 Capital of Texas Hwy.
Suite 300
5) Select options on the "Display" page as required.
A
NOTE: These schematics are Austin, TX 78704
tel: (512)381-3700 A
www.sigmatel.com
preliminary and are subject to 6) Select options on the "Buttons" page as required.
Title
STMP35XX Reference Schematics
change. 7) If required, select one of the "FM Tuner" pages.
Page
Revision History
8) If required, select any of the circuits on the "Optional Circuits" page.
Size This design is the property of SigmaTel, Inc. It is offered Rev
B B
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 1 of 15
5 4 3 2 1
5 4 3 2 1

USB 2.0 Connector Microphone Bias Options


Route USB D+ and D- according to the High Speed USB2.0 Design Guidelines.
D+ and D- should have a 90 ohm differential trace impedance. OPTION 1: Microphone using LRADC1 MIC_BIAS
Use 20 mil minimum spacing between D+ and D- and other signal lines.
Note: If the LRADC1 line is unavailable, LRADC2 may be used for the
D
In order to maximize ESD immunity, the industrial design plastics should expose the Microphone Bias. If both LRADC1 and LRADC2 are unavailable, use D
USB Connector as little as possible. OPTION 2.
L13 and L14 are placeholders for optional ferrites that can be populated for ESD LRADC1
immunity if necessary. If they are not required, populate a 0 ohm resistor. X1 C37
MIC
CN1 Pins 6-9 are pins connecting to the USB connector outer shield
0.1uF
L22 WM-62A Microphone
USB_5V
CN1
USB_AMP_MINI 600 Ohms @ 100MHz AGND
DCR < 350mOhms
6 1 R18 R160
7 2 USB_D-
3
8 4 0 Ohm 0 Ohm OPTION 2: Microphone using VDDIO bias
9 5 C132
NOPOP T1 Use this circuit if it is not VDDIO_P
L14 COMMON MODE CHOKE
600 Ohms @ 100MHz GND NOPOP possible to use the LRADC
DCR < 350mOhms R19 R161 microphone bias circuit. R25
2.2K
C USB_D+ C
L13 10%
C36 600 Ohms @ 100MHz 0 Ohm 0 Ohm R26
0.1uF DCR < 350mOhms C133
NOPOP
X1 2.2K 10% C37
GND GND GND MIC
C38 0.1uF
WM-62A Microphone C39 + 10uF
0.1uF 6.3V
Tantalum

AGND

B B

SigmaTel, Inc.
3815 Capital of Texas Hwy.
Suite 300
Austin, TX 78704
A tel: (512)381-3700 A
www.sigmatel.com
Title
STMP35XX Reference Schematics
Page
USB & MICROPHONE
Size This design is the property of SigmaTel, Inc. It is offered Rev
B B
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 2 of 15
5 4 3 2 1
5 4 3 2 1

100QFP STMP35XX AUDIO OPTIONS


For a design using a 100QFP with an FM Tuner or Line-In Jack:

AC-Coupled Headphone Jack OPTION 1: LINE-IN CIRCUIT ONLY OPTION 3: FM TUNER ONLY
D D
L4 C32 L19 FM_R LINE_IN_R
600 Ohms @ 100MHz 220uF 600 Ohms @ 100MHz C126
J1 1 4V J5 1
LINE_OUT_R LINE_IN_R FM_L LINE_IN_L
DCR < 350mOhms Tantalum

+
DCR < 350mOhms
2 2 1uF
3 L5 C33 3 L20 C127
headphone 600 Ohms @ 100MHz 220uF line-in jack
LINE_IN_L
4V 600 Ohms @ 100MHz
LINE_OUT_L
DCR < 350mOhms Tantalum DCR < 350mOhms 1uF

+
C34 C35 L21
HP_GND_A
R20 R21 0.01uF 0.01uF 600 Ohms @ 100MHz
100 100 DCR < 350mOhms
10% 10%
L6 R22 R23
600 Ohms @ 100MHz 16 16 AGND
DCR < 350mOhms 10% 10%

OPTION 2: LINE-IN JACK + FM TUNER For the 100 Pin QFP package, only
AGND AGND AGND L19 one set of LINE IN inputs are
C 600 Ohms @ 100MHz C126 available. If a LINE-IN Jack and an C
NOTE: HP_GND_A is the antenna for designs with an FM Tuner LINE_IN_R FM Tuner are both included in the
J5 2 DCR < 350mOhms
3 1uF
FM_R design, they will need to share the
4
5
FM_L LINE-IN input. This circuit uses a
1 L20 C127 switched audio jack to switch
CUI SJ-3525N
line-in jack 600 Ohms @ 100MHz
LINE_IN_L between LINE-IN and FM Tuner.
DCR < 350mOhms 1uF When nothing is plugged into the
L21
600 Ohms @ 100MHz
jack, the FM Tuner is connect to the
DCR < 350mOhms LINE-IN inputs. When a plug is
inserted, the FM Tuner will be
AGND disconnect.

For a design using a 100QFP with no FM Tuner or Line-In Jack:


B B

Direct Drive Headphone Jack


L4
600 Ohms @ 100MHz
J1 1 LINE_OUT_R
DCR < 350mOhms
2 L5
3 600 Ohms @ 100MHz
headphone
LINE_OUT_L
DCR < 350mOhms
C34 C35
0.01uF 0.01uF

R22 R23
16 16
SigmaTel, Inc.
L6 10% 10% 3815 Capital of Texas Hwy.
600 Ohms @ 100MHz Suite 300
Austin, TX 78704
A
LINE_IN_R tel: (512)381-3700 A
DCR < 350mOhms www.sigmatel.com
Title
This connection should be as close to
the Headphone Jack as possible. LINE_IN_L STMP35XX Reference Schematics
Page
100QFP AUDIO OPTIONS
Size This design is the property of SigmaTel, Inc. It is offered Rev
B B
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 3 of 15
5 4 3 2 1
5 4 3 2 1

144BGA STMP35XX AUDIO OPTIONS


For a design using a 144BGA with FM TUNER and Line-In Jack :
AC-Coupled Headphone Jack Direct Drive Headphone Jack
D L4 C32 L4 D
600 Ohms @ 100MHz 220uF 600 Ohms @ 100MHz
J1 1 4V J1 1
LINE_OUT_R LINE_OUT_R
DCR < 350mOhms Tantalum

+
DCR < 350mOhms
2 2 L5
3 L5 C33 3 600 Ohms @ 100MHz
headphone 600 Ohms @ 100MHz 220uF headphone
LINE_OUT_L
4V DCR < 350mOhms
LINE_OUT_L
DCR < 350mOhms Tantalum

+
C34 C35
C34 C35 0.01uF 0.01uF
HP_GND_A
R20 R21 0.01uF 0.01uF
100 100
10% 10% R22 R23
L6 R22 R23 16 16
600 Ohms @ 100MHz 16 16 L6 10% 10%
DCR < 350mOhms 10% 10% 600 Ohms @ 100MHz
HP_GND_A LINE_IN_R
OR DCR < 350mOhms

This connection should be as close to


AGND AGND AGND LINE_IN_L
the Headphone Jack as possible.
C NOTE: HP_GND_A is the antenna for designs with an FM Tuner NOTE: HP_GND_A is the antenna for designs with an FM Tuner C

LINE-IN CIRCUIT FM TUNER LINE-IN JACK + FM TUNER If a LINE-IN Jack and an FM Tuner
L19 L19
600 Ohms @ 100MHz C126 600 Ohms @ 100MHz C126 are both included in the design,
FM_R LINE_IN2_R
J5 1 they will need to share the LINE-IN
LINE_IN_R LINE_IN2_R
DCR < 350mOhms J5 2 DCR < 350mOhms
2 1uF
FM_L LINE_IN2_L
3 1uF input. This circuit uses a switched
FM_R
3 L20 C127 4 FM_L audio jack to switch between
line-in jack 5
600 Ohms @ 100MHz
LINE_IN_L
1 L20 C127 LINE-IN and FM Tuner. When
DCR < 350mOhms 1uF CUI SJ-3525N
LINE_IN2_L nothing is plugged into the jack,
line-in jack 600 Ohms @ 100MHz
L21 DCR < 350mOhms 1uF the FM Tuner is connect to the
600 Ohms @ 100MHz L21 LINE-IN inputs. When a plug is
DCR < 350mOhms 600 Ohms @ 100MHz
DCR < 350mOhms
inserted, the FM Tuner will be
disconnect.
AGND
AGND

B B

For a design using a 144BGA with FM Tuner or Line-In Jack:


Direct Drive Headphone Jack OPTION 1: LINE-IN CIRCUIT ONLY
L19
L4 600 Ohms @ 100MHz C126
600 Ohms @ 100MHz J5 1 LINE_IN2_R
J1 1 DCR < 350mOhms
LINE_OUT_R
DCR < 350mOhms 2 1uF
2 L5 3 L20 C127
3 600 Ohms @ 100MHz line-in jack
LINE_IN2_L
headphone 600 Ohms @ 100MHz
LINE_OUT_L
DCR < 350mOhms DCR < 350mOhms 1uF

C34 C35 L21


0.01uF 0.01uF 600 Ohms @ 100MHz
SigmaTel, Inc.
DCR < 350mOhms 3815 Capital of Texas Hwy.
Suite 300
R22 R23 Austin, TX 78704
A 16 16 AGND tel: (512)381-3700 A
L6 10% 10% www.sigmatel.com
600 Ohms @ 100MHz Title
HP_GND_A LINE_IN_R STMP35XX Reference Schematics
DCR < 350mOhms OPTION 2: FM TUNER ONLY Page
This connection should be as close to FM_R LINE_IN2_R 144BGA AUDIO OPTIONS
the Headphone Jack as possible. LINE_IN_L
Size This design is the property of SigmaTel, Inc. It is offered Rev
FM_L LINE_IN2_L
NOTE: HP_GND_A is the antenna for designs with an FM Tuner B B
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 4 of 15
5 4 3 2 1
5 4 3 2 1

STMP35XX 100-Pin TQFP - BOOST MODE VDDIO_P Power Switch


This circuitry creates a VDDIO_P for peripheral devices. When the
This circuit shows the STMP35XX in a NiMH or 1.5V Alkaline player is powered-down, VDDIO_P will drop to GND. This allows
boost-mode configuration. For the NiMH case, the battery may be VDDD peripheral devices to receive a power-on reset, since VDDIO drops
charged using USB_5V as a source. The charge current will be to the battery voltage when the player is powered down.
delivered through the DCDC_BATT pin. Care must be taken in the The PFET used in this circuit should have an
C2 C3 C4 + C1
design to ensure that the user may not charge an alkaline battery. 0.01uF 0.1uF 1uF 68uF Rds,on less than 2 ohms when Vgs = -2.8V.
Si2305DS
A good choice is an Si2305 transistor or
equivalent. 1 G
D 3
VDDIO VDDIO_P S
2
D GND D
SOT-23
VDDIO R140 TOP VIEW
100K 10% Q15
Si2305

C9 C10 C11
+ R141 MMBT3904
C8 100K
0.01uF 0.1uF 1uF 68uF
VDDD R142 10% B
L1 1
VDDD Q16
One cap for each pin (39, 11, 86) 0 Ohm resistor C 3
100K 10% MMBT3904
2 E
GND SOT-23
L2 C5 C6 C7 GND GND TOP VIEW
R39 4.7uH 0.1uF 0.1uF 0.1uF
Power/Play 10K BT1 VDD_BAT 1W
Switch 10%
POS
1
PLAY_SW
+
D14
R41 3 + 10BQ015
NTC LRADC2 C14 C15
20K 68uF 1uF 1 Amp GND
VDDIO SW2 10% Schottky
PSWITCH
_ NEG
2 NOPOP
One cap for each pin (29, 96) VDDIO
SW PUSHBUTTON
R42 C42 SW24 NiMH / Alkaline Battery GND
"Power/Play/Pause 10K 1uF SW PUSHBUTTON
10% VDD_BAT C12 C13
Button" "Reset Button"
0.1uF 0.1uF

PSWITCH
GND GND

79

49

47

48

50

54

11
39
86

10
38
87

29
96

28
97
U1 GND
Note: For players with a non-removeable battery (i.e. rechargeable), it VDD5V
61

DCDC_VddIO

VddD2
VddD1
VddD3

VddIO1
VddIO2
DCDC_VddD

DCDC_Gnd

DCDC_Mode2
PSWITCH

DCDC_Batt

VssD2
VssD1
VssD3

VssIO1
VssIO2
may be necessary to include switch SW24 (Reset) to allow the user to USB_5V Vdd5V
C enter Player Recovery Mode. For players with a removeable battery C129 C130
USB_D+ 80
USB_DP
C
0.1uF 1uF 81
(i.e. alkaline), this switch is not necessary. USB_D- USB_DM
67 Vag 37 IO7
GP31 / SM_D7 / CF_D7
NOTE: Vag and Vbg filter 66
Vbg GP30 / SM_D6 / CF_D6
36 IO6
C17 35
GND caps should have their C16
0.1uF GP29 / SM_D5 / CF_D5
34
IO5
1uF GP28 / SM_D4 / CF_D4 IO4
ground return paths to 33
IMPORTANT DESIGN NOTES VssA1, pin 72.
GP27 / SM_D3 / CF_D3
32
IO3
GP26 / SM_D2 / CF_D2 IO2
The D14 diode may be required for battery GP25 / SM_D1 / CF_D1
31 IO1
VDDA AGND 30
charge applications. 64
GP24 / SM_D0 / CF_D0 IO0
VddHP
73 27 WP#
VddA1 GP55 / SM_WPn
The L2 inductor is a critical component - for best battery One cap between 76
VddPLL GP54 / SM_WEn
26 WE#
C18 C19 C20 25
life, L2 should be a quality, low-ESR inductor. The each PWR and 0.1uF 0.1uF 0.1uF 63
GP56 / SM_READY / CF_WAITn FLASH_RDY
GND pair. VssHP
Panasonic ELL6H inductor or equivalent is 72 9
recommended for this component. 78
VssA1
VssPLL
STMP35XX GP51 / CF_IOWRn
GP52 / CF_IORDn
8
GPIO_51
GPIO_52

The industrial design plastics should mechanically AGND 65


100-Pin TQFP 22
LINE_OUT_R HPR GP42 / CF_A10 GPIO_42
62 21
prevent a battery accidentally inserted backwards from LINE_OUT_L HPL GP41 / SM_ALE / CF_A9
20
ALE
GP40 / SM_CLE / CF_A8 CLE
making contact with the battery terminals. MIC 55
MIC GP39 / SM_SEn / CF_A7
19 SE#
18 CE0#
GP38 / SM_CE0n / CF_A6
Route VDD_BAT as a 30mil trace from the positive LINE_IN_R 59
LINE1R / HP_COMMON GP37 / SM_CE2n / CF_A5
17 CE2#
57 16
battery terminal to the L2 inductor, and from the L2 LINE_IN_L LINE1L / HP_SENSE GP36 / SM_CE3n / CF_A4
15
CE3#
GP35 / CF_A3 GPIO_35
inductor to the STMP35XX DCDC_BATT pin. LRADC1 58 LRADC1 / MIC_BIAS GP34 / CF_A2
14 GPIO_34
LRADC2 60 13 GPIO_33
LRADC2 / TEMP_SENSE / MIC_BIAS GP33 / CF_A1
VDD_BAT 56 12 GPIO_32
BATT GP32 / CF_A0

GP14 / SPI_MOSI / SM_WP2n


Route GND back to the battery negative terminal as either
24
a 30mil trace or as part of a wide digital ground plane 70
GP45 / SM_CE1n / CF_CE0n
23
CE1#
REF_RES GP53 / SM_REn / CF_OEn RE#
71 44 GPIO_43
REFp GP43 / CF_REGn
68 43 GPIO_50
ADCL GP50 / CF-RESETn

GP7 / I2S_DataO2
GP6 / I2S_DataO1
GP5 / I2S_DataO0

GP13 / SPI_MISO
69 7

GP2 / I2S_DataI2
GP1 / I2S_DataI1
GP0 / I2S_DataI0
GP3 / I2S_WCLK

GP12 / SPI_SCK
GPIO_44

GP17 / I2C_SDA
ADCR GP44 / CF_CE1n

GP4 / I2S_BCLK

GP16 / I2C_SCL
100 GP15 / SPI-SSn
77 VddXTAL 45 GPIO_49
B
R32 GP49 / CF_BVD1 B
42

98 GP19 / TIO1
99 GP18 / TIO0
ONCE_DSO

TESTMODE
ONCE_DSK
ONCE_DRn
GP48 / CF_WPn GPIO_48
ONCE_DSI
STMP35XX BOOT MODE SELECT 620 C21 C22 C23 C25 41
GP47_CF_READY GPIO_47
3.3V NAND w/ Play 1% 0.1uF 0.001uF 0.001uF 0.1uF 40
GP46 / CF_CDn GPIO_46
GPIO

GP11

GP10
75
Recovery is the Default

GP9

GP8
XTALi
74
XTALo
BOOT MODE 00 01 02 03 08 Boot Mode.
46
52
51
53

88
89
90
91
92
93
94
95
82
83
85
84
1 1 0 1 0 AGND

6
1
2
3
4
5
3.3V NAND w/Play Recovery
Populate either a pull-up
3.3V NAND w/PSwitch Recovery 1 1 0 1 1 XTAL must be Y1
or a pull-down on these I2C_DATA
close to the I2C_CLK
1.8V NAND w/Play Recovery 1 1 0 0 0 GPIOs to select the SPI_SCK
STMP35XX 24.000MHz GND
1.8V NAND w/PSwitch Recovery 1 1 0 0 1 desired Boot Mode SPI_MISO
SPI_MOSI
C26 C27
SPI Master 1 0 1 0 1 All resistors are 47K 22pF 22pF GROUNDING & POWER
SPI_SS
RES0603. However, it GPIO_18
SPI Slave 1 0 1 1 1 GPIO_19
may be necessary to use VDDA L3 VDDD
I2C Master 1 0 1 1 0 a stronger pull-down, GPIO_08
AGND
GPIO_10
I2C Slave 1 0 0 1 1 such as a 10K, GPIO_09
600 Ohms @ 100MHz
DCR < 350mOhms
depending on the LCD ONCE_DSI GPIO_11
USB 1 0 0 1 0 ONCE_DSO GPIO_00
used. ONCE_DSK GPIO_01
JP2
ONCE_DRN GPIO_02 1 2
VDDIO 1 GPIO_03
VDDIO R13
GPIO_04
GPIO_05
GPIO_06
R6 R7 R8 R9 R10 47K AGND GND
GPIO_07
47K 47K 47K 47K 47K 10%
10% 10% 10% 10% 10% Tie all grounds together
NOPOP NOPOP
GPIO_00 under the IC
GPIO_01
A A
GPIO_02
SigmaTel, Inc.
GPIO_03 3815 Capital of Texas Hwy.
Suite 300
GPIO_08 Austin, TX 78704
tel: (512)381-3700
www.sigmatel.com
R11 R12 R14 R15 Title
47K 47K 47K 47K STMP35XX Reference Schematics
10% 10% 10% 10%
NOPOP NOPOP Page
STMP35XX 100-Pin TQFP - Boost Mode
0 Size This design is the property of SigmaTel, Inc. It is offered Rev
GND C B
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 5 of 15

5 4 3 2 1
5 4 3 2 1

STMP35XX 100-Pin TQFP - 1 CHANNEL BUCK MODE


This circuit shows STMP35XX in a Li-Ion single buck-mode configuration.
This schematic assumes a Li-Ion battery voltage of 3.0V to 4.2V. The Li-Ion
BT1 VDD_BAT U15 VDDIO VDDIO_P
battery will be recharged using USB_5V as a source, with the constant
POS 1 1 IN OUT 5
current charge current being delivered through the BATT pin. + 2 GND
+ C15 + C124 ENABLE 3 4 +
C14 EN FB C9 C10 C11 C8
3 68uF 1uF 10uF 0.01uF 0.1uF 1uF 68uF
NTC LRADC2
Zetex ZXCL300
3.0V Regulator
_ NEG
2 150mA
Regulator Enable VDD_BAT
D D
Circuit Li-Ion Battery GND
R70
100K
10%
MMBT3904
ENABLE
1 B
R176 One cap between each
C 3 Q13 L1
USB_5V
MMBT3904
PWR and GND pair. VDDD
2 E 0 Ohm resistor
100K 10%
SOT-23
TOP VIEW
GND L2 C5 C6 C7
4.7uH 0.1uF 0.1uF 0.1uF
VDDD 1W

R39
Power/Play 10K C2 C3 C4 + C1
Switch 10% 0.01uF 0.1uF 1uF 68uF GND
PLAY_SW
One cap between each
R41 VDDIO
20K
PWR and GND pair.
VDD_BAT SW2 10%
PSWITCH GND
C12 C13
SW PUSHBUTTON VDD_BAT 0.1uF 0.1uF
R42 C42 SW24
"Power/Play/Pause 10K 1uF SW PUSHBUTTON
PSWITCH
10% "Reset Button" GND
Button"

79

49

47

48

50

54

11
39
86

10
38
87

29
96

28
97
U1 GND
VDD5V
61

DCDC_VddIO

VddD2
VddD1
VddD3

VddIO1
VddIO2
DCDC_VddD

DCDC_Gnd

DCDC_Mode2

VssD2
VssD1
VssD3

VssIO1
VssIO2
PSWITCH

DCDC_Batt
USB_5V Vdd5V
C GND C
C129 C130 80
USB_D+ USB_DP
Note: For players with a non-removeable battery (i.e. rechargeable), 0.1uF 1uF 81
USB_D- USB_DM
it may be necessary to include switch SW24 (Reset) to allow the 67 37
Vag GP31 / SM_D7 / CF_D7 IO7
user to enter Player Recovery Mode. For players with a removeable NOTE: Vag and Vbg filter 66
Vbg GP30 / SM_D6 / CF_D6
36 IO6
35
battery (i.e. alkaline), this switch is not necessary. GND caps should have their C16
C17 GP29 / SM_D5 / CF_D5
34
IO5
1uF GP28 / SM_D4 / CF_D4 IO4
ground return paths to 0.1uF 33
GP27 / SM_D3 / CF_D3 IO3
VssA1, pin 72. 32 IO2
GP26 / SM_D2 / CF_D2
GP25 / SM_D1 / CF_D1 31 IO1
VDDA AGND
IMPORTANT DESIGN NOTES 64
GP24 / SM_D0 / CF_D0
30 IO0
VddHP
73 27 WP#
VddA1 GP55 / SM_WPn
The L2 inductor is a critical component - for best battery One cap between 76
VddPLL GP54 / SM_WEn
26 WE#
C18 C19 C20 25
life, L2 should be a quality, low-ESR inductor. The each PWR and 0.1uF 0.1uF 0.1uF GP56 / SM_READY / CF_WAITn FLASH_RDY
63
GND pair. VssHP
Panasonic ELL6H inductor or equivalent is 72 9
recommended for this component. 78
VssA1
VssPLL
STMP35XX GP51 / CF_IOWRn
GP52 / CF_IORDn
8
GPIO_51
GPIO_52

The industrial design plastics should mechanically AGND 65


100-Pin TQFP 22
LINE_OUT_R HPR GP42 / CF_A10 GPIO_42
62 21
prevent a battery accidentally inserted backwards from LINE_OUT_L HPL GP41 / SM_ALE / CF_A9
20
ALE
GP40 / SM_CLE / CF_A8 CLE
making contact with the battery terminals. MIC 55
MIC GP39 / SM_SEn / CF_A7 19 SE#
18 CE0#
GP38 / SM_CE0n / CF_A6
Route VDD_BAT as a 30mil trace from the positive LINE_IN_R 59
LINE1R / HP_COMMON GP37 / SM_CE2n / CF_A5
17 CE2#
57 16
battery terminal to the STMP35XX input. LINE_IN_L LINE1L / HP_SENSE GP36 / SM_CE3n / CF_A4
15
CE3#
GP35 / CF_A3 GPIO_35
LRADC1 58 14 GPIO_34
LRADC1 / MIC_BIAS GP34 / CF_A2
Route GND back to the battery negative terminal as LRADC2 60
LRADC2 / TEMP_SENSE / MIC_BIAS GP33 / CF_A1 13 GPIO_33
56 12
either a 30mil trace or as part of a wide digital ground VDD_BAT BATT GP32 / CF_A0 GPIO_32

GP14 / SPI_MOSI / SM_WP2n


plane GP45 / SM_CE1n / CF_CE0n 24 CE1#
70 23 RE#
REF_RES GP53 / SM_REn / CF_OEn
71 44 GPIO_43
REFp GP43 / CF_REGn
68 43 GPIO_50
ADCL GP50 / CF-RESETn

GP7 / I2S_DataO2
GP6 / I2S_DataO1
GP5 / I2S_DataO0

GP13 / SPI_MISO
69 7

GP2 / I2S_DataI2
GP1 / I2S_DataI1
GP0 / I2S_DataI0
GP3 / I2S_WCLK
GPIO_44

GP12 / SPI_SCK

GP17 / I2C_SDA
ADCR GP44 / CF_CE1n

GP4 / I2S_BCLK
B B

GP16 / I2C_SCL
100 GP15 / SPI-SSn
77 45 GPIO_49
R32 VddXTAL GP49 / CF_BVD1
STMP35XX BOOT MODE SELECT 42

98 GP19 / TIO1
99 GP18 / TIO0
ONCE_DSO

TESTMODE
ONCE_DSK
ONCE_DRn
GP48 / CF_WPn GPIO_48
ONCE_DSI

3.3V NAND w/ Play 620 C21 C22 C23 C25 41


GP47_CF_READY GPIO_47
GPIO 1% 0.1uF 0.001uF 0.001uF 0.1uF 40
Recovery is the Default GP46 / CF_CDn GPIO_46

GP11

GP10
75
XTALi

GP9

GP8
BOOT MODE 00 01 02 03 08 Boot Mode. 74
XTALo
3.3V NAND w/Play Recovery 1 1 0 1 0
46
52
51
53

88
89
90
91
92
93
94
95
82
83
85
84
Populate either a pull-up AGND

6
1
2
3
4
5
3.3V NAND w/PSwitch Recovery 1 1 0 1 1 or a pull-down on these XTAL must be Y1
I2C_DATA
1.8V NAND w/Play Recovery 1 1 0 0 0 GPIOs to select the close to the I2C_CLK
1.8V NAND w/PSwitch Recovery 1 1 0 0 1 desired Boot Mode STMP35XX 24.000MHz GND
SPI_SCK
SPI_MISO
SPI_MOSI
SPI Master 1 0 1 0 1 All resistors are 47K C26 C27 GROUNDING & POWER
22pF 22pF
RES0603. However, it SPI_SS
SPI Slave 1 0 1 1 1 GPIO_18
may be necessary to use GPIO_19
VDDA L3 VDDD
I2C Master 1 0 1 1 0 a stronger pull-down,
GPIO_08
I2C Slave 1 0 0 1 1 such as a 10K, AGND
GPIO_10
600 Ohms @ 100MHz
depending on the LCD GPIO_09
DCR < 350mOhms
USB 1 0 0 1 0 ONCE_DSI GPIO_11
used. ONCE_DSO GPIO_00
JP2
ONCE_DSK GPIO_01
VDDIO 1 1 2
ONCE_DRN GPIO_02
GPIO_03
VDDIO R13
GPIO_04
GPIO_05
R6 R7 R8 R9 R10
GPIO_06
47K 47K 47K 47K 47K 47K 10% AGND GND
GPIO_07
10% 10% 10% 10% 10%
NOPOP NOPOP Tie all grounds together
GPIO_00
under the IC
GPIO_01
A A
GPIO_02

GPIO_03 SigmaTel, Inc.


3815 Capital of Texas Hwy.
GPIO_08 Suite 300
Austin, TX 78704
tel: (512)381-3700
R11 R12 R14 R15 www.sigmatel.com
47K 47K 47K 47K Title
10% 10% 10% 10% STMP35XX Reference Schematics
NOPOP NOPOP
Page
STMP35XX 100-Pin TQFP - 1 Channel Buck Mode
0
GND Size This design is the property of SigmaTel, Inc. It is offered Rev
C B
on an "as is" basis, and carries no implied warranty.
Date: Thursday, September 04, 2003 Sheet 6 of 15
5 4 3 2 1
5 4 3 2 1

VDDIO_P VDDIO

STMP35XX 144-Pin BGA 2 Channel BUCK MODE


C9 C10 C11 +
This circuit shows STMP35XX in a Li-Ion buck-mode configuration. 0.01uF 0.1uF 1uF C8
68uF
This schematic assumes a Li-Ion battery voltage of 3.0V to 4.2V. The
Li-Ion battery will be recharged using USB_5V as a source, with the
charge current being delivered through the BATT pin. L1
GND One cap for each Vdd/Vss pin pair 0 Ohm resistor VDDD
BT1 VDD_BAT
POS 1
+ C5 C6 C7
0.1uF 0.1uF 0.1uF
3 +
NTC LRADC2 C14 C15
68uF 1uF
L18
D D
_ NEG 2 4.7uH
1W GND

Li-Ion Battery GND One cap for each Vdd/Vss pin pair VDDIO

VDDD L2
C12 C13 C119 C120
0.1uF 0.1uF 0.1uF 0.1uF
4.7uH 1 W GND
C2 C4 + C1 VDD_BAT GND
C3
0.01uF 0.1uF 1uF 68uF
PSWITCH
GND

D12

C12
B12

A12

A10

A11

B10

G6

G8
G5

G7
D3

D6
D8

H7

H8
H5
A3

A9

E8

E7

E6
F6

F8

F5

F7
GND U1

DCDC_VddIO

VddD1
VddD2
VddD3

VddIO1
VddIO2
VddIO3
VddIO4
DCDC_VddD

DCDC_Gnd

DCDC_Mode0
DCDC_Mode1
DCDC_Mode2

DCDC_VddA

DCDC2_Gnd

VssIO1
VssIO2
PSWITCH

DCDC_Batt

DCDC2_Batt

VssD1
VssD2
VssD3

VssIO3
VssIO4
DCDC2_Vout
R39
Power/Play 10K
Switch 10% VDD5V
PLAY_SW USB_5V B7 Vdd5V
R41 C129 C130 C2 J12
USB_D+ USB_DP GP79 / CF_D15 / RAM_D15 IO15
20K 0.1uF 1uF C1 J11
VDD_BAT SW2 USB_D- USB_DM GP78 / CF_D14 / RAM_D14 IO14
10% H11
GP77 / CF_D13 / RAM_D13 IO13
PSWITCH B4 G11 IO12
Vag GP76 / CF_D12 / RAM_D12
A5 G12 IO11
SW PUSHBUTTON C17 Vbg GP75 / CF_D11 / RAM_D11
NOTE: Vag and Vbg filter caps C16 GP74 / CF_D10 / RAM_D10
F9 IO10
R42 C42 SW24 GND 1uF 0.1uF F12
10K 1uF SW PUSHBUTTON should have their ground return GP73 / CF_D9 / RAM_D9 IO9
"Power/Play/Pause paths to VssA1, pin 105. GP72 / CF_D8 / RAM_D8 E9 IO8
10% "Reset Button" F10
Button" GP31 / SM_D7 / CF_D7 / RAM_D7
F11
IO7
GP30 / SM_D6 / CF_D6 / RAM_D6 IO6
GP29 / SM_D5 / CF_D5 / RAM_D5 G9 IO5
AGND G10 IO4
VDDA GP28 / SM_D4 / CF_D4 / RAM_D4
H10 IO3
GP27 / SM_D3 / CF_D3 / RAM_D3
GND D5 H12 IO2
VddHP GP26 / SM_D2 / CF_D2 / RAM_D2
B2 VddA1 GP25 / SM_D1 / CF_D1 / RAM_D1 H9 IO1
C Note: For players with a non-removeable battery (i.e. rechargeable), One cap between B1
VddPLL GP24 / SM_D0 / CF_D0 / RAM_D0
J10 IO0
C
C18 C19 C20
it may be necessary to include switch SW24 (Reset) to allow the each PWR and 0.1uF 0.1uF 0.1uF C6
GND pair. VssHP
user to enter Player Recovery Mode. For players with a removeable B5 VssA1 GP55 / SM_WPn
K12 WP#
E5 L11
battery (i.e. alkaline), this switch is not necessary. VssPLL GP54 / SM_WEn / CF_WEn
M12
WE#
GP56 / SM_READY / CF_WAITn FLASH_RDY
AGND L4
GP51 / CF_IOWRn GPIO_51
GP52 / CF_IORDn J5 GPIO_52

IMPORTANT DESIGN NOTES LINE_OUT_R


LINE_OUT_L
A6
B6
HPR STMP35XX M10 GPIO_42
HPL GP42 / CF_A10 / RAM_A10
L10
The L2 and L18 inductors are critical components - for best A7
144-Pin BGA GP41 / SM_ALE / CF_A9 / RAM_A9
L9
ALE
MIC MIC GP40 / SM_CLE / CF_A8 / RAM_A8 CLE
J8 SE#
battery life, these inductors should be a quality, low-ESR C8
GP39 / SM_SEn / CF_A7 / RAM_A7
K8
LINE_IN_R LINE1R / HP_COMMON GP38 / SM_CE0n / CF_A6 / RAM_A6 CE0#
inductor. The Panasonic ELL6H inductor or equivalent is LINE_IN_L B8
LINE1L / HP_SENSE GP37 / SM_CE2n / CF_A5 / RAM_A5 J7 CE2#
K7
recommended. C5
GP36 / SM_CE3n / CF_A4 / RAM_A4
L6
CE3#
LINE_IN2_R LINE2R GP35 / CF_A3 / RAM_A3 GPIO_35
LINE_IN2_L D4 LINE2L GP34 / CF_A2 / RAM_A2 K6 GPIO_34
The industrial design plastics should mechanically GP33 / CF_A1 / RAM_A1
L5 GPIO_33
A8 M5
prevent a battery accidentally inserted backwards from LRADC1
C7
LRADC1 / MIC_BIAS GP32 / CF_A0 / RAM_A0 GPIO_32
LRADC2 LRADC2 / TEMP_SENSE / MIC_BIAS
making contact with the battery terminals. VDD_BAT D7
BATT
GP45 / SM_CE1n / CF_CE0n K10 CE1#
Route VDD_BAT as a 30mil trace from the positive GP53 / SM_REn / CF_OEn
M11 RE#
C4 D11
battery terminal to the STMP35XX input. C3
REF_RES GP43 / CF_REGn
C11
GPIO_43
REFp GP50 / CF_RESETn GPIO_50
A4 M4 GPIO_44
ADCL GP44 / CF_CE1n
Route GND back to the battery negative terminal as B3
ADCR GP49 / CF_BVD1
D10 GPIO_49
E4 E11
either a 30mil trace or as part of a wide digital ground R32 VddXTAL GP48 / CF_WPn
E10
GPIO_48
GP47 / CF_READY GPIO_47
plane 620 C21 C22 C23 C25
GP46 / CF_CDn
E12 GPIO_46
1% 0.1uF 0.001uF 0.001uF 0.1uF

GP81 / CF_A12 / RAM_BA0


GP82 / CF_A13 / RAM_BA1
GP80 / CF_A11 / RAM_A11

GP61 / CF_A14 / RAM_A12


GP62 / CF_A15 / RAM_A13
GP84 / RAM_DQM1

GP83 / RAM_DQM0
GP86 / RAM_CASn

GP85 / RAM_RASn
GP92 / I2S_DataI0
GP7 / I2S_DataO2
GP6 / I2S_DataO1
GP5 / I2S_DataO0

GP87 / RAM_WEn

GP91 / I2S_WCLK
GP89 / RAM_CKE
GP13 / SPI_MISO

GP88 / RAM_CSn

GP90 / RAM_CLK
GP14 / SPI_MOSI

GP93 / I2S_BCLK
GP2 / I2S_DataI2
GP1 / I2S_DataI1
GP0 / I2S_DataI0
GP3 / I2S_WCLK

GP12 / SPI_SCK

GP17 / I2C_SDA
B B

GP16 / I2C_SCL
GP15 / SPI_SSn
AGND

GP63 / CF_A16
GP64 / CF_A17
GP65 / CF_A18
GP66 / CF_A19
GP67 / CF_A20
GP68 / CF_A21
GP69 / CF_A22
GP70 / CF_A23
GP4 / I2S_SCK
A1
XTALi
STMP35XX BOOT MODE SELECT A2

GP19 / TIO1
GP18 / TIO0
ONCE_DSO

TESTMODE
ONCE_DSK
ONCE_DRn

XTALo
ONCE_DSI

3.3V NAND w/ Play XTAL must be Y1


GPIO Recovery is the Default close to the

GP11

GP10
GP9

GP8
BOOT MODE 00 01 02 03 08 Boot Mode. STMP35XX 24.000MHz
C10

C26 C27
B11

K11
3.3V NAND w/Play Recovery 1 1 0 1 0

L12
M2

M3

M9
M8

M7

M6

M1
G4
G3

G2

G1
D9

C9

H3
H4
H2

D2

D1

H6

H1
E3

E1

K2

K4

K3

K1
E2
B9

K9

K5
F4
F3

F2

F1
L1

L2

L3

L8

L7
J1

J4

J2

J3

J9

J6
Populate either a pull-up 22pF 22pF
3.3V NAND w/PSwitch Recovery 1 1 0 1 1 or a pull-down on these
1.8V NAND w/Play Recovery 1 1 0 0 0 GPIOs to select the
1.8V NAND w/PSwitch Recovery 1 1 0 0 1 desired Boot Mode AGND GND

SPI Master 1 0 1 0 1 All resistors are 47K GROUNDING & POWER


SPI Slave 1 0 1 1 1 RES0603. However, it
may be necessary to use VDDA L3 VDDD
I2C Master 1 0 1 1 0 a stronger pull-down, ONCE_DSI
ONCE_DSO I2C_DATA
I2C Slave 1 0 0 1 1 such as a 10K, ONCE_DSK I2C_CLK
600 Ohms @ 100MHz
depending on the LCD ONCE_DRN SPI_SCK
DCR < 350mOhms
USB 1 0 0 1 0 SPI_MISO
used. VDDIO R13
SPI_MOSI
JP2
VDDIO 1 1 2
47K 10%
SPI_SS
GPIO_18
R6 R7 R8 R9 R10
GPIO_19
47K 47K 47K 47K 47K AGND GND
10% 10% 10% 10% 10%
GPIO_08
NOPOP NOPOP Tie all grounds together
GPIO_00 GPIO_10
GPIO_09 under the IC
GPIO_01 GPIO_11
GPIO_00
A A
GPIO_02 GPIO_01
GPIO_02
GPIO_03 GPIO_03 SigmaTel, Inc.
GPIO_04 3815 Capital of Texas Hwy.
GPIO_08 GPIO_05 Suite 300
GPIO_06 Austin, TX 78704
GPIO_07 tel: (512)381-3700
R11 R12 R14 R15 www.sigmatel.com
47K 47K 47K 47K Title
10% 10% 10% 10% STMP35XX Reference Schematics
NOPOP NOPOP
Page
STMP35XX 144-Pin BGA - 2 Channel Buck Mode
0
GND Size This design is the property of SigmaTel, Inc. It is offered Rev
C B
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 7 of 15
5 4 3 2 1
5 4 3 2 1

STMP35XX 100-Pin TQFP - Switched USB Jack - BOOST MODE VDDIO_P Power Switch
This circuitry creates a VDDIO_P for peripheral devices. When the
This circuit shows the STMP35XX in a NiMH or 1.5V Alkaline VDDD
player is powered-down, VDDIO_P will drop to GND. This allows
boost-mode configuration. The USB Jack is used for both USB and for peripheral devices to receive a power-on reset, since VDDIO drops
supplying the battery connection. Battery charge is not available in C2 C3 C4 + C1 to the battery voltage when the player is powered down.
0.01uF 0.1uF 1uF 68uF
this configuration.
The PFET used in this circuit should have an
Rds,on less than 2 ohms when Vgs = -2.8V. Si2305DS
GND A good choice is an Si2305 transistor or 1 G
equivalent.
VDDIO D 3
VDDIO VDDIO_P S
D 2 D

+ SOT-23
C9 C10 C11 C8
0.01uF 0.1uF 1uF 68uF R140 TOP VIEW
Q26 100K 10% Q15
Si2305 Si2305
VDDIO
R141 MMBT3904
GND 100K 10%
VDDD R142 B
L1 1
R182 Q27 VDDD Q16
Power/Play R39 10K Si2312DS One cap for each pin (39, 11, 86) 0 Ohm resistor C 3
MMBT3904
Switch 10K 10% 10% 100K 10%
2 E
PLAY_SW VDD_BAT
5V_or_1.5V L2 SOT-23
GND C5 C6 C7 GND GND TOP VIEW
R41 0.1uF 0.1uF 0.1uF
VDDIO SW2 20K 10% Q28 4.7uH 1 W
FMMT717 +
PSWITCH C14 C15
68uF 1uF
SW PUSHBUTTON R183
R42 C42 200
"Power/Play/Pause 10K 1uF 10% GND
10% IMPORTANT DESIGN NOTES
Button" R184 GND
1.5V_PRESENT Q29 One cap for each pin (29, 96) VDDIO The PFET used Q26 and Q30 in this circuit should have an Rds,on less
MMBT3904
10K 10%
than 2 ohms when Vgs = -2.8V. A good choice is an Si2305 transistor or
GND equivalent.
VDD_BAT C12 C13
GND 0.1uF 0.1uF The PNP transistor used for Q28 should have low Vce,sat
characteristics. When the power button is pressed, the transistor
PSWITCH
base current will be about 1mA when the 5V_or_1.5V power rail is .9V.
Q30 GND
Si2305 At this point, the STMP35XX will begin to start up and VDD_BAT will

79

49

47

48

50

54

11
39
86

10
38
87

29
96

28
97
U1 GND
5V_or_1.5V require about 35mA, which will be the current flowing through the
61

DCDC_VddIO

VddD2
VddD1
VddD3

VddIO1
VddIO2
DCDC_VddD

DCDC_Gnd

DCDC_Mode2
PSWITCH

DCDC_Batt

VssD2
VssD1
VssD3

VssIO1
VssIO2
C
Vdd5V collector of the FMMT717 transistor. Given 35mA of collector current C
R185 R186
USB_D+ 80
USB_DP
and 1mA base current, the Vce,sat of the FMMT717 transistor will be
22K 10K C129 C130 81
10% 10% 0.1uF 1uF
USB_D- USB_DM about 12mV. Because the voltage on the PSWITCH pin must also be
1.5V_PRESENT 67
Vag GP31 / SM_D7 / CF_D7
37 IO7 > 900mV during startup, the battery voltage required for startup using
66 36 IO6 the FMMT717 transistor will be about 912mV. Similarly, the battery
C17 Vbg GP30 / SM_D6 / CF_D6
NOTE: Vag and Vbg filter caps C16 GP29 / SM_D5 / CF_D5
35 IO5
Q31 R187
should have their ground return 1uF 0.1uF
GP28 / SM_D4 / CF_D4
34 IO4
voltage required for startup using a FMMT591A transistor will be about
MMBT3904 47K GND 33
R188 10% paths to VssA1, pin 72. GP27 / SM_D3 / CF_D3 IO3 940mV. If a PNP transistor with higher Vce,sat. characteristics is
32 IO2
10K GP26 / SM_D2 / CF_D2 used, such as the MMBT3906, the startup voltage will be 1.05V or
GP25 / SM_D1 / CF_D1 31 IO1
10% VDDA AGND 30 higher. Please consult the transistor datasheet.
GP24 / SM_D0 / CF_D0 IO0
64
VddHP
73 27 WP#
VddA1 GP55 / SM_WPn
One cap between 76
VddPLL GP54 / SM_WEn
26 WE# The NFET used for Q27 should have characteristics similar to the
C18 C19 C20 25
GND
each PWR and 0.1uF 0.1uF 0.1uF GP56 / SM_READY / CF_WAITn FLASH_RDY Si2312DS N-channel mosfet. The minimum gate threshold voltage
63
GND pair. VssHP
72 9 must be 1.2V or less. The most important characteristic of this
78
VssA1
VssPLL
STMP35XX GP51 / CF_IOWRn
GP52 / CF_IORDn
8
GPIO_51
GPIO_52 mosfet is the Rds,on for a given Vgs. The Rds,on should be 0.06
100-Pin TQFP ohms or less when Vgs = 1.8V. Using a mosfet with higher Rds,on
AGND 65 22
LINE_OUT_R
62
HPR GP42 / CF_A10
21
GPIO_42 characteristics may decrease battery life.
LINE_OUT_L HPL GP41 / SM_ALE / CF_A9 ALE
20 CLE
GP40 / SM_CLE / CF_A8
MIC 55
MIC GP39 / SM_SEn / CF_A7 19 SE# The L2 inductor is a critical component - for best battery life, L2
18
59
GP38 / SM_CE0n / CF_A6
17
CE0# should be a quality, low-ESR inductor. The Panasonic ELL6H
LINE_IN_R LINE1R / HP_COMMON GP37 / SM_CE2n / CF_A5 CE2#
LINE_IN_L 57
LINE1L / HP_SENSE GP36 / SM_CE3n / CF_A4
16 CE3# inductor or equivalent is recommended for this component.
GP35 / CF_A3 15 GPIO_35
LRADC1 58 14 GPIO_34
LRADC1 / MIC_BIAS GP34 / CF_A2
LRADC2 60
LRADC2 / TEMP_SENSE / MIC_BIAS GP33 / CF_A1 13 GPIO_33 Route VDD_BAT as a 30mil trace from the positive
56 12
VDD_BAT BATT GP32 / CF_A0 GPIO_32 battery terminal to the STMP35XX input.

GP14 / SPI_MOSI / SM_WP2n


GP45 / SM_CE1n / CF_CE0n 24 CE1#
70
REF_RES GP53 / SM_REn / CF_OEn
23 RE# Route GND back to the battery negative terminal as either
71 44
68
REFp GP43 / CF_REGn
43
GPIO_43 a 30mil trace or as part of a wide digital ground plane
ADCL GP50 / CF-RESETn GPIO_50

GP7 / I2S_DataO2
GP6 / I2S_DataO1
GP5 / I2S_DataO0

GP13 / SPI_MISO
69 7

GP2 / I2S_DataI2
GP1 / I2S_DataI1
GP0 / I2S_DataI0
GP3 / I2S_WCLK
GPIO_44

GP12 / SPI_SCK

GP17 / I2C_SDA
ADCR GP44 / CF_CE1n

GP4 / I2S_BCLK
B B

GP16 / I2C_SCL
100 GP15 / SPI-SSn
77 45 GPIO_49
R32 VddXTAL GP49 / CF_BVD1
STMP35XX BOOT MODE SELECT 42

98 GP19 / TIO1
99 GP18 / TIO0
ONCE_DSO

TESTMODE
ONCE_DSK
ONCE_DRn
GP48 / CF_WPn GPIO_48
ONCE_DSI

3.3V NAND w/ Play 620 C21 C22 C23 C25 41


GP47_CF_READY GPIO_47
GPIO 1% 0.1uF 0.001uF 0.001uF 0.1uF 40
Recovery is the Default GP46 / CF_CDn GPIO_46

GP11

GP10
75
XTALi

GP9

GP8
BOOT MODE 00 01 02 03 08 Boot Mode. 74
XTALo
3.3V NAND w/Play Recovery 1 1 0 1 0
46
52
51
53

88
89
90
91
92
93
94
95
82
83
85
84
Populate either a pull-up AGND

6
1
2
3
4
5
3.3V NAND w/PSwitch Recovery 1 1 0 1 1 or a pull-down on these XTAL must be Y1
I2C_DATA
1.8V NAND w/Play Recovery 1 1 0 0 0 GPIOs to select the close to the I2C_CLK
1.8V NAND w/PSwitch Recovery 1 1 0 0 1 desired Boot Mode STMP35XX 24.000MHz GND
SPI_SCK
SPI_MISO
SPI_MOSI
SPI Master 1 0 1 0 1 All resistors are 47K C26 C27 GROUNDING & POWER
22pF 22pF
RES0603. However, it SPI_SS
SPI Slave 1 0 1 1 1 GPIO_18
may be necessary to use GPIO_19
VDDA L3 VDDD
I2C Master 1 0 1 1 0 a stronger pull-down,
GPIO_08
I2C Slave 1 0 0 1 1 such as a 10K, AGND
GPIO_10
600 Ohms @ 100MHz
depending on the LCD GPIO_09
DCR < 350mOhms
USB 1 0 0 1 0 ONCE_DSI GPIO_11
used. ONCE_DSO GPIO_00
JP2
ONCE_DSK GPIO_01
VDDIO 1 1 2
ONCE_DRN GPIO_02
GPIO_03
VDDIO R13
GPIO_04
GPIO_05
R6 R7 R8 R9 R10
GPIO_06
47K 47K 47K 47K 47K 47K 10% AGND GND
GPIO_07
10% 10% 10% 10% 10%
NOPOP NOPOP Tie all grounds together
GPIO_00
under the IC
GPIO_01
A A
GPIO_02

GPIO_03 SigmaTel, Inc.


3815 Capital of Texas Hwy.
GPIO_08 Suite 300
Austin, TX 78704
tel: (512)381-3700
R11 R12 R14 R15 www.sigmatel.com
47K 47K 47K 47K Title
10% 10% 10% 10% STMP35XX Reference Schematics
NOPOP NOPOP
Page
STMP35XX 100-Pin TQFP - Boost Mode
0
GND Size This design is the property of SigmaTel, Inc. It is offered Rev
C B
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 8 of 15
5 4 3 2 1
5 4 3 2 1

NAND Flash U3 MultiMedia Card Socket Integration


1 48
FLASH_RDY
NC NC
2 NC NC 47 Pullup VDDIO_P VDDIO_P VDDIO_P VDDIO_P VDDIO_P VDDIO_P VDDIO_P VDDIO_P On Page STMP35XX
3 46 VDDIO_P
4
NC NC
45 Labels Labels
NC NC R27 R30 R137 R138 R29 R28 R189 R190
5 NC I/O7 44 IO7 MMC_CLK SPI_SCK
6 43 R35 47K 47K 47K 47K 10K 10K 47K 47K
SE I/O6 IO6
7 42 10K 10% 10% 10% 10% 10% 10% 10% 10%
D FLASH_RDY R/B I/O5 IO5 MMC_DATA_IN SPI_MOSI D
8 41 10%
RE# RE I/O4 IO4 MMC_SS
GND 9 40 U2
CE0# CE NC MMC_DATA_OUT SPI_MISO
10 NC NC 39 FLASH_RDY MMC_DETECT 11 CARD_DETECT#
VDDIO_P 11 38 VDDIO_P
NC NC MMC_SS SPI_SS
12 VCC VCC 37 MMC_WP 10 WRITE_PROTECT
C40 13 36
VSS VSS MMC_DETECT GPIO_32
0.1uF 14 35 C41 7
NC NC MMC_DATA_OUT DATA_OUT
15 34 0.1uF 2
16
NC NC
33
WP# Pulldown MMC_DATA_IN
5
DATA_IN MMC_WP GPIO_52
CLE CLE NC MMC_CLK SCLK
ALE 17 ALE I/O3 32 IO3 MMC_CS 1 CS# MMC_CS CE3#
GND W E# 18 WE I/O2 31 IO2 8 DAT1
W P#
19 WP I/O1 30 IO1 9 DAT2 I2C_CLK I2C_CLK
W P# VDDIO_P
20 NC I/O0 29 IO0 GND L16
21 28 R157 4
NC NC Vdd I2C_DATA I2C_DATA
22 27 47K L15 and L16 are optional ferrites that may 600 Ohms @ 100MHz 6
NC NC 10% DCR < 350mOhms C100 GND
23 NC NC 26 be required for ESD immunity. If they are 3 GND IO7 IO7
24 25 L15 0.1uF 12
NC NC not required, populate a 0-ohm resistor. SOCKET_GND IO6 IO6
13 SOCKET_ESD_GND IO5 IO5
NOTES: FLASH GND 600 Ohms @ 100MHz IO4 IO4
DCR < 350mOhms IO3 IO3
1. The WP# pull-down resistor is required to protect GND AVX #: 10 5638 009 353 833
IO2 IO2
MMC/SD Socket
the flash memory from inadvertent writes during IO1 IO1

C power transitions.
CE0# Pullup IO0 IO0
C
FLASH_RDY FLASH_RDY
VDDIO_P
2. The CE# pull-up resistor is required to keep the RE# RE#
flash de-selected during power transitions. R163
CE0# CE0#
47K
10%
CLE CLE
3. A pull-up resistor is required on the FLASH_RDY
signal because the flash output is open drain. CE0# WE# W E#

WP# W P#

STMP35XX CHIP ENABLE ASSIGNMENT


B B

If using more than one NAND chip, the first


chip MUST be attached to CE0#, the second
Optional Second NAND Flash MUST be attached to CE1#, and the third
U14
1 48
MUST be attached to CE2#. The software
2
NC NC
47
CE1# Pullup requires that the NAND chip enables start at
NC NC
3 46
4
NC NC
45 VDDIO_P CE0# and be consecutive.
NC NC
5 NC I/O7 44 IO7
6 SE I/O6 43 IO6 If using a NAND and a MMC Card, it is
7 42 R168
FLASH_RDY
8
R/B I/O5
41
IO5
47K recommended that the MMC Card use CE3#
RE# RE I/O4 IO4
GND
CE1# 9 CE NC 40 10% by default, but this is not required.
10 NC NC 39
VDDIO_P 11 38 VDDIO_P
NC NC CE1#
12 VCC VCC 37
C117 13 36
0.1uF VSS VSS C118
SigmaTel, Inc.
14 35
NC NC 0.1uF 3815 Capital of Texas Hwy.
15 NC NC 34 NOTES: Suite 300
CLE 16 33
17
CLE NC
32
Austin, TX 78704
A
ALE ALE I/O3 IO3 tel: (512)381-3700 A
GND WE# 18 WE I/O2 31 IO2 1. The CE# pull-up www.sigmatel.com
19 WP I/O1 30 IO1
WP# resistor is required to Title
20 NC I/O0 29 IO0 GND
21 NC NC 28 keep the flash STMP35XX Reference Schematics
22 NC NC 27
23 NC NC 26 de-selected during Page
24 NC NC 25
power transitions. Main Memory - NAND & MMC
FLASH Size This design is the property of SigmaTel, Inc. It is offered Rev
B B
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 9 of 15
5 4 3 2 1
5 4 3 2 1

Integration
NAND Flash U3
1 48
FLASH_RDY On Page STMP35XX
NC NC
2 NC NC 47 Pullup Labels Labels
3 46 VDDIO_P
NC NC
4 NC NC 45 IO7 IO7
5 NC I/O7 44 IO7 IO6 IO6
6 43 R35
SE I/O6 IO6 IO5 IO5
7 42 10K
D FLASH_RDY R/B I/O5 IO5 IO4 IO4 D
8 41 10%
RE# RE I/O4 IO4 IO3 IO3
GND 9 40
CE0# CE NC IO2 IO2
10 NC NC 39 FLASH_RDY IO1 IO1
VDDIO_P 11 38 VDDIO_P
NC NC IO0 IO0
12 VCC VCC 37
C40 13 36
VSS VSS FLASH_RDY FLASH_RDY
0.1uF 14 35 C41
NC NC 0.1uF
15 34
16
NC NC
33
WP# Pulldown RE# RE#
CLE CLE NC
ALE 17 ALE I/O3 32 IO3 CE0# CE0#
GND W E# 18 WE I/O2 31 IO2 W P#
19 WP I/O1 30 IO1 CLE CLE
W P#
20 NC I/O0 29 IO0 GND
21 28 R157
NC NC W E# WE#
22 27 47K
NC NC 10%
23 NC NC 26 W P# WP#
24 NC NC 25

NOTES: FLASH GND IO15 IO15


IO14 IO14
1. The WP# pull-down resistor is required to protect the IO13 IO13
flash memory from inadvertent writes during power IO12 IO12

transitions.
CE0# Pullup IO11 IO11
C IO10 IO10 C
IO9 IO9
VDDIO_P
IO8 IO8
2. The CE# pull-up resistor is required to keep the
flash de-selected during power transitions. R163
47K
10%
3. A pull-up resistor is required on the FLASH_RDY
signal because the flash output is open drain. CE0#

STMP35XX CHIP ENABLE ASSIGNMENT


B B

If using more than one NAND chip, the first


chip MUST be attached to CE0#, the second
Optional Second NAND Flash MUST be attached to CE1#, and the third
U14
1 48
MUST be attached to CE2#. The software
2
NC NC
47
CE1# Pullup requires that the NAND chip enables start at
NC NC
3 46
4
NC NC
45 VDDIO_P CE0# and be consecutive.
NC NC
5 NC I/O7 44 IO7
6 SE I/O6 43 IO6 If using a NAND and a MMC Card, it is
7 42 R168
FLASH_RDY
8
R/B I/O5
41
IO5
47K recommended that the MMC Card use CE3#
RE# RE I/O4 IO4
GND
CE1# 9 CE NC 40 10% by default, but this is not required.
10 NC NC 39
VDDIO_P 11 38 VDDIO_P
NC NC CE1#
12 VCC VCC 37
C117 13 36
0.1uF VSS VSS C118
SigmaTel, Inc.
14 35
NC NC 0.1uF 3815 Capital of Texas Hwy.
15 NC NC 34 NOTES: Suite 300
CLE 16 33
17
CLE NC
32
Austin, TX 78704
A
ALE ALE I/O3 IO3 tel: (512)381-3700 A
GND WE# 18 WE I/O2 31 IO2 1. The CE# pull-up www.sigmatel.com
19 WP I/O1 30 IO1
WP# resistor is required to Title
20 NC I/O0 29 IO0 GND
21 NC NC 28 keep the flash STMP35XX Reference Schematics
22 NC NC 27
23 NC NC 26 de-selected during Page
24 NC NC 25
power transitions. Main Memory - NAND Flash
FLASH Size This design is the property of SigmaTel, Inc. It is offered Rev
B A
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 10 of 15
5 4 3 2 1
5 4 3 2 1

DOT-MATRIX LCD OPTIONAL PWM EL BACKLIGHT


L23
VDDIO_P U6 100uH Integration
1 VDDIO 1 W, 3.7 ohms Note: To drive the EL backlight
Vdd TDK part #: NLC322522T-101K D15
2 C86 using 3 GPIOs, populate R194 On Page STMP35XX
C43
0.1uF and remove R195 and Q37. If Labels Labels
D DL4148 D
3 GND R191 R192 only 2 GPIOs are available, LCD_CS# GPIO_08
VDDIO_P C44 GND
GPIO_18
C131 1M 1M populate R195 and Q37, and LCD_DS GPIO_10
4 Q32 0.1uF 10% 10%
V5 BSS123 100V Q33 Q34 remove R194.
LCD_RS GPIO_11
0.1uF C45 R193 BSS123 BSS123
5 47K
V4 LCD_D0 GPIO_00
10%
C46 0.1uF D16 D17
GPIO_19 LCD_D1 GPIO_01
6 V3 R194 VDDIO
LCD_D2 GPIO_02
0.1uF C47 GND DL4148 DL4148 0 Ohm
7 V2 LCD_D3 GPIO_03

2
1
R195
C48 0.1uF BSS123 10K
LCD_D4 GPIO_04
8 R196 Q35 R197 10%
V1 BSS123 J6 Q36
3 G BL_ON LCD_D5 GPIO_05
0.1uF EL Lamp BSS123
9 D 1 47K 10% 47K 10% Q37
CAP2+ LCD_D6 GPIO_06
C49 S R198 R199 BSS123
2
1uF 47K 47K
BL_ON LCD_D7 GPIO_07
10 SOT-23 10% 10%
CAP2-
TOP VIEW LCD_RESET GPIO_44
C C
11 CAP1- BL_ON GPIO_09
C50
1uF
GPIO_19 GPIO_19
12 GND
C51 CAP+
GPIO_18 GPIO_18
1uF
13 CAP3-
14 Vout
C52
0.1uF Optional LED Backlight Optional LEDs
15 GND Size series resistor
values based of the Use for LED-only players.
VDDIO_P
GND LED chacteristics GPIO_05 GPIO_07
LCD_D7 16 DB7
17 R47
LCD_D6 DB6
18 510 R149 R151
LCD_D5 DB5
19 10% 510 510
LCD_D4 DB4
20 10% 10%
LCD_D3 DB3
LCD_D2 21 DB2
22 D1
LCD_D1 DB1
23 LED
LCD_D0 DB0 D10 D12
B 24 LTST-C150GKT LTST-C150GKT B
LCD_DS E
25 GREEN LED GREEN LED
R/W#
1

26 D
LCD_RS A0 G
27 Q1
LCD_RESET RES#
28 3 ZXM61N02FCT
LCD_CS# CS# BL_ON
S
2

29 NC GND
30 R49
NC 47K
R51 R52 Shing Yih LCD 10%
47K 47K
10% 10%

GND
GND GND

SigmaTel, Inc.
3815 Capital of Texas Hwy.
Suite 300
Austin, TX 78704
A tel: (512)381-3700 A
www.sigmatel.com
Title
STMP35XX Reference Schematics
Page
Display & Backlight
Size This design is the property of SigmaTel, Inc. It is offered Rev
B A
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 11 of 15
5 4 3 2 1
5 4 3 2 1

Integration
Hold Switch
1
OPTIONAL JOG DIAL On Page STMP35XX
PLAY Labels Labels
VDDIO SW1 R44
2 SW SLIDE-SPDT
PLAY_SW GPIO_34
10K 10%
SCAN_C4 GPIO_42

1
9
D SW 20 D
GND
HOLD

COM
CH_GND
3 SCAN_C3 GPIO_46
HOLD_SW COM 2 SCAN_R3
If a HOLD switch is not CW1 3 SCAN_C2 SCAN_C2 GPIO_47
4
required, your design R43 CW2
SCAN_C1 GPIO_48
MUST either disable the 47K 5
PUSH SCAN_C1

CH_GND
10% 6
HOLD functionality in the CCW2
7
SCAN_R3 GPIO_50

GND
CCW1 SCAN_C3
firmware OR leave the R43 SCAN_R2 GPIO_43
pull-down on the ALPS SLLB120 Jogdial
SCAN_R1 GPIO_49

10
HOLD_SW line. Rotary Encoder

8
GND
PSWITCH PSWITCH
L18
HOLD_SW GPIO_35
600 Ohms @ 100MHz
DCR < 350mOhms GND
Buttons

SCAN_C1 SCAN_C2 SCAN_C3 SCAN_C4


C C

SW 3 SW4 SW 5
OPTIONAL ROTARY ENCODER
SW PUSHBUTTON SW PUSHBUTTON SW PUSHBUTTON VDDIO

MENU VOLUME+ VOLUME- R172


10K
10%
R173
SCAN_R3
CE2#
10K 10% C121
0.01uF
SW 6 SW7 SW 8 SW 9 SW 18
NC 1
2 B GND
SW PUSHBUTTON SW PUSHBUTTON SW PUSHBUTTON SW PUSHBUTTON B SW1
SW1 3 SCAN_C1
4 SW2
SW2 SCAN_R3
B REVERSE FORWARD ERASE A-B 5 B
SW1
COM 6 GND
7 A
A VDDIO
SCAN_R2 NC 8

EVE-GA1 R174
10K
Rotary Encoder 10%
SW 10 SW 11 SW 12 SW 13 R175
GPIO_33
SW PUSHBUTTON SW PUSHBUTTON SW PUSHBUTTON SW PUSHBUTTON 10K 10% C122
0.01uF
STOP RECORD EQ MODE
GND
SCAN_R1

R44 R45 R46


SigmaTel, Inc.
NOTE: If the HOLD switch or certain button SCAN lines are not 3815 Capital of Texas Hwy.
10K 10K 10K
10% 10% 10% required for your design, you MUST either include pull-down Suite 300
Austin, TX 78704
resistors on the HOLD, SCAN_R1, SCAN_R2, and SCAN_R3 lines OR tel: (512)381-3700
A A
disable the unused lines in the firmware. www.sigmatel.com
Title
GND STMP35XX Reference Schematics
Page
Buttons
Size This design is the property of SigmaTel, Inc. It is offered Rev
B B
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 12 of 15
5 4 3 2 1
5 4 3 2 1

Integration
On Page STMP35XX
L8
CoilCraft#: 0603CS-R18X_BG C53 Labels Labels
180nH @ 100MHz 100pF Use HP_GND_A as an antenna FM_CLOCK I2C_CLK
HP_GND_A
FM_DATA I2C_DATA
C54 C55
47pF 22pF R53
D FM_R LINE_IN_R D
100K
10%
FM_L LINE_IN_L

BUS_EN SE#
FM_GND
FM_GND
SW P1 GPIO_33

FM_WE GPIO_51
R54
22 10% VDDIO_P

C114
C56 + 22uF
100nF Tantalum
FM_GND 10V

C57 FM_GND
4.7nF R55
VDDIO_P 18K

L11
C
R58 CoilCraft#: 0603CS-33NX_BG C
22 33nH @ 250MHz D6 R57 R56
10% Philips BB202 100K 10K

40

39

38

37

36

35

34

33

32

31
C60 Varactor FM_GND U9 FM_GND

NC

LOOPSW

TCAGC

RFI2

RFGND

RFI1

AVCC

AGND

IFGAI

NC
33nF C61
33nF 1 30
C58 C59 D7 NC NC
22nF 22nF L12 Philips BB202 2 29
CoilCraft#: 0603CS-33NX_BG Varactor CPOP DIFL2
33nH @ 250MHz 3 28
VCOT1 DIFL1
4 VCOT2 TCIFC 27

FM_GND 5 26
VCOVCC VREF
VDDIO_P
PHILIPS
FM Tuner
TEA5767HN
FM_GND 6 DGND MPXO 25 MPX
7 DVCC TMUTE 24
R59
22 8 23 C63 C64 C65 C66 C67 C68
10% DATA RAVO 33nF 330pF 33nF 47nF 47nF 47nF
VDDIO_P 9 22
CLOCK LAVO
B B
C62 10 21
100nF NC NC

BUSEN

XTAL1

XTAL2
BUSM

SWP1

SWP2
R125 R126 R127 R128 R167 FM_GND

PDLF

PHLF
W/R
47K 47K 47K 47K 47K

NC
10% 10% 10% 10% 10% C69
FM_GND
FM_R
11

12

13

14

15

16

17

18

19

20
FM_DATA
100nF
FM_CLOCK
TP14 FM_GND C70
FM_WE
FM_L
BUS_EN
100nF

SW P1
VDDIO_P R61

JP3
SigmaTel, Inc.
47K 10% 1 2
3815 Capital of Texas Hwy.
NOTE: Currently, the TEA5767 is used in 3-wire mode. In R200 R60 0 Ohm Suite 300
47K 10% C73 33K Resistor Austin, TX 78704
A
future versions of the 35XX SDK, the TEA5767 may be NOPOP 1nF 10% Jumper tel: (512)381-3700 A
accessed in I2C mode, which frees up one GPIO. In order to C74 C76 C77 FM_GND AGND www.sigmatel.com
support both modes, FM_DATA and FM_CLOCK should have 22pF 2.2nF 2.2nF Title
FM_GND STMP35XX Reference Schematics
pull-up resistors, and the BUS_MODE pin should have options C75
to populate either a pull-up or pull-down resistor. X2 22nF Page
32.768KHz FM Tuner - Philips TEA5767HN
Crystal
Size This design is the property of SigmaTel, Inc. It is offered Rev
B B
FM_GND FM_GND
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 13 of 15
5 4 3 2 1
5 4 3 2 1

Integration
Optional FM Tuner Module On Page STMP35XX
The Panasonic BTF-03 integrates the TEA5767 and most of the Labels Labels
discrete components.
FM_CLOCK I2C_CLK
VDDIO_P R177
VDDIO_P VDDIO_P
FM_DATA I2C_DATA
C128
D 22 10% 0.1uF D
FM_R LINE_IN_R
R125 R126
VDDIO_P 47K 47K
FM_L LINE_IN_L
GND U16 10% 10%

24
BTF-03
BUS_EN SE#
R169 1 23

GND
47K 10% GND GND
2 VCC CL 22 FM_CLOCK SW P1 GPIO_33
BUS_EN 3 BUEN DA 21 FM_DATA
SW P1 4 SW1 EN 20 FM_WE FM_WE GPIO_51
5 SW2 BUS MODE 19 R61
6 XTAL GND 18 VDDIO_P
C127 7 17
GND GND 47K 10%
7pF 8 16
MPX GND R200
FM_R 9 RIGHT GND 15
10 14

GND
FM_L LEFT RF N 47K 10%
Y2 11 13 C126
GND GND NOPOP
32.768kHz FM_GND
HP_GND_A
12
150pF
GND

L16 JP3
C
600 Ohms @ 100MHz 1 2 C
DCR < 350mOhms 0 Ohm
Resistor
Jumper
FM_GND AGND

GND

Option 2:
DA-102 (TEA5767)
R61
VDDIO_P
47K 10% NOTE: Currently, the TEA5767 is used in 3-wire mode. In
R200 future versions of the 35XX SDK, the TEA5767 may be
VDDIO_P accessed in I2C mode, which frees up one GPIO. In order to
47K 10%
NOPOP U16 support both modes, FM_DATA and FM_CLOCK should have
R167 FM_GND VDDIO_P
47K 10% 1 16
pull-up resistors, and the BUS_MODE pin should have options
GND ANT HP_GND_A
RES-0603 2 15 to populate either a pull-up or pull-down resistor.
BUSMODE VCC
B FM_WE 3 R/W GND 14 B
SW P1 4 SW1 GND 13
BUS_EN 5 ENABLE MPX 12
FM_DATA 6 DATA OUT-R 11 FM_OUT_R
FM_CLOCK 7 CLK OUT-L 10 FM_OUT_L
8 XTAL GND 9
R168
47K 10% DA-102 L54
VDDIO_P RES-0603 D&A Corporation 600 Ohms @ 100MHz
R126 IND-0805 Ferrite
47K
VDDIO_P 10%

AGND

SigmaTel, Inc.
3815 Capital of Texas Hwy.
Suite 300
Austin, TX 78704
A tel: (512)381-3700 A
www.sigmatel.com
Title
STMP35XX Reference Schematics
Page
FM Tuner Modules
Size This design is the property of SigmaTel, Inc. It is offered Rev
B B
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 14 of 15
5 4 3 2 1
5 4 3 2 1

U6
SEGMENT LCD U12
SEG7 1 48 SEG8 SEG0 1
OPTIONAL 16-bit NAND Flash OPTIONAL I2C EEPROM Boot
SEG6 SEG7 SEG8 SEG9 SEG1 SEG0
2
SEG6 SEG9
47 2 SEG1 NOTE: 16-bit NAND Flash support is only available on the 144BGA Use Microchip 24LCxx-I/P or Equivalent
VDDIO_P SEG5 3 46 SEG10 SEG2 3
SEG4 4
SEG5 SEG10
45 SEG11 SEG3 4
SEG2 package. Booting from an EEProm requires setting the Boot
SEG3 5
SEG4 SEG11
44 SEG12 SEG4 5
SEG3 U3 FLASH_RDY
R52 SEG2 6
SEG3 SEG12
43 SEG13 SEG5 6
SEG4
1 48 Pullup Mode to "I2CMaster".
47K SEG1 SEG2 SEG13 SEG14 SEG6 SEG5 NC VSS VDDIO_P C98
7 SEG1 SEG14 42 7 SEG6 2 NC I/O15 47 IO15
10% SEG0 8 41 SEG15 SEG7 8 3 46 0.1uF VDDIO_P
SEG0 SEG15 SEG16 SEG8 SEG7 NC I/O7 IO7
LCD_CS# 9 40 9 4 45 IO14 GND
CS SEG16 SEG17 SEG9 SEG8 NC I/O14 R35
LCD_RD# 10 RD SEG17 39 10 SEG9 5 44 IO6
SEG18 SEG10 NC I/O6 10K R63 R64
LCD_CLK 11 38 11 6 43 IO13
WR SEG18 SEG19 SEG11 SEG10 SE I/O13 10% U10 2.2K 2.2K
LCD_DATA 12 37 12 FLASH_RDY 7 42 IO5
DATA SEG19 SEG20 SEG12 SEG11 R/B I/O5 10% 10%
GND 13 36 13 RE# 8 41 IO12 1 8
VSS SEG20 SEG21 SEG13 SEG12 GND RE I/O12 A0 Vdd
14 35 14 CE0# 9 40 IO4 FLASH_RDY 2 7
D
VDDIO_P R51 10K OSCO SEG21 SEG22 SEG14 SEG13 CE I/O4 A1 WP D
15 OSCI SEG22 34 15 SEG14 10 NC NC 39 3 A2 SCL 6 I2C_CLK
10% SEG23 SEG15 VDDIO_P VDDIO_P
16 33 16 11 38 4 5 I2C_DATA
VLCD SEG23 SEG24 SEG16 SEG15 NC PRE Vss SDA
17 32 17 12 37
C52 VDD SEG24 SEG25 SEG17 SEG16 C40 VCC VCC EEPROM-I2C-8Pin
18 31 18 13 36
0.1uF IRQ SEG25 SEG26 SEG18 SEG17 0.1uF VSS NC C41
19 30 19 14 35
20
BZ SEG26
29 SEG19 20
SEG18
15
NC NC
34 0.1uF WP# Pulldown
COM0 BZ SEG27 SEG20 SEG19 NC NC
21 28 21 CLE 16 33 IO11
GND Y2 COM1 COM0 SEG28 SEG21 SEG20 CLE I/O11
22 27 22 ALE 17 32 IO3
COM2 COM1 SEG29 SEG22 SEG21 ALE I/O3 WP#
23 26 23 GND WE# 18 31 IO10
VDDIO_P COM3 COM2 SEG30 SEG23 SEG22 WE I/O10
24 25 24 19 30 IO2 GND
32.768kHz COM3 SEG31 SEG24 SEG23 WP# WP I/O2 R157
25 SEG24 20 29 IO9
HT1621 - LCD Controller SEG25 NC I/O9 47K
26 SEG25 21 28 IO1
R50 SEG26 NC I/O1 10%
27 SEG26 22 NC I/O8 27 IO8
47K C50 C51 COM3 28 23 26
COM2 COM3 NC I/O0 IO0
10% 22pF 22pF NOTE: Some versions of the LCD controller do 29 24 25
COM1 COM2 NC VSS
30 GND
LCD_IRQ# not require an external crystal - in that case, Y2, COM0 31
COM1
COM0 FLASHMP3
C50, and C51 are not required. GND
SEGMENT LCD NOTES:
GND
1. The WP# pull-down resistor is required to protect
CE0# Pullup
Integration the flash memory from inadvertent writes during VDDIO_P
LCD_CS# GPIO_11 power transitions.
LCD_CLK GPIO_10
R163
LCD_IRQ# GPIO_05
2. The CE# pull-up resistor is required to keep the 47K
LCD_RD# GPIO_06
10%
LCD_DATA GPIO_04 flash de-selected during power transitions.
CE0#
3. A pull-up resistor is required on the FLASH_RDY
signal because the flash output is open drain.
Optional EL Backlighting
IMPORTANT: The EL Backlight Driver should have a current
C draw between 5mA and 20mA at 3.0V. C
OPTIONAL ONCE PORT
OPTIONAL: Wall Power + USB Power Switch
U12 C92 VDDIO
1 8 180pF This circuit allows the STMP35XX
BL_ON HON CAP2
2 7
3
Vss CAP1
6 to power from an external wall
COIL Vdd VDDIO_P R68
R97 4
EL2 EL1
5 R65 R66 R67 power supply. In the case where
47K GND C93 10K 10K 10K 10K
10% VDDIO_P SP4423 0.1uF wall power and USB power are VDDIO
USB Sense
10% 10% 10% 10% J2 both connected, the STMP35XX
L17 GND
ONCE_DSI 1 2 will power and/or recharge using R169
ONCE_DSO 3 4
2
1

GND 10mH, 32 ohm


ONCE_DSK 5 6
the wall power supply. 47K 10%
ONCE_DRN 7 8 KEY
Place close to SP4423 PSWITCH 9 10 To implement this circuit, remove GPIO_33
J3
EL Lamp ONDEZ 11 12 the direct USB_5V connection on R170
13 14
the STMP35XX VDD5V pin, and USB_5V Q24
HEADER 7X2
R69 R70 connect the USB_5V line through 100K 10%
MMBT3904
10K 10K a FET as shown.
10% 10% GND
J4
PJ-202A-2.0mm
OPTIONAL HEADPHONE REMOTE Power Jack
5V DC, 1 A, D13
This circuitry may be built into the headphone cord to provide remote control functionality. 1
Wall
If using this circuit, use the Headphone Jack + Remote Control circuit. Transformer 10BQ015
1 Amp

2
Schottky
VDD5V
R177 R178 R179 R180 R181
USB_5V
2.0K 5% 3.01K 5% 5.1K 5% 10.0K 5% 30.0K 5% GND Q25
Si2305
To LRADC Pin of Heaphone Jack
Note: the voltage on the STMP35XX
2
1

2
1

2
1

2
1

2
1

SW19 SW20 SW21 SW22 SW23 VDD5V pin needs to be between 4.5V
B B
and 5.25V. If using a DC power R171
"PLAY" "FF" "RW" "VOL+" "VOL-" 47K 10%
supply greater than 5V, it may be
VOLTAGE AT necessary to insert a diode drop to
4
3

4
3

4
3

4
3

4
3

meet this input voltage requirement.


LRADC Input 0.5V 1.0V 1.5V 2.0V 2.5V GND

=
GND

Headphone Jack + Remote Control


VDDIO

R176
10.0K
J1 1 HP_CONN_R 1%
2 HP_CONN_L L7
3 LRADC1
4 HP_GND_A 600 Ohms @ 100MHz
headphone DCR < 350mOhms

A A

SigmaTel, Inc.
3815 Capital of Texas Hwy.
Suite 300
Austin, TX 78704
tel: (512)381-3700
www.sigmatel.com
Title
STMP35XX Reference Schematics
Page
Optional Circuits
Size This design is the property of SigmaTel, Inc. It is offered Rev
C B
on an "as is" basis, and carries no implied warranty.
Date: Monday, September 08, 2003 Sheet 15 of 15
5 4 3 2 1