Beruflich Dokumente
Kultur Dokumente
REFERENCE BOOK
~
Zilog VOLUME 1
July 1981
Copynght 1981 by Zllog, Inc. All rIghts reserved. No part
of this publIcation may be reproduced, stored In a retrIeval
system, or transmitted, In any form or by any means, elec-
tronIc, mechanIcal, photocopymg, recordmg, or otherWIse,
wIthout the prIor WrItten permISSion of 2110g.
The mformatIon contamed herem IS subject to change
wIthout notice Z110g assumes no responsIbilIty for the use of
any CircUitry other than CIrcUItry embodIed In a 2110g pro-
duct. No other CircUlt patent licenses are ImplIed.
Inll'odaclion
Zllog's name has become synonomous wIth 10qlc products is onl) half the key that unlocks the
InnovatIon and advanced mIcroprocessor archItec- future of mlcroprocessor-based end products: the
ture sInce the IntroductIOn of the Z80 CPU In other half is the creative application of those
1975. The Zllog Family of mIcroprocessors and products. Advanced microprocessor products and
mIcrocomputers has grown to Include the products their creative application lead to end product
lIsted In the table below. Each product exhIbIts designs with more features, more simply imple-
speclal features that make It stand above sImIlar mented, at a lower system cost. It is hoped thi s
products In the semIconductor marketplace. These reference book will stimulate new product design
specIal features have proven to be of substant Ial ideas as well as fresh approaches to the design of
aId In the solutlon of mIcroprocessor deslqn traditional microprocessor-based products.
problems.
The material In thIS book IS belleved to be
ThIs reference book contaIns a collect Ion of accurate and up-to-date. If you do fInd errors,
application informat ion about l Hog microprocessor or would lIke to offer suggestIons for future
pr oduct s. It inc ludes technical art lC les, appli- applIcatIon notes, we would apprecIate hearIng
cation notes, concept papers, and benchmarks. The from you. Correct Ion lnputs should be dnected to
reference book is intended as the first of several Components DIVISIon TechnIcal PublIcatIons, and
such volumes. We at Ziloq believe that designing applIcatIon sugqestlons should be dIrected to
innovative microprocessor integrated circuit Components Dlvislon Appilcatlon Enqlneerlng.
1
Table of CODleDls
ze Single-Chip Microconputer FBMily
Advanced Architecture of the l8 Microcomputer 1-3
A Comparison of M:U Units 1-15
l8600 Interrupt Request Register 1-29
12-8it Addressing with the Z8600 Family 1-31
lB Family Software Framing Error Detection 1-33
A Programmer's Guide to the lB Microcomputer 1-35
Z-Fuily Memries
Interfacing the l6132 Intelligent Memory 4-3
Z-8US 5
Z-BUS Component Interconnect 5-3
l-BUS ar~ Peripheral Support Packages Tie Distributed Computer Systems Together 5-19
General 6
An Optimizing Driver for NEC Spinwriters and Diablo Printers 6-3
lRTS 8000 lilog Real-Time Software for the Z8000 Microprocessor 6-61
Peripheral Controller Chip Ties into B- and 16-Bit Systems 6-65
Adapting Unix to a 16-Bit Microcomputer 6-71
Major Firms Join Unix Parade 6-77
iii
Z8Singie Chip Microcomputer Family I
The Advanced Architectural Features of the Z8 Microcomputer
Stephen Walters
Manager of Component Applications
ZUog, Inc.
10460 Bubb Road
Cupertino, CA 95014
INTRODUCTION
The semiconductor industry accomplished puters. Tne Z8 combines a powertul instruction
dramatic technological advances in the area of set, simplified system expansion oft chip, and
MOS integrated circuit microprocessors during tlexible serial and parallel I/O capabilities
the 1970's, and as the next decade begIns two to provide design solutions for a wide range of
trends are very clear. The first is the con- application problems.
tinued increased capability of the high-end
general purpose microprocesso:s. Si~t7en bit The Z8 has a l6-bit Program Counter and a
microprocessors will mature WIth addItIonal separate l6-bi t Stack Pointer. The memory space
''big machine" features, and 32-bit microprocess- may be extended beyond the 2K bytes of ReM and
ors will develOp. 124 bytes ot RAM on chip, up to l26K bytes of
program and data memory. There are 32 bits of
The second trend is in the area of single I/O which can be configured into a variety ot
chip microcomputers. Single chlP microcomput- bit, nibble, and byte organizations, and the
ers are offering substantlally greater process- serial I/O port is a complete full duplex asyn-
ing power than when they were fust introduced. chronous recelver/transmitter. Tne Z8 inter-
Microcomputers are no longer limited to low end rupt structure allows the user to mask and pri-
app1icatlons where unit cost and power dissipa- oritize the interrupt functions under program
tion are the prImary design considerations. control, and the interrupts are directed. to the
appropriate service routine through l6-blt
Zilog is applying classical computer archi- vectors in the first 12 locations of program
tecture concepts to the design of its microcom- memory. Two counter/timers are provided to off
puter products. Upon close examinatlon of the load time base generation and interval detect-
Zllog Z8 Microcomputer, one notices features ion tasks from the Z8. Tne Z8 will operate with
that once were available only on general purpose an 8 MHz clock and the exact frequency up to 8
bus oriented microprocessor products such as; MHz may be set with an external crystal, an
external RC, or an external clock source. The
separate program and data space Z8 operates from a single 5 volt power supply
and offers a power down mode that allows the
the stack pointer and the PU~ 124 general purpose registers on chip to oper-
and POP instructions ate from a back up battery. A Block Diagram of
the Z8 is given in Figure 1.
l26K byte total memory address
space
vectored interrupts
the CALL and RET (Return) instruc-
ions for procedllre calls.
The trend in high-end single chip microcomputer
architecture is clear and the consequences are
ObVI0US. The multi-chip solutions of today that
employ 8-bit general purpose microprocessors
wil! be replaced by more powerful 8-bit or 16-
blt single Chip microcomputers in the future.
This paper will discuss the arcmtectural
teatures ot the Z8 Microcomputer and descnbe
an appllcation of the Z8 that takes advantage
of the off chip expansion capability.
ARCHlTECl'URAL OVERVIEW .,0 ADDRESS OR uo ADDRESSIDATA OR 110
(BIT PROGRAMMABLE) (NIBBLE PROGRAMMABLE) (BYTE PROGRAMMABLE)
T, T, T, T,
CLOCK
X A&-AI5
>C PO
X A8- A15
x::=
X Ao-A1
> 8--C X AD-A,
X 0 0-0, OUT
x::=
... "---J '--- AS
'---I '---
DS
\ / OS
\ /
R/Vi
7 R,'" \
OM
X >C o. ____~x~====~~==~x::=
I REAO CYCLE I 1_ I wRn E CYCLE
LOCATION IDENTIFIERS
255 STACK POINTER (BITS 7-0) SPL
2 .. STACK POINTER (BITS 15-8) SPH
253 REGISTER POINTER RP
252 PROGRAM CONTROL FLAGS FLAGS
251 INTERRUPT MASK REGISTER IMR
250 INTERRUPT REQUEST REGISTER IRQ
24. INTERRUPT PRIORITY REGISTER IPR
248 PORTS 0-1 MODE P01M
247 PORT 3 MODE P3M
246 PORT 2 MODE P2M
245 TO PRESCALER PREO
244 riMER/COUNTER 0 TO
243 T1 PRESCAlER PRE1
242 TIMER/COUNTER 1 T1
241 TIMER MODE TMR
240 SERIAL. 1/0 510
NOT
IMPLEMENTED
127
GENERAlPURPOSE
REGISTERS
PORT 3 '3
.2
PORT 2
PORT 1 .,
PORT 0 PO
15
pop instructions are Z8 instructions which in- a parity error flag which indicates a parity
clude implicit stack operations. error if it is set to a ONE.
I/O S1RUC1URE Timer/Count~r TO is the. baud rate generator
and runs at lb tImeS the senal data bit rate.
Parallel I/O The receiver is double duffered and an internal
interrupt (IRQ3) is generated when a character
The Z8 microcomputer has 32 lines of I/O i~ loadeq ~nto the :eceive buffer register. A
arranged as four 8-bit ports. All of the I/O dIfferent Internal Interrupt (IRQ4) is generated
ports are TTL compatible and are configurable as when a character is transmitted.
input, output, input/output, or address/data.
The handshake control lines for Ports 0, 1, and COUNI'ER/TIMERS
2 are bits from Port 3 that have been programmed
through a Mode control register, except for ~, . The Z8 has two 8-bit programmable counter/
~, and R/Wwhich are available as separate Z8
tImers, each of which is driven by a program-
pins. The I/O ports are accessed as separate mable 6-bit prescaler. The T pres caler can be
internal registers by the Z8. Ports 0 and I driven by internal or external clock sources
share one Mode control register, and Ports 2 and the TO prescaler is driven by the inte~l
and 3 each have a Mode control register for clock only. The two prescalers and the two
configuring the port. counters are loaded through four control regis-
ters (see Figure 4) and when a counter/timer
Port 0 can be programmed to be an I/O port reaChes the "end of count" a timer interrupt is
or as an address output port. More specifically generated (IRQ4 for TO' and IRQS for T ). The
Port 0 can be configured to be an 8-bit I/O port counter/timers can be programmed to s~p upon
or a 4-bit address output port (A8-AlI) for ' reaching the end of count, or to reload and
external memory and one 4-bit I/O port, or an continue counting. Since either counter (one at
8-bit address output port (A8-AlS) for external a time) can have its output available external
melOOry. to the Z8, and Counter/Timer TI can have an
external input, the two counters can be cas-
Port I can be programmed as an I/O port caded.
(with or without handshake), or an address/data
port (~-AD7) for interfacing with external Port 3 can be progranvned to provide timer
memory. If Port I is progrrumned to be an add- outputs for external time base generation or
ress/data port, it cannot be accessed as a reg- trigger pulses.
ister.
INTERRUPT STRlJCTURE
Port 2 can be configured as individual
input or output bi ts, and Port 3 can be program- The Z8 provides for six interrupts from
med to be parallel I/O bits, and/or serial I/O e~ght different sources including four Port 3
bits, and/or handshake control lines for the lInes (P30-P33), serial in, serial out, and two
other ports. Figure 5 shows the port Mode counter/timers. These interrupts can be masked
registers. and prioritized using the Interrupt Mask Regis-
ter, (register.2SI) and the Interrupt Priority
The off chip expansion capability using ~gIster (:egIster 249). All interrupts can be
Ports 0 and I offers the added feature of being disabled WIth the master Interrupt enable bit
Z-Bus compatible. All Z-Bus compatible peri- in the Interrupt Mask Hegister.
pheral chips that are av~ilable now, ar,d will be
available in the future, will interface directly Each of the six interrupts has a 16-bit
WIth the Z8 multiplexect addreSS/data bus. interrupt vector that points to its interrupt
service routine. These six 2-byte vectors are
placed in the first twelve locations in the pro-
Serial I/O gram melOOry space (see Figure 2).
MODE~
~
---r-
PO,-PO,
-.J
OUTPUT", 00
INPUT", 01
L- Po,-PO, MODE
00 .. OUTPUT
01 INPUT
A,-A'5 .. IX 'X .. A,-A"
EXTERNAL MEMORY TIMING STACK SELECTION
NORMAL'" 0 o ..
EXTERNAL
EXTENDED .. 1 1 .. INTERNAL
Pl o-P1 7 MODE R247 IF7 HI Port 3 Mode Regls,.r (P3M; Write Only)
00 "" BYTE OUTPUT
01 .. BYTE INPUT
~~ : ~?&ttl~PEDANCE "'Do-A~
~~
PORTS 0 AND 1 MODES (POlM) O1 POAT 2 PULLUPS ACTIVE
PO AT 2 PUll UPS OPEN DAAIN
NOT USED
R246 (F6Hl Port 2 Mode Regla'er (P2M; Write Only) o P32 '" INPUT P35 = OUTPUT
1 P32 '" ir.(Vij P3S =: FlOYO
00 P33 '" INPUT P34 .::: OUTPUT
~ ~}P33 '" INPUT P34 '" DliI
11 P33 '" om P34 '" RDY1
' -_ _ _ _ _ _ _ ~~:~ ~ ~T(lIN)::: ~~~;UT(TOUT)
C>A>B=OOI
NOT USED-----=::r-
INTERRUPT GROUP PRIORITY
UNDEFINED = 000
I
IAQ1, IRQ, PRIORITY (GROUP C)
o '"
o -.
1
IROI > IRQ4
1 .::: IR04 '> IRQl
IROO. IR02 PRIORITY (GROUP 8)
IR02
= IROO >
.> IROO
IRD2
8 ::> C ::> A =- 100 IA03, lAOS PRIORITY (GROUP A)
C ::> 8 ::> A
8 "" A ;>
UNDEFINED = 111
=
101
C .:: 110 '-------- ~ ~ :=gi ; :=g~
1-7
routine (for nested interrupts), or upon return- which is-128 locations or +127 locations from
ing from the interrupt service routine using the the address of the instruction following the
IRET instruct10n. The interrupt cycle process jump instruction. The Immediate mode provides
is shown in Figure 7. the operand in the instruction.
................................_............................................................_.............................. There are eight instruction functional
:
i: groups;
INTERRUPT SOURCES
:
:
~
:
Load Bit Manipulation
Arithmetic Block Transfer
Logical Rotate and Shift
Program Control CPU Control
1-8
ciceros
didots
cieros and didots
centimeters
relative units
Instantaneous, one keystroke conversion
of values between any of the above
units of measurement.
Arithmetic operations using values
which are expressed in any of the
above units of measurement.
One keystroke execution of an extremely
accurate copyfitting algorithm which
finds any unknown copyfitting value
after the five known ones have been
entered, from among the following
copy descriptors:
width
depth
size
Z8/64 Package leading
type style ctensi ty
Figure 9 character count
Graphic proportional enlargement/
Z8 APPLICATION reduction computations by finding
anyone of the following values
Typeset Innovations, Inc. is a company after the other two are entered:
based in AuStin, Texas, that has designed a
graphics computing system based on the Z8 micro- original size
computer. The ProGrafix is a specialized elec- reproduction size
tronic computational aid for use by graphics enlargement/reduction ratio
arts professionals in the sizing and pricing of
graphic elements. Graphics arts professionals Memory storage and recall of intermedi-
are exemplified by typesetting job estimators, ate results, pricing constants, and
typographers, graphic designers, printers, ad- other user-created values.
vertising layout artists, and book and magazine
designers. When final packaging is complete the Pro-
Grafix will appear similar to the drawing
Graphic artists have in the past performed shown in Figure 10. The computational aid will
copyfitting through trial and error. With the have an 8 digit display, 7 annunciator LED's to
increasing costs of graphics materials, the indicate measurement units, an on/off switch,
trial and error method has become a noticab1e and a 40 key keyboard matrix. The key funct-
expense that can be minimized with a more ac- ions are defined in Table 1.
curate copyfitting technique. When Typeset Innovations began the design
of the ProGrafix early in 1980, they looked for
The ProGrafix performs the following a microcomputer that had the following charact-
functions; eristics;
Entry and display of values in the A real (available)microcomputer
units of measurement which are powerful enough to do the job
commonly used in the typographical
arts, including: Compact coding
picas Fast
points
picas and points Easy to program
inches
External expansion of memory
and I/O
1-9
~ ~ One line from Port 2 was used for the fifth
column input to the Z8 from the 40 key keypad.
\ / The remaining 7 I/O lines available from Port 2
were used for segment select on the numeric dis-
play.
The numeric display is "scan refreshed" by
the ZS at a rate that is approximately 100 times
per second. As the digits ~f the display are
being refreshed the keypad 1S scanned as a mat-
rix of 8 by 5 keys. The counter/timers on the
ZS are both used; one to time the display re-
fresh and the other as a timer for keypad de-
bounc~. An external stack is used for temp-
orary variable storage and durin~ the servic-
ing of interrupts. Only two ZS mterrupts are
used by the ProGrafix, one for the display re-
fresh counter and the other for the key de-
bounce timer.
The development of the software for the
ProGrafix, which included a BCD Floating Point
35 package, was done on a Zilog development system
34
with the ZS PLZ/ASM assembler. The object code
was down loaded to a ZS Development Module (DM)
i
I
where the hardware was initially debugged. The
I external memory was added to the Z8DM in the
space provided for wire wrap. When the system
~ was 90% - 95% debugged, a prototype circuit
board was built and the Z8 in a Protopak pack-
age with an EPRa.1 was used for final system de-
ProGrafix Computational Aid bug.
Figure 10 The production version of the ProGrafix
will use an LCD numeric display instead of the
LED display. This will make additional address
The Z8 offered all of these characteristics and lines available for expanding off chip memory.
more. By the second quarter of 1980, the Pro- In addition, a printer option is planned that
Grafix prototypes were working. will connect to the serial port of the ZS.
The prototype implementation is shown in The ProGrafix is expected to sell for under
Figure 11. External Ra.1 and RAM were added $500 without a printer and under $750 with a
using Port 1 and half of Port a (AS-All). The printer. The availability of the ProGrafix has
ability to add more than 2K b~tes of extern~l been targeted for May of 19S1.
memory with only 12 address l1nes (AO-A~l) ~s
possible because the Data Strobe (D6) ~1ne 1S The configuration of the ProGrafix com-
only active when locations above the f1rst 2K putational aid around the 28 provided a very
bytes are accessed. Memory locations ~rom 0 to flexible and powerful microcomputer system that
2K bytes are internal to the Z8; locat1ons from can be expanded to accomodate a wide variety of
2K bytes to 4K bytes (ROMO are external to the applications by simply changing the software.
Z8 and selected by address line All=l and TIS; Typeset Innovations is currently looking for
and locations from 4K bytes to 6K bytes (RAM) other products that can be implemented with the
are external to the Z8 and selected by address hardware that was developed for the ProGrafix.
line All = 0 and ns active.
CONCLUSION
The remaining four bits of Port 0 were
used to drive the Unit of Measure LED's and the The Z8 represents the coming of age of the
"sign" for the numeric display. more powerful microcomputers. While the ZS can
be a cost effective design solution for low end
Four of the I/O lines available from Port 3 applications, it can also be expanded to attack
were used to select one of eight digits on the much more sophisticated design problems. The
numeric display through a 4 to 16 decoder and to architecture of the ZS was designed in a forward
scan the rows of the keypad. The other four I/O looking manner, and the integration of more cap-
lines were used to read back the columns from ability onto the same chiP.is now limi~ed ~nly
the keypad. by the constraints of the 1ntegrated C1rcu1t
technology.
1-10
TABLE 1
Key 22 designated as DlDOT which provides for Key 38 designated as +/- reverses the sign of
the function of entering information in didot the value in display register X.
points and for converting the information on
the display into didot points. Key 39 designated as = invokes the last entered
arithmetic operation using the X and Y registers
Key 23 designated as RlJ/IN which is used to as operands and p'laces the result in display
store or recall of the relative units per em register X.
space parameter.
Key 40 designated as ON/OFF powers the micro-
Key 24 designated as RATIO which is used to computer system on and off.
store or recall the value of the ratio para-
meter in the proportional sizing algorithm.
1-11
\
Z8
MICROCOMPUTER
2K
2K BYTES
BYTES
RAM
PORT 1 ROM
ADDRESS
ASt------~
PORT0r--~~~--+------
UNIT OF MEASURE
PORTO INDICATOR LEOS
t---4---
PORTO~----~~!-~r-----------~
PORT 2
PORT 3
PORT 3
40 KEY
KEYPAD
PORT2~----~~-----l_ _ _ _....J
1 COLUMN
1-12
APPENDIX A
Load Instructions
Arithmetic Instructions
Logical Instructions
Program-Control Instructions
JP c c. dat Jump
JR cc. dat Jump Relative
RET Return
1-13
APPENDIX A (cont.)
Bit-Manipulation Instructions
Instruction Operands Name of
Instruction
Block-Transfer Instructions
1-14
A Comparison of
Microcomputer Units
ZI
Zllog Benchmark Report
MAY 1981
General-Purpose
Registers 124 12B 12B
Special-function
Registers
Status/Control 16 16 17
I/O ports 4 4 4
I/O
Parallel lines 32 32 29
Ports Four 8-bit Four 8-bit Three 8-bit,one 5-bit
Handshake Hardware on None Hardware on
three ports one port
Interrupts
Source 8 5 7
External source 4 2 2
Vector 6 5 7
Priority 4B Programmable 2 Programmable Nonprogrammable
orders orders
Maskable 6 5 6
External
Memory 120K bytes 124K bytes 64K bytes
Stack
Stack pointer 16-8it B-Bit 16-Bit
Internal stack Yes, uses Yes Yes
8-bits
External stack Yes No Yes
1-15 4-23-81
Table 1. MCU Comparison
(Continued)
Counter/
Tillll!rs
Counters Two 8-bIt Two 16-bl t One 16-bIt
Dr two 8-bit
Prescalers Two 6-bit No prescale None
with 16-bIts;
5-bl t prescale
with 8-b1 ts
Addressing
Modes
Reglster Yes Yes No
Induect RegIster Yes Yes No
Indexed Yes Yes Yes
D,rect Yes Yes Yes
RelatlVe Yes Yes Yes
ImmedIate Yes Yes Yes
ImplIed Yes Yes Yes
Index
Registers 124, Any 1, Uses the 1, Uses
general- accumu lator 16-blt Index
purpose for 8-bl t reglster
reglster offset
Seual
COIIIIIIUI1ication
Interface
Full duplex
UART Yes Yes Yes
Interrupts
for transmlt
and receIve One for each One for both One for both
Reglsters
Double buffer ReceIver ReceIver Transml tter/Rece lver
SerIal Data Rate 62.5K b/s 187.5K bls 62.5K bls
@8 MHz @12 MHz @4 MHz
93.5K bls
@12 MHz
Speed
Ins truct lon
executlDn average 2.2 Usee 1.5 Usee 3.9 Usee
1.5 Usec @12 MHz
Longest
InstructlDn 4.25 Usee 4 Usec 10 Usec
2.8 Usee @12 MHz
On-Chip ROM. All three chips have internal ROM The number of general-purpose registers on each
for program memory. The Z8611 and the 8051 have chip is comparable. However, because of its
4K byt es of inte rnal ROM, and the MC6801 has 2K flexible design, the ZB611 clearly has a more
bytes. In some cases, external memory may be powerful register architecture.
The MC6801 has 21 special function registers used On-Chip Peripheral Functions
for status, control, and I/O. These include:
In addition to the CPU and memory spaces, all
One register for RAM/EROM control chips provide an interrupt system and extensive
One serial receive register I/O facilities including I/O pins, parallel I/O
One serial transmit register ports, a bidirectional address/ data bus, and a
One register for serial control and status serial port for I/O expansion.
One serial rate and mode register
One register for status and control of port 3
One register for status and control of the Interrupts. The Z.8611 acknowledges interrupts
timer from eight sources, four are external from pins
Two registers for the 16-bit timer IRQO-IRQ3, and four are internal from serial-in,
Two registers for 16-bi t input capt ure used serial-out, and the two counter/timers. All
with timer interrupts are maskable. and a wide variety of
Two registers for 16-bit output compare used priorities are realized with the Interrupt Mask
with timer Register and the Interrupt Priority Registers (see
Four data direction registers associated with Table 1). All ZB611 interrupts are vectored, with
the four I/O ports six vectors located in the on-chip ROM. The
Four I/O ports vectors are fixed locations, two bytes long, that
contain the memory address of the service routine.
The MC6B01 has 29 lines for I/O (three B-bit ports The B051 handles serial I/O using one of its
and one 5-bit port). One port has two lines for parallel ports. The B051 bit rate is controlled
Chips
Zilog offers an entire family of' microcomputer All three microcomputers offer a Power Down mode.
chips for product development and final product. The Z8611 and the 8051 save all of t hei r regis-
The Z8611 is a single-chip microcomputer with 4K ters with an auxilary power supply. The MC6801
bytes of mask-programmed ROM. For development, two uses an auxiliary power supply to save only the
other chips are offered. The Z8612 is a 64-pin, first 64 bytes of its register file.
development version with full interface to ex-
ternal memory. The Z8613 is a prototype version The Z8611 uses one of the crystal input pins for
that uses a functional, piggy-back, EPROM proto- the external power supply to power the registers
pak. The Z8613 can use either a 4K EPROM (2732) in Power Down mode. Since the XTAL2 input must be
or a 2K EPROM (2716). Zilog also offers a ROMless used, an external clock generator is necessary and
version in a 40-pin package that has all the fea- is input via XTAL1. The B051 and the MC6B01 both
tures of the Z8611 except on-board ROM (Z8681). have an input reserved for this function. The
MC6801 uses the Vcc standby pin, and the 8051 uses
Intel offers a similar line of development chips the Vpd pin.
1:6801 Machine
Cycles Bytes 1:6801 Machine
LDAB 11$40 2 2 Cycles Bytes
LDAA I1CHARAC 2 2 LDX 115 6 3
LDX I1TABLE 3 3 LOAD WORK 4 2
LOOP: CMPA $0, X 4 2 LOOP: LSRD 3 1
BEQ OUT 4 2 DEX 3
INX 3 1 BNE LOOP 4 2
DECB 2 STAD WORD 4 2
BNE LOOP 4 2 N = 10X5+11 = 61 Cycles
OUT: - 4 MHz = 61-"6
Instructions 6
Bytes = 11
N = 7+40X17 = 687 cycles
4 MHz = 6B7 ....s
Instructions = B Z8611 Clock
Bytes = 15 Cycles Bytes
LD INDEX, 115 6 2
Z8611 Clock LOOP: CCF 6
Cycles Bytes RRC WORD + 6 2
LD INDEX, 1140 6 2 RRC WORD 6 2
LOOP: LD DATA, TABLE (INDEX) 10 3 DJNZ INDEX, LOOP 12 or 10 2
CP DATA, CHARAC 6 2 N = 6+4X30+2B = 154 Cycles
JR Z, OUT 12 or 10 2 12 MHz = 26Ms
DJNZ INDEX, LOOP 12 or 3D 2 Instructions = 5
OUT: - Bytes = 9
141:6801 MIId1ine
LCALL ADDRN 2 Cycles Bytes
N = 1+9X7+11 = 75 Cycles LDAB 'COUNT 2 2
au MHz = 75.u.s LOOP: LDX ADDR1 4 3
Instructions = 12 LDAA 0, X 4 2
Bytes = 21 INX 3 1
STAA ADDR1 4 2
LDX ADDR2 4 3
MC6801 Machilw STAA 0, X 4 2
Cycles Bytes INX 3 1
LDAB '2 2 2 STX ADDR2 4 2
LDX TABLE 3 3 DECB 2
LOOP: RORA 2 BNE LODP 4 2
BCS OUT 4 2 N = 64X36+2 = 2306 Cycles
ABX 3 ~ MHz =2306 4e
JMP LOOP 3 2 Instructions = 11
DUT: LDX 0, X 5 3 Bytes = 21
JMP 0, X 4 3
N = 8X12+14 = 110 Cycles
114 MHz = 110","s Z8611 Clock
Instructions = 8 Cycles Bytes
Bytes = 17 LD INDEX, ICOUNT 6 2
LOOP: LDEI MDDR2, IltADDR1 18 2
DJNZ IM>EX, LOOP 12 or 10 2
I8'" Clock N = 6+63X30+28 = 1924 Cycles
Cycles Bytes 1ii12 MHz = 321"'"B
CLR INDEX 6 2 Instructions = 3
LOOP: INC INDEX 6 Bytes = 6
RLC DATA 6 2
JR NC, LOOP 12 or 10 2
LD ADDR,TABLE 1, (IM>EX) 10 3
LD ADDR+1,TABLE 2, (INDEX) 10 3
JP IlADDR 12 2
N = 6+24X7+54 = 228 Cycles
1112 MHz = 38"-8
Instructions = 7
Bytes = 15
8051 Machine
B051 Machine Cycles Bytes
Cycles Bytes LCALL SUBR 2 :5
XRL PO, IYY 2 :5
N = 2 Cycles
1!!112 MHz = 2AS SUBR: -
Instructions
Bytes = :5 REf 2
N = 4 Cycles
@12 MHz = 4&s
Ins truct IOns = 2
MC6801 Machine Bytes = 4
Cycles Bytes
LDAA PORTO :5 2
HC6801 Machine
EORA IYY 2 2 Cycles Bytes
STAA PORTO :5 2 JSR SUBR 9 2
N = 8 Cycles
1!!14 MHz = BM-s
Instructions :5 SUBR: -
Bytes = 6
RTS 5
N = 14 Cycles
@4 MHz = 144s
Z8611 Clack InstructIons 2
Cycles Bytes Bytes = :5
XOR PORTO, flY Y 10 2
N = 10 Cycles
Z8611 Clock
812 Itlz = 1.7_ Cycles Bytes
Instructions = 1 CALL @SUBR 20 2
Byte = 2
SUBR: -
RET 14
N = 34 Cycles
@12 MHz = 5.7..us
InstructIons = 2
Bytes = 3
Results
Table 2 summarizes the reaults of this comparison.
The relative performance column lists the speeds
of the MC6B01 and B051 divided by the ZB611 speeds
(12 MHz). The overall performance averages the
separate relative performances. The higher the
number, the faster the ZB611 as compared to the
-MC6B01 and the B051.
MC6801 8051 Z8 Z8
Benchmark (4 tfiz) (12 tfiz) (8 tfiz) (12 tfiz) Relative Performance
Test cycles time cyc les tillle cycles time cycles time MC6801 8051
CRC
Generation 367 367 139 139 546 137 546 91 4.03 1.53
Character
Search 687 687 280 280 1524 382 1524 254 2.70 1.10
Computed
GOTO 110 110 75 75 228 57 228 38 2.89 1.97
Shift Right
5 Bits 61 61 46 46 154 38 154 26 2.35 1.78
Move
64-byte
block 2306 2306 577 577 1924 481 1924 321 7.18 1.80
Subroutine
Overhead 14 14 4 4 34 8.5 34 5.7 2.46 0.70
Toggle a
Port Bit 8 8 2 2 10 2.5 10 1.7 4.71 1.18
Overall
Performance 3.76 1.44
Computed GO TO 17 21 15 8 12 7 110 75 38
~
Zilog Application Brief
October 1980
The Interrupt Request Register (IRQ, R250) The designer must ensure that unexpected and
stores requests from the six possible Inter- undesirable Interrupt requests will not occur
rupt sources (IRQO_I RQ5) In the Z8600 series after the EI Is executed. One method of
microcomputer. In addition to other func- doing this Is to reset all Interrupt enable
tions, a hardware reset to the Z8600 disables bits In the IMR for levels that ere possible
the IRQ register and resets its request bits. Interrupt sources; the EI instruction may
Before the IRQ will register requests, It then be safely executed. Once EI Is exe-
must first be enabled by executing an Enable cuted, the program may immediately execute a
Interrupts (EI) Instruction. Setting the Disable Interrupts (DI) instruction. The
Enable Interrupt bit In the Interrupt Mask code necessary to perform these operations Is
Register (IMR, R251) Is not an equivalent as follows:
operation for this purpose; to enable the
IRQ, an EI Instruction Is required. The RESET: LD IMR, #%XX !SET INTERRUPT MASK!
function of this EI Instruction Is distinct EI ! ENABLE GLOBAL I NTER-
from Its task of globally enabling the Inter- RUPT, ENABLE IRQ!
rupt system. Even In a pol led system where
IRQ bits are tested In software, It Is where XX has a ~ In each bit position cor-
necessary to execute the EI. responding to the Interrupt level to be
disabled. If all IMR bits are to be reset, a
CLR IMR Instruction may be used.
EI INSTRUCTION
R Z8600
RESET ------------~
~
Zilog Application Brief
January 1981
12-BIT The Z8601 can manipulate data In four memory Is generated each time an address greater
ADDRESSING spaces: Internal program memory, Internal than 2047 Is used.
II ITH THE Z8600 register file, external program memory, and
SERIES FAMILY external data memory. The Internal register
file Is not discussed In this paper. Port 3 The Z8601 has 2K bytes of on-chip program
may be conf Igured opt lona II y to prov Ide a memory. The user cannot directly access
Data Memory (~) strobe that Is used to external memory In the address range of 0 to
select program and data memory. The Z8601 2K since this address range Is decoded as an
generates another signal, Data Strobe (DS), I nternal address. The Z8600 accesses ex-
that signals an external memory operation. OS ternal memory In the following manner:
%FFFF %FFFF
EXTERNAL EXTERNAL
PROGRAM DATA
MEMORY MEMORY
%0800 %0800
%07FF %07FF
INTERNAL NOT
%0000 %0000
~
Zilog Application Brief
October 1980
INTRODUCTION The ZII09 Z8600 UART microcomputer Is a hlgh- Three possible error conditions can occur
performance, single-chip device that Incor- during reception of serial data: framing
porates on-ch Ip ROM, RA'I, parallel I/O, error, parity error, and overrun error. A
serial I/O, and a baud rate generator. The framing error condition occurs when a stop
UART Is capable of ful I-duplex, asynchronous bit Is not received at the proper time
serial communication at nine standard (Figure 1). This can result from noise In
software-selectable baud rates from 110 to the data channel, causing erroneous detection
19.2K baud; other nonstandard rates can also of the previous start bit or lack of detec-
be obtained under software control. Odd tion of a properly transmitted stop bit. The
parity generation and checking can also be Z8600 UART does not incorporate hardware
selected. framing error detection but does facilitate a
simple, low-overhead software detection
method.
MElliOO In the middle of the stop bit time, the Z8600 dltion exists and the fol lowing code Is used
UART automatically posts a serial Input to test th is:
I nterrupt request on IRQ3. The serl al Input
can also be tested by reading Port 3 bit 0 TM P3, 1%01 ! TEST FOR P30 = 1 I
(P30) as shown In Figure 2. Thus, within JR Z, FERR I ELSE FRAMING ERROR!
the Interrupt service routine or pol ling
loop, It Is only necessary to test P3 0 In The execution time of this framing error test
order to Identify a framing error. If P30 Is Is on I y 5.5 A(s at 8 MHz. In the worst case
Low when IRQ3 goes High, a framing error con- (19.2K baud), this would result In 1% over-
head. Only five program bytes are required.
SERIAL _
DATA IN P3 0
Z8600
617-1881-0004 1-33
CONClUSION Wh II e the Z8600 UART does nat Incorporate maxImum penalty of 1% at 19.2K baud usIng no
hardware framing error detection, thIs additional hardware and only fIve bytes of
feature can be Implemented In software with a program memory.
617-1881-0004 1-34
A Programmer's Guide to
the Z8 Microcomputer
~
Zilog
Application
Note
Doll Freund
October 1980
1-35
2. Accessing 2.2 Register Pointer. Wlthm the register The address calculabon for the latter case
Register addressing modes provIded by the Z8, a regis- IS !llustrated in FIgure I. Nohce that 4-blt
Memory ter may be speclhed by Its full 8-blt address workmg-reglster addressmg offers code com-
(Contmued) (0-%7F, %FO-%FF) or by a short 4-blt pactness and fast execuhon compared to ItS
address. In the latter case, the reglSter is 8-blt counterpart.
v18wed as one of 16 workmg regIsters with- To modify the contents of the Register
m a working regIster group. Such a group Pomter, the Z8 provIdes the mstrucbon
must be aligned on a 16-byte boundary and is SRP #value
addressed by RegIster Pomter RP (%FD). As
an example, assume the RegIster Pomter con- Execuhon of thIs mstruchon will load the
tams %70, thus pointmg to the workmg reg- upper four bIts of the RegIster Pomter; the
Ister group from % 70 to % 7F. The LD mstruc- lower four bIts are always set to zero. Although
bon may be used to mlhahze regIster %76 to a load mstruchon such as
an ImmedIate value m one of two ways: LD RP,#value
LD %76,#1 !8-blt regIster address IS gIven could be used to perform the same functJon,
by instrucbon (3 byte mstruc- SRP provIdes execuhon speed (six vs. ten
bon)! cycles) and code space (two vs. three bytes)
or advantages over the LD mstrucbon. The
LD R6,#1 !4-blt workmg regIster address mstruchon
IS gIven by mstruction; 4-blt
SRP #%70
working regIster group
address IS gIven by RegIster IS used to set the RegIster Pomter for the above
Pomter (2 byte mstrucbon)! example.
, 0 0
2.3 Context Switching. A typical function assume such a register allocation scheme has
performed during an interrupt service routine been implemented in which the interrupt ser-
is context switching. Context switching refers vice routine for IRQO may access only working
to the saving and subsequent restoring of the register Group 4 (registers %40-%4F). The
program counter, status, and registers of the service routine for IRQO should be headed by
interrupted task. During an interrupt machine the code sequence:
cycle, the Z8 automatically saves the Program PUSH RP !preserve Register Pointer of
Counter and status flags on the stack. It is the interrupted task!
responsibility of the interrupt service routine to SRP #%40 !address working register
preserve the register space. The recommended group 4!
means to this end is to allocate a specific por-
tlon ot the register hie tor use by the service Before exiting, the service routine should
routine. The service routine thus preserves the execute the instruction
register space of the interrupted task by avoid- POP RP
ing modification of registers not allocated as its to restore the Register Pointer to its entry
own. The most efficient scheme with which to value.
implement this function in the Z8 is to allocate It should be noted that the technique
a working register group (or portion thereof) to described above need not be restricted to
the interrupt service routine. In this way, the interrupt service routines. Such a technique
preservation of the interrupted task's registers might prove efficient for use by a subroutine
is solely a matter of saving the Register Pointer requiring intermediate registers to produce its
on entry to the service routine, setting the outputs. In this way, the calling task can
Register Pointer to its own working register assume that its environment is intact upon
group, and restoring the Register Pointer prior return from the subroutine.
to exiting the service routine. For example,
20091101
2. Accessing 2.4 Addressing Mode. The Z8 provIdes three LD R2,#%60
Register addressIng modes for acceSSIng the regIster !workIng regIster 2 IS the buf-
Memory space: Direct Register, Induect RegIster, and fer pOInter regIster!
(ContInued) Indexed. out_agaIn:
2.4.1 Direct Register Addressmg. ThIs 10 RO,@R2
addressIng mode is used when the target regIs- !load Into workIng regISter 0
ter address IS known at assembly hme. Both the byte pOInted to by workIng
long (8-blt) regIster addressIng and short regIster 2!
(4-blt) workIng regISter addressIng are sup- INC R2 !Increment pOInter!
ported In thIS mode. Most Instruchons sup- CALL SERIAL_OUT
portIng thIS mode provIde access to sIngle !output the byte!
8-blt regIsters. For example: DJNZ Rl ,out _again
!loop hll done!
LD %FE,#HI STACK
!load regIster %FE (SPH) wIth IndIrect addreSSIng may also be used for
the upper 8-blts of the label acceSSIng a 16-blt regIster paIr Via the INCW
STACK! and DECW Instruchons. For example,
AND O,MASK_REG INCW @RO !Increment the regIster pair
!AND regISter 0 wIth regIster whose address IS contaIned In
named MASK_REG! workIng regISter O!
OR 1,R5 lOR regIster 1 wIth workIng DECW @%7F
regIster 5! !decrement the regISter paIr
Increment word (INCW) and decrement whose address IS contaIned In
word (DECW) are the only two Z8 Instruchons regIster %7F!
whIch access 16-bit operands. These Instruc- The contents of regIsters RO and %7F should
hons are Jllustrated below for the dIrect reg- be even numbers for proper access; when
Ister addressIng mode. referenCIng a regIster paIr, the least slgmflcant
INCW RRO !Increment workmg regIster address bIt IS forced to the appropnate value
paIr RO, Rl: by the Z8. However, the regIster used to POInt
Rl- Rl + to the regIster pair need not be an even-
numbered regIster.
RO - RO + carry!
DECW %7E SInce the Indirect addreSSIng mode permIts
!decrement workIng regIster calculatIon of a target address pnor to the
paIr %7E, %7F: deSIred regIster access, thIs mode may be used
to sImulate other, more complex addreSSIng
%7F - %7F
modes. For example, the Instruchon
%7E - %7E - carry!
SUB 4,BASE(R5)
Note that the Instruchon
!NCW RR5 reqUIres the Indexed addreSSIng mode whIch IS
not dIrectly supported by the Z8 SUBtract
wJll be flagged as an error by the assembler InstructIOn. ThIs Instruchon can be sImulated
(RR5 not even-numbered). as follows:
2.4.2 Indirect Register Addressmg. In thIs 10 R6,#BASE
addressIng mode, the operand is pOInted to by !workIng regIster 6 has the
the regIster whose 8-blt regIster address or base address!
4-blt workIng regIster address IS gIven by the ADD R6,R5 !calculate the target address!
Instruction. ThIs mode IS used when the target SUB 4,@R6 !now use Indirect addreSSIng to
regIster address IS not known at assembly hme perform the actual subtract!
and must be calculated during program execu-
hon. For example, assume regIsters %60-%7F Any ava!lable regIster or workIng register
contain a buffer for output to the senal line vIa may be used In place of R6 in the
repehhve calls to procedure SERIAL_OUT. above example.
SERIAL_OUT expects workIng regIster 0 to 2.4.3 Indexed Addressmg. The Indexed
hold the output character. The follOWIng addreSSIng mode IS supported by the load
Instruchons Jllustrate the use of the indIrect InstructIon (LD) for the transference of bytes
addreSSIng mode to accomphsh thIs task: between a workIng regISter and another regIs-
LD Rl,#%20 ter. The effechve address of the latter regIster
!workIng register 1 is the byte IS gIven by the Instruchon whIch IS offset by
counter: output %20 bytes! the contents of a deSIgnated workIng (Index)
1-37
2. Accessing register. This addressmg mode provides LD RI ,#BUF + LENGTH-I
Register effICient memory usage when addressmg LD RO,#LENGTH
Memory consecullve bytes m a block of register !startmg at buffer end, look for
(Contmued) memory, such as a table or a buffer. The 1st non-blank!
workmg register used as the mdex m loopl:
the effecllve address calculallon can CP @Rl,#' ,
serve the addillonal role of counter for JR ne,foundl
control of a loop's durallon. !found non-blank!
For example, assume an ASCII character DEC Rl !dec pomter!
buffer eXists m register memory startmg at DJNZ RO,loopl
address BUF for LENGTH bytes. In order !are we done?!
to determme the logical length of the char- allJlanksl: !length = O!
acter strmg, the buffer should be scanned foundl:
backward unlll the first nonoccurrence of a 6 mstrucllons
blank character. The followmg code 13 bytes
sequence may be used to accomphsh 3 /LS overhead
thiS task: 9.5 /LS (average) per character tested
LD RO,#LENGTH The latter method requires one more byte of
!length of buffer! program memory than the former, but IS faster
!startmg at buffer end, look for by four execullon cycles (l /Ls) per character
1st non-blank! tested.
loop: As an alternate example, assume a buffer
LD RI ,BUF -I(RO) eXists as descnbed above, but It IS deSired to
CP R!,#' , scan thiS buffer forward for the first occur-
JR ne,found rence of an ASCII carnage return. The follow-
!found non-blank! mg Illustrates the code to do this:
DJNZ RO,loop
LD RO,# - LENGTH
!look at next! !startmg at buffer start, look for
all_blanks: !length = O! 1st carnage return ( = %OD)!
found: next:
5 mstrucllons LD r I ,BUF + LENGTH(RO)
12 bytes CP RI,#%OD
1.5 /LS overhead JR eq,cr !found It!
10.5 /LS (average) per character tested INC RO !update counter/mdex!
At labels "all_blanks" and "found," RO JR nZ,next
contams the length of the character !try agam!
strmg. These labels may refer to the same cr:
locallon, but they are shown separately for ADD RO,#LENGTH
an apphcallon where special processmg IS !RO has length to CR!
reqUired for a strmg of zero length. To per- 7 mstructlOns
form thiS task Without mdexed address- 16 bytes
mg would reqUire a code sequence 1.5 /LS overhead
such as: 12 /LS (average) per character tested
SECTION Accessing Program and External Data LDE or the mdlrect workmg register address-
Memory mg mode m LDCI and LDEI. In addmon to
3 In a smgle mstrucllon, the Z8 can transfer a performmg the deSignated byte transfer, LDCI
byte between register memory and either pro- and LDEI automallcally mcrement both the
gram or external data memory. Load Constant mdlrect registers specIfied by the mstruchon.
(LDC) and Load Constant and Increment These mstrucllons are therefore effiCient for
(LDCn reference program memory; Load performmg block moves between reqlster and
External (LDE) and Load External and Incre- either program or external data memory. Smce
ment (LDEI) reference external data memory. the mdlrect addressmg mode IS used to specdy
These mstrucllons reqUire that a workmg the operand address wlthm program or exter-
register pair contam the address of the byte m nal data memory, more complex addressmg
either program or external data memory to be modes may be simulated as discussed ear her
accessed by the mstrucllon (mdlrect workmg m Sechon 2.4.2. For example, the mstruchon
register pair addressmg mode). The register LDC R3,BASE(R2)
byte operand IS specIfied by usmg the direct
workmg register addressmg mode m LDC and reqUires the mdexed addressmg mode, where
1-38
3. Accessing BASE IS the base address of a table m program LD POIM,#%(2)000I001O
Program and memory and R2 con tams the offset from table !blt 3-4: enable ADo-AD7;
External Data start to the desired table entry. The followmg bit 0-1: enable Aa-All!
Memory code sequence simulates this mstrucllon With LD P3M,#%(2)OOOOIOOO
(Contmued) the use of two addlhonal registers (RO and RI !blt 3-4: enable DM!
m this example). The two bytes following the mode selechon of
LD RO,#HI BASE ports 0 and I should not reference external
LD R 1.#LO BASE memory due to plpelimng of mstruchons wlthm
!RRO has table start address! the 2S. Note that the load mstruchon to P3M
ADD Rl.R2 sallsfles this reqUirement (provldmg that It
ADC RO,#O reSides wlthm the Internal 2K bytes of
!RRO has table entry address! memory).
LDC R3,@RRO 3.2 LDC and LDE. To Illustrate the use of the
!R3 has the table entry! Load Constant (LDC) and Load External (LDE)
3.1 Configuring the Z8 for I/O Applications Instruchons, assume there eXists a hardware
vs. Memory Intensive Applications. The 2S conflgurallon With external memory and Data
offers a high degree of flexibility m memory Memory Select enabled. The following module
and 1/0 mtenslve applicahons. Thirty-two port Illustrates a program for tokemzlng an ASCII
bits are provided of which 16, 12, eight, or mput buffer. The program assumes there IS a
zero may be configured as address bits to list of delimiters (space, comma, tab, etc.) In
external memory. This allows for addressmg of program memory at address DELIM for
62K, 4K or 256 bytes of external memory, COUNT bytes (accessed via LDC) and that an
whICh can be expanded to 124K, SK, or 512 ASCII Input buffer eXists In external data
bytes If the Data Memory Select output (DM) IS memory (accessed via LDE). The program
used to dlstmgUlsh between program and data scans the mput buffer from the current locahon
memory accesses. The followmg mstrucllons and returns the start address of the next token
Illustrate the code sequence reqUired to con- (I.e. the address of the first nondelimlter
figure the 2S With 12 external addressmg Imes found) and the length of that token (number of
and to enable the Data Memory Select output. characters from token start to next delimiter).
Z8ASM 2.0
LOC OBJ CODE STMT SOURCE STATEMENT
1 SCAN MODULE
2 CONSTANT
3 COUNT._ 6
4 GLOBAL
5 $SECTION PROGRAM
P 0000 20 3B 2C 6 DELIM ARRAY [COUNT BYTE]
P 0003 2E OA 00
7 [ t t , , ,
1.1 I
'.' , ~OA , ~ODl
8
P 0006 9 scan PROCEDURE
10 1*****************************************************
11 Purpose To find the next token within an
12 ASCII buffer.
13
14 Input RRO = address of current location
15 within input buffer in external
16 memory.
17
18 Output RR4 address of start of next token
19 RRO address of new token's ending
20 delimi ter
21 R2 length of token
22 R3 ending delimiter
23 R6,R7,R8,R9 destroyed
24
25 *****************************************************1
26 ENTRY
P 0006 BO E2 27 clr R2 linit. length counter!
28 DO
P 0008 82 30 29 LDE R3,@RRO !get byte from input bufferl
P OOOA AO EO 30 incw RRO lincrement pointerl
P OOOC 06 002E' 31 call check Ilook for non-delimiter 1
P OOOF FD 0015' 32 IF C THEN
P 0012 80 0018' 33 EXIT Ifound token start!
34 FI
P 0015 80 0008' 35 00
1-39
3. Accessing 36
Program and P 0018 48 EO 37 ld R4, RO
External Data
P 001A 58 E1 38 ld R5, R1 IRR4 = token starting addrl
39 DO
Memory P 001C 2E 40 inc R2 linc. length counter!
(Contmued) P 001D 82 30 41 LDE R3,@RRO !get next input byte!
P 001F D6 002E' 42 call check !look for delimiter!
P 0022 7D 0028' 43 IF NC THEN
P 0025 8D 002D' 44 EXIT !found token endl
45 FI
P 0028 AO EO 46 incw RRO !point to next byte!
P 002A 8D 001C' 47 OD
48
P 002D AF 49 ret
P 002E 50 END scan
51
P 002E 52 check PROCEDURE
53 !**************** *****************************
54 Purpose = compare current character with
55 delimiter table until table
56 end or match found
57
58 input DELIM = start address of table
59 COUNT = length of that table
60 R3 = byte to be scrutinized
61
62 output Carry flag = 1 => input byte
63 is not a delimiter (no match found)
64
65 Carry flag = 0 => input byte
66 is a delimiter (match found)
67 R6,R7,R8,R9 destroyed
68
69 ******* ********************************************!
70 ENTRY
P 002E 6C 00* 71 ld R6,IIHI DELIM
P 0030 7C 00* 72 ld R7,IILO DELIM !RR6 pOints to
73 delimiter list!
P 0032 8c 06 74 ld R8, /lCOUNT !R8 = length of list!
75 here:
P 0034 C2 96 76 LDC R9,@RR6 !get table entry!
P 0036 AO E6 77 incw RR6 !point to next entry!
P 003& A2 93 78 cp R9,R3 !R3 = delimiter?!
P 003A 6B 03 79 jr eq,bye !yes. carry = O!
P 003C 8A F6 80 djnz R8,here !next entry!
P 003E DF 81 scf Stable done. R3
82 not a delimiter!
83 bye:
P 003F AF 84 ret
P 0040 85 END check
86 END SCAN
o ERRORS
ASSEMBLY COMPLETE
27 Instrucimns
58 byres
ExecullOn 11me 18 a functIOn 01 the number of leadIng deilm1ters
before token start (x) and the number of characters In the
taken (y): 123 p.s overhead + 59x p.s + 102y p.s
(average) per token
3.3 LDCI. A common function performed in Z8 register or two program bytes for a working
applications is the initialization of the register register). This approach is also the most effi-
space. The most obvious approach to this func- cient technique for initializing less than eight
tion is the coding of a sequence of "load consecutive registers or 14 consecutive work-
register with immediate value" instructions ing registers. For a larger register block, the
(each occupying three program bytes for a
1-40
3. Accessing LDCI instruction provides an economical 3.4 LDEI. The LDEI instruction is useful for
Program and means of initializing consecutive registers from moving blocks of data between external and
External Data an initialization table in program memory. The register memory since auto-increment is per-
Memory following code excerpt illustrates this tech- formed on both indirect registers designated
(Conhnued) nique of initializing control registers %F2 by the instruction. The following code excerpt
through %FF from a 14-byte array (INIT_tab) illustrates a register buffer being saved at
in program memory: address %40 through %60 into external
SRP #%00 memory at address SAVE:
!RP not %FO! 10 RI0,#HI SAVE
10 R6,#HI INIT_tab !external memory!
LD R7,#LO INIT_tab 10 Rll,#LO SAVE
10 R8,#%F2 !address!
! 1st reg to be initialized! LD R8,#%40
LD R9,#14 !starting register!
!length of register block! LD R9,#%21
loop: !number of registers to save in
LDCI @R8,@RR6 external data memory!
!load a register from the loop:
init table! 10EI @RRIO,@R8
DJNZ R9,Ioop IImt a register!
!continue till done! DJNZ R9,Ioop
7 instructions !until done!
14 bytes 6 instructions
7.5 ,",S overhead 12 bytes
7.5 ,",S per register initialized 6 ,",s overhead
7.5 ,",S per register saved
1-41
4. Bit AND operation; the overflow flag (V) IS always As in Test under Mask, the FLAGS control
Manipu- reset. All other flags are unaffected. Table 2 register is the only register affected by thiS
lations Illustrates the flag settmgs which result from operation. The zero flag (Z) IS set if all selected
(Continued) the TM instruction on a variety of source and destination bits are I; it IS reset otherwise. The
destination operand combinations. Note that a sign flag (S) is set or reset to reflect the result
given TM mstruction will never result in both of the AND operation; the overflow flag (V) is
the Z and S flags being set. always reset. Table 3 Illustrates the flag set-
4.2 Test Complement under Mask. The Test tmgs whICh result from the TCM mstructlon on
Complement under Mask instruction is used to a variety of source and destination operand
test selected bits for logic 1. The logICal opera- combinations. As with the TM instruction, a
tion performed IS given TCM mstruction will never result in both
the Z and S flags bemg set.
(NOT destmatlon) AND source.
Destination Source Flags Destination Source Flags
XSP_
x-1
x-2
x-3 ,
sp_
Itt
~ Ai
PCu)W
SP_ PCHfGH
LABEL 2: CALL @RR4
!mdlrect addressmg: PC IS
loaded With the contents of
workmg register pair R4, R5;
address LABEL 2 + 2 IS pushed
x-4 onto the stack!
INITIAL FOLLOWING FOLLOWING
STATE PUSH R1 CALL
2009-1102
1-42
5. Stack LABEL 3: CALL @%7E the stack and regIster memory, thus provldmg
Operations !mdlrect addressmg: PC IS program access to the stack for savmg and
(Contmued) loaded wIth the contents of restormg needed values and passmg
regIster paIr %7E, %7F; parameters to subroutmes.
address LABEL 3 + 2 IS pushed ExecutIOn of a PUSH mstruchon causes the
onto the stack! stack pomter to be decremented by I; the
5.3 RET. The return (RET) mstruchon causes operand byte IS then loaded mto the locahon
the top two bytes to be popped from the stack pomted to by the decremented stack pomter.
and loaded mto the Program Counter. TYPI- Execution of a POP instruction causes the byte
cally, thIS IS the last mstruchon of a subroutme addressed by the stack pomter to be loaded
and thus restores the PC to the address follow- into the operand byte; the stack pointer is then
mg the CALL to that subroutme. incremented by I. In both cases, the operand
byte IS deSIgnated by eIther a dIrect regIster
5.4 Interrupt Machine Cycle. Durmg an mter-
address or an mdlrect regIster reference. For
rupt machme cycle, the PC followed by the
example:
status flags IS pushed onto the stack. (A more
detaded dIscussIOn of mterrupt processmg IS PUSH Rl !dlrect address: push workmg
provIded m Sechon 6.) regIster I onto the stack!
5.5IRET. The mterrupt return (lRET) mstruc- POP 5 !dlrect address: pop the top
hon causes the top byte to be popped from the stack byte mto regIster 5!
stack and loaded mto the status flag regIster, PUSH @R4 !mdlrect address: pop the top
FLAGS (%FCl, the next two bytes are then stack byte mto the byte
popped and loaded mto the Program Counter. pomted to by workmg reg-
In thIS way, status IS restored and program Ister 4!
execuhon contmues where It had left off when PUSH ilL 17 !mdlrect address: push onto
the mterrupt was recogmzed. the stack the byte pomted to
5.6 PUSH and POP. The PUSH and POP by regISter 17!
mstruchons allow the transfer of bytes between
1-43
- - . - - . - -. . -.~--
6. Interrupts 6.2 Vectored Interrupt Processing. Enabled may be allowed servIce withm the current
(Contmued) mterrupt requests are processed m an mterrupt servICe rout me (nested) or may be
automahc vectored mode m whIch the mter- held until the current service rout me IS com-
rupt servIce routme address IS retneved from plete (non-nested).
wlthm the hrst 12 bytes of program memory. To allow nested interrupt processmg, inter-
When an enabled mterrupt request IS rupts must be selechvely enabled upon entry
recogmzed by the 28, the Program Counter IS to an mterrupt service routme. Typically, only
pushed onto the stack (low order 8 bIts hrst, higher-pnonty interrupts would be allowed to
then hIgh-order 8 bIts) followed by the FLAGS nest within the current mterrupt servIce. To do
regIster (#%FC). The correspondmg mterrupt thIs, an interrupt routine must "know" which
request bIt IS reset m IRQ, mterrupts are mterrupts have a hIgher prlOnty than the cur-
globally dIsabled (bIt 7 of IMR IS reset), and rent mterrupt request. SelectIOn of such nest-
an mdlrect Jump IS taken on the word m loca- mg pnorities is usually a reflechon of the
hon 2x, 2x + I (x = mterrupt request number, prlOnhes estabhshed m the Interrupt Pnority
Osxs5). For example, If the bytes at RegIster OPR). Given thIs data, the first
addresses %0004 and %0005 contam %05 and mstruchons executed m the service routme
%78 respechvely, the mterrupt mach me cycle should be to save the current Interrupt Mask
for IRQ2 wIll cause program execuhon to con- Register, mask off all mterrupts of lower and
tmue at address %0578. equal pnonty, and globally enable mterrupts
When mterrupts are sampled, more than one (EI). For example, assume that service of inter-
mterrupt may be pendmg. The Interrupt Pnor- rupt requests 4 and 5 are nested WIthin the ser-
Ity RegIster (IPR) controls the selechon of the vIce of mterrupt request 3. The following Illus-
pending interrupt wIth hIghest pnority. While trates the code requIred to enable IRQ4
thIs mterrupt IS bemg servIced, a higher- and IRQ5:
pnonty mterrupt may occur. Such mterrupts
CONSTANT
%(2) 00110000
GLOBAL
IRQ3_servlce PROCEDURE ENTRY
!servlce routme for IRQ3!
PUSH IMR !save Interrupt Mask RegIster!
!mterrupts were globally dIsabled durmg the mterrupt
machme cycle - no DI IS needed pnor to modlhcahon of IMR!
AND IMR,#INT_MASK_3 !dlsable all but IRQ4 & 5!
EI
!. .. ! !servlce mterrupt!
!mterrupts are globally enabled now - must dIsable them prIOr to
modlhcahon of IMR!
DI
POP IMR !restore entry IMR!
IRET
END IRQ3_servICe
Note that IRQ4 and IRQ5 are enabled by the interrupts, the followmg code sequence could
above sequence only If theIr respechve IMR be used:
bits = I on entry to IRQ3_servlce. POP FLAGS
The servIce rout me for an mterrupt whose !FLAGS .... @SP!
processmg is to be completed wIthout interrup- !PC ...- @SP!
RET
hon should not allow mterrupts to be nested
within It. Therefore, It need not modify the This accomphshes all the funcllons of IRET,
IMR, smce interrupts are dIsabled automah- except that IMR is not affected.
cally during the mterrupt machine cycle. 6.3 Polled Interrupt Processing DIsabled
The servIce routine for an enabled mterrupt mterrupt requests may be processed in a
IS tYPIcally concluded wIth an IRET instruc- polled mode, m whIch the corresponding bIts
llon, whIch restores the FLAGS register and of the Interrupt Request RegIster (IRQ) are
Program Counter from the top of the stack and exammed by the software. When an interrupt
globally enables mterrupts. To return from an request bIt IS found to be a logic I, the inter-
mterrupt servIce routme wIthout re-enabling rupt should be processed by the appropriate
1-44
6. Interrupts servICe routine. During such processing, the lIshed prionties. For example, assume that
(Contmued) Interrupt request bIt In the IRQ must be IRQO, IRQ I , and IRQ4 are to be polled and
cleared by the software In order for subsequent that established prlOnhes are, from hIgh to
interrupts on that line to be dIstingUIshed from low, IRQ4, IRQO, IRQI. An instruction
the current one. If more than one interrupt sequence like the followmg should be used to
request is to be processed In a polled mode, poll and servICe the mterrupts:
polling should occur m the order of estab-
I. .. !
!poll Interrupt mputs here!
TCM IRQ, #%(2)00010000 !IRQ4 need servIce?!
JR NZ, TESTO !no!
CALL IRQ4_servICe !yes!
TESTO: TCM IRQ, #%(2)00000001 !IRQO need servICe?!
JR NZ, TESTI !no!
CALL IRQO_servlce !yes!
TEST!: TCM IRQ, #%(2)00000010 !IRQI need servIce?!
JR NZ, DONE !no!
CALL IRQ I_serVICe !yes!
DONE: I. .. !
1-45
7. Timer/ counters may simulate a readable prescaler. When TOUT is dnven by the mternal clock,
Counter This capability IS a reqUirement for high that clock IS directly output on P36.
Functions resoluhon measurement of an event's durahon. While programmed as TOUT. P36 IS disabled
(Continued) The basIc approach reqUires that one hmer/ from bemg modified by a write to port register
counter be mltlalized With the desired counter %03; however, ItS current output may be
and prescaler values. The second timer/ exammed by the 28 software by a read to port
counter IS mlhalized With a counter equal to register %03.
the prescaler of the hrst timer/counter and a 7.3 TIN Modes. Port 3, bit 1 (P31) may be con-
prescaler of 1. The second hmer/counter must figured as an mput (TIN) whICh IS used m con-
be programmed for conhnuous mode. With Junchon With TI in one of four modes:
both hmer/counters driven by the mternal
clock and started and stopped simultaneously, External clock mput
they will run synchronous to one another; thus, Gate mput for mternal clock
the value read from the second counter will Nonretrlggerrable mput for mternal clock
always be eqUivalent to the prescaler of
the hrst. Retrlggerable mput for mternal clock
7.1 Time/Count Interval Calculation To For the latter two modes, It should be noted
determme the hme mterval (I) until EOC, the that the eXistence of a synchronlzmg circuit
equahon Wlthm the 28 causes a delay of two to three
mternal clock perIOds followmg an external
l=tXpXV
trigger before clockmg of the counter actually
characterizes the relation between the begms.
prescaler (p), counter (v), and clock mput Each High-to-Low transliwn on TIN Will
period (I); t IS given by generate mterrupt request IRQ2, regardless of
1I(XTAU8) the selected TIN mode or the enabled/disabled
where XTAL IS the 28 mput clock frequency; state of T1. IRQ2 must therefore be masked or
p IS m the range 1 - 64; v is m the range enabled accordmg to the needs of the
I - 256. When programmmg the prescaler and applIcatwn.
counter registers, the maximum load value IS The "external clock mput" TIN mode sup-
truncated to SIX and eight bitS, respectively, ports the countmg of external events, where an
and IS therefore programmed as zero. For an event IS seen as a Hlgh-to-Low translhon on
mput clock frequency of 8 MHz, the prescaler TIN. Interrupt request IRQ5 IS generated on
and counter register values may be pro- the nth occurrence (smgle-pass mode) or on
grammed to hme an mterval m the range every nth occurrence (conhnuous mode) of
that event.
II'S xlxl:Si:slJLsx64 x 256 The "gate mput for mternal clock" TIN mode
1 JLS :s I :s 16.384 ms provides for durahon measurement of an exter-
To determme the count (c) until EOC for TI nal event. In thiS mode, the T] prescaler IS
With external clock mput, the equation driven by the 28 mternal clock, gated by a
High level on TIN. In other words, T] Will
c = p x v
count while TIN IS High and stop counhng
charactenzes the relahon between the T I while TIN IS Low. Interrupt request IRQ2 IS
prescaler (p) and the TI counter (v). The generated on the Hlgh-to-Low translhon on
dlvlde-by-8 on the mput frequency is bypassed TIN. Interrupt request IRQ5 IS generated on T]
m thiS mode. The count range IS EOC. ThiS mode may be used when the Width
X 1 :s c :s 64 x 256 of a Hlgh-gomg pulse needs to be measured.
In thiS mode, IRQ2 IS typically the mterrupt
I :s c :s 16,384 request of most Importance, smce It signals the
7.2 TOUT Modes. Port 3, bit 5 (P36) may be end of the pulse bemg measured. If IRQ5 IS
conhgured as an output (TOUT) whICh IS generated prior to IRQ2 m thiS mode, the
dynamically controlled by one of the followmg: pulse Width on TIN IS too large for T] to
measure m a smgle pass.
To The "nonretrlggerable mput" TIN mode pro-
TI Vides for automahc delay hmmg followmg an
Internal clock external event. In thiS mode, T] IS loaded and
When dnven by To or TI, TOUT IS reset to a clocked by the 28 mternal clock followmg the
logiC 1 when the corresondmg load bit IS set m hrst Hlgh-to-Low translhon on TIN after T] IS
timer control register TMR (%FI) and toggles enabled. TIN translhons that occur after thiS
on EOC from the correspondmg counter. pomt do not affect T]. In smgle-pass mode, the
1-46
7. Timer/ enable bIt IS reset on EOC; further TIN transl- ately; IRQ5 IS generated at every EOC untll
Counter hons wlll not cause T] to load and begm count- the software resets the enable bIt. ThlS TIN
Functions mg untll the software sets the enable blt agam. mode may provIde such funchons as watch-dog
(Contmued) In contmuous mode, EOC does not modIfy the hmer (e.g., mterrupt J! conveyor belt stopped
enable blt, but the counter IS reloaded and or clock pulse mIssed), or keyboard hme-out
countmg contmues Immedwtely; IRQ5 IS (e.g., mterrupt If no mput m x ms).
generated every EOC unhl software resets the
7.4 Examples. Several possIble uses of the
enable bIt. ThIS TIN mode may be used, for hmer/counters are gIven m the followmg four
example, to hme the lme feed delay followmg
examples.
end of lme detechon on a prmter or to delay
data samplmg for some length of hme follow- 74.1 TIme of Day Clock. The followmg
mg a sample strobe. module lliustrates the use of T] for
The "retnggerable mput" TIN mode wlll load mamtenance of a hme of day clock, whIch IS
and clock T] wIth the Z8 mternal clock on kept m bmary format m terms of hours,
every occurrence of a HIgh-to-Low transItIOn mmutes, seconds, and hundredths of a second.
on TIN. T] wdl hme-out and generate mterrupt It IS desIred that the clock be updated once
request IRQ5 when the programmed hme every hundredth of a second; therefore, T] IS
mterval (determmed by T] prescaler and load programmed m contmuous mode to mterrupt
regIster values) has elapsed smce the last lOa hmes a second. Although T] IS used for
Hlgh-to-Low transItIOn on TIN. In smgle-pass thIs example, To IS equally sUIted for the task.
mode, the enable bIt IS reset on EOC; further The procedure for Imhahzmg the hmer
TIN translhons wlll not cause T] to load and (TOD_INIT), the mterrupt servIce routme
begm countmg unhl the software sets the (TOD) whIch updates the clock, and the mter-
enable bIt agam. In contmuous mode, EOC rupt vector for T] end-of-count (lRQ_5) are
does not modJ!y the enable bIt, but the counter lliustrated below. XTAL = 7.3728 MHz IS
IS reloaded and countmg contmues Immedl- assumed.
Z8ASM 2.0
LOC OBJ CODE STMT SOURCE STATEMENT
1 TIMER1 MODULE
2 CONSTANT
3
4
HOUR -
MINUTE -
R12
R13
5 SECOND - R14
6
7
HUND - R15
$SECTION PROGRAM
8 GLOBAL
9 !IRQ5 interrupt vector!
10 $ABS 10
P 0000 OOOF' 11 IRQ_5 ARRAY [1 WORD] .- [TaD]
12
13 $REL
P OOOC 14 TaD INIT PROCEDURE
15 ENTRY
P 0000 E6 F3 93 16 LD PRE1,11%(2)10010011
17 !bit 2-7: prescaler = 36;
18 bit 1: internal clock;
19 bit 0: continuous mode!
P 0003 E6 F2 00 20 LD T1 ,110 ! (256) time-out =
21 1/100 second!
P 0006 46 F1 OC 22 OR TMR, 11%0 C !load, ena ble T1!
P 0009 8F 23 DI
P OOOA 46 FB 20 24 OR IMR,II%20 tenable T1 interrupt!
P OOOD 9F 25 EI
P OOOE AF 26 RET
P OOOF 27 END TOD_ INIT
28
P OOOF 29 TOD PROCEDURE
30 ENTRY
P OOOF 70 FD 31 PUSH RP
32 !Working register file %10 to %1F contains
33 the time of day clock!
P 0011 31 10 34 SRP 11%10
P 0013 FE 35 INC HUND !1 more .01 sec!
P 0014 A6 EF 64 36 CP HUND,1I100 ! full second yet?!
P 0017 EB 13 37 JR NE, TOD_EXIT !jump i f no!
P 0019 BO EF 38 CLR HUND
P 001B EE 39 INC SECOND !1 more second!
P 001C A6 EE 3C 40 CP SECOND,1I60 !full minute yet?!
P 001F EB OB 41 JR NE, TOD_EXIT !jump i f no!
1-47
7. Timer/ P 0021 BO EE 42 CLR SECOND
Counter P 0023 DE 43 INC MINUTE 11 more minute!
P 0024 A6 ED 3C 44 CP MINUTE, 1160 Ifull hour yet?1
Functions P 0027 EB 03 45 JR NE, TOD_EXIT !jump if nol
(Continued) P 0029 BO ED 46 CLR MINUTE
P 002B CE 47 INC HOUR
48 TOD_EXIT:
P 002C 50 FD 49 POP RP Irestore entry RP!
P 002E BF 50 IRET
P 002F 51 END TOD
52 END TIMER1
o ERRORS
ASSEMBLY COMPLETE
TOD_INIT: TaD:
7 instructIons 17 mstructIOn
15 bytes 32 bytes
16 p.s 19.5 p.s (average) including mterrupt response lIme
7.4.2 VarIable Frequency, VarIable Pulse Imhal loadmg of the T I counter regIster IS
Width Output. The followmg module followed by sethng the T I load bIt of hmer con-
Illustrates one possIble use of TOUT. Assume It trol regIster TMR (%Fl); thIS achon causes
IS necessary to generate a pulse tram WIth a TOUT to be reset to a logIc 1 output. Each
10% duty cycle, where the output IS repetihve- subsequent modlflcahon of the T I counter
ly hIgh for 1.6 ms and then low for 14.4 ms. To regIster does not affect the current TOUT level,
do thIS, TOUT IS controlled by end-of-count smce the T I load bit IS NOT altered by the
from II. although To could alternately be software. The new value IS loaded on EOC,
chosen. ThIS example makes use of the 28 and TOUT will toggle at that hme. The TI mter-
feature that allows a hmer's counter regIster to rupt servICe routme should SImply modIfy the
be modlhed WIthout dlsturbmg the count m TI counter regIster WIth the new value, alter-
progress. In contmuous mode, the new value IS natmg between the long and short mterval
loaded when TI reaches EOC. TI IS hrst values.
loaded and enabled WIth values to generate In the example whICh follows, bIt 0 of
the short mterval. The counter regIster IS then regIster %04 IS used as a software flag to mdl-
ImmedIately modIfied WIth the value to cate whICh value was loaded last. ThIS module
generate the long mterval; thIS value IS loaded Illustrates the procedure for TI/ToUT Imhahza-
mto the counter automahcally on TI EOC. The hon (PULSE_INIT), the T I mterrupt service
prescaler selected value must be the same for rouhne (PULSE), and the mterrupt vector for
both long and short mtervals. Note that the TI EOC (lRQ_5). XTAL = 8 MHz IS assumed.
Z8ASM 2.0
LOC OBJ CODE STMT SOURCE STATEMENT
1 TIMER2 MODULE
2 $SECTION PROGRAM
3 GLOBAL
4 !IRQ5 interrupt vectorl
5 $ABS 10
P 0000 0017' 6 ARRAY [1 WORD) [PULSE)
7
8 $REL
P 'oooc 9 PULSE_INIT PROCEDURE
10 ENTRY
P 0000 E6 F3 03 11 LD PRE1,1I~(2)00000011
12 Ibit 2-7: prescaler = 64;
13 bit 1: internal clock;
14 bit 0: continuous model
P 0003 E6 F7 00 15 LD P3M,1I00 Ibit 5: let P36 be Tout I
P 0006 E6 F2 19 16 LD Tl,1I25 Ifor short intervall
P 0009 8F 17 DI
P OOOA 46 FB 20 18 OR IMR,II~(2)00100000 lenable Tl interruptI
P OOOD E6 Fl 8C 19 LD TMR,II~(2)10001100
20 Ibit 6-7: Tout controlled
21 by Tl;
22 bit 3: enable Tl;
23 bit 2: load Tl I
24 ISet long interval counter, to be loaded on T1 EOCI
P 0010 E6 F2 El 25 LD T1,1I225
26 IClear alternating flag for PULSEI
1-48
7. Timerl P 0013 BO 04 27 CLR ~04 1= 0 25 next;
Counter 28 1 225 next
Functions P 0015 9F 29 EI
P 0016 AF 30 RET
(Contmued) P 0017 31 END PULSE_ INIT
32
33
P 0017 34 PULSE PROCEDURE
35 ENTRY
P 0017 E6 F2 E1 36 LD T1,IJ225 Inew load valuel
P 001A B6 04 01 37 XOR %04,01 Iwhich value next?1
P 001D 6B 03 38 JR Z, PULSE_EXIT 1shoul d be 225!
P 001F E6 F2 19 39 LD T1,II25 Ishould be 251
40 PULSE_ EXIT:
P 0022 BF 41 IRET
P 0023 42 END PULSE
43 END TIMER2
o ERRORS
ASSEMBLY COMPLETE
PULSE_INIT: PULSE:
10 InstructIOns 5 InstructIOns
23 bytes 12 bytes
23 ps 25 ps (average) Including Interrupt response tIme
7.4.3 Cascaded Tlmer/Counters. For some Tj to funchon as a smgle umt. TOUT. program-
apphcahons It may be necessary to measure a med to toggle on To end-of-count, should be
greater hme mterval than a smgle hmer/ wIred back to TIN, whIch IS selected as the
counter can measure (16.384 ms). In thIS case, external clock mput for Tj. WIth To program-
TIN and TOUT may be used to cascade To and med for contmuous mode, TOUT (and therefore
TIN) goes through a Hlgh-to-Low transihon
XTAL
(causmg Tj to count) on every other To EOC.
Interrupt request IRQ5 IS generated when the
programmed hme mterval has elapsed. Inter-
rupt requests IRQ2 (generated on every TIN
Hlgh-to-Low translhon) and IRQ4 (generated
on To EOC) are of no IInportance m this
apphcahon and are therefore dIsabled.
To determme the hme mterval (I) unhl EOC,
the equahon
I=t x pO x vO x (2 x pI x vI-I)
charactenzes the relahon between the To
prescaler (pO) and counter (vO)' the Tj
prescaler (pI) and counter (vI), and the clock
TO INTERRUPT LOGIC (IRQ4)
mput penod (t); tIS defmed m Sechon 7.1.
Assummg XT AL = 8 MHz, the measurable
hme mterval range IS
I JJ.S x I x I x (2 x I - I) ~ I ~
I JJ.S x 64 x 256 x (2 x 64 x 256 -I)
I JJ.S ~ I ~ 536.854528 s
FIgure 3 lllustrates the mterconnection
between To and Tj. The followmg module
lllustrates the procedure required to Imhahze
TO INTERRUPT LOGIC (lRQS)
the hmers for a 1.998 second delay mterval:
2009-1105
1-49
7. Timer/ Z8ASM 2.0
Counter LOC OBJ CODE STMT SOURCE STATEMENT
Functions 1 TIMER3 MODULE
(Conhnued) 2 GLOBAL
P 0000 3 TIMER_16 PROCEDURE
4 ENTRY
P 0000 E6 F3 28 5 LD PRE1,U%(2)00101000
6 !bit 2-7: prescaler = 10;
7 bit 1: external clock;
8 bit 0: single-pass model
P 0003 E6 F7 00 9 LD P3M,UOO Ibit 5: let P36 be Tout!
P 0006 E6 F2 64 10 LD Tl,11100 !Tl counter registerl
P 0009 E6 F5 29 11 LD PREO,U%(2)00101001
12 Ibit 2-7: pres caler = 10 ;
13 bit 0: continuous mode!
P OOOC E6 F4 64 14 LD TO,11100 !TO counter register!
P OOOF 8F 15 DI
P 0010 56 FB 2B 16 AND IMR,U%(2)00101011 !disable IRQ2 (Tin);
17 and IRQ4 (TO) !
P 0013 46 FB 20 18 OR IMR,U%(2)00100000 I enable IRQ5 (Tl) !
P 0016 9F 19 EI
P 0017 E6 Fl 4F 20 LD TMR,U%(2)01001111
21 !bit 6-7: Tout controlled
22 by TO;
23 bit 4-5: Tin mode is ext.
24 clock input;
25 bit 3 : enable Tl;
26 bit 2: load Tl;
27 bit 1: enable TO;
28 bit 0: load TO !
P 001A AF 29 RET
P 001 B 30 END TIMER_16
31 END TIMER3
o ERRORS
ASSEMBLY COMPLETE
11 mstructIOns
27 bytes
26.5 JAS
7.4.4 Clock MonItor. Tj and TIN may be used The follOWing module Illustrates the pro-
to mom tor a clock lme (m a dIskette dnve, for cedure for mlhahzlng T) and TIN
example) and generate an mterrupt request (MONITOR_INIT) to momtor a clock wIth a
when a clock pulse IS mIssed. To accomplish perIOd of 2 p.s. XTAL = 8 MHz IS assumed.
thIs, the clock lme to be momtored IS wIred to Note that thIS example selects single-pass
P3j (TIN). TIN should be programmed as a rather than continuous mode for Tj. ThIS IS to
retnggerable mput to Tj, such that each fall- prevent a conhnuous stream of IRQ5 Interrupt
Ing edge on TIN wJll cause Tj to reload and requests In the event that the momtored clock
contmue counhng. If T j IS programmed to falls completely. Rather, the Interrupt serVICe
hme-out after an Interval of one-and-a-half routme (CLK_ERR) IS left wIth the chOIce of
hmes the clock penod being momtored, Tj whether or not to re-enable the momtormg.
WIll hme-out and generate Interrupt request Also shown IS the Tj mterrupt vector (IRQ_5).
IRQ5 only If a clock pulse IS mIssed.
Z8ASM 2.0
LOC OBJ CODE STMT SOURCE STATEMENT
1 TIMER4 MODULE
2 $SECTION PROGRAM
3 GLOBAL
4 !IRQ5 interrupt vectorl
5 $ABS 10
P 0000 0015' 6
7
IRQ_5 ARRAY [1 WORD] .- [CLK_ERR]
8 $REL
P OOOC 9 MONITOR_ INIT PROCEDURE
10 ENTRY
P 0000 E6 F3 04 11 LD PREl ,11%( 2)000001 00
12 !bit 2-7: prescaler = 1;
13 bit 1: external clock;
14 bit 0: single-pass mode!
P 0003 E6 F7 00 15 LD P3M,UOO !bit 5: let P36 be Tout I
P 0006 E6 F2 03 16 LD Tl,113 ITl load register,
17 = 1.5 * 2 usec I
1-50
7. Timer/ P 0009 8F 18 DI
Counter P OOOA 56 FB 3B 19 AND IMR,II%(2)00111011 I disable IRQ2 (Tin) I
P OOOD 46 FB 20 20 OR IMR,II%(2)00100000 lenable IRQ5 (T1) I
Functions P 0010 9F 21 EI
(Contmued) 22
P 0011 E6 F1 38 23 LD TMR,II%(2)00111000
24 !bit 4-5: Tin mode is
25 retrig. input;
26 bit 3: enable T1 I
P 0014 AF 27 RET
P 0015 28 END MONITOR_ INIT
29
30
P 0015 31 CLK ERR PROCEDURE
32 ENTRY
33 ! ... ! Ihandle the missed clock!
34
35 !if clock monitoring should continue . !
P 0015 46 F1 08 36 OR TMR,III(2)00001000
37 Ibit 3: enable T1
P 0018 BF 38 IRET
P 0019 39 END CLK_ERR
40 END TIMER4
a ERRORS
ASSEMBLY COMPLETE
MONITOR_INIT: eLK_ERR:
9 instructIOns 2 + InstrucflOns
21 bytes 4 + bytes
21.5 p.s 18.5 + p.s including Interrupt response tlms
r
panty IS enabled, the eIghth bIt (D7) IS
!RQ3 replaced by the odd-panty bIt when trans-
Interrupt P3 j IRQ2 mItted and a panty-error flag (= I 11 error)
Request 30 !RQO
P32
when receIved. Table 5 Illustrates the state of
P33 IRQI
the panty bIt/panty error flag durmg senal
Counter/ { P3j TIN 110 WIth panty enabled.
TImer P36 TOUT Although the Z8 dIrectly supports either odd
panty or no panty for senal I/O operatIOn,
Data Memory
Select { P34 DM even panty may also be prOVIded WIth addl-
Status Out honal software support. To receIve and
{ P30 SerIal In transmIt WIth even panty, the Z8 should be
SenalllO
P3 7 SenalOut conhgured for senal I/O WIth odd panty
Table 4. Port 3 Special Functions dISabled. The Z8 software must calculate panty
I-51
8. I/O Character Loaded Transmitted To Received From Character
Functions Into SIO Serial Line Serial Line Translerred To SIO Note*
(Contmued) 11000011 01000011 01UUOOII 01000011 no error
11000011 0100001 I 01000111 11000111 error
Table 5. Serial 1/0 With Odd Parity Ldt most bll 1S l)'j
and modify the eighth bit pnor to the load of a sahshed by To counter 2 and prescaler = 3.
character mto SIO and then modlfy a panty The followmg code sequence will configure the
error flag followmg the load of a character To counter and To prescaler registers:
from SIO. All other processmg reqUlred for LD To,#2 !To counter = 2!
senal 1/0 (e.g. buller management, error LD PREO,#%(2)00001101
handlmg, etc.) IS the same as that for odd !blt 2-7: prescaler = 3; bit 0:
panty operahons. contmuous mode!
To conhgure the 28 for Senal I/O, It IS
necessary to: Interrupt request 3 (lRQ3) is generated
whenever a character IS transferred into the
Enable P30 and P37 for senal I/O and select receive buffer; mterrupt request 4 (lRQ4) is
panty,
generated whenever a character IS transferred
Set up To for the deSired bit rate, out of the transmit buffer. Before acceptmg
Conhgure IRQ3 and IRQ4 for polled or such mterrupt requests, the Interrupt Mask,
automahc mterrupt mode, Request, and Pnonty Registers (lMR, IRQ, and
IPR) must be programmed to configure the
Load and enable To. mode of mterrupt response. The sechon on
To enable P30 and P37 for senal I/O, bit 6 of Interrupt Processing prOVides a discusslOn of
P3M (R247) IS set. To enable odd panty, bit 7 mterrupt configurations.
of P3M IS set; to dlSable It, the bit IS reset. For To load and enable To, set bits 0 and 1 of
example, the mstruchon the timer mode register (TMR) via an mstruc-
LD P3M,#%40 hon such as
wlll enable senal I/O, but disable panty. The OR TMR,#%03
mstruchon ThiS will cause the To prescaler and counter
LD P3M,#%CO registers (PREO and To) to be transferred to the
To prescaler and counter. In addlhon, To IS
wlll enable senal I/O, and enable odd panty. enabled to count, and serial 1/0 operations
In the followmg dlscusslOns, bit rate refers to will commence.
all transmitted bitS, mcludmg start, stop, and Characters to be output to the serial lme
panty (If enabled). The senal bit rate IS given
should be wntten to senal I/O register SIO
by the equahon: (%FO). IRQ4 Will be generated when all bits
mput clock frequency have been transferred out.
bIt rate =
(2 x 4 x TO prescaler x TO counter x 16) Characters input from the senal line may be
The final dlvide-by-16 IS incurred for senal read from SIO. IRQ3 will be generated when a
communicahons, smce m thiS mode To runs at full character has been transferred into SIO.
16 hmes the bit rate in order to synchromze The followmg module illustrates the rec81pt
the data stream. To conhgure the 28 for a of a character and its Immediate echo back to
specifiC bit rate, appropriate values must first the serial lme. It IS assumed that the 28 has
be selected for To prescaler and To counter by been conhgured for serial 1/0 as descnbed
the above equation; these values are then pro- above, with IRQ3 (receive) enabled to mterrupt,
grammed into registers TO (%F4) and PREO and IRQ4 (transmit) configured to be polled.
(%F5) respectively. Note that PREO also con- The received character is stored m a Circular
trols the continuous vs. smgle-pass mode for buffer in register memory from address %42 to
To; continuous mode should be selected for %5F. Register %41 contains the address of
serial 1/0. For example, given an input clock the next available buffer pOSlhon and should
frequency of 7.3728 MHz and a selected bit have been imhalized by some earlier routine
rate of 9600 bits per second, the equahon is to #%42.
1-52
8. 110 Z8ASM 2.0
Functions LOC OBJ CODE STMT SOURCE STATEMENT
(Conhnued) 1 SERIAL_IO MODULE
2 CONSTANT
3 next_addr %41
4 start %42
5 length ._ %1E
6 $SECTION PROGRAM
7 GLOBAL
8 !IRQ3 vector!
9 $ABS 6
P 0006 0000' 10 ARRAY [1 WORD] ._ [GET_CHARACTER]
11
12 $REL o
P 0000 13 GET CHARACTER PROCEDURE ENTRY
14
15 !Serial 1/0 receive interrupt service!
16 !Echo recelved character and wait for
17 echo completion!
P 0000 E4 FO FO 18 ld SIO,SIO !echo!
19
20 !save it ln circular buffer!
P 0003 F5 FO 41 21 ld @next_addr,SIO !save In buffer!
P 0006 20 41 22 inc next_addr !point to next position!
P 0008 A6 41 60 23 cp next_addr,#start+length
24 !wrap-around yet?!
P OOOB EB 03 25 jr ne,echo_wait !no.!
P OOOD E6 41 42 26 ld next_addr,#start !yes. point to start!
27 !now, wait for echo complete!
28 echo_wait:
P 0010 66 FA 10 29 tcm IRQ,#%10 !transmitted yet?!
P 0013 EB FB 30 jr nZ,echo_wait !not yet!
31
P 0015 56 FA EF 32 and IRQ,II%EF !clear IRQ4!
P 0018 BF 33 IRET !return from interrupt!
P 0019 34 END GET_CHARACTER
35 END SERIAL_IO
o ERRORS
ASSEMBLY COMPLETE
10 mstructJOns
25 bytes
35.5 p.s + 5.5 p.s for each addltJOnal pass through the echo_wad loop,
mcludmg Interrupt response tIme
8.2 Automatic Bit Rate Detection. In a typical Ulshmg between the bit rates shown m Table 6
system, where serial commumcahon IS and assumes an input clock frequency of
reqUIred (e.g. system wIth a terminal), the 7.3728 MHz, a To pres caler of 3, and senal I/O
desIred bIt rate IS eIther user-selectable vIa a enabled wIth panty dIsabled. This example
sWItch bank or nonvanable and "hard-coded" reqUIres that a character wIth Its low order
m the software. As an alternate method of blt- bIt = I (such as a carnage return) be sent to
rate detectIOn, It IS possIble to automahcally the senal channel. The start bIt of thIs
determine the bIt rate of senal data receIved character can be measured by countmg the
by measurmg the length of a start bit. The number of zero bits collected before the low
advantage of thIs method IS that It places no order I bIt. The number of zero bIts actually
reqUIrements on the hardware design for this collected into data bIts by the senal channel IS
funchon and provIdes a convement (automallc) less than n (as gIven m the above equallon),
operator interface. due to the detechon of start and stop bIts.
In the techmque descnbed here, the serial Figure 4 illustrates the colle chon (at 19,200
channel of the 28 is mitialized to expect a bIt
rate of 19,200 bits per second. The number of
bits (n) received through Port pin P30 for each
bit transmitted is expressed by
n = 19,200/b
I..< - - - - 1 BIT TIME AT 1,200 BITS PER SECOND---__ I
where b = transmIssion bit rate. For example, 5T '" STAAT BIT SP = STOP BIT On = DATA BIT n
if the transmISSIOn bit rate were 1200 bIts per EACH INTERVAL SHOWN", 1 BIT TIME
second, each incoming bIt would appear to the AT 19,200 BITS PER SECOND
2009-1106
I-53
8.110 Number of Bits Received Number of 0 Bits Collected
Functions Bit Rate Per Bit Transmitted as Data Bits TO Counter
(Conhnued) dec binary dec binary
19200 I 0 00000000 I 00000001
9600 2 I 00000001 2 00000010
4800 4 3 00000011 4 00000100
2400 8 7 00000111 8 00001000
1200 16 13 00001101 16 00010000
600 32 25 00011001 32 00100000
300 64 49 00110001 64 01000000
150 128 97 01100001 128 10000000
bits per second) of a zero bit transmitted to the character has been received, thus "flushing"
Z8 at 1,200 bits per second. Notice that only 13 the serial line. This can be accomplished
of the 16 zero bits received are collected as eIther vIa a software loop, or by programming
data bIts. T I to generate an interrupt request after
Once the number of zero bits In the start bit the appropriate amount of time has elapsed.
has been collected and counted, it remains to Since a character is composed of eight bits
translate thIs count into the appropriate TO plus a mimmum of one stop bit following the
counter value and program that value Into To start bIt, the length of time to delay may be
(%F4). The patterns shown in the two binary expressed as
columns of Table 6 are utihzed in the (9 x n)/b
algorithm for this translation.
As a final step, if incoming data is to com- where nand b are as defined above. The
mence immediately, it is advisable to wait until followmg module illustrates a sample program
the remainder of the current "elongated" for automatic bit rate detection.
Z8ASM 2.0
LOC OBJ CODE STMT SOURCE STATEMENT
1 bit_rate MODULE
2 EXTERNAL
3 DELAY PROCEDURE
4 GLOBAL
P 0000 5 main PROCEDURE
6 ENTRY
P 0000 8F 7 di !disable interrupts!
P 0001 56 FB 77 8 and IMR,II%77 !IRQ3 polled mode!
P 0004 56 FA F7 9 and IRQ,II%F7 !clear IRQ3!
P 0007 E6 F7 40 10 ld P3M,II%40 !enable serial I/O!
P OCOA E6 F4 01 11 ld TO,1I1
P OOOD E6 F5 OD 12 ld PREO,II(3 SHL 2)+1 !bit rate = 19,200;
13 continuous count mode!
P 0010 BO EO 14 clr RO ! init. zero byte counter!
P 0012 E6 F1 03 15 ld TMR,113 !load and enable TO!
16
17 ! colI ect input bytes by counting the number of null
18 characters received. Stop when non-zero byte received!
19 collect:
p 0015 76 FA 08 20 TM IRQ ,11%08 !character received?!
p 0018 6B FB 21 jr z,collect !not yet!
p 001 A 18 FO 22 ld R1 ,SID !get the character!
P 001C 56 FA F7 23 and IRQ,II%F7 !clear interrupt request!
p 001F 1E 24 inc R1 !compare to 0 ... !
P 0020 1A 05 25 djnz R1,bitloop ! (in 3 bytes of code)!
p 0022 06 EO 08 26 add RO,1I8 !update count of 0 bits!
P 0025 8B EE 27 jr collect
28 bitloop: !add in zero bits from low
29 end of 1st non-zero byte!
p 0027 EO E1 30 RR R1
P 0029 7B 03 31 jr c,count_done
P 002B OE 32 inc RO
P 002C 8B F9 33 jr bitloop
34
35 !RO has number of zero bits collected!
36 !translate RO to the appropriate TO counter value!
37 count_done: ! RO has count of zero bits!
p 002E 1C 07 38 ld R1 ,117
p 0030 2C 80 39 ld R2,II%80 !R2 will have TO counter value I
p 0032 90 EO 40 RL RO
41
P 0034 90 EO 42 loop: RL RO
1-54
- -
30 InstructIOns
68 bytes
ExecutIon tIme IS varIable based on transIDlSSlOn bIt rate.
8.3 Port Handshake. Each of Ports 0, 1 and 2 CLR P2M !Port 2 mode register: all Port
may be programmed to function under input or 2 bits are outputs!
output handshake control. Table 7 defines the OR %03,#%40
port bits used for the handshakmg and the !set DAV2: data not available!
mode bit settmgs required to select handshak- LD P3M,#%20
mg. To input data under handshake control, !Port 3 mode register: enable
the Z8 should read the mput port when the Port 2 handshake!
DAV input goes Low (signifying that data is LD %02,DATA
available from the attached device). To output !output hrst data byte; DAV2
data under handshake control, the 28 should will be cleared by the 28 to
write the output port when the RDY mput goes mdlCate data avaJlable to
Low (signifying that the previously output data the peripheral device!
has been accepted by the attached device). Note that followmg the imtia!Jzalion of the out-
Interrupt requests IROO, IROI. and IR02 are put sequence, the software outputs the first
generated by the fallmg edge of the handshake data byte without regard to the state of the
signal mput to the 28 for Port 0, Port 1, and RDY2 mput; the 28 will automatically hold
Port 2 respectively. Port handshake operations DAV2 High until the RDY2 input is High. The
may therefore be processed under interrupt penpheral device should force the Z8 RDY2
control. input line Low after It has latched the data in
Consider a system that requires commumca- response to a Low on DAV2. The Low on RDY2
lion of eight parallel bits of data under hand- wJll cause the 28 to automahcally force DAV2
shake control from the 28 to a peripheral High unhl the next byte IS output. Subsequent
deVICe and that Port 2 IS selected as the output bytes should be output in response to interrupt
port. The following assembly code Illustrates request IR02 (caused by the Hlgh-to-Low tran-
the proper sequence for imlializmg Port 2 for sllion on RDY2) m either a polled or an
output handshake. enabled mterrupt mode.
{ set b,t 6 & reset b,t 7 of set b,t 3 & reset b,t 4 of set b,t 7 of P2M
To selec! Input handshake: POIM (program h,gh POIM (program byte as (program hIgh b,t as Input)
rubble as Input) Input)
{reset b,ts 6, 7 of POIM reset b,ts 3, 4 of POIM reset b,t 7 of P2M
To select output handshake: (program hIgh rubble as (program byte as output) (program hIgh b,t as output)
output)
To enable handshake. { set b,t 5 of Port 3 (P35); set b,t 4 of Port 3 (P34)' set b,t 6 of Port 3 (P36);
set b,t 2 of P3M set b,ts 3, 4 of P3M set b,t 5 of P3M
1-55
SECTIOR Arithmetic Routines cessed one nibble at a hme from left to right,
This sechon gives examples of the arithmehc begmnmg with the high-order nibble of the
9 and rotate mstructlons for use m multiplica- lower memory address. %30 IS added to each
tion, divIsion, conversion, and BCD arithmehc nibble If It IS m the range 0 to 9; otherwise
algorithms. %37 IS added. In this way, %0 IS converted to
9.1 Binary to Hex ASCII. The followmg %30, %1 to %31, ... %A to %41, ... %F to
module illustrates the use of the ADD and %46. Figure 5 Illustrates the conversIOn of RRO
S'N AP arithmehc mstruchons m the conversion (contents = %F2BE) to ItS hex ASCII
of a 16-bit bmary number to ItS hexadeCImal eqUivalent; the deshnahon buffer IS pomted to
ASCII representahon. The 16-blt number IS by RR4.
viewed as a strmg of four nibbles and IS pro-
BIT 0, 4 , Do 0, .3 Do
I 1'. I I I I If I
REGISTER
". "'
0, ., Do 0, 3 Do 0, .3 Do 0, 3 Do
"R4 - I (I 11 I I I I I I I I I I
Figure 5. Conversion 01 (BRO) 10 Hex ASen
Z8ASM 2.99 INTERNAL RELEASE
LOC OBJ CODE STMT SOURCE STATEMENT
1 ARITH MODULE
2 GLOBAL
P 0000 3 BINASC PROCEDURE
4 !*****************************************************
5 Purpose To convert a 16-blt binary
6 number to Hex ASCII
7
8 Input RRO 16-blt binary number.
9 RR4 = pOinter to destination
10 buffer in external memory.
11
12 Output Resulting ASCII string (4 bytes)
13 in desLination buffer.
14 RR4 incremented by 4
15 RO,R2,R6 destroyed.
16 *****************************************************!
17 ENTRY
18
P 0000 6c 04 19 Id R6,#%04 lnibble count!
P 0002 FO EO 20 again: SWAP RO !look at next nibble!
P 0004 28 EO 21 ld R2, RO
P 0006 56 E2 OF 22 and R2,#IOF !isolate 4 bits!
23 !convert to ASCII : R2 + #%30 if RO in range 0 to
24 else R2 + #%37 (in range OA to OF)
25
P 0009 06 E2 30 26 ADD R2,11%30
P OOOC A6 E2 3A 27 cp R2,iI%3A
P OOOF 7B 03 28 Jr ult,sklP
P 0011 06 E2 07 29 ADD R2,11107
P 0014 92 24 30 skip: Ide @RR4, R2 !save ASCII In buffer!
P 0016 AO E4 31 incw RR4 !polnt to next
32 buffer position!
P 0018 A6 E6 03 33 cp R6,11%03 ! time for second byte?!
P 001B EB 02 34 Jr ne,same_byte !no. !
P 0010 08 E1 35 Id RO, R1 !2nd byte!
36 same_byte:
P 001F 6A E1 37 djnz R6,agaln
P 0021 AF 38 ret
P 0022 39 END BINASC
40 END ARITH
o errors
Assembly complete
15 instructIOns
34 bytes
120.5 ,.. (average)
20091107
1-56
9. Arithmetic 9.2 BCD Addition. The following module Illus- sIgnificant dIgIt In bIts 7-4. Bytes WIthin a
Routines trates the use of the add wIth carry (ADC) and BCD string are arranged In memory WIth the
(Conhnued) decImal adjust (DA) Instruchons for the addl- most sIgnificant dIgIts stored In the lowest
lion of two unsIgned BCD strings of equal memory locahon. FIgure 6 Illustrates the
length. WIthin a BCD string, each nibble representallon of 5970 III a 6-dlglt BCD string,
represents a deCImal dIgIt (0-9). Two such starling III regIster %33.
dIgIts are l--acked per byte wIth the most
BIT D, 3 Do D, .3 Do Dr .3 Do
REGISTER
I %33
I I I
%34
I I I
%36
I
Z8ASM 2.0
LOC OBJ CODE STMT SOURCE STATEMENT
1 ARITH MODULE
2 CONSTANT
3 BCD_SRC._ R1
4 BCD_DST: = RO
5 BCD_LEN: = R2
6 GLOBAL
P 0000 7 BCDADD PROCEDURE
8 !*****************************************************
9 Purpose = To add two packed BCD strings of
10 equal length.
11 dst <-- dst + src
12
13 Input RO pointer to dst BCD string.
14 R1 pOinter to src BCD string.
15 R2 byte count in BCD string
16 (digit count = (R2)*2 ).
17
18 Output BCD string pointed to by RO is
19 the sum.
20 Carry FLAG = 1 if overflow.
21 RO , R1 as on entry.
22 R2 = 0
23 *****************************************************1
24 ENTRY
25
P 0000 02 12 26 add BCD_SRC,BCD_LEN Istart at least !
P 0002 02 02 27 add BCD_DST,BCD_LEN !significant digits!
P 0004 CF 28 rcf !carry = O!
29 add_again:
P 0005 00 E1 30 dec !point to next two
31 src digits!
P 0007 00 EO 32 dec !point to next two
33 dst digits!
P 0009 E3 31 34 ld R3,@BCD_SRC !get src digitsl
P OOOB 13 30 35 ADC R3,@BCD_DST !add dst digits!
P OOOD 40 E3 36 DA R3 !decimal adjust!
P OOOF F3 03 37 ld @BCD_DST,R3 !move to dst I
P 0011 2A F2 38 djnz BCD_LEN, add_again !loop for next
39 digitsl
P 0013 AF 40 ret ! all done I
41
P 0014 42 END BCDADD
43 END ARITH
o ERRORS
ASSEMBLY COMPLETE
11 mstructIOns
20 bytes
ExecutIOn tIme IS a functIOn at the number at bytes (n) m mput BCD strmg:
20 p.s + 12.5 (n - 1) p.s
2009-1108
1-57
9. Arithmetic 9.3 Multiply. The followmg module Illustrates to the high-order byte of the parlial product.
Routines an efficient algorithm for the mulliphcatlOn of As the high-order bits of the mulliphcand are
(Contmued) two unsigned 8-bit values, resultmg m a 16-blt vacated by the shift, the resultmg parlial-
product. The algorithm repelilively shifts the product bits are rotated m. Thus, the mulliph-
mulliphcand right (usmg RRC), with the low- cand and the low byte of the product occupy
order bit bemg shifted out (mto the carry flag). the same byte, whICh saves register space,
If a one IS shifted out, the mullipher IS added code, and execution lime.
9 Insfrucflons
16 bytes
92.5".. (average)
9.4 Divide. The followmg module Illustrates diVisor IS subtracted from the high byte of the
an effICient algorithm for the diVISion of a dividend. As the low-order bits of the dividend
16-bit unsigned value by an 8-bit unsigned are vacated by the shift left, the resultmg
value, resultmg m an 8-blt unsigned quolient. parlial-quotlent bits are rotated m. Thus, the
The algorithm repelihvely shifts the dividend quolient and the low byte of the dividend
left (via RLC). If the high-order bit shifted out occupy the same byte, whICh saves register
IS a one or If the resultmg high-order dividend space, code, and execulion lime.
byte IS greater than or equal to the diVISor, the
1-58
9. Arithmetic Z8ASM 2.0
Routines LOC OBJ CODE STMT SOURCE STATEMENT
(Conhnued) 1 ARITH MODULE
2 CONSTANT
3 COUNT RO
4 DIVISOR R1
5 DIVIDEND_HI R2
6 DIVIDEND_LO R3
7 GLOBAL
P 0000 8 DIVIDE PROCEDURE
9 1*****************************************************
10 Purpose To perform a 16-bit by 8-bit unsigned
11 binary division.
12
13 Input = R1 = 8-bit divisor
14 RR2 16-bit dividend
15
16 Output = R3 8-bit quotient
17 R2 8-bit remainder
18 Carry flag = 1 if overflow
19 = 0 if no overflow
20 *****************************************************!
21 ENTRY
P 0000 DC 08 22 ld COUNT,II8 ILOOP COUNTER!
23
24 !CHECK IF RESULT WILL FIT IN 8 BITSI
P 0002 A2 12 25 cp DIVISOR,DIVIDEND_HI
P 0004 BB 02 26 jr UGT,LOOP !CARRY o (FOR RLCll
27 IWON'T FIT. OVERFLOW!
P 0006 DF 28 SCF !CARRY 11
P 0007 AF 29 ret
30
31 LOOP: !RESULT WILL FIT. GO AHEAD WITH DIVISION!
P 0008
10 E3 32 RLC DIVIDEND_LO IDIVIDEND * 21
P OOOA
10 E2 33 RLC DIVIDEND_HI
P OOOC
7B 04 34 jr c,subt
P OOOE
A2 12 35 cp DIVISOR,DIVIDEND_HI
P 0010
BB 03 36 jr UGT,next ICARRY = 01
P 0012
22 21 37 subt: SUB DIVIDEND_HI, DIVISOR
P 0014
DF 38 SCF !TO BE SHIFTED INTO RESULTI
P 0015 OA F1 39 next: djnz COUNT,LOOP Ino flags affected I
40
41 !ALL DONE!
P 0017 10 E3 42 RLC
43 ICARRY 0: no overflow!
P 0019 AF 44 ret
P 001A 45 END DIVIDE
46 END ARITH
o ERRORS
ASSEMBLY COMPLETE
15 InstructJOns
26 bytes
124.5 p.s (average)
1-59
ZSOSBil Microprocessor Family 2
Microprocessor Basics: Part 16
The Z80 8-bit microprocessor combines all the Table 1. ZSO system components
processing power of the 8080 with 80 additional
instructions. And to keep chip count to a minimum, Part if Description Price" ..
100 qty
many of the peripheral circuits necessary for 8080
systems have been built into the Z80. All members Z80-CPU 8-bit CPU, 2.5 MHz .. $26.50
Z80-CTC founter/tlmer, 2.5 MHz .. $17.00
of the Z80 family are built with n-channel, silicon- ZBO-PIO Parallel 1/0, 2.5 MHz .. $11.00
gate, depletion-load technology; function at single- ZBO-D~,Il Direct memo access, 2.5 MHz .. $38.00
phase clock rates of 4 MHz; require just a 5-V supply; lBO-SIO Serial 110, 2.5 MHz .. N.A.
and have TTL-compatible inputs and outputs. Support boards unit qty
The circuit family consists of the Z80-CPU and the MeB Microcomputer board-kit $435.
following peripherals: a counter-timer circuit (CTC), -assembled $495.
MDC Memory/floppy-disc controller $795.
a parallel input/output circuit (PIO), a direct- RMB RAM memory board $750.
memory-access controller (DMA), and a serial 108 In&utloutput board $350.
input/output circuit (8IO), as well as a group of PMB P OM/ROM memory board $395.
PPBI
support boards (Table 1). All the circuits are available EPROM EPROM programmer (for 270B) $475.
in 2.5 or 4-MHz versions, ceramic packages, and PPBI
extended temperature ranges. All are housed in 40-pin PROM PROM programmer
DIPs, except the CTC, which comes in a 28-pin DIP. (for 7620, 7640) $475.
CPB!
All peripheral circuits can be daisy-chained for ROM ~~mbjnation programmer $575.
priority interrupt control. 8ince most peripheral VDB !Video-display board $475.
circuits necessary for system operation are built into * 4-MHz versions of these parts are available.
the Z80, a minimum system consists of the Z80, a ** a to 70-C ratings In plastiC packages
system clock, a power-on reset circuit and any memory
and peripheral circuits desired (Fig. 1). At the system
level, the ~P supports vectored priority-interrupt
structures without any extra hardware.
:;~;;!:ii
, ' '~"" ':',
" 1,O} DATA BUS
The wait input (WAIT) indicates to the I'P that the
addressed memory or liD device isn't ready for a data
transfer (the I'P will enter wait states for as long as
,':\Pl~fF;',?': 0
7
this line is Low). This line allows memory or peripher-
al of any speed to be synchronized with the Z80.
2.:"l~~t~~~ ~ajor buses on the Z80 ar~an
address bus. a
To reset the I'P or initialize it once it is on, the
RESET line can be pulled Low. When pulled Low, it
data bus and a control bus. The control bus can be split
Into three smaller buses-one for system control. one for forces the Z80's program counter to 0016, disables the
processor control and one for bus control. interrupt-enable flip-flop, sets register I to 16016, sets
register R to 0016, and sets the interrupt node to 0.
The last two lines are the interrupt-request (INT)
control (five lines), and I'P-bus control (two lines). One and nonmaskable-interrupt (NMI) inputs. When
bus-control line functions as a bus-request line pulled Low, the INT line interrupts the processor at
(BUSRQ), which is an input that requests not only the end of the current instruction if the software-
the I'P'S address and data buses, but also the memory- controlled interrupt-enable flip-flop (IFF) is enabled,
request, liD-request, read-data and write-data lines and if the BUSRQ line is High. Each time the I'P
of the system-control bus to go to a high-impedance accepts an interrupt, an acknowledge signal (IORQ
state so that other devices can use the bus. The other during an MI time) is sent out at the beginning of the
bus-control line, an output signal called bus-acknowl- next instruction cycle.
edge (BUSAK), goes high to indicate when the lines The NMI line is a negative-edge triggered input, has
go into a high-impedance third state. a higher priority than the INT line, and is recognized
All six system-control signals are outputs from the at the end of the current instruction regardless of the
I'P. An Mlline (machine cycle 1) goes Low to indicate IFF state. When triggered, it forces the Z80 to begin
when the I'P is in the op-code-fetch part of an execution at location 0066 16 after saving the current
instruction. The memory-request line (MREQ) goes contents of the program counter in an external stack.
Low when the address bus holds a valid address for
a memory-read or write operation. An liD-request line
(IORQ) goes Low to indicate that the lower byte of Interrupts and flags add flexibility
the address bus holds a valid liD-port address for an Three interrupt modes are available to the program-
liD-read or write operation. mer. Mode 0 permits the interrupting device to insert
Memory-read and memory-write lines (RD and WR) any instruction on the data bus and have the I'P
are also active when Low. RD indicates that the I'P execute it. Mode 1 has the I'P automatically execute
wants to read data from a memory or liD device, while a restart to location 0038 16-no external hardware is
WR indicates that the data bus holds data to be stored required (the contents of the program counter are
in the addressed location. When the sixth system- pushed onto the internal stack).
control line, a refresh signal (RFSH), goes Low, it Mode 2, the most powerful, permits an indirect call
2-3
3. By daisy-chaining the peripheral support circuits, any the highest priority Interrupt. Just 16 Ie packages are
number of peripheral chips can be added to this Z80-based needed to build this data-acquisition subsystem; and of
process-control system. The device closest to the ILP has the 16, nine are memories.
to any memory location. In this mode, the ILP forms operation is even, or is used to indicate overflow when
the indirect address from the upper byte of the I signed 2's complement arithmetic is performed.
register and eight bits that are supplied by the The two nontestable bits are Half-carry and Sub-
interrupting device. tract flags. The Half-carry flag is a BCD-carry or
Two identical8-bit flag registers (F and F') are part borrow result from the least-significant four bits of
of the Z80. Six of the bits in each register can be used the operation. (When a DAA instruction is used, this
as conditions for jump, call or return instructions; flag corrects the result of a previously packed decimal-
they are set or reset by various ILP operations. Both add or subtract operation.) The Subtract flag corrects
the F and F' registers have four testable flag bits and BCD operations by helping identify the previous
two nontestable bits. The four testable bits are the instruction; The correction differs for addition and
Carry flag, Zero flag, Negative-sign flag and subtraction.
Parity/overflow flag. Shifting operations can be performed on any reg-
The Carry flag contains carry from the highest- ister or memory location rather than just on the
order accumulator bit-add, subtract, shift and rotate accumulator. What's more, I/O operations can also
instructions can alter its state. If an operation loads be done with any register, rather than just the
a zero into the accumulator, the Zero flag gets set. accumulator. Sixteen-bit direct loads and stores can
Otherwise, it is reset. Used with signed numbers, the be sent to the BC-register pair, the DE pair or the
Negative-sign flag gets set if the result of an operation IX or IY registers-instead of just the HL as in the
is negative (bit 7 of the accumulator is the sign bit). 8080. Consequently, the number of exchange and
The dual-purpose Parity/overflow bit gets set when register-move operations is reduced considerably.
the parity of the result in the accumulator for a logic Also, 16-bit arithmetic operations using the HL pair
2-4
Z80 microprocessor architecture
Built into the Z80 microprocessor are all bus-
control, memory-control, and timing signals in addi-
tion to eight general-purpose I6-bit registers and an
arithmetic-and-logic unit (ALU). The Z80 is upward-
compatible with the Intel 8080A' and 8085 I'Ps.
All the 8080 registers are duplicated within the Z80
and, in addition to the eight 8-bit registers (A, F, B,
C, D, E, Hand L) of the 8080, there is an alternate
set (A', F/, B', C/, D', E/, H' and 1') and several other
special-purpose registers. The additional registers
include two I6-bit index registers (IX and IY), an 8-
bit interrupt-vector register (I) and an 8-bit memory-
refresh register (R). Also carried forward from the
8080 register set are the I6-bit stack pointer and the
I6-bit program counter (PC).
Normally, all instructions reference the main reg-
ister set, and alternate registers are accessed via two
exchange commands that swap register contents in
the banks. One command, exchanges the accumulator
and register flags, while another instruction, ex- register contents are loaded onto the low-order seven
changes the other six general-purpose registers. Since bits of the address bus, and a status line on the
both instructions are single-byte, minimum-execu- processor goes low to indicate the presence of a valid
tion-time instructions, a complete swap can be done refresh count. Because this entire process takes place
in four clock cycles (II's for a 4-MHz clock). These while the op code is decoded internally, it never
commands and registers are very handy for rapid interferes with any other I'P activity on the bus.
single-level interrupt handling. The I register forms the high-order eight bits of an
The Z80's two index registers have no direct cor- address. When an interrupt occurs and the Z80 is in
ollary in the 8080 architecture, but in operation they the vectored mode, the lower order eight bits are
resemble the single index register in the 6800 I'P" supplied by an interrupting peripheral. In response
Instructions using this mode such as the accumulator- to the interrupt, the I'P does an Indirect Call instruc-
load command [LD A, (IX + 7)) contain a single-byte tion with the composite address. All the support chips
offset field (+7, in this case). The effective address have corresponding registers that store the low-order
of the operand is the sum of the offset and the IX- eight bits and supply them to the Z80 when the
register contents. This addressing mode is particular- interrupt is acknowledged.
ly convenient for table references, multibyte entries Able to perform 12 basic operations-add, subtract,
or for passing a pointer to a group of subroutine AND, OR, Ex-OR, compare, test-bit, reset-bit, set-bit,
parameters. The offset byte is interpreted by the Z80 increment, decrement, and left or right-shift and
as a 2's complement number, so both positive and rotate (arithmetic or logic)-the ALU communicates
negative indexing is possible. with the registers and external-data bus by means of
A special feature of the Z80 is its ability to refresh a buffered internal bus. As each instruction is fetched
dynamic memory automatically. Its memory-refresh from memory, it is loaded into the instruction register
register acts as a 7-bit counter that is incremented and decoded by the control section, which supplies all
after every op-code fetch. After the fetch, the R- the control signals for the Z80's subsystems.
have been expanded over the 8080's to include add with instruction can be executed in a single cycle or repeat
carry and subtract with borrow. sequence. Decrementing the HL and DE addresses is
also possible.
By using the block move command, the ,uP can
Software gives the ZSO horsepower
transfer bytes of data at 5.25 ,us/byte (for a 4-MHz
Many of the instructions available only in the Z80 clock). Block operations are also available for memory
support the manipulation of multi byte blocks of data searches and I/O operations. And shift and rotate
-a great plus in data communications and text operations have been enhanced. For decimal
manipulation. For instance, a block-move instruction arithmetic, 4-bit shifts through the accumulator can
takes data from the memory location specified by the greatly speed up BCD multiplication and division, and
HL-register pair, deposits them in the location speci- bit-manipulation instructions permit fast access to
fied by the DE pair, increments the HL and DE any bit in either the external memory or an internal
registers and then decrements the BC pair, which is register.
assumed to hold a byte counter for the operation. This Other enhancements of the instruction set include
2-5
Mnemonic Description
Software capabilities of the zao 8 bit load instructions
M
external memory. Results are held in the accumulator, 16-bit load instructions
and appropriate flags are set. Bit-manipulation com- LD dd, nn Load registers dd With nn
mands allow any bit in the accumulator, any general- LD IX,nn Load register I X With nn
purpose register or any external memory location to LD IY, nn Load register IY with nn
LD HL, (nn) Load L With contents of location
be set, reset or tested with a single instruction. Jump, nn and H With (nn+1)
Call and Return instructions are used to transfer LD dd, (nn) Load registers dd with location nn
between various locations in the program. LD IX, (nn) Load IX With location nn
I/O instructions permit a wide range of transfers LD IY, (nn) Same but for I Y
between external memory locations or general- LD (nn), HL Load location nn With H L
purpose Z80 registers and external I/O devices. In LD (nn), dd Load locatIOn (nn) with register pair dd
either case, the port number is provided on the lower LD (nn), IX Same but for I X
LD (nn), IY Same but for I Y
eight bits of the address bus during any I/O operation.
LD SP, HL Load stack pOinter from H L
Also, the basic /iP-control commands include such LD SP, IX Load stack pOinter from I X
instructions as setting or resetting the interrupt- LD SP, IY Load stack pOinter from IY
enable flip-flop or setting the mode of interrupt PUSH qq Load register pair qq onto stack
response. PUSH IX Load I X onto stack
In addition to the seven addressing modes of the PUSH IY Load IY onto stack
8080-direct, register, register indirect, modified POP qq Load register pair qq with top of stack
page 0, extended, implied and immediate-the Z80 has POPIX Load IX with top of stack
three more addressing modes: relative, indexed, and POP IY Load IY With top of stack
bit addressing-that can be used. Exchange, transfer and search instructions
A special byte-call instruction lets the Z80 program EX DE, HL Exchange contents of DE & HL
proceed to any of eight locations in page 0 of the EX AF, A' F' Exchange contents of AF & A' F'
memory. This modified page 0 addressing allows a EXX Exchange all SIX general purpose registers
With alternates
single byte to specify a complete 16-bit address, which
EX (SP), HL Exchange stack pOinter contents With
saves memory space. H L contents
Relative addressing lets the Z80 use the byte follow- EX ISP), IX Same but use IX register
ing the op code to specify a displacement from the EX (SP), IY Same but use IY register
current program-counter value. The displacement LDI Load (HL) Into DE, Increment DE and
H L, decrement Be
value is in 2's-complement form, which permits up
LDIR Same but loop until (BC) = 0
to a + 127 or -128 byte displacement. Extended
LDD Load location (PE) With location (HU and
addressing includes two bytes of address in the decrement DE, HL and BC
instruction. LDDR Same but loop until (BC) = 0
Index registers can also be used as part of the CPI Compare contents of AC with (H L), set Z
address. In the indexed addressing mode, a byte of flat if =, increment HL and decrement
BC
data following the op code is a displacement value that CPIR Same but repeat until BC = 0
must be added to the specified index register (the op CP s Compare operand s with AC
code indicates which register) to form a memory CPD Same as CPI but decrement HL
pointer. Also available is an implied addressing mode CPDR Same as CPIR but decrement HL
in which the op code uses the contents of one Z80 8-bit arithmetic and logic instructions
register or more as the operands. The last addressing ADD A, r Add contents of r to AC
mode lets the Z80 access any memory location or liP ADD A, n Add byte n to AC
register and permits any bit to be set, reset or tested. ADD A, (H L) Add contents of H L to AC
2-6
ADD A, (lX+d) Add location (lX+d) to AC Jump, c all and return instructions
ADD A, (IY+d) Same but (lY+d) JP nn Unconditional jump to location nn
ADC A, s Add with carry operand s to AC JP cc, nn If condition cc True, do a JP nn
SUB s Subtract contents of r, n, HL, IX+d or otherWise conti nue
IY+d from AC JR e Unconditional jump to PC+e
SBC s Same but also subtract carry flag JR C:
e If C ~ a continue. If C ~ 1 do JR e
ANDs Logic AND of operand sand AC JR NC, e Reverse of JR c, e
ORs Same but OR with AC JR Z, e If Z ~ a continue. If Z ~ 1 do JR e
XOR s Same but EX-OR with AC JR NZ, e Reverse of JR Z, e
INC r Increment register r JP (HU Load PC from (HL)
INC (HU Increment location (H L) JP (IX) Load PC from (I X)
INC (lX+d) Same but use (lX+d) JP (IY) Load PC from (I Y)
INC (lY+d) Same but use (lY+d) DJNZ, e Decrement register B and Jump
DEC m Decrement operand m relative If 8 = 0
16~bit Arithmetic instructions CALL no Unconditional call subroutme at
location nn
ADD HL, ss Add register pair ss to HL CALLec, nn Call subroutine at location nn If
ADC HL, ss Same but Include carry flag condition cc IS True
SBC HL, ss From H L subtract contents of 5S and RET Return from subroutine
carry flag RET cc If cc false continue, otherWise do RET
ADD IX, pp Add register pa I r pp to I X RETI Return from Interrupt
ADD IY, rr Same but use rr and I Y RETN Return from nonmaskable Interrupt
INC ss Increment register pair S5 RST p Store PC In stack, load a In PC H
INC IX Increment I X register and restart vector In PC L
INC IY Same but I Y register
Input/output instructions
DEC ss Decrement register pair ss
IN A, n Load AC with Input from deVice n
DECIX Same but IX register
IN r, (C) Load r with Input from deVice C
DECIY Same but IV register
INI Store contents of location speCified by C
General purpose arithmetic & control instructions tn address speCified by H L, decrement
DAA DeCimal adjust accumulator Band tncrement H L
CPL Complement (AC) INIR Same but repeat until B = a
NEG Complement (AC) and add 1 IND Same as INI but decrement HL too
CCF Complement carry flag INDR Same as I N IR but decrement H L too
SCF Set carry flag ~ 1 OUT n, A Load output port (n) with AC
Nap No operation OUT (C), r Load output port (C) with register r
HALT Halt, walt for Interrupt or reset OUTI Load output port (C) with location (HU
DI and tncrement HL and decrement S
Disable Interrupts
EI Enable Interrupts OTIR Same but repeat until B = a
OUTD Same as OUTI but decrement H L
IMr,l Set IlP to interrupt mode r,l
IM1 Set p,P to Interrupt mode 1 OTDR Same as OTIR but decrement HL
1M2 Set pP to Interrupt mode 2
Rotate and shift instructions
RLCA Rotate AC left Notes
RLA Same but Include carry flag b represents a 3-blt code that indicates position of the bit to
RRCA Rotate AC right be modified
RRA Same but Include carry flag cc represents a 3-blt code that indicates which of eight condi-
RLC r Rotate regl ster r left tion codes are to be used
RLC (HU Rotate location (H LI left
d IS an a-bit offset value
RLC (IX+d) Same but location (IX+d)
RLC (lY+d) Same but locallon (IY+d) dd refers to register pairs BC, DC, HL or the stack pomter
RLm Same as any RLC but Include e represents a signed two's complement number between
carry flag -126and +129
RRCm Same as R LC but shift right m is an a-bit number
RR m Same as R L m but shift rrght
n IS an a-bit number
SLA s Shift left (any R LC regISter)
nn refers to two 8-blt bytes
SRA s Same but shift right and keep MSB
SRLs Same as SLA but shift right p represents one of eight restart vector locations on page f)
RLD Simultaneous 4-blt rotate from AC L to pp refers to register pairs BC, DE, the IX register or the stack
L, L to Hand H to AC L pointer.
RRD Simultaneous 4-bit rotate from AC L to qq refers to regISter pairs AF, BC, DE or HL
H, H to Land L to AC L
r or r' refers to registers A, S, C, 0, E, H or L or their
Bit set, reset and test instructions
alternates
BIT b, r Test bit b of register r
rr refers to register pairs BC, DE, the IV register or the stack
BIT b, (HL) Test bit b of location (H L)
pOinter
BITb, (lX+d) Test bit b of location (IX+d)
BITb, (IY+d) Test bit b of location (lY+d) s refers to either the r registers, the n data word or the con-
SET b, r Set bit bin register r to 1 tents of locations speCified by the contents of the H L,
SET b, (HU Same but use contents of location H L I X +d or I Y +d registers
SET b, (IX+d) Same but use contents of location IX+d S5 refers to register pairs SL., [IE. HL or the stack pOinter
SET b, (IY+d) Same but use contents of location IY+d
RES b, s Reset bit b of operand m
2-7
relieve the Z80 from doing timing loops, software
overhead is minimized. For the controller of Fig. 3,
14 ICs are needed-and nine of them are memories
(2048 bytes of ROM and 4096 bytes of RAM).
The Z80-PIO, a parallel-interface controller, has two
8-bit ports and provides TTL-compatible interfaces
(Fig. 4a). Port A has four possible modes of operation:
byte output, byte input, byte bidirectional bus and bit.
Port B has all the modes except byte bidirectional.
The port I/O logic consists of handshake control and
six registers (Fig. 4b): an 8-bit input register, an 8-
bit output register, a 2-bit mode-control register, an
8-bit mask register, an 8-bit I/O-select register and
a 2-bit mask-control register. The last three are used
only when the port is programmed to operate in the
bit mode. Of the 40 pins on the PIO, 24 are required
by the port and CPU buses, six more for ,uP interfac-
ing, three for interrupt control, four for handshaking
the I/O ports and three for power, ground and the
single-phase clock.
Four of the six internal registers are loaded by the
Z80 for characteristic programming. The contents of
the 2-bit mode-control register determine which of the
four PIO operating modes is to be used. Similarly, the
2-bit mask-control register specifies the active state
4. With two parallel, 8-bit I/O ports, the PIO CIrcUit (a) can (High or Low) of any peripheral-interface lines which
use either of the ports In a parallel system or on a line-by- are to be monitored. It also permits an interrupt to
line basis for 16 separate I/O lines. Inside each port, five be generated when all unmasked pins are active (AND
control registers are loaded by the Z80 before operation to condition) or when any unmasked pin is active (OR
initialize the port (b).
condition). The code loaded into the mask register
determines which peripheral-device interface pins are
the decimal-adjust command, which now works after to be monitored for the specified status condition. And
subtract as well as add operations. Negate-instruc- the code held in the I/O-select register determines
tions and looping commands are also part of the set. which pins are inputs or outputs during bit-mode
The looping instruction decrements the B register and operation. The other two registers hold incoming or
takes a relative branch if that register has not reached outgoing data.
zero. Other operations are shown in the box on Z80 To relieve some software overhead in timing situ-
software (see page 58). ations, the CTC provides four channels of program-
mable timing and counting functions that can be set
with software (Fig. 5). Each channel operates in either
Put the ZSO to work
a timer or counter mode, and programmable inter-
With the four basic Z80 peripheral circuits described rupts can occur on counter or timer states. Other
virtually any high-performance microcomputer can be features include a readable down counter, a selectable
constructed. For example, a process-control system 16 or 256 clock prescaler for each timer, a selectable
can be built around the Z80, as shown in Fig. 3. The positive or negative trigger for timer initiation and
peripherals handled by the Z80 controller include automatic reload of counter or timer constants. In
three parallel input/output circuits and one addition three channels have zero count/timeout out-
counter/timer. The PIOs handle a 16-key keyboard, puts capable of driving Darlington transistors.
a printer, a multichannel aid converter and 16 control Each channel has two registers, both eight bits long
lines. Because the peripheral chips can be daisy- and loaded by the ,uP. One register, the time-constant
chained, a priority interrupt structure can be formed register, loads the preset value into the down counter.
with little or no software or hardware overhead. Using The other, called a channel-control register, contains
the interrupt mode, the requesting PIO causes the ,uP the mode and condition information for channel opera-
to go to a service routine, and, after the routine, a tion. Also included in each channel are an 8-bit down
special instruction-return-from-interrupt-goes counter and an 8-bit prescaler. The counter is decre-
back to the PIO and allows the ,uP to service lower- mented by the prescaler in the timer mode and by
priority interrupts. the clock-trigger input in the counter mode.
All support chips have two lines for daisy-chaining Of the 28 pins on the CTC, eight connect to the data
-the Interrupt-enable-in (lEI) and Interrupt-enable- bus, seven to the control lines, three handle interrupt
out (lEO). Since a CTC is used in the controller to control and three are required for power, ground and
2-8
number of bytes has been transferred-without halt-
ing the transfer.
Inside the DMA controller are bus-interface circuits
for both the data and address buses, logic and registers
to control parameters of the circuit, and address and
byte-count circuitry to generate port addresses. There
are also provisions for incrementing or decrementing
the address, timing circuitry for adjusting the
read/write timing of both ports being addressed, and
compare logic that permits a byte-matching operation
(if a match is encountered, a flag is set in the DMA's
status register). Also built-in is the interrupt and
BU8RQ logic, which includes a control register that
specifies conditions for the chip to generate an inter-
rupt, all the priority-encoding logic to select between
generation of an INT or BU8RQ output, and an
interrupt-vector register for automatic vectoring to an
interrupt-service routine.
Of the 40 pins on the DMA controller, 24 are needed
for the address and data bus, and five are needed for
the liP control bus. Eight more handle the interrupt
control and timing, and three more are necessary for
power, ground and clock inputs.
For serial communications, the serial-input/output
circuit (810) provides two full duplex programmable
5. Each eTe provides four channels of counting/timing channels capable of handling asynchronous,
capability with an 8-bit counter on each channel (a). There synchronous, and synchronous-bit protocols (IBM
is a control register for each channel and a programmable Bisync, HDLC and SDLC). It can also generate cyclic-
8-bit prescaler (b).
redundancy check codes in any synchronous mode. The
810 has four independent serial ports-two for trans-
the single-phase clock. Three of the four input chan- mitting and two for receiving (Fig. 7). Asynchronous
nels have one input and one output line and the fourth data with 5, 6, 7 or 8 bits and 1, 1-% or 2-stop bits
channel has only an input line. as well as even, odd or no-parity generation or check-
ing can be handled.
The circuit has X 1, 16, 32 and 64 clock modes and
Speed up data transfer with DMA
data rates from 0 to 600 kHz. The transmitter sections
One of the interface circuits, a direct-memory- have eight modem-control lines, quadruple buffers on
access controller, is designed to effect the high-speed receiver data and error registers, and double buffers
transfer of a block of data between any two ports in on the transmitter sections. The bus-I/O control block
a Z80 system and can also be used with other J.LPs. includes the logic for selecting channels and registers,
The circuit is a programmable, single-channel device read/write control, and control of special timing for
that provides all address, timing and control signals interrupt-acknowledge cycles. Interrupt logic includes
for the data transfer (Fig. 6). Also, the DMA circuit the daisy-chain provision as well as two special 8-bit
can search a block of data for a particular, bit- control registers to handle the various interrupt op-
maskable byte, with or without transferring the data. tions, as well as an 8-bit vector register for interrupt
Capable of transfer-only, search-only or search-and- response.
transfer operations at up to 1.2 Mbyte/s, the circuit Three receive buffers allow enough time for inter-
can automatically increment or decrement the port rupt servicing of fast data rates. The receiver-shift
address from a programmed starting address. register is controlled by the receive-control logic,
Four communications modes are available on the which includes two 8-bit registers for receive-mode
chip-a byte-at-a-time mode that transfers one byte selection and options. There are two more 8-bit reg-
per request, a burst mode that lets the transfer isters for programmable-sync characters. The
continue as long as ports are ready, a continuous mode external-status register is an 8-bit, read-only register
that locks out the J.LP until the operation is completed, that indicates the state of the modem-control pins as
and a transparent mode that steals refresh cycles. well as several internal-status conditions. An internal-
When the circuit finds a match or finishes a transfer, status register also indicates the state of the 810. Each
it can be programmed to generate an interrupt. Or channel has its own receive, transmit and status-
a complete repeat cycle can be programmed for register banks.
automatic repeat or repeat on command. A built-in Now that you are familiar with all the basic system-
block counter can generate a signal when a certain building blocks, you can mold them with software into
2-9
a working system. Because of the Z80's rich instruc- are handled by a text editor and stored in a dual floppy-
tion set, assembling software programs by hand can disc file management system. Once filed, the program
be too complicated for most applications; you should is ready for testing and can be translated by an
use either a dedicated development system or time- assembler or compiler into code for the Z80. The code
sharing service. can be tested by a hardware/software debug package
that provides interrogation, control and tracing
Development systems speed software
capabilities.
In the monitor mode the system has four operating
The Z80 development systems and the software environments: file, edit, debug and assemble. The file
available from Zilog include several large dedicated capabilities are pretty standard types of features-
units that permit hardware or software development, storing records on disc, pulling records from disc,
or both (Table 2). Also available are assemblers, changing records and saving the new results. The
compilers and time-sharing services as well as Basic debug and assembler features of the development
and PLZ. (Cobol and Fortran will be available soon.) system offer some pretty powerful capabilities. With
All program statements in the development systems the debug commands, you can set up breakpoints,
compare blocks of memory and trace an operation.
In the debug mode, for instance, system trans-
actions can be loaded into a special memory as the
program executes in real time. And, once any user-
defined condition has occurred (such as the setting of
bit 6 of port 8B ls or reading from address 21C8 Is), the
program execution can be suspended and the system
can re-enter the monitor mode. A complete record of
the last 256 transactions just prior to program termi-
nation is in the system memory and available to the
user.
The main assembler in the development system
supports the following features: macros, conditional
assembly, the ability to assemble a large file and a
sorted-symbol table with cross reference. All these
options as well as the printing and listing options are
available by setting parameters at the time of as-
6. The dlrect-memory-access controller has three classes sembly. A relocatable assembler with I/O man-
of operation: transfer-only, search-only or search-and- agement provides relocatable code and has a linking
transfer. Any device on the system bus can be controlled loader. These permit you also to specify other files
by the OMA; internal counters keep track of source and that should be included within the current file being
destination addresses.
7. Two independent full-duplex serial I/O channels are operate In asynchronous or synchronous modes, includ-
built into the SIO. Either channel can be programmed to ing BiSync and HOLC/SOLC.
2-10
Table 2. Hardware and software support
Type Price Name Description
unit qty.
Systems $8990 Z8().hardware & 3 kb~es ROM. 1 kbyte RAM for system monitor;
software 16 k yte RAM; real-time debug module; dual
development floppy discs; in-circuit emulator; RS-232 or current
system loop interface; software and user's manuals; extra card
slots; 2 chassis system. Universal interface to printers, PROM
programmers. etc.
$6990 ZSO-software Same as above, except no in-circuit emulation capability.
development
system
$6990 ZaO-ha rdware Same as first system, except no universal interface.
development
system
$5990 ZSO-microcomputer Dual floppy disc system in Single chassis
system containln~ an~ combination of zao board
products MC , MDC, etc.)
Resident N.A. OSza()..rcerating As$embler: translates assembly language
software system or zao mnemonics into machine language. Includes
development macro's, conditional assembly, the ability
~stems and to assem.ble programs of virtually any length and sorted
CB family symbol tables with complete cross-reference listings.
Relocating a$Sembler and linking loader: Facility for linking
programs which have been assembled independently and executing
Editor environment: allows the user to input and modify texts.
such as, assembly language source programs.
File environment: controls and manipulates disc files that the
user creates while writing, debugging and executing
programs.
Debug environment: allows the user to load, test and save programs
using an assortment of debugging aids.
assembled so you can combine programs. with a syntactic and semantic style that blends Algol,
The text editor in the system includes many com- PL/I and Pascal. It permits access to the Z80 architec-
mands (for more than many full minicomputer edi- ture, can compile efficient code and is easy to translate
tors) to help you manipulate the source files. Although into machine code. Two levels are available: PLZ Level
it is a line editor (the pointer always indicates the I combines assembly language with statements neces-
beginning of a line), some string-oriented commands sary to create relocatable program modules; Level II
are available. Automatic paging permits you to edit is similar to a high-level systems language in which
files that are larger than available memory work single statements can substitute for sequences of
space. Put and Get commands help you copy sections assembly-language statements .
from one disc file to another or insert them into a
program. Over 20 commands in the editor permit text
repeats, alterations, storage, line-number printing
and macro capabilities.
To develop higher-level language programs, you can
use a Basic interpreter. This permits programs to be
written and debugged interactively. Also made for
resident use is PLZ, a procedure-oriented language
2-11
DESIGNING A MICROPROCESSOR
DRIVEN MULTIPURPOSE
PERIPHERAL CONTROLLER
Requirements for a revised generation of peripheral Clearly, a microprocessor is the way to package the
controllers became apparent while the ModComp requisite intelligence Cf'. a single board. This approach
CLASSIC computer series was still in the conceptual relieves the designer of complex hardware and/or
stage of design. System packaging was based on card custom microcode design; a microprocessor's firmware
edge pluggable wirewrapped boards for modularity is generally more maintainable than microcode fitted
and ease of maintenance. To devote a full board space to custom logic. Also, interfacing to future devices should
(approximately 550 integrated circuits) to a single be easier.
card reader or line printer controller seemed unreason
able; this configuration would waste space and entail
extra cost. The decision therefore was made to pack.
age several such low performance controllers on one General Architecture
board. Specifying that the design approach would be
toward a multiported controller adaptable to many Since a microprocessor based controller is extremely
different devices in mix/match configuration avoided slow in relation to a controller implemented with
the problem of choosing which controllers to coni oin. discrete logic, the designer must take into consideration
Also, the new controller had to operate with existing the microprocessor's response time. This response de
software and would therefore require some intelli ficiency can be concealed for the most part under
gence. For example, the existing card reader controller the overhead of the host's interrupt.driven input/out.
is fully buffered and can transfer data in a direct put (I/O) bus without slowing down the overall
12bit card image; in a transitional 8bit code called system. Several nearly instant system responses are
"half.AsclI," packed either one or two bytes per word; still required, however, such as the setting of control
or in any 8bit code downloaded by the host mini ler busy status for the addressed port in response to
computer, again packed' one or two bytes per word. a transferinitiate command. These responses are gen
It performs multipunch detection while translating to erated by hardware in the form of a programmed logic
8bit codes. Other controllers to be reimplemented array (PLA) to set status latches. A Z80A microproces
are similarly sophisticated. sor computes all other status which are stored as 16
MULTIFUNCTION CONTROLLER
r----------------
,
,,
I
IL _____________________________________________ ~
I
Fig 1 Controller block diagram. Layout exhibits straightforward bus architecture. Distinguishing feature is address-
ing scheme conSisting of displacement register (DREG) and peripheral-select PLA. This hardware makes possible
firmware-transparent bank switching
2-14
Mi(!roprocessor Clock Periods Time in port 0, a line printer in port 1, and an asynchronous
8080A-2 167 at 320 ns 53.4 J.'S channel in ports 2 and 3. Packaging requirements
Z80A 92 at 250 ns 23.0 J.'S specified a total of 80 signal pins for all four ports.
9900 114 at 300 ns 34.2 J.'S This constraint, together with an analysis of all the
68BOO 58 at 500 n. 29.0 J.'S parallel devices, led to a 20-bit port configured as eight
Calculations based upon these short routines indi- bidirectional bits for data transfer, four bidirectional
cated that of the machines coded for, only the l80A bits for status or control (handshaking, etc), seven
would be adequate_ All further design was tailored ex- input bits for status or control, and one output bit
plicitly for the l80A; no detailed hardware or firm- for control (Fig 2) .
ware design was produced for the other machines. Of the seven input bits, two can be programmed
(These values were attained by a designer most ,online for signal inversion, and one of these two can
familiar with the l80. Greater familiarity with other be connected to either a pullup or pulldown resistor
microprocessors might lessen the disparity in perfor- for device power sensing. The two groups of bidirec-
mance, but the l80's powerful instruction set, vectored tional bits, including control of their buffers, can be
interrupt scheme, and twin register sets made it the reprogrammed online_ (For a card reader, all bits are
undisputed choice for this application.) input; for a line printer, all bits are output.) This
The four device ports (numbered 0 to 3) must be interface configuration can be made to handle most
adaptable to both serial and parallel devices. Original- common 8-bit devices. For serial devices, the 20-pin
Iy, the multifunction controller specification called limitation requires that the parallel buffers be re-
for support of a card reader, three types of line printers moved and replaced with a universal synchronous/
(two parallel and one serial), a paper tape punch, asynchronous receiver/transmitter (USART) , as well
a paper tape reader, a serial console terminal, and as appropriate line drivers and receivers.
a full-duplex Rs-232-C asynchronous channel with full The l80A-PIO parallel r/o controller chip provides
modem control and fully programmable parameters_ the required bit-programmable port capability (Fig 2),
A typical configuration might include a card reader but it has only two 8-bit ports_ Six PIO chips are
,-
I
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ---,
CONTROLLER
I
2-15
needed to drive four 20-bit controller ports. Since
one and one-half Pro chips provide 24 bits, the extra
{ol
four bits control the buffers connected to the pro-
grammable bits. The two shared Pro controllers handle
only data paths, and therefore are not connected to
the microprocessor's interrupt system. All six chips are
configured to operate in hit control mode; hence, their
handshake lines are not used. Handshaking is accom-
plished hy addressing various port bits. Each controller
port has one complete Pro chip that can generate any
needed interrupt.
For serial applications, all 24 hits are availahle to
be programmed as required to best support the spe
cialized serial hardware. To minimize serial hard-
ware, the decision was made to restrict console tasks
to port 0 or 1, and the channel task to ports 2 and
3 together. A serial line printer uses the console
hardware. A USART is connected so that it is handled
as though it were an external device. Serial handling
may seem somewhat clumsy, hut the hardware involved
in the microprocessor's hus structure is simplified since
there is no need to interface directly to a specific chip.
This approach also helps to standardize the tasks in
their port handling. The Z80-sro serial Ij0 chip was
not yet available when this controller was designed.
Examination of the preliminary sro specification, how-
ever, indicated that use of the sro would seriously
complicate the controller's internal structure; even if
the IC had been available, it probably would not have
been used. (The area in question is the displacement
register, which will be discussed later.)
Some of the devices to be controlled require either
timeouts or cyclic testing of status. These timing func-
tions are triggered by a Z80A-CTC (counter-timer cir-
cuit); its four channels are allocated one to each
controller port, and are used as timers for intervals
.up to 16.4 ms (the longest timeout possible with the
4-MHz clock). Longer timeouts are made by firmware
counting of CTC interrupts.
A seventh, or frontend, Pro is used between the micro-
processor and the host's I/O to load the various re-
quests into the appropriate FIFO buffers and to provide
a vectored interrupt signal to the microprocessor when
the C/D FIFO contains information to be processed.
Sixteen-bit status and data words for the host are
stored in separate 4 x 4 register files whose inputs
are I/O mapped for loading by the microprocessor.
2-16
152 ***********
153 POLL
1~4 ***********
155
156 POLLING ROUTINE -
TEST EACH TASK SEQUENTIALLY FOR POLLING
157 SERVICE REQUESTS, CALL TASK IF POLL FLAG IS NON-ZERO.
158 OPE~ INTERRUPT WINDOW ONCE EACH PASS.
159
9U71 110603 160 LD DE,POLF ;FETCH POLL FLAG ADDRESS
9074 ?1 0098 161 LD HL,DADR ; FETCH DISPL PEG ADDRESS
9077 FB 162 POLL El ;ENABLE INTERRUPTS
9078 04 163 INC B
9079 04 164 INC
907A F3 165 DI ;DISABLE INTERRUPTS FOR PO LL SERVICE
907A 70 166 LD (HLl ,8 ; WRI TE DISPLPCEMENT
907C 1A 167 LC A,{DE) iTHI S PORT NEED POLLING SERVICE?
907D B7 168 OR A
907E CA7790 169 JP Z,POLL iNO,TRY NEXT PORT
9081 09 17u EXX ;YE~, SAVE CURRENT PARAMETERS
9082 2 AD 403 171 LD HL, (POLE) ; FETCH TASK POLL SERVICE E NT RY
9085 CD8C90 172 CALL ICA LL ;CALL POLL ROLITINE INDIRECT
9088 D9 17~ EXX ;GET OWN REG SET
9089 C37790 174 JP POLL ;NOW GO POL L NE XT PORT
175 THE Z80 DOES NOT HAV E A CALL-INDIRECT INSTRUCTION
176 THE FOLLOWING JUMP SERVES THE PURPOSE.
908C E9 177 ICALL JP (HL)
(b)
cated location in RAM is loaded with a common ignore. Once initialized, the system enters an idle loop
thiscommand return. If it is present, the first 10 ROM whose function is to control timesharing among the
locations-containing PIO interrupt, CTC interrupt, com tasks present. This idle loop, called the polling loop
mand interrupt, data transfer interrupt, and polling [Fig 3(b)], enables a task in two ways: intermpt
service entry addresses-are transferred to dedicated service (priority enabling) and polling service (round-
locations in either executive or task RAM. Control is robin enabling). Any activity must begin with an in-
then transferred to an initializer within the task itself; terrupt, either from a task's CTC port or from the
this routine sets up the port PIOS and CTC as required outside world (the host or the device connected to the
for the particular task, and generates and loads valid particular port). A CTC or device PIO interrupt is vec-
status to replace the initial status loaded by the execu tored to the relevant task routine, which takes ap-
tive. Control is then returned to the executive initializer, propriate action. An interrupt from the host's rio,
which processes all four ports in this manner before through the frontend PIO, is vectored to an executive
enabling the hardware to respond to the rio. routine which extracts the contents of the current C/D
2-17
FIFO buffer location, decides whether it is a command (2) Generating one request for a data transfer eitl!er
or data, and transfers control to the task routine to or from the I/O. This request may be either a
whose address is in the pertinent dedicated location. DI or a DMP request; the executive service routine tests
Whichever task routine is activated completes its action current controller parameters to decide which type is
and returns control to the polling loop. The task ac- proper.
tivity in question may need service of a type which
(3) Initializing or terminating the host's DMP hard-
cannot be triggered by further interrupts (such as
ware by generating specialized DMP requests for these
emptying 'a buffer asynchronously with its filling, to a
functions.
device that does not handshake). Such service is acti-
vated by the setting of a dedicated location, called the ( 4) Requesting startup or shutdown service of the
polling flag, to any nonzero value. host's software by generating an SI, and optionally
Each task has its own polling flag and an associated resetting controller busy when setting the 51.
polling entry dedicated location. During each pass of
(5) Reinitializing the calling task exactly as is done
the polling loop, an interrupt window is opened for
at power-up. Primarily a diagnostic tool, this function
2 p.S. If no interrupt is pending, or upon return from
is essentially free-the same routines are used in both
the servicing of an interrupt, the loop tests one port's
cases.
polling flag. If the flag is zero, the port number is
incremented and the polling loop restarts, opening Primary value of the executive services is to reduce
the interrupt window. Each port is tested once every the size of the tasks, since each task is limited to 768
four passes through the loop. If the polling flag is non- bytes of ROM and 256 bytes of RAM. An added ad-
zero, the loop fetches the address of the task polling vantage lies in the fact that a task designer need not
routine from the dedicated location and calls that routine. reinvent the wheel by designing all the common func-
The task routine takes the action for which it has tions again for each new task; the effort required to
been set up and resets the polling flag if no further implement new tasks is thereby minimized.
polling service is required, and then returns to the As mentioned above, tasks are limited in size. A
polling loop, which continues as before. Note that in- more ~erious problem, however, is the necessity that
terrupt service always receives priority over polling any task (with certain specific exceptions) be installed
service; this arrangement provides the fastest possible into any port position. It is clear that the various port
response to the outside world, and is guaranteed by memory areas will have difIerent starting addresses.
specifying that all interrupt routines must enable the A conventional software program designed to be loaded
interrupt before returning to the polling loop. If another into various areas of memory (relocatable software)
interrupt is pending, it is serviced immediately. is accompanied by a list of locations within the program
To minimize both interrupt and polling service which must be modified upon loading to reflect the
times, the system takes advantage of the Z80's two program's starting address. Once programmed, however,
sets of working registers. One set contains registers A, a ROM set cannot be changed; so it would seem that
B, C, 0, E, H, and L; the second set is a duplicate each task must come in four versions, one for each
of the first. A single instruction (EXX) will exchange port. This constraint was considered unacceptable;
all but A with their duplicates, and another instruction stocking of all the difIerent ROM sets would create
(EX, AF, AF') will exchange A and the machine's flag problems for both manufacturer and user. The solution
register. The latter instruction is not used in the multi- to this problem lies in relocatable firmware, which
function controller-A is considered volatile by each can be implemented by memory mapping, of which
routine. The polling loop does the context swap for bank switching is a simplified form. Two address bits
polling routines, but interrupt routines must do the (AIO and All) are used to select one of the four
swap themselves. One set is dedicated to the polling tasks, and the most significant address bit (A15) is
loop; register B contains the number of the next port used to control whether the bank switch is invoked
whose polling flag will be tested, register pair DE [Fig 4(a)]. All tasks, then, can originate at memory
contains the address of the polling flag in memory, address zero. It is possible to address any memory
and register pair HL contains the address of the poll- location in absolute mode (A15 = I), but only the
ing routine being called. The second register set is
available for use by any task or executive service
selected task is accessible in relative mode (A15 =
0). The executive is always addressed absolutely to
routine. The Z80 also has two index registers, IX and make its services available to any task. The addresses
IY, but these registers are not used in the controller of those services are assembled with each task as
because indexed instructions suffer a I-lLs/instruction "external" equates.
time penalty.
The executive provides several services to any task Located in executive RAM, the push-pop stack is
in the form of callable subroutines. These services addressed absolutely. PIO and CTC interrupt dedicated
perform the functions of locations are also in executive RAM, but these locations
are addressed relatively so that accesses to the same
(I) Decoding commands that a task has determined relative address in each task will be routed to the
to be of a control nature, such as controller interrupt proper absolute address by the bank switching control
connection, data transfer termination, etc_ Appropriate hardware. The interrupts themselves are routed through
action is taken and control is returned to thl( calling the same absolute addresses by the vectors loaded into
routine if required. the hardware.
2-18
(b) FIAMWARE ADDRESS BITS
(a) DATA BUS (D) MP ADDRESS BUS (Al
I {OO}' 4000
0100 0000 0000 0 ~6 0 "'" :gg~
I 11
SELECT DREG DREG CONTENTJ
4006
nn
(e) INTERRUPT REGISTER VECTOR
SEG~
C002
C004
C006
I",B"-y'-'PA-"S"'S-=occ".=.EG=--_ _ _ PORT
Fig 5 Typical interrupt routine. Routine monitors controller status change from HOLD to READY
when operator depresses RUN switch. It reports new status to host, sets Pia to interrupt when next
line feed occurs, and loads interrupt dedicated location in executive RAM with address of routine
which tests for bottom~of-form status. It sets polling flag-if controller is busy, data transfer com-
mences (polling vector will have been set to address data-to-printer routine); if not, service inter-
rupt is generated to notify host that printer is available (polling vector will address SI-generation
routine). Manipulation of DO in internal controller status word (CSTAT) copies enable bit stored
in 01 into status that will be read by host if SI is made
as though it were an output. Upon recogmzmg this line. If a handshake is required, the strobe is set true
input transfer, the firmware ignores the FIFO data and and allowed to remain set until an acceptance is
proceeds to ready the next transfer. signalled by the device. Data from an input device
Data requests may be generated by several mechan are read from the half PIO and then accepted, if the
isms. An interrupt routine servicing a device whose device requires a response, by strobing in the same
data rate is controlled by the device (eg, a terminal, manner as for output. The CTC is used for two func
through a USART) generates a request when it has tions: cyclic activity and single.shot timeouts. Most
data for input or when the device requires output. A cyclic activity tests and updates status for devices whose
polling routine emptying an input buffer generates status can change during periods of controller inac-
requests as long as there are data in the buffer. Finally, tivity. Such changes are often due to operator inter
an output data transfer interrupt routine filling a buffer vention. Single-shot timeouts are required for devices
generates a request every time it is triggered by the which take long periods to execute some function or
receipt of a transfer, after loading the iust-received functions and do not signal the completion of such
data into its buffer. functions. A currently supported paper tape punch, for
Data are transferred to an output device by writing example, takes a full second to run up to speed when
the data to the half PIO and then writing a one followed started; it is left running for lOs after the completion
by a zero to another output bit assigned as the strobe of a transfer to avoid repeated up and down cycles
2-20
and the consequent startup delays. Several concurrent Vectors are loaded into the various ports' interrupting
timeouts may be controlled by a common clock handler peripherals, two locations apart, and these two address
routine, and this activity by no means precludes cyclic bits select which port's dedicated location is addressed
functions as well. when the firmware uses relative mode. For example,
the firmware addresses location 4000 (hexadecimal) ,
and anyone of the four 10cations--4000 (equivalent
Hardware Architecture to COOO) , 4002, 4004, or 4006-is accessed as con
trolled by DREG [Fig 4(b)]. The firmware cannot
The memory bank switching function is the central
address these locations directly in relative mode since
capability of the hardware, and is implemented with
DREG overlays the programmed address. During a hard
a single' 2bit register called the displacement register
ware interrupt response, location COxx is addressed with
(DREG). Input to DREG is data bus bits Dl and D2
the xx being supplied by the interrupting peripheral
[Fig 4(a)]. This register is loaded either by an
[Fig 4(c)]. Port O's PIO supplies 00 to address COOO,
executive routine or hardware interrupt routine. The
port l's PIO addresses C002, etc, with A15 forcing
executive routine which fetches the C/D FIFO contents
absolute addressing to one of four locations which all
loads two of the extra FIFO bits into DREG by a mapped
appear as 4000 to the firmware. This method (Fig 5)
memory write. The register is addressed as though it
is used for all interrupt vectoring. Extended use of
were a memory location; hence, any firmware has the
DREG makes it unnecessary for a task ever to know
-ability to load it, but tasks normally do not do so.
in which port it is installed, thereby significantly in
The two loaded bits are a binary encode of the port
creasing the overall throughput of the controller.
selected by the host's controller address bus, and when
used as AlO and All, they select the specified task's
memory area. Hardware interrupt response loads Dl
and D2 into DREG using the interrupting device's vector
Summary
to select the task whose device made the interrupt. Although the multifunction controller is limited to an
Dedicated interrupt entry locations are allocated to aggregate throughput of from 4000 to 8000 bytes/s,
provide the proper vectors. It is this function which depending upon configuration, this performance exceeds
precluded use of the SIO. The SIO generates a series the requirements of the peripheral devices it is designed
of vectors for a given port, so that bits 1 and 2 cannot to handle. The microprocessor based design offers satis
be used for port selection. factory solutions to most problems and objectives of
DREG outputs are multiplexed with AIO and All a multipurpose intelligent peripheral controller: it
from the microprocessor, and the multiplexer is steered allows reasonably fast response to the host, enables
by A15. When A15 is a zero (relative mode), the
the system designer to mix or match peripherals, and
multiplexer gates DREG's outputs to the controller's
provides an adaptable interface for additional periph.
internal address bus, and anyone of the four task
erals. It can easily be configured for installation into
areas can be accessed. When A15 is a one (absolute
a system, and is relatively inexpensive to manufacture
mode), the microprocessor's actual address is used,
and simple to service.
and any area of memory can be addressed. The execu
tive is always addressed absolutely; certain tasks,
which occupy more than one port and are always Bibliography
installed in the same port location, are also addressed
absolutely to avoid the necessity of constantly reload T. Dollhoff, "!'P Software: How to Optimize Timing & MemolY
ing DREG when executing different subroutines. Usage," DiBital DesiBn, Feb 1977, Pl> 44-51
DREG addresses not only memory but also most other L. TeschIer, "Interface Software for Microcomputers," Machine
DesiBn, Aug 10, 1978, pp 105109
port oriented hardware in the controller. This scheme J. G. Wester and W. D. Simpson, Soltware DesiBn 1M' Micro
is necessary to speed execution times; if a task were processors, Texas Instruments, Inb, Dallas, Tex, 1976
required to recognize its port address, and compute ZiIog, Inc, Z80CPU Technical Manual, Z80.PIO Technical Man-
and load the addresses of all its devices, most routines ual, Z80CTC Technical Manual, Cupertino, Calif, 1976
would become unreasonably long. To avoid this prob
lem, all PIOs and the CTC are selected by a peripheral.
select PLA, which is steered by a combination of ad
dress bits 0 to 7 and the DREG outputs. DREG steers Currently a design engineer and mem-
both data and status register files and most of the port ber of the technical staff with MODCOMP,
Richard Binder has held various posi-
oriented hardware in the front end. This hardware tions in the 110 development group, de-
includes a multiplexer whose inputs are the controller's signing interfaces for an electrostatic
optionselection switches, and several registers used printer/plotter, magnetiC tape formatter,
to control interrupt generation to the host. card reader, moving head discs, and
bulk core memory modules. He at-
In addition, DREG supplies a port selection function tended Rose Polytechnic Institute, and
in addressing the executive RAM, but in this case DREG's has worked as a mechanical designer
outputs are multiplexed with address bits Al and A2. and technical illustrator.
221
~
Zilog Tutorial
January 1980
I NTROOUCT ION Interrupts provide a means of processing the system designer great flexibility in
Information on a random or asynchronous Implementing an Interrupt driven system.
basis. The Z80 CPU and peripheral family This document describes the Z80 CPU interrupt
support Interrupts using a daisy-chain process and evaluates the design of the
approach. As opposed to paral lei priority daisy-chain interrupt scheme. The reader can
resolution, the daisy chain uses an refer to the following documents for addi-
efficient, minimal-hardware method of priori- tional information:
tizing multiple Interrupting devices. In
addition, a paral lei priority resolution Z80 Assembly language Programming
scheme can be configured with the Z80 through Manua I (03-0002-01)
the use of a priority encoder and other Z80/Z80A CPU Technical Manual (03-0029-01 )
externai hardware. Z80/Z80A 510 Technical Manual (03-3033-01 )
Z80/Z80A PIO Technical Manual (03-0008-01)
Coupled with the powerful vectored interrupt Microcomputer Components Data
capabliitles of the Z80, this approach al lows Book (o3-a032-01 )
Non-Maskable The non-maskable Interrupt (NMI) is different and can be used for Interrupt conditions like
Interrupts from the maskable interrupt In several a power fail detect. NMT Is an edge-sensi-
respects. NMI Is always enabled and cannot tive signal that has a lower priority than
be disabled by the programmer. It is BUSRQ and higher priority than INT. When the
employed when very fast response Is desired CPU acknowledges an occurrence of NMT, the
independent of the maskable interrupt status processor begins a normal opcode fetch. How-
611-1809-0003 2-23
ever, the data read from memory is ignored preserved and maskable interrupts are dis-
and instead the CPU restarts its operation abled, until either an EI instruction is
from location 66H. The restart operation executed or a RETN instruction is used to
Involves pushing the Program Counter onto the exit the ~ service routine.
stack, jumping to location 66H, and continu- The RETN instruction is discussed in'detail
Ing to process there. During this time, the in the ZSO CPU Technical Manual. Figure 2
status of the maskable interrupt condition is shows the timing used for NMT interrupts.
PC TO PC TO
LASTMCYCLE_I-IGNOREDM1CYCLE_-STACKCYCLE-I-STACKCYCLE-\
LAST T STATE-l-- I
I T, I T2 I T3 I T4 T, I TZ I T3 T, I T2 I T3
<t>
-I 1- 80NSMIN
NMI~
AO-A'5:::::::::::::::)XC:::Jp~C::::Jx(:RuEIF]R~E~sEH:J)C:::::JS~P~1::::::)YC:::::JS~PS-Z2:::::::X:
iVf1--------,
------------L-__~--------------------------------
WR------------------------------------.~~------~~
RFSH -------------,
DO-D7--------------------~<:::::::::::::J>--<~ __________J}__
Figure 2. Non-maskable Interrupt Request Operation
Maskable Maskable interrupts (iNT) are acknowledged special MT cycle. During an interrupt
In1'errup1's with a lower priority than the NMT but al low acknowledge cycle, RD Is inactive, IORQ is
the programmer more flexibility. ntf is active, and two wait states are automatically
enabled under software control by way of the added.
EI Instruction and disabled via the 01 in- Since the ZSO peripheral devices have logic
struct i on. When the ZSO CPU samp Ies iNT and to interpret this special cycle with no
It Is active, the processor begins an Inter- additional external circuitry, a minimal
rupt acknowledge cycle so long as BUSRQ and amount of hardware is needed by the system
NMT are not active. The processor does not and there is no loss in efficiency. Figure 3
use an interrupt acknowledge signal but shows the detailed timing for the ZSO CPU
instead issues the acknowledge by executing a interrupt acknowledge cycle.
T, T4
eLK
M1
IORQ-----------------~
RD-----------------------------------
(HIGH)
Figure 3. Interrupt Acknowledge Cycle
FOR CALL
r--=.-I-.--~ 1
OR RST
ONLY
1....-""'::':=:""";''';'';;'''---1
Maskable In the maskable interrupt Mode 0 (as with the read sequences, since the Instruction must
In'terrupt 8080 interrupt response mode), the Interrupt- come from the Interrupt hardware. Timing for
Mode 0 Ing device places an Instruction on the data the additional bytes of a multlbyte Instruc-
bus for execution by the Z80 CPU. The in- tion Is the same as for a single byte In-
struction used Is normally a Restart (RST) struction (see NMI In Figure 2).
Instruction, since this Is an efficient one-
byte call to any of eight subroutines located When an Interrupt Is recognized by the CPU,
In the first 64 bytes of memory. (Each sub- succeeding Interrupts are automatically
routine Is a maximum of eight bytes.) How- disabled. An EI Instruction can be executed
ever, any Instruction may be given to the Z80 anytime after the Interrupt sequence begins.
CPU. The subroutine can then be Interrupted,
al lowing nested Interrupts to be used. The
The first byte of a multlbyte instruction Is nesting process may proceed to any level as
read during the interrupt acknowledge cycle. long as al I pertinent data is saved and
Subsequent bytes are read In by normal memory restored correctly.
read cycles. The Program Counter remains at
Its prelnterrupt state, and the user must Upon RESET, the CPU automat i ca I IY sets
Insure that memory will not respond to these interrupt Mode O.
Maskable Interrupt Mode 1 provides minimally complex 38H instead of 66H. As with the NMT, the CPU
In'terrup't peripherals access to Interrupt processing. pushes the Program Counter onto the stack
Mode 1
It Is similar to the NMT Interrupt, except automatically (Figure 2).
that the CPU automatically CALLs to location
Interrupts)
Mode 2 Is the most powerful of the three
LOW ORDER ) VECTOR TABLE
maskable Interrupt modes. It allows an HIGH ORDER
Indirect cal I to any memory location by a PC
single 8-blt vector supplied by the periph-
eral. In this mode, the peripheral generat-
Ing the Interrupt places the vector onto the
data bus In response to an Interrupt ack- IREG
nowledge. The vector then becomes the least
significant eight bits of the 16-bit indirect INTERRUPT
pointer, whereas the I register i~ the CPU SERVICE
ROUTINE
forms the most s~gnlficant eight bits. This
address points to an even address In the
vector table which then becomes the starting
address of the Interrupt service routine.
Interrupt processing thus starts at an INTERRUPT VECTOR
arbitrary 16-bit address, al lowing any loca-
tion In memory to begin the service routine.
NOTES
Since the vector is used to identify two 1 Interrupt vector generated by penpheral IS read by CPU dur-
adjacent bytes that form a 16-blt address, mg mterrupt acknowledge cycle
the CPU requires an even starting address for Vector combmed with I register contents form 16-blt memory
the vector's low byte. Figure 5 shows the address pomtmg to vector table.
Two bytes are read sequentIally from vector table These 2
sequence of events for processing vectored bytes are read mto PC.
Interrupts. 4 Processor control IS transferred to mterrupt serVlCe routme
and executIon continues.
The I register Is loaded by the user from the
A register. There is no restriction on its Figure S. Vector Processing Sequence
Return trom When execution of the Interrupt service recognized interrupt, and a method of reset-
Maskable routine Is complete, return to the main ting the peripheral's interrupt condition
Interrupt program (or another service routine) occurs must be found. This is accomplished by using
differently In each mode. In Mode 0, the the RETI Instruction. If Mode 2 Is used by
method of return depends on which Instruction the programmer, the RETI Instruction must be
was executed by the CPU. If an RST Instruc- executed in order to utilize the daisy chain
tion Is used, a simple RET suffices. In Mode properly. Figure 6 shows the RETI Instruc-
1, the CPU treats the Interrupt as a CALL tion timing for the Z80 CPU. A more complete
Instruction, so an RET Is used. Mode 2, description of how RETI affects the periph-
however, uses the vector Information from the erals Is given In Chapter 3.
peripheral chip to identify the source of the
eLK
M1,
/ \ /
RD
\ / \ /
Do-D7 >G)( ~
MREQ
\ / \ /
IORQ
(HIGH)
CPU INSERTED
IT WAIT STATES
T2 I Tw I Tw I T3
eLK
HALT---.L__________________________ -r-------------------
INT============ =====LI- - - - - - J f - - - -
M1----~_____r----~L___~------~____~--~
IROQ-----------------------------------------~----J
Figure 7. Exit Halt State with Maskable Interrupt
INTERRUPT Understanding maskable Interrupt processing (lEI), Interrupt enable output (lEO), and
PROCESSI~ requires a familiarity with how the Z80 Interrupt request (INT). The Interrupt
BY zao peripherals respond to the CPU interrupt request line Is an open-drain circuIt that Is
PERIPHERALS sequence. The Z80 family products were OR wired to the INT pins of the other devIces
designed around the daisy-chain Interrupt In the cha I n and connected to the iN'f pin on
confIguration, whIch utIlIzes mInimal the Z80 CPU. This line provides the Inter-
external hardware (compared to paral lei con- rupt request to the CPU.
tention resolutIon Interrupt prIorIty net-
works). Many devIces handle Interrupts via a
handshake arrangement, e.g. the use of The lEI and lEO lines provide the means for
Interrupt request and Interrupt acknowledge establIshing priority among several request-
signals. This Is the most straIghtforward Ing devices. The priority of a devIce Is
and probably the fastest method of Implement- determined by Its position In the chain. The
Ing prioritization using more than one lEI pin of the highest priority device In the
InterruptIng devIce. However, this method chain Is connected to +5 volts. The lEO pin
requires a separate Interrupt request signal of the same device Is connected to the lEI
for each peripheral device and eIther a pin of the next highest priority device. The
separate acknowledge sIgnal for each device lEO pin of that device goes to the lEI pin of
or a software acknowledge. Extra hardware Is the next lower device, as shown In Figure 8,
needed to provide contentIon resolutIon and so on to the last device In the chain,
should two or more devIces request an Inter- where the lEO pIn Is left open. When a
rupt sImultaneously. WIth the Z80 product device has an Interrupt pending, It activates
famIly, however, such extra hardware Is Its TNf output which requests service from
unnecessary and the software does not need to the CPU and brings Its lEO pin Low, thereby
remove the Interrupt request from the perIph- preventing the lower devices In the chaIn
eral device. This Is made possIble through from responding to further Interrupt opera-
use of the daisy-chaIn priority network, tions. When the CPU acknowledges the Inter-
whIch can best be vIsualIzed as a type of rupt, the requesting device removes Its
bucket brl gade. Interrupt request (iNT) signal. After the
Interrupt processing Is completed, the
The Z80 perIpheral products Implement this peripheral wIll reset Itself with an RETI
daIsy chaIn wIth Just three extra sIgnal Instruction, whIch will brIng lEO HIgh and
lines on each chIp: Interrupt enable Input restore the chaIn to Its quIescent state.
~----~------------~------------~------------r------L
IP
H H L
lEO lEO lEO
lEI 2 3 4
~-----.------------~------------~------------r------H
IUS
H H L
2 3 4
+5V
~----~------------~------------~------------r------L
IUS
2 4
+5V
~----~--------------~-------------,--------------~------H
IUS
L L L
2 3 4
+5V
~----~--------------~-------------,--------------~------H
IUS
H H L
2 3 4
+5V
~----~------------~------------.------------.r------H
2 3 4
NOTES.
1. DevIce 3 has an mterrupt pendmg (lP set), whIch causes Its
lEO pm to go low preventmg devIce 4 from mterruptmg.
2 CPU acknowledges the mterrupt and devIce 3 has Its mter-
rupt under serVIce (IUS set), The devIce's IP IS then reset
DevlCe 1 requests servIce, suspendmg devICe 3 processmg.
(Assummg mterrupts were reenabled.)
4. DevIce 1 has Its mterrupt under servICe.
5 CPU completes processmg for devIce 1 and returns to devIce 3
serVIce rouhne
6. CPU completes proceSSIng for devIce 3 and the daISY cham
returns to qUlescent state.
Figure 8. ZSO Peripheral Device Interrupt Processing Sequence
eLK
INT-----,
M1---------~
IORQI-------------------~~
RDI--~(H~IG~H~)-------------------------------------------------------------
Return fram When the CPU executes an RETI Instruction, when the ED Is seen during the ED-4D
Interrupt the device with an Interrupt under service Instruction fetch. The device whose Inter-
Operation resets Its Interrupt condition, provided that rupt Is under service does not allow lEO to
lEI Is High. AI I Z80 peripheral products go High, but when It sees lEI High, It will
sample the data bus for this Instruction when reset Itself when the 40 byte Is fetched.
MT goes active along with RD.
Figure 10 shows the relationship of IP and
The RETI Instruction decode by the peripheral IUS to INT, lEI, and lEO. IP Is set by an
device has certain characteristics that the Interrupt condition on the peripheral (such
designer should be aware of. Since a pe~h as the transmit buffer becoming empty) when-
eral can request an Interrupt (activate INT ever Interrupts are enabled. However, IP
and bring lEO Low) at any time, It Is pos- being set will only cause iNf to go active
sible for a device whose Interrupt Is cur- (requesting an Interrupt) If IUS Is not set
rently under service to have Its lEI pin Low. and lEI Is High. IP Is not necessarily
This Is undesirable, since such a condition cleared by the Interrupt acknowledge cycle.
prevents the peripheral from resetting IUS Some specific action must be taken within the
properly. To overcome this problem, all Z80 service routine, such as filling a transmit
family peripherals bring lEO High momentarily buffer. Under these conditions, IUS becomes
RETURN TO
n / - - -__ 1DLE
STATE
b) Truth Table of DaIsy Cham Durmg Idle c) Truth Table of DaIsy Cham Durmg
or Interrupt Acknowlege Condition, "ED" Decode of Opcode Fetch
Note That IP Is Not Part of lEO CondItIon.
~.~
INT SAMPlE
~---------'\~----------------~/
, -_ _ _ _~-\' I--T'M1(IEO)
lEO=>< ~
~:
INTERRUPT PENDING
DEVICE CAN CHANGE
IORQ-----------------------~
i\I '--_ _ / -oJ
IEI _ _ _ _ _ _ _ _ _ _ _ --1V !
~TS{IEI)r____
~T,--I
RIPPLE TIME FOR DAISY CHAIN =
TdM1(IEO) + TdIEI(IEOF) * (N-2] +T,IEI(IO) + TTL BUFfER DELAY (IF ANY)
~~ I
DELAY TIME FOR N2 DEVICES lEI SETUP TIME FOR LAST DEVICE IN
FOR ALL IN CHAIN UNDER CHAIN BEFORE lORa ACTIVE EDGE
DEVICES, TO WORST CASE
PREVENT CONDITIONS
FURTHER
INTERRUPTS, FROM
M1 ACTIVE EDGE
iii
IO~-----------------~~~~L-~-----------
CLK
INT'----~
MII-------,.
IORQI-----------~f_-~~
WAIT--------------------+-----------~
UNDI!R
SERVICE---------------------~~
Figure 12A. DailY Chain Look-Ahead Logic lor More Than Four Peripheral Devices
CLK
iii----,
IORQI-------------,
WAIT'---------------;""
I~I~'------------------;~
.,
CLK
~-------IORQ
I~-----------------------~f-----~
}>----------------WAIT
.,
CLK
....D,
----~
1..1iI.1'------------7-~ 1
1
I
..... ,-
(lElM)
----------------~--r_----~~
I
_I_ II
I
I. TdlEI(IEOd I
1I
_I
I To!ED(Ieort I T$IEJ(4D} 1/
~,-------------------rl--------------~,----+1, TlEO,) zaD ZIOA
'-I---T,-----II
RIPPLE TIME FOR CTC 220 180
DAISY CHAIN IN SID. DART 150 100
RETI CONDITION PIO 210 180
DMA 210 180
NOTES:
1. Selup lune for lEI 10 "40" decode - 200n. (4 0 MHz)
2 Must look at lEI durmg ED-4D because nested Interrupts
allow more than 1 IUS latch to be set at one hme.
3. Delay tome from EO decode Wllh IP set 10 lEO h,gh
- 300ns (Iyp) 400ns (max) @2.5 MHz. ThlS In In add!toon 10
rIpple time for other deVlceS m chaln.
T, ,. TdED(IEOr)
---....,--
+ +
TdIEI(IEOr) [N-2]
eLK
MR.Q-------------r------------------f-----------~----------~
AD----------~------------------f_----------_f--------------,
IROQ------~~--------~
WAIT--------'~""
INTACK----------,
IOAQ----------------------------~
READ'----------------------------~\
WRI----------------------------------------------r-~
}--------WRITE
RESET--------------------------------------------~~~
RD--------------------------------------~ r------READ
LS04
IORQI----------------------r--~ -I
IORQ
LS04
M1
LS04
NOTE
1. RD and WR should only be
LS04 connected to 8500 perIpherals
and not to Zao penpherals.
CLK------t----i
WAIT-----------------1 __ I
' -__J - - - - - - - - - - - - - W A I T
Figure 16. Interface Logic For Connecting 8500 Series Peripherals To zeD System
611-1809-0003 12/1/80
A ZaO-Based System
Using the DMA
With the SIO
~
Zilog
Application Brief
January 1981
INTRODUCTION In certain applications, serial data com- be accomplished either by pol ling the USART,
mun i cat Ions can be hand I ed more eft I cl entl y which forces the CPU to take time away from
by using a DMA device In conjunction with a other activities, or by Initiating an Inter-
serial controller. This appl icatlon brief rupt mechanism, which requires CPU time only
describes the use of the Z80A 510 and Z80A If there Is data to be moved. However, when
DMA hardware and software In a Z80-based large blocks of data need to be moved, even
system to transfer data to the 510 via the the interrupt mechanism becomes awkward. In
DMA. these cases, a Direct Memory Access (DMA)
device Is especially valuable.
Transfers through a serial data medium are
usually done with a serial controller device, With DMA transfer, data Is moved directly
often a Universal Synchronous/Asynchronous between memory and I/O (or additional memory)
Receiver/ Transmitter (USART), such as the without CPU Intervention. Once Initiated by
Z80 510. Additionally, some sort of con- the CPU, DMA operation continues transpar-
trolling device Is required to manipulate the ently to CPU operation until completed. Then
data on a character-by-character basis, the DMA device can either Interrupt the CPU
(usually a CPU). Transferring characters can or restart Its cycle using the previously
programmed parameters.
HARDWARE The hardware used in the example for this i zed to transfer data from a pattern In
DESCR I PTI ON brief consists of a Z80A CPU, a Z80A DMA memory to the 510 when the 510 requests a
controller, a Z80A 510/2, some RAM and ROM, byte via the WAIT/RDY signal line. The 510
and some support circuitry (Figure 1). then sends the byte to a terminal, which
displays it for visual inspection. After a
The Z80A DMA contains a 16-blt address bus, block of bytes has been sent, the DMA
an 8-blt data bus, and 13 control lines for restarts itself (Auto Restart mode) and the
external interfacing. The Z80 DMA can gen- process repeats continuously. Since the data
erate Independent addresses for Port A and pattern in memory consists of displayable
Port B. Each address can be vari ab Ie or ASC I I characters, data is eas II y ver I fled by
fixed. Variable addresses can be programmed observ i ng the characters d Isp Iayed on the
to either increment or decrement from the terminal.
programmed start i ng ad dres ses, whereas f Ixed
address I ng eli mI nates the need for separate One feature of the Z80 DMA is the ease with
enabl ing lines for I/O ports. which it Interfaces with the Z80 CPU. The
DMA is des Igned to connect dlrectl y to the
Readable registers contain the current CPU, as Illustrated In Figure 2. The 16
address of each port and a count of the address lines, eight data lines, and seven
number of bytes searched and/or transferred. control I ines are connected directly to the
Additional registers allow the DMA to perform correspond i ng II nes on the Z80 CPU. These
blt-maskable data comparisons on the data signals are then buffered by the 74LS241s and
that is being searched and/or transferred. d i str i buted to the rest of the system. The
The DMA has 21 writeable control registers data bus Is buffered by the 74LS245 bidirec-
and seven readable status registers, which tional octal buffer. Other connections to
together provide a high degree of program- the DMA include clock, cr/WAIT, iNT, RDYand
mability. lEI.
BIDIRECTIONAL
BUFFER
3C 7A
MY TlEO
4.7K 4.7K
+5V-"Mr-- ~+5V
5V
r---------------------------------------+----r----------~'~~~~3----------R~~~
~24'
~I '2~
Vee
'+'.0 5 A" 17 V" RDY lEI
r-JJ t1--- A15
'1._ i'D S 4 A,. 18
74LS241
f'--'0't---t:>---It"'2'---- A14
218
21A
- - - 74LS74
3 A" 19
r---E &-- Au 22C
2
~ ~A
A" 20
, A" 2'
~ ..L--A
22B
22A
40 22
A"
~ ~A10 23B
39 A, 23
'-"" ~A 23A
30 As 24
........!
------~--~~-------''47NiM1 37 A, 39
tl!--A 24C
Z80A 39 A, 40
, Z80A '9
------+-------------_'''I6mr
CPU 35
34
As
A. 2
DMA
Ir' +5V
33 A, 3
r---l' f---A 24.
,-"M---+ 5 V
~,q)~~2~-~I--~~--~2~4
32 A,
5 r-;; 74LS241 ~As 2'A
- - - - ___
MWAIT I
....7407
WAIT
1 31
30
A,
Ao 0
r--"
t--"
tL---As
~A
25C
258
18 IOWAIT 13-' 12 _ 4.1K
r---!-'4 f------ A 25A
~
Vr407 TIEO
5 V 4.7K 3 74LS02 5
WAIT
6
iUSREQ 25 ~+5V15 BUSREQ ..J '5 A 26C
2 #2 1
BUSACK 23 14 BAI r-l' f---A 25.
iOiiQ ~
MR~
IORO T
: 74LsOO
74LS10
3 DMASEL
8
EN
:4LS1~
lORa 20
iUi
WA
21
22
10
BRD
8YiR
,
r1L--Ao
19
+5V
25A
~'9
:
M1 26M"1
~
27
10J 8 74LSOO
MREQ 1"'
19 .......____ --1---",2 MREQ
74LSOO 13 D, 27 ,-J '8C
~[]~'7~0
9 D, 29 '8A
r--
~ir-'.....-'3'D"....,..~
7
8
12
D.
D,
D,
31
32
33
r: '98
'9A
20C
74504
. - -_ _7~
_-1
15 D, 34 208
14 D, 35 20A
~r+- :r .J:A ~9
J ~ r!--
74LS74
~~CLK ,.--! 74LS241
IORQ 10C
tf},p
~ Ro lOB
2;'" HH3006A
,C
74504 T 2 18
7~S241
ClK1
278
WAIT
2 74LS02 ~
~...
rr---"'H~I>----t'5,--
tz---
t1L- M1
WR
MREQ 11A
'OA
118
DM ASEL
Jv 1 ~+5
Figure 2. Schematic of CPU and DMA Interface
10K
ROY +5V
rW/RDY~V
.1
RESET
RD
RESET
M1
RD
e
....
lEI
TxD
RxD
Tx
w
INT INT zz CTS R8-232C
e AlS
BUFFERS
:I:
A ~ U
TO
MODEM
( Do-Dr DTR
'I II' DCD
Ar
L LS138 Z80A
810/2
RxC
AI C
A. 8 TxD
~
AI A RS232C
RxD
r}
BUFFERS
RTS TO
MODEM
L B
LS139
...~
z DCD
CTS
OTR
P
z
A CE e
:I:
u
AlB
DlC
CLK
CLK 1
....... J
TO CPU CLK DRVR.
COt:LUS' ON This example shows onl y one aspect of using The DMA can then be programmed to search for
the DMA with the 510. Use of the DMA with this character during data transfers and to
the 510 during receive deserves special con- Interrupt the CPU when the character Is
sideration. Since the DMA operates without detected. This method al lows for variable-
CPU processing, data received by the 510 does length message blocks, up to the maximum byte
not normally Indicate when the end of a count the DMA wil I accommodate. The disad-
message occurs. One solution to this problem vantage with this method Is that the user
Is to send fixed-length data blocks so that must dedicate one character as the special
the CPU can be Interrupted when the DMA EOB character.
reaches terminal count. This is done by
programming a fixed-length block count Into
the DMA and enabling It to Interrupt the CPU The un i q ue featu res of the DMA and 5 I 0 com-
upon End-Of-Block (EOB). As an alternative bine to form a powerful and flexible data
to the terminal count Interrupt, the 510 can communication mechanism. Due to the de-
be programmed to Interrupt the CPU when the signed-In compatibility of the 510 and DMA,
closing f lag is detected in SOLC mode. This interfacing with both In hardware and soft-
al lows the CPU to detect the end of a message ware becomes a simp I If i ed task. Programm i ng
using the 510 Instead of the DMA. Is easy because very little CPU intervention
Is necessary after initialization. Thus, the
Another method of detecting the end of a user is afforded a powerful tool for imple-
message is to dedicate a special EOB char- menting an efficient, cost-effective data
acter used to terminate all message blocks. process i ng system.
APPEll[) 'X Fol lowing Is a printout of the DMA/SIO test ditions or to receive characters. However, no
program. This program uses the DMA to code is shown that handles the characters
transfer data from a pattern In memory to the once they are received. Error conditions are
510, which then sends the data, In async reset by the interrupt service routine,
format at 9600 baud, to a terminal for dis- although nothing is shown for these condi-
play. The process continues until it is tions either. The user normally sets a
external I y Interrupted, such as by a reset. condition flag after resetting the error
condition, so that the driver program can
Interrupts are used to process error con- determine the appropriate course of action.
751-1809-0002 2-39 2-6-81
DMASIO
LOC OBJ CODE M STMT SOURCE STATEMENT ASM 5.9
1 DMAISIO TEST PROQRAM
:2
:3 By M. PITCHER - 10/10/80
4
5 QENERATES BLOCK OF DATA IN RAM.
6 THEN OUTPUTS TO SIO VIA DMA.
7 THEN CONTINUES FOREVER.
8
9 RAM: EGU :2000H I RAM START ADOR
10 RAMSIZ: EGU 1000H I RAM SIZE
11 SICOA: EGU 0 I SIO CH.A DATA PORT
1:2 SIOCA: EGU SIOOA+1 I SIO CH.A CTRL PORT
13 SICDB: EGU SIODA+:2 I SIO CH.B DATA PORT
14 SIOCB: EGU SIOOB+1 I SIO CH.B CTRL PORT
15 DMA: EGU OFOH I DMA PORT ADDR
16 DST: EGU SIODA I DESTINATION ADDR
17 BL~IZ: EGU 64 I XFER BLK SI ZE
18 DMABLK: EGU BLKSIZ-1 IDMA BLOCK SIZE VALUE
19
20
21 START DMA AFTER INITIALIZAiION (WR6. 87H)
22 DMA PARAMETERS
23
24 DMAWRO: EGU 0
25 XFER: EGU 1
26 SRCH: EGU 2
27 XFRSCH: EGU, 3
28 A_B: EGU 4
29 ALSTA. EGU 8
30 AHSTA: EGU 10H
31 ALBLEN: EGU 20H
32 AHBLEN: EGU 40H
33
34 DMAWR1: EGU 4
35 Ala: EGU 8
36 AINCR: EGU 10H
37 ADECR: EGU 0
38 AFIXED: EGU 20H
39 AVTIM: EGU 40H
40
41 DMAWR2: EGU 0
42 1310: EGU 8
43 BINCR: EGU 10H
44 BDECR: EGU 0
45 BFIXED. EGU 20H
46 BVTIM: EGU 40H
47
48 DMAWR3: EGU 80H
49 DMAEN: EGU 40H
50 INTEN: EGU 20H
51 MCHBVT' EGU 10H
52 MSKBYT EGU 8
53 SOMCH EGU 4
54
55 DMAWR4: EGU 81H
56 BYTE. EGU 0
57 CONT: EGU 20H
58 BURST: EGU 40H
59 ICB' EGU 10H
60 INTRDY: EGU 40H
61 DMASAV: EGU 20H
62 IV: EGU 10H
63 PCB: EGU 8
64 PULSE: EGU 4
65 INTEOB: EGU 2
66 INTMCH: EGU 1
67
68 BHSTA, EGU 8
69 BLSTA: EGU 4
70
71 DMAWR5: EGU 82H
219 *E,)
220
221 INTERRUPT SERVICE ROUTINES
222
223 CHBTBE:
0064 CDD800 224 CALL SAVE ;CH.B TX BUFFER EMPTY
0067 3EOO 225 LD A,SIOWRO
0069 D303 226 OUT (SIOCB), A
006B 3E28 227 LD A.TBERES
006D D303 228 OUT (SIOCB). A
006F C9 229 RET
230
231 CHORCA:
0070 CDD800 232 CALL SAVE ;CH. B RX CHAR AVAIL
0073 DB02 233 IN A, (SIODB)
0075 C9 234 RET
235
236 CHBESC.
0076 CDD800 237 CALL SAVE ,EXTERNAL/STATUS CHG
0079 3EOO 238 LD A,SIOWRO
007B D303 239 OUT (SIOCB). A
007D 3E10 240 LD A.ESCRES
007F D303 241 OUT (SIOCB), A
0081 3A0020 242 LD A, (SIOFLG)
0084 CBE7 243 SET 4,A
0086 320020 244 LD (SIOFLG).A
0089 C9 245 RET
246
247 CHBSRC:
008A CDD800 248 CALL SAVE ;CH. B SPECIAL RX COND
008D 3EOO 249 LD A.SIOWRO
008F D303 250 OUT (SIOCB). A
0091 3E30 251 LD A,SRCRES
0093 D303 252 OUT (SIOCB), A
0095 3A0020 253 LD A, (SIOFLG)
0098 CBEF 254 SET 5. A
009A 320020 255 LD (SIOFLG).A
009D C9 256 RET
257
258 CHATBE:
009E CDD800 259 CALL SAVE ;CH.A iX BUFFER EMPTY
OOAl 3EOO 260 LD A,SIOWRO
00A3 D301 261 OUT (SIOCA), A
OOA5 3E28 262 LD A,TBERES
00A7 D301 263 OUT (SlOCA). A
00A9 C9 264 RET
265
266 CHAACA:
OOAA CDD800 267 CALL SAVE .CH. A RX CHAR AVAIL.
OOAD DBOO 268 IN A, (SIODA)
OOAF C9 269 RET
270
271 CHAESC:
OOBO CDD800 272 CALL SAVE ;EXTERNAL/STATUS CHO
00B3 3EOO 273 LD A.SIOWRO
00B5 D301 274 OUT (SIOCA),A
00B7 3E10 275 LD A,ESCRES
00B9 D301 276 OUT (SIOCA). A
OOBB 3A0020 277 LD A. (SIOFLG)
OOBE CBC7 278 SET O,A
OOCO 320020 279 LD (SIOFLG), A
00C3 C9 280 RET
281
282 CHASRC.
00C4 CDD800 283 CALL SAVE ,CH.A SPECIAL RX CONDo
00C7 3EOO 284 LD A,SIOWRO
I)OC9 D301 285 OUT (SIOCA). A
314 *EJ
315
316 i. CONSTANTS
317
318 OMATAB:
OOEF 83 319 DEFB 83H ; WR6. DISABLE DMA
OOFO C3 320 DEFB OC3H ; WR6. RESET
OOFl C3 321 DEFB OC3H ; WR6. RESET
00F2 C3 322 DEFB OC3H ; WR6. RESET
00F3 C3 323 DEFB OC3H ; WR6. RESET
00F4 C3 324 DEFB OC3H ; WR6. RESET
00F5 C3 325 DEFB OC3H ; WR6. RESET
OOF6 79 326 DEFB OMAWRO+XFER+ALSTA+AHSTA+ALBLEN+AHBLEN
00F7 01 327 DEFB SRC.AND.255 PORT A ADDR (Ll
00F8 20 328 DEFB SRC/256 PORT A ADDR (H)
00F9 3F 329 DEFB DMABLK. AND. 255 ; PORT A COUNT (L)
OOFA 00 330 DEFB DMABLK/256 ;PORT A COUNT (H)
OOFB 14 331 DEFB DMAWR1+AINCR
OOFC 28 332 DEFB DMAWR2+BIO+BFIXED
OOFD 85 333 DEFB DMAWR4+BVTE+BLSTA
OOFE 00 334 DEFB OST.ANO.255 ; PORT B AD DR (U
OOFF B2 335 DEFB OMAWR5+AUTORS+CEWAIT
0100 C7 336 OEFB OC7H ;WR6. RESET A TIMING
0101 CB 337 OEFB OCBH WR6. RESET B TIMING
0102 CF 338 DEFB OCFH ; WR6. LOAD PORT B
0103 05 339 DEFB DMAWRO+XFER+A_B ; A -> B
0104 CF 340 OEFB OCFH ;WR6. LOAD COUNTERS
341 DMAEND' EGU $
342
343 SlOTA:
0105 00 344 DEFB SIOWRO ; CH. RESET
0106 18 345 DEFB CHRES
0107 01 346 DEFB SIOWRl i RDV/WAIT. INT. MODE
0108 DO 347 DEFB WREN+RDV+RXIAP
0109 04 348 DEFB SIOWR4 ; MODE
OlOA OF 349 DEFB X1 +STOP2+EVEN+PAR lTV
010B 05 350 DEFB SIOWR5 ; TX PARAMS.
010C AA 351 DEFB DTR+TX7+TXEN+RTS
0100 03 352 DEFB SIOWR3 i RX PARAMS.
OlOE 40 353 DEFB RX7
354 SIOEA: EGU $
355
356 SIOTB:
~
Zilog
Application
Note
July 1980
MESSAGE FLOW
PARITY MAY BE
ODD, EVEl OR NONE
MARKING I I I I: I I I
START 00 1 Do PARITY STOP I MARKING
f ,.'.)OR
STOP BITS
2
5, 6, 7, OR 8 BITS PER
CHARACTER RECEIVED
1,2,3,4, S, 6, 7, ORa BITS PER
CHARACTER TRANSMITTeD
~i~1 ~I~'
26-0003-0340 2-47
Protocol If the transmItter's clock IS slightly faster shll be received properly. ThIs tolerance of
(Continued) than the receIver's clock, the transmItter can mmor frequency deviations IS an Important
be programmed to send additional stop bIts, advantage of usmg asynchronous 1/0. Note
whICh will allow the receIver to catch up. If however that errors, called "framing errors,"
the receiver runs slightly faster than the trans- can still occur if the transmItter and receIver
mitter, then the receiver will see somewhat differ substantially in speed, smce data bIts
larger gaps between characters than the trans- may then be erroneously treated as start or
mItter does, but the characters will normally stop bIts.
Modes The SIO may be used m one of three modes: conjunction wIth a DMA (dIrect memory
Polled, Interrupt, or Block Transfer, depend- access) controller or with the 280 or 28000
mg on the capabilities of the CPU. In Polled CPU block transfer mstruchons for very fast
mode the CPU reads a status regIster m the transfers. The SIO interrupts the CPU or DMA
SIO periodICally to determine If a data only when the fIrst character of a message
character has been received or is ready for becomes avaIlable, and thereafter the SIO uses
transmissIOn. When the SIO IS ready, the CPU only ItS Walt/Ready output pm to signal ItS
handles the transfer wlthm its mam program. readiness for subsequent character transfers.
In Interrupt mode, which is far more com- Due to the faster transfer speeds achievable,
mon, the SIO informs the CPU via an mterrupt Block Transfer mode is most commonly used in
SIgnal that a single-character transfer is synchronous commumcation and only rarely in
reqUIred. To accomplish this, the CPU must be asynchronous formats. It IS therefore not
able to check for the presence of interrupt treated with speCIfic examples in this appllca-
signals (or "mterrJlpt requests") at the end of hon note.
most mstruction cycles. When the CPU detects Smce Polled mode requires CPU overhead
an interrupt It branches to an mterrupt service regardless of whether or not an 1/0 devICe
routme which handles the single-character desires attenhon, Interrupt mode IS usually the
transfer. The begmmng memory address of preferred alternahve when it is supported by
this interrupt servICe routine can be derived. the CPU. Note that the chOIce of Polled or
in part, from an "interrupt vector" (8-blt byte) Interrupt mode is mdependent of the chOIce of
supplied by the SIO during the interrupt synchronous or asynchronous I/O. ThIs latter
acknowledge cycle. choICe is usually determmed by the type of
In Block Transfer mode, the SIO is used m device to whICh the system IS communicating.
SIO Con- The SIO comes m four dIfferent 40-pin versions explain thIs m full.
figurations configurations: SIO/O, SIO/1, SIO/2, and There are 41 different SIgnals needed for
SIO/9. The first three of these support two complete two-channel Implementahon in the
independent full-duplex channels, each with SIO/O, SIO/l, and S10/2, but only 40 pms are
separate control and status regIsters used by available. Therefore, the verSIOns differ by
the CPU to write control bytes and read status either omithng one SIgnal or bonding two
bytes. The SIO/9 differs from the first three signals together. The dual-channel asyn-
versions in that It supports only one full-duplex chronous-only 280 DART has the same pm
channel. The product speclflCahons for these configuration as the SIO/O.
SIO-CPU The serial-to-parallel and parallel-to-senal addihonal external logIC to utilize effiCIently
Hardware conversions required for serial 1/0 are per- thIs mterrupt facility. Some non-Z80 system
Interfacing formed automahcally by the SIO. The device is desIgns do not utihze the vectored interrupt
connected to a CPU by an 8-bit bidirechonal structure of the SIO at all. Instead, these
data path, plus interrupt and I/O control require the CPU to poll the SIO's status
signals. through the data bus or to use non-vectored
The SIO was desIgned to mterface easIly to SIO interrupts.
a 280 CPU, as shown in Figure 2. Other MICroprocessors such as the 8080 and 6800
microprocessors require a small amount of need some signal translation logic to generate
external logic to generate the necessary inter- SIO read/write and clock timing. CPU signals
face signals. whICh synchronize a perIpheral device read or
The SIO provides a sophishcated vectored- wrIte operahon are gated to form the proper
interrupt facility to SIgnal events that require 1/0 signals for the SIO. The SIO IS selected
CPU intervention. The interrupt structure is by some processor-dependent function of the
based on the 280 peripheral daisy chain. Non- address bus in a memory or I/O addressmg
280 mIcroprocessors that are unable to utilize space.
external vectored mterrupts require some
2-48
Reference In the next section we begIn with a dis- materIal covered, the folloWIng publications
Material cussIon of features common to all forms of are needed:
asynchronous 1/0_ ThIs is followed by dIscus-
Z80 SIO Product SpecIficatIon or Z80 DART
sIOns of polled asynchronous 1/0 and Interrupt Product SpecIfication
asynchronous I/O_ Next IS a serIes of fre-
quently asked questions about the SIO when Z80 SIO TechnIcal Manual
used In asynchronous applications_ Finally, an Z80 Family Program Interrupt Structure
example of a sImple Interrupt-driven asyn-
Z80 CPU TechnIcal Manual
chronous application IS gIven and dIscussed In
detaIl. For a complete understandIng of the Z80 Assembly Language Programming
Manual
+5V
22 KH
INT~-<~
04 __________________________ ~~
Al~--------------------------------~
________________________________
~ ~ CIO
aoao zao
MPU SID
Do-II,
AD
ffiiffi
00-01
c-
BIA
6800
... o.
C/D
zao
MPU RlVi AD SID
VMA
00 IORQ
DBE
iii
ClK
26-0003-0341
2-49
SECTION Operational Considerations. channels supported by the SIO If both chan-
All of the SIO ophons to be discussed here nels are used. Before giving an overview of
2 are software controllable and are set by the how Imtialization IS done, we will descnbe
CPU. Thus, use of the SIO begins with an some of the basic characterlshcs of SIO oper-
Imtialization phase where the various options ahons that are common to both the Polled and
are set by wnting control bytes. These options Interrupt-driven modes.
are established separately for each of the two
Addressing The CPU must have a means to Identify any device. These latter SIX lines are usually wired
the SIO specific I/O device, mcluding any attached to an external decoding chip which activates
SIO. In a Z80 CPU environment, this IS done that SIO's Chip Enable (CE) input pin when its
by using the lower 8 bits of the address bus address appears on A2-A7 of the address bus.
(Ao-A7). TYPICally, the AI bit is wired to the The bar notation drawn above the names of
SIO's B/A mput pm for selecting access to certam signal lines, such as B/A and C/O,
Channel A or Channel B, and the Ao bit IS refer to signals which are interpreted as achve
wired to the SIO's C/O input pin for selecting when their logic sense-and voltage level-is
the use of the data bus as an avenue for Low. For example, the B/A pm specihes Chan-
transferrmg control/status information (C) or nel B of the SIO when It carries a logic 1 (high
actual data messages (D). The remaming bits voltage) and it specihes Channel A when it
of the address bus, A2-A7, contam a port carnes a logic 0 (low voltage).
address that uniquely Identihes the SIO
Asynch- Bits per Character. The SIO can receive or selection can be made mdependently for each
ronous transmit 5, 6, 7, or 8 bits per character. This channel.
Format can be different for transmission and recep- Start and Stop Bits. There are two types of
Operations hon, and different for each channel. ASCII framing bits for each character: start and stop.
characters, for example, are usually transmit- When transmlttmg asynchronously, the SIO
ted as 7 bits. The SIO can m fact transmit automahcally mserts one start bit (logic 0) at
fewer than 5 bits per character when set to the the begmmng of each character transmitted.
5-bit mode; this IS discussed further in the sec- The SIO can be programmed to set the
tion entitled "Queshons and Answers." number of stop bits mserted at the end of each
Parity. A panty bit IS an addlhonal bit added character to either I, I y" or 2. The receiver
to a character for error checkmg. The panty always checks for I stop bit. Stop bits refer to
bit is set to 0 or I m order to make the total the length of time that the stop value, a logic
number of Is in the character (mcludmg panty I, will be transmitted; thus I Y2 stop bits means
bit) even or odd, depending on whether even that a I will be transmitted for the length of
or odd parity IS selected. The SIO can be set clock time that 1Y2 bits would normally take
either to add an ophonal parity bit to the "bits up. A logIC I level that conhnues after the
per character" described above, or not to add specified number of stop bits IS called a
such a bit. When a parity bit is mcluded, "markmg" condihon or "mark bits."
either even or odd panty can be chosen. This
CPU-SIO The SIO always passes 8-blt bytes to the followed by the panty bit (If parity is enabled)
Character CPU for each character received, no matter and by the stop bit, which will be logic I
Transfers how many "bits per character" are specified in unless there is a framing error. The remainder
the SIO Imhalization phase. If the number of of the byte, if space is still available, IS filled
"bits per character" IS less than mght, parity with logic Is (markmg). If the "bits per char-
and/or stop bits will be mcluded m the byte acter" IS eight, then the byte sent to the CPU
sent to the CPU. The received character starts will contam only the data bits. In all cases, the
with the least-slgnihcant bi! (Do) and continues start bit is stripped off by the SIO and is not
to the most-sigmhcant bit; it IS immediately transmitted to the CPU.
Clock The SIO has hve mput pms for clock programmed to cause reception/transmissIOn
Divider signals. One of these mputs (CLK) is used clockmg at the actual mput clock rate or at
only for internal hmmg and does not affect 1/16, 1/32, or 1/64 of the input clock rate. The
transmiSSIOn or recephon rates. The other four receiver and transmitter clock divisions withm
clock mputs (RxCA, TxCA, RxCB, and a given channel must be the same, although
TxCB) are used for timing the reception and their mput clock rates can be different. The xl
transmission rates in Channels A and B. Only clock rate can be used only if the transitions of
these last four are involved m "clock dlvld- the Receive clock are synchromzed to occur
mg." A clock divider withm the SIO can be durmg valid data bit hmes.
2-50
Auto The SIO has an Auto Enables feature that Detect (DCD) mput w!ll enable receplion, and
Enables allows automalic SIO response and telephone a transihon to logICal 0 on the respeclive Clear
answermg. When Auto Enables is set for a par- To Send (CTS) mput Wlll enable transmISSIOn.
ticular channel, a transllion to logICal 0 (Low ThIS IS described below under the headmg
mput level) on the respeclive Data Carner "Modem Control."
Special There are three error condilions that can Parity error. If panty bits are attached by
Receive occur when the SIO IS recelvmg data. Each of the external I/O device and checked by the
Conditions these will cause a status bIt to be set, and If SIO whde reC81vmg characters, a panty
operaling m Interrupt mode, the SIO can error WIll occur whenever the number of
optionally be programmed to mterrupt the logic I data bIts m the character (mcludmg
CPU on such an error. The error condilions the panty bIt) does not correspond to the
are called "special receIve condItions" and odd/even settmg of the panty-checkmg
they mclude: funclion.
Framing error. If a stop bit is not detected Receiver overrun error. SIO buffers can
m ItS correct location after the panty bIt (if hold up to three characters. If a character IS
used) or after the most-slgmficant data bIt rec81ved when the buffers are full (I.e.,
(11 parity is not used), a frammg error wdl characters have not been read by the CPU),
result. The start bIt preceding the char- an SIO receIver overrun error wdl result. In
acter's data bIts IS not considered m deter- thIS case, the most recently receIved char-
mming a frammg error, although character acter overwntes the next most recently
assembly WIll not begm until a start bIt IS rec81ved character.
detected.
Modem FIve signal Imes on the SIO are prOVIded SYNC (Synchronization). A spare mput to the
Control for optional modem control, although these SIO m asynchronous apphcahons. ThIS mput
lines can also be used for other general- may be used for the Ring IndICator funclion, If
purpose control functions. They are: necessary, or for general-purpose mputs.
RTS (Request To Send). An output from the In most apphcalions of asynchronous I/O
SIO to tell ItS modem that the SIO IS ready to that use modems, the RTS and DTR control
transmit data. Imes and the Auto Enables function are acli-
DTR (Data Terminal Ready). An output from va ted durmg the mlliahzalion sequence, and
the SIO to tell its modem that the SIO is ready they are left achve until no further I/O IS
to receIve data. expected. ThIS causes the SIO to tell ItS
modem continuously that the SIO IS ready to
CTS (Clear To Send). An mput to the SIO transmIt and receIve data, and It allows the
from its modem that enables SIO transmiSSIOn modem to enable automahcally the SIO's trans-
If the Auto Enables funclion IS used. miSSIOn and receplion of data. FIgure 3 dlus-
DCD (Data Carrier Detect). An mput to the trates thIS.
SIO from ItS modem that enables SIO recep-
lion if the Auto Enables funclion IS used.
SIO
(CHANNEL A) MOOEM
REQUEST TO SEND
CLEAR TO SEND
TRANSMITTER
TxD
--------~
26-0003-0342
2-51
_._._----------------.------ - ---------~-
External/ A change in the status of certain external Note that the DCD and CTS status bits are
Status inputs to the SIO will cause status bits in the the mverse of the SIO lines, i.e., the DCD bit
Interrupts SIO to be set. In the Polled Mode, these status will be I when the DCD line is Low.
bits can be read by the CPU. In the Interrupt Any transihon in any direction (i.e., to 10glC
mode, the SIO can also be programmed to o or to logic I) on any of these inputs to the
interrupt the CPU when the change occurs. SIO will cause the related status bit to be
There are three such "external/status" condi- latched and (optionally) cause an mterrupt.
tions that can cause these events: The SIO status bIts are latched after a transI-
tion on anyone of them. The status must be
DCD. Reflects the value of the DCD input.
reset (using an SIO command) before new
CTS. Reflects the value of the CTS input. transihons can be reflected m the status bits.
Break. A series of logic 0 or "spacing" bits.
Initialization The SIO contains eight write registers for read registers, but register RR2 eXIsts only m
Channel B (WRO-WR7) and seven write Channel B.
registers for Channel A (all except write Let us now look at the typical sequence of
register WR2). These are described fully in write registers that are loaded to imtialize
the Z80 510 Technical Manual and are the SIO for eIther Polled or Interrupt-driven
summarized m Appendix B. The registers are asynchronous 1/0. Figure 4 illustrates the
programmed separately for each channel to sequence. Except for step E, this loadmg is
configure the functional personality of the done for each channel when both are used.
channel. WR2 exists only m the Channel B Steps E and F are described further m the sec-
regIster set and con tams the mterrupt vector hon on "Interrupt-Driven Environments."
for both channels. BIts in each register are Registers WR6 and WR7 are not used m
named D7 (most significant) through Do. With asynchronous 1/0. They apply only to syn-
the exception of WRO, programmmg the write chronous communicahon.
registers requires two bytes: the first byte is to The related pubhcahons on the SIO should
WRO and contains pOlnter bits for selection of be referred to at this point. They WI!! be
one of the other registers; the second byte is necessary in followmg the discussion of func-
written to the register selected. WRO is a hons. In particular, the followmg material
special case in that all of the baSIC commands should be reviewed:
can be written to it with a single byte. Z80SIO Technical Manual, pages 9-12
There are also three read registers, named ("Asynchronous Operahon")
RRO through RR2, from whIch status results
of operations can be read by the CPU (see Z80SIO Techmcal Manual, pages 29-37
Appendix B). Both channels have a set of ("Z80 SIO Programmmg")
2-52 2600030343
SECTION Polled Environments. which it is capable. Initialization for Polled I/O
In a typical Polled environment, the SIO 1S follows the general outhne descnbed in the
3 imtialized and then periodically checked for last section. We now give an overview of
completion of an I/O operahon. Of course, if routines necessary for the CPU to check
the checking 1S not frequent enough, received whether a character has been received by the
characters may be lost or the transmitter may SIO or whether the SIO is ready to transmit a
be operated at a slower data rate than that of character.
Character To check whether a character has been In any case, 1f bit Do of register RRO 1S 0,
Reception received, and to obtam a received character 1f polled rece1ve processing terminates with no
one is avaJlable, the sequence lllustrated m character to receive. Depending on the facil-
F1gure 5 should be followed after the SIO is 1hes of the associated CPU, th1S step may be
inihalized. We assume that recephon was repeated until a character is avaJlable (or
enabled dunng mihalizahon; 1f it was not, the poss1blya time-out occurs), or the CPU
Rx Enable b1t in register WR3 must be turned may return to other tasks and repeat th1S
on before recephon can occur. Th1s must be process later.
done for each channel to be checked. If b1t Do of register RRO 1S I, then at least
B1t Do of reg1ster RRO is set to I by the SIO one character is available to be read. In this
if there 1S at least one character avmlable to be case, the value of register RRI should first be
received. The SIO contams a three-character read and stored to avoid losmg any error mfor-
mput buffer for each channel, so more than mahon (the manner m which it is read is
one character may be available to be recelVed. explamed later). The character in the data
Removmg the last available character from the reg1ster is then read. Note that the character
read buffer for a parhcular channel turns off must be read to clear the buffer even if there 1S
bit Do. an error found.
If b1t Do of reg1ster RRO is 0, then no Finally, it 1S necessary to check the value
character 1S available to be received. In this stored from register RR I to determme if the
case it is recommended that checks be made of character rece1ved was valid. Up to three bits
bit D7 to determme 1f a Break sequence (null need to be checked: bit 6 1S set to I for a
character plus a frammg error) has been framing error, bit 5 1S set to I for a receiver
received. If so, a Reset External/Status Inter- overrun error (which occurs when the receive
rupts command should be given; this will set buffers are overwntlen, 1.e., no character has
the External/Status b1ts in register RRO to the been removed and more than three characters
values of the signals currently being received. have been received), and b1t 4 is set to I for a
Thus, 1f the Break sequence has termmated, panty error (if panty is enabled at inihal-
the next check of bit D7 will so indicate. It may ization hme). In case of a receiver overrun or
also be desirable to check bit 3 of reg1ster RRO parity error, an Error Reset command must be
which reports the value of the Data Carner glven to reset the bits.
Detect (DCD) bit.
2600030344 2-53
Character To check that an imtiahzed SIO IS ready to character to be transmItted to the SIO, com-
Transmission transmIt a character on a channel, and If so to pleting the transmIt processing. On the
transmit the character, the steps illustrated In Z80 CPU, thIs IS done WIth an OUT Instruction
Figure 6 should be followed. We assume that to the SIO data port.
the Request To Send (RTS) bIt In WR5, If
required by the external receiving deVICe,
and the TransmIt (Tx) Enable bIt were set at
Inlhahzahon.
Depending on the external receIving deVICe,
the following bIts In regIster RRO should be
checked: bit 3 (DCD), to determine If a data
carner has been detected; bIt 5 (CTS), to
determine If the deVICe has SIgnalled that it IS
clear to send; and bit 7 (Break), to determine
if a Break sequence has been receIved. If any
of these sltuahons have occurred, the bIls In
register RRO must be reset by sending the
Reset External/Status Interrupts command, and
the transmIt sequence must be started again.
Next, bIt 2 of regIster RRO IS checked. If thIs
bIt IS 0, then the transmIt buffer IS not empty
and a new character cannot yet be transmItted.
Depending on the capabIllhes of the CPU, thIs
IS repeated unhl a character can be trans-
mitted (or a hmeout occurs), or the CPU may
return to other tasks and start again later.
If bit 2 of regIster RRO IS I, then the transmIt
buffer IS empty and the CPU may pass the Figure S. Pelled Transmit
Assumptions Now let us consider some examples in more We specify this example by giving the con-
for an detail. We assume we are given an external trol bytes (commands) written to the SIO and
Example device to whICh we will input and output 8-bit the status bytes that must be read from the
characters, with odd panty, using the Auto SIO. Recall that to write a command to a regis-
Enables feature. We will support this device ter, except register WRO, the number of the
with I/O polling routines following the patterns register to be written is first sent to register
Illustrated in Figures 5 and 6. We assume that WRO; the follOWing byte will be sent to the
the CPU will provide space to receIve char- named regIster. SimIlarly, to read a regIster
acters from the SIO as fast as the characters other than RRO (the default), the number of the
are received by the SIO, and that the CPU will register to be read is sent to register WRO; the
transfer characters as fast as the output can be following byte WIll return the register named.
accomphshed by the SIO.
Initialization We begin with the initialization code for the Reset External/Status Interrupts commands as
SIO. This follows the outline illustrated In late as possible in the initialization so that the
Figure 4. In the following sample code, each status bits reflect the most recent information.
time reglSter WRO is changed to point to Since it doesn't hurt, we include these com-
another register, the Reset External/Status mands each time WRO is changed to point to
Interrupts command is gIven simultaneously. another register. This is an easy way to code
Whenever a transition on any of the external the initialization to insure that the appropriate
lines occurs, the bits reporting such a transi- resets occur.
tion are latched until the Reset External/Status In the example below, the logic states on the
Interrupts command is given. Up to two transi- c/lS control line and the system data bus
tions can be remembered by the SIO. There- (D7- Do) are illustrated, together with
fore, it is desirable to do at least two different comments.
2-54 26-0003-0345
Initialization Bit. sent to the 510
(Contmued) C/i) DB Ds D4 D3 D2 DO Effect. and Comment.
Reset and In the receive and transmit routines that fol- call for an "error sequence." This sequence
Error low, we treat errors such as a transition on the consists of giving the Error Reset command
Sequences Data Carrier Detect line by calling for a "reset and beginning the driver over again. The
sequence" to set the values in read register command also takes the form of a write to
RRO to reflect the current values found at register WRO:
the pins. This sequence consists of giving
DB DO
the Reset External/Status Interrupts com-
mand and beginning the driver over again. o o o o o o
The command takes the form of a write to Resets the latches In regIster RRJ.
register WRO:
When specifying the result of reading
DB DO register RRO or RRI or specifying data, we will
o o o o o o o indicate the values read as follows:
PermIts the stalus bIts in RRO to reflect current status. DO
This command does not turn off the latches D D D D D D D D
for such things as parity errors stored in bits Read a byte from the deSIgnated regIster..
4-6 of register RRl. When such an error
occurs and the latches must be reset, we will
Receive and Now we will first give an example necessary to execute an "error sequence" if it
Transmit of the receive routine. This parallels the is the only error received. However, it is not
Routines preceding discussion of "Character harmful to do so.
Reception." Next, we give an example of transmission
The framing error in this routine is reported code that parallels the above discussion on
on a character-by-character basis and it is not "Character Transmission."
2-55
Receive and Bits sent and received
Transmit C/o D6 Ds D4 D3 D2 Dl DO Effects and Comments (Receive Routine)
Routines
I D D D D D D D D Read a byte from RRa (the default read regIster); 11
(Continued) DO:= 0 then no character IS ready to be receIved. In
thlS case, 11 D7 (Break) or D3 (Data Carner Detect)
have changed state, then execute a "reset sequence."
If DO = 0 and D7 and D3 have not changed state, then
no character is ready to be receIved, eIther loop on
thIS read or try agam later.
I 0 a a 0 0 a 0 I Pomt WRa to read from RRI, we wIll now check for
errors In the character read Note that Reset Exter-
nal/Status Interrupt Commands are not done normally
to aVOld losmg a Ime-status change.
I D7 D6 Ds D4 D3 D2 Dj Do Read a byte from RR I; 11 eIther b,t D6 = I (frammg
error), D5 = (receIve overrun error), or D4::; 1
(panty error), the character IS mvahd and an "error
sequence" should be executed after the followmg step.
0 D7 D6 Ds D4 D3 D2 Dj Do Read m the data byte receIved. ThIs must be done to
clear the S10 buffer even If an error IS detected.
Interrupt The interrupt vector, register WR2 of Chan- to a different memory location for each inter-
Vectors nel B, is an 8-bit memory address. When an rupt condition. This is a very useful construct;
interrupt occurs (and note that an Interrupt it permits short, special-purpose interrupt
can only occur after interrupts have been routines. The alternative, to have one general-
enabled by writing to register WRl) the inter- purpose interrupt routine which must deter-
rupt vector is normally taken as one byte of an mine the situation before proceeding, can be
address used by the CPU to find the location quite inefficient. This is usually undesirable
of the interrupt service routine. It is also since the speed of interrupt-service routines is
possible to cause the particular type of inter- often a critical factor in determining system
rupt condition to modify the address vector in performance.
WR2 before branching, resulting in a branch
2-56
Interrupt There are at most eIght dIfferent types of Note that when a character IS received,
Vectors mterrupts that the SIO may cause, four for either the SpecIal ReceIve CondItion or Rx
(Contmued) each of the two channels. If bit 1 in register Character AvaJ!able mterrupt WIll occur,
WR1 of Channel B has been turned on so that depending on whether or not an error
an interrupt wJ!1 modify the interrupt vector, occurred; the two will never occur SImul-
the three bits (1-3) of the vector will be taneously. Therefore, these two interrupts have
changed to reflect the parhcular type of mter- equal prIOrity. Note also that you can select
rup!. These mterrupts follow a hardware-set not to be interrupted on some of the eIght con-
prIOrity as follows, starting WIth the hIghest d!llOns; m thIS case, the presence of a par-
prIOrity: ticular condihon for which interrupts are not
Channel A SpecIal ReceIve Condihon sets bits desired can be determined by pollmg.
3-1 of WR 1 to 111, Suppose that mterrupts have been enabled
for all possIble cases, and that the Status
Channel A Character ReceIved sets bIts 3-1 Affects Vector bit has also been enabled,
to 110, allowmg a different routine to handle each
Channel A TransmIt Buffer Empty sets bIts 3-1 possIble mterrup!. As each mterrupt causes a
to 100, branch to a location only two bytes hIgher than
Channel A External/Status Translhon sets bits the last interrupt, It IS not possIble to place a
3-1 to 101. routine dIrectly at the location where the vec-
tored mterrupt branches. In a Z80 CPU envi-
Channel B SpecIal ReceIve Condihon sets bIts ronment, these addresses refer to a table m
3-1 to all, memory which con tams the actual startmg
Channel B Character ReceIved sets bits 3-1 locahon of the mterrupt service routine. Also,
to 010, smce the state mformation saved by a CPU is
Channel B TransmIt Buffer Empty sets bIts 3-1 rarely all of the mformahon necessary to prop-
to 000, erly preserve a computahon state, a tYPICal
interrupt serVICe rout me will begin by saving
Channel B External/Status Transition sets bits addlhonal information and end by restoring
3-1 to 001. that informahon. This IS shown briefly m the
For example, suppose that the mterrupt vec- examples of code m AppendIx A.
tor had the value 1111000 1 and the Status It IS possIble to connect several SIOs usmg
Affects Vector bIt IS enabled, along WIth all the interrupt mechamsm and the lEI and lEO
interrupt-enable bIts. When an External/Status lmes on the SIO to determme a priority for
transition occurs m Channel A, the three zeros interrupt service. ThIS mechamsm is discussed
(bits 3-1) would be modified to 10 1, Yleldmg on page 42 of the Z80 SIO Technical Manual
an interrupt vector of 11111011. The value of and in the Z80 Family Program Interrupt
the interrupt vector, as modified, may be Structure Manual. We do not go mto it further
tained by reading regIster RR2 in Channel B. in thIS application note.
Initialization In general, the Imhalizahon procedure register other than register WRO, the number
illustrated in FIgure 4 can still be followed. All of the register to be written is first sent to
six steps (A through F) are required here. register WRO, and the followmg byte will be
After completing the first four steps, whICh are sent to the named regIster. SImilarly, to read a
the same as mihahzahon for polled 1/0, It IS register other than RRO (the default), the
necessary to load an interrupt vector mto WR2 number of the register to be read is first writ-
of Channel B. Information IS then written into ten to regIster WRO and the next byte read WIll
regIster WR1 specifying whICh interrupts are return the contents of the register named.
to be enabled and whether a specific kind of In our example below, each time regIster
mterrupt should modify the interrupt vector. WRO IS changed to pomt to another register,
Now let us give an example. As m the polled the Reset External/Status Interrupts command
example, we assume that we are gIven a IS also gIven. Whenever a transihon on any of
device to which we WIll input and output 8-bit the external/status lines occurs, the bits report-
characters, WIth odd parity, using the Auto ing the transItion are latched until the Reset
Enables feature. We also assume the CPU wJ!1 External/Status Interrupts command is given.
provide space to store characters as received. Up to two transItions can be remembered by
We do not discuss the SIO commands and the mternal logIC of the SIO. Therefore, it is
registers in detail. ThIS IS done in the Z80 SIO desirable to do at least two different Reset
Technical Manual. A summary of the regIster External/Status Interrupt commands as late as
bIt assignments taken from the Z80 SIO Serial possible in the imhahzation so that the status
Input/Output Product Specification IS included bits reflect the most recent information. Smce
at the end of this note. Recall that to write a It doesn't hurt, we give these commands each
2-57
.~~" ...,-~--~---~ - -. --_.----------~~~---.--'-:::-----------~~----
Initialization time WRO is changed to point to another reg- The .olumns below show the logic states on
(Continued) ister. This is an easy way to code the initial- the C/D control line and the system data bus
ization to assure that the appropriate resets (D7-DO), together with comments.
occur.
2-58
Special A Special Receive Condition interrupt value of register RR 1 to gather statistics on
Receive occurs (a) If a parity error has occurred, (b) if performance or determine whether to accept
Condition there is a receiver overrun error (data is being the character. In some applications, a
Interrupts overwritten because the channel's three-byte character may still be acceptable if received
receiver buffer is full and a new character is with a framing error.
being received), or (c) if there is a framing In specifying the result of reading register
error. The processing in this case is the fol- RRO, RRl, or specifying data, we will indicate
lowing: the values as follows:
1. Issue an Error Reset command (to register 0., DB Ds Dc D3 D2 Dl Do
WRO) to reset the latches in register RRI. DID I DID I D D D D
2. Read the character from the read buffer and Read a byte from the deslgnated reglster.
discard it to empty the buffer. We now present an example of processing a
It may be deSirable to read and store the Special Receive Condition interrupt.
Received (Rx) When an Rx Character Available interrupt with character lengths of 5, 6, or 7 bits, the
Character occurs, the character need only be read from received parity bit will be transferred with the
Interrupts the read buffer and stored. If parity is enabled character. Any unused bits will be Is.
Transmit (Tx) The final kind of interrupt is a Tx Buffer rupts until the next character has been loaded
Buffer Empty Empty interrupt. If another character is ready into the transmitter buffer.
Interrupts to be transmitted on this channel, a Tx Buffer The Reset Tx Interrupt Pending command to
Empty interrupt indicates that it is time to do WRO takes the following form:
so. To respond to this interrupt, you need only DO
send the next character. If no other character
is ready to transmit, It may be desirable to o I 0 I o o
mark the availability of the transmit mechanism Reset Tx Interrupt Pendmg command; no Tx Empty Inter-
for future use. In addition, you should send a rupts wlll be glven unl1l after the next character has been
Reset Tx Interrupt Pending command. This placed m the transmlf buffer.
command prevents further transmitter inter-
_ 2-59
Z8D To take these examples further, let us use SIOdata. The address of the S10's Channel B
Assembler Z80 Assembler code to implement the routines data port.
Code for a single channel. We assume that the loca- X. An address pointing to locations in memory
tion stored in register WR2 points to the that will be used to store various values.
appropriate interrupt service routine. We also
assume that the following constants have We wIll write data as binary constants; the
already been defined: "B" suffix indicates this. In most cases, binary
constants will be referred to by the command
SIOctrl. The address of the S10's Channel B names. We begin with the initialization
control port (we assume Channel B in order to routine:
include code to initialize the interrupt vector).
INIT: LD C,SIOctrl ;place the address of the SIO m the C regIster for
; use In subsequent output
LD A,OOOllOOOB ;load Channel Reset command In A reglster
OUT (C) ,A ;glve Channel Reset command
Now let us look first at some sample codes This is followed by a simple receive interrupt
for the Special Receive Condition interrupt routine that will fetch the character received
routine, following the example above. and store it in a temporary location.
SIOspecmt: PUSH AF ;save regIsters whIch WIll be used In thls routme
LD A,OOOOOOOIB ;wnte to regIster WRO pomtmg It to regIster RRI
OUT (SIOctrl) ,A
IN A,(SIOctrl) ;fetch regIster RR I
LD (X) ,A ;store result for later error analYSIS
LD A,OOIIOOOOB ;send an Error Reset command to reset deVIce
; latches
OUT (SIOctrl) ,A
IN A,(SIOdata) ;fetch the character receIved-we wIll dIscard thIS
; character smce an error occurred durmg ItS
; receptIon
POP AF ;restore saved regIsters
EI ;enable mterrupts
2-60
zao SIOrecmt: PUSH AF ;save regIsters which WIll be used In thIs routIne
Assembler IN A,(SIOdata) ;feich the character receIved
Code LD (X) ,A ;store result for later use
(Continued) POP AF ; restore saved regIsters
EI ;enable mterrupts
RET! ; return from mterrupt
Of course, thIs last routIne IS probably far chapter entitled "A Longer Example."
too SImple to be useful. It IS more likely that We now gIve a sImple Interrupt routIne for
an Interrupt routIne wIll fIll up a buffer of an External/Status Interrupt, agaIn assumIng
characters. A more complex example of a that the status contents of SIO regIster RRO are
receive interrupt routIne IS contaIned in the stored in temporary locallon X:
FInally, we gIve the proceSSIng for a routIne whICh would transmIt a buffer-full of
transmIt Interrupt routine in the case where no informalIon at a lIme. A more complex exam-
more characters are to be transmItted. ple IS Included In the seclIon enlItled "A
It IS lIkely that thIS code would Just be a por- Longer Example."
lIon of a more general transmIt Interrupt
2-61
SECTIOR Questions and Answers.
Q: Can a sloppy system clock cause prob- A: No, prOVIded that setup hmes speclhed for
S lems m SIO operabon? the SIO are met.
A: Yes; the speclhcabons for the system Q: If the Auto Enables bIt m regIster WR3 IS
Hardware clock are very hght and must be met closely set, WIll a change m state on the DCD (Data
Considerations to prevent SIO malfunchon. The clock hIgh Carner Detect) or CTS (Clear To Send)
voltage must be greater than Vcc - 0.6V but lmes shll cause an mterrupt?
less than +5.5V. The clock low voltage A: Yes, prOVIded that External/Status Inter-
must be greater than - 0.3V but less than rupts are enabled (bit 0 m register WR1).
+0.45V. The translhons between these two
levels must be made m less than 30 ns. ThIs Q: Is the Ml lme used by the SIO If no mter-
does not apply to the RxC and TxC mputs rupts are enabled?
whICh are standard TTL levels. A: No, and m thIS case the Ml mput should
Q: When IS a receIved character avaJlable to be bed hIgh.
be read? Q: WIll the SIO continue to mterrupt for a
A: Data wlll be avallable a maxImum of 13 condlhon If the condItion persIsts and the
system clock cycles from the nsmg edge of mterrupt remams enabled?
the RxC SIgnal whICh samples the last bIt of A: Yes.
the data.
Q: What is the maXImum data rate of
Q: What IS the maxImum hme between the SI07
character-mserhon for transmlSSlOn and A: It IS 115 the rate of the system clock
next-character transmIssIon? (CLK). For example, If the system clock
A: ThIs wIll vary dependmg on the speed of operates at 4 MHz, the SIO's maxImum
the lme over whIch the character IS bemg transfer rate IS 800K bts (lOOK bytes)
transmItted. per second.
Q: Are the control lmes to the SIO synchro- Q: What pms are edge senslhve and should
nous wIth the system clock so that nOlse may be strapped to aVOld strange mterrupts?
eXIst on the buses any bme before setup A: The external synchromzahon (SYNC) pms
reqUIrements are sallshed? and any other external status pms that are
A: Yes. not used, mcludmg CTS, and DCD.
Q: In asynchronous use must recelVer and Q: What happens if the transmItter or
transmItter clock rates be the same? receIver IS dIsabled, whIle processmg a
A: No, the SIO allows receIve and transmIt character, by turmng off ItS assocIated
for each channel to use a different clock enable bIt (bIt 3 m register WR5 for transmIt
(thus up to four dlfferent clocks for recelV- or bIt 0 m regIster WR3 for rec81ve)?
mg and transmlttmg data can be used on A: The transmItter WIll complete the
each SIO). However, the clock mulhpher character transmlSSlOn m an orderly fashIon.
for each channel must be the same. The receIver, however, wlll not hmsh. It WIll
Q: Do Walt states have to be added when lose the character bemg receIved and no
usmg the SIO wIth other processors other mterrupt WIll occur.
than the Z80 CPU?
Register Q: Does the Tx Buffer Empty (bIt 2 m regIster A: The most recently receIved character
Contents RRO get set when the last byte m the buffer overwnles the next most recently receIved
IS m the process of bemg shlfted out? character.
A: No. The hI IS set when the transmIt buffer Q: Does the Reset External/Status Interrupts
has already become empty. SImIlarly, the command reset any of the status bIts m
Tx Buffer Empty mterrupt WIll not occur regIster RRO?
unhl the buffer IS empty. The same IS true A: No. However, when a transltlOn occurs on
for recephon: the Rx Character AvaIlable any of the hve External/Status bIts m
bt (bIt 0 m regIster RRO) IS not set unhl the regIster RRO, all of the status bIts are
enhre character IS m the receIve buffer, and latched m theIr current poslhon untd a
the Rx Character AVallable mterrupt WIll Reset External/Status Interrupts command IS
not occur unhl the enhre character has lSsued. Thus, the command does permIt the
been moved mto the buffer. appropnate bIts of regIster RRO to reflect
Q: If an Rx Overrun error occurs (and the current SIgnal values and should be
bIt 5 of regIster RRI becomes latched on) done ImmedIately after procebsmg each
because a new character has arnved, whICh translhon on the channel.
character gets lost?
2-62
Special Q: If the CPU does not have the return from Q: How can the SIO be used to transmIt
Uses mterrupt sequence (RETI instruchon on the characters contammg fewer than 5 bIts?
280 CPU), how may the SIO be mformed of A: FIrst, set bits 6 and 5 m regIster WR5 to
the complehon of mterrupt handlmg? mdICate that hve or fewer bIts per character
A: ThIs may be done by wntmg the Return WIll be transmItted. The SIO then deter-
From Interrupt command (bmary, 00111000) mmes the number of bits to actually transmit
to WRO m Channel A of the SIO. from the data byte itself. The data byte
Q. If the CPU can be mterrupted but cannot should consIst of zero or more Is, three Os,
be used wIth vectored mterrupts, how and the data to be transmItted. Thus, begm-
should processing be done? nmg the data byte WIth 11110001 will cause
A: ImmedIately after bemg interrupted, pro- only the last bIt to be transmItted:
ceed m a manner SImIlar to polling the SIO Contents of data byte
(d = arbitrary value)
for both receIve and transmit. Alternahvely,
the Status Affects Vector bIt (bIt 2 in D7 D6 D5 D4 D3 D2 D] Do
regIster WRl) may be set and a 0 byte I I I I 0 0 0 d I
I I I 0 0 0 d d 2
placed mto the interrupt vector (regIster I I 0 0 0 d d d 3
WR2 in Channel B). Then, the contents of I 0 0 0 d d d d 4
the interrupt vector can be used to deter- 0 0 0 d d d d d 5
mme the cause of the mterrupt and the 'The rIghtmost number of bits mdlcated will be transmitted
channel on whIch the mterrupt occurred.
ThIS can be quened by readmg regIster RR 1 Q: Can a Break sequence be sent for a hxed
of Channel B. Also, Ml should be hed HIgh number of character peTlods?
and no eqUIvalent to an interrupt acknowl- A: Yes. Break IS continuously transmItted as
edge should be issued. logIC 0 by settmg bIt 4 of register WR5. You
Q: How can the Walt/Ready (W/RDY) SIgnal can then send characters to the transmItter
be used by the CPU m asynchronous I/O? as long as the Break level IS desired to per-
A: The W/RDY signal is most commonly used SISt. A Break signal, rather than the char-
m Block Transfer Mode WIth a DMA, and acters sent, WIll actually be transmItted, but
thIS use IS described in the Z8G DMA each bIt of each character sent w!ll be
Technical Manual. However, W/RDY may clocked as If It were transmItted. The All
be dIrectly connected to the 280 CPU WAIT Sent bit, bit 0 of regIster RR1, IS set to 1
Ime m order to use the block 1/0 instruc- when the last bit of a character IS clocked
hons OTDR, OTIR, INDR, and INIR. In thIS for transmIssIOn, and thIS may be used to
case, the SIO can be used for block transfer determme when to reset bit 4 of regIster
recephon. To do thIS, the SIO is configured WR5 and stop the Break signal.
to interrupt on the hrst character received Q: If a Break sequence IS mitiated by setting
only (by settings bits 4 and 3 of regIster bit 4 of regIster WR5, WIll any character
WRI to 01) and addihonal characters are m the process of bemg transmitted be
sensed using the W/RDY line. The block 1/0 completed?
mstruchons decrement a byte counter to A: No. Break is effechve immedIately when
determine when I/O IS complete. bit 4 of WR5 is set. The "all sent" bit in
regIster RRI should be mOnitored to deter-
Q: Can the SYNC pin have any use in asyn-
mine when It IS safe to Inlhate a Break
chronous I/O?
sequence.
A: It may be used as a general-purpose
mput. For example, by connecting It to a
modem ring indicator, the status of that ring
mdICator can be monitored by the CPU.
2-63
YES
YES
YES NO
RETURN
2-66
Receiver Buffer Initialization Receive Character Routine (see Figure 10)
Buf_Imt. LD A,BufLength 111 receiver buffer
I RxChar. PUSH AF
LD B,A Iwith FF characters PUSH BC
LD HL,RBuffer ; to detect errors
LD A,SIOAData
LD A,OFFH
LD C,A
Buf_l LD (HL),A ,a loop for Buf_Imt IN A,(C) ,get character
INC HL LD B,A
DJNZ Buf_l LD A,(RBufCtr)
RET CP BulLength
BufLength: EQU BO ; buffer length JR Z,Over
XBuffer' DEFS BufLength ,Tx buffer starting location INC A ;bump counter
RBuffer. DEFS BufLength ,Rx buffer starting location LD (RBufCtr),A
XBufPtr DEFS 2 ,Tx pOinter LD A,B
RBufPtr DEFS 2 ;Rx pOInter LD HL,(RBufPtr) ,bump pOinter
RBulCtr. DEFS ,Rx counter LD (HL),A
INC HL
LD (RBufPtr),HL
CP CR
Transmit Routine (see Figure 8)
JR NZ,RxExlt
InIhates transmiSSIon of a buffer-full of data and terminates when
an error IS detected or a complete buffer has been received LD A,Complete
LD (RxStat),A
RxStat DEFS ,Receive Status Word
JR RxExlt
TxStat DEFS ,Transmit Status Word
Over LD A,Overflow ,mdlcate error
Complete EQU I
LD (RxStat),A
CR' EQU ODH
Break EQU BaH RxEXlt POP BC
EOM EQU BaH POP AF
Overflow EQU OFFH EI
RET!
Transfer LD HL,XBuffer ,setup to begIn Tx
INC HL
Special Receive Condition Routine (see Figure II)
LD (XBufPtr),HL
LD HL,RBuffer SpRxCond: PUSH AF
LD (RBufPtr),HL PUSH BC
XOR A ,A=O LD A,SIOAData
LD (RBufCtr),A LD C,A
LD (TxStat),A LD A,RI ,get RRI
LD (RxStat),A INC C
LD A,SIOAData ;start Tx task OUT (C) ,A
LD C,A IN A,(C)
LD HL,(XBuffer) ,1rst character LD (RxStat),A ,save status
LD A,(HL) LD A,ER ; Reset Errors
OUT (C),A DEC C
OUT (C),A
Tloop. LD A,(TxStat) ,await Tx complehon or error
DEC C
CP a
IN A,(C) ;get character
RET NZ
LD A,(RxStat) POP BC
CP Overflow POP AF
RET Z EI
CP Complete RET!
RET Z
JR NZ,Tloop External/Status Routine (see Figure 12)
RET ExtStatus: PUSH AF
PUSH BC
Transmitter Buller Empty Routine (see Figure 9)
LD A,SIOACtri
TxBEmpty PUSH AF
LD C,A
PUSH BC
IN A,(C) ;get RRO
PUSH HL
LD (TxStat),A
LD HL,(XBufPtr) LD A,RESI ,Reset Ext Stat Int
LD A,SIOAData OUT (C),A
LD C,A
POP BC
LD A,(HL)
POP AF
OUT!
EI
CP CR
RET!
JR NZ, TxBExit ,last character?
END
LD A,RT!P ,Reset Tx Int Pendmg
INC C
OUT (C),A ; to control port
TxBExit LD (XBufPtr),HL ;save pomter
POP HL
POP BC
POP AF
EI
RET!
2-67
Appendix B
Read Register Bit Functions
READ REGISTER 0
III ~I L-
IL..== R,
INTCHARACTER
PENDING (CHAVAILABLE
~~~UFFER EMPTY
A ONLY)
}
SYNC/HUNT
CTS
Tx UNDEARUN/EOM
BREAK/ABORT
READ REGISTER 1t
, . .
, , , , ,I
1010101010101010
L-ALLSENT
III
1
0
0
1
0
0
I FI ELO BITS
o
I FIELD BITS IN
IN PREVIOUS SECOND PREVIOUS
BYTE
o
BYTE
3
4
}
1 1 0 o 5
0 0 1 o 6
1
~
1~~ ~
0 1
:
o 0 0 2 8
READ REGISTER 2
2-68
Appendix C
Write Register Bit Functions
.
WRITE REGISTER 0 WRITE REGISTER 4
, , , , 0, 100 1
10, 10101010101
I I I
0 0 0 REGISTER 0
0 0 1 REGISTER 1
0 1 0 REGISTER 2
0 1 1 REGISTER 3 SYNC MODES ENABLE
1 0 0 REGISTER 4 1 STOP BIT/CHARACTER
1 0 1 REGISTER 5 1 '12 STOP BITS/CHARACTER
1 1 0 REGISTER 6 2 STOP BITS/CHARACTER
1 1 1 REGISTER 7
8 BtT SYNC CHARACTER
0 0 0 NUll CODe 16 BIT SYNC CHARACTER
0 0 1 SEND ABOR T(SDLC) SOLe MODE (01111110 FLAG)
0 1 0 RESET EXTISTATUS INTERRUPTS EXTERNAL SYNC MODE
0 1 1 CHANNEL AESET
1 0 0 ENABLE tNT ON NEXT Rx CHARACTER X1 CLOCK MODE
1
1
1
0
1
1
1
0
1
ERROR RES ET
RESET TxlN T PENDING
NULL CODe
RESET Rx CRG CHECKER
REseT Tx CRG GENERATOR
REseT Tx UNDERRUN/EOM LATCH
~ ! ~)~i ~~~~:~~::ARtT~TRESR(PARITY
1 1
AFFECTS VECTOR) }
INT ON ALL Rx CHARACTERS (PARITY DOES NOT AFFECT
o
o
1
0
1
0
Tx
Tx
Tx
5 BITS (OR LESS)/CHARACTER
7 BITS/CHARACTER
6 BITS/CHARACTER
VECTOR) 1 1 Tx 8 BITS/CHARACTER
WAIT/READY ON RIT
WAIT/READY FUNCTION
oTR
'----WAIT/READy ENABLE
I~I~I~I~I~I~I~I~I
IIII I~SYNC
L- R,ENABLE
CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SOLC)
Rx CRC ENABLE
ENTER HUNT PHASE
AUTO ENABLES
IIIII1 l'=l1E!!H'lSYNC
SYNC
SYNC
BIT
BIT
BIT
11
12
13
SYNC BIT 14
SYNC BIT 15
Rx 5 BITS/CHARACTER
Rx 7 BITS/CHARACTER 'For SOLe 11 Must
Rx 6 BITS/CHARACTER to 01111110' For
Rx 8 BITS/CHARACTER
2-69
Usilg the Z80 SIO With SOLe
~
Zilog Applcation Brief
Man:h 1981
INTRODUCTION This application brief describes the use of The reader shou I d be familiar with hardware
the Z80 SIO with the Increasingly popular aspects of the SIO such as Interfacing to the
Synchronous Data Link Control (SOLC) com- CPU and a modem. A more detailed description
munications protocol. A general description of the SOLC protocol Is given In the IBM
of the SOLC protocol and Implementation of publication Synchronous Data Link Control
the protocol using the SIO are discussed. General Information (document # GA27-3093-2).
Descriptions for transmit and receive opera- A description of the Z80 SIO can be found In
tions are given for use with simple contol the Zllog Data Book (document # 0D-2034-A).
frame sequences.
DESCRIPTION Data communication today requires a communi- b Ii shed for a part I cu I ar dev ice, the other
cation protocol that can transfer data devices Ignore the message until the next
quickly and reliably. One such protocol, flag character Is detected.
Synchronous Data Link Control (SOLC), Is the
link control used by the IBM Systems Network The address field contains one or more octets
Architecture (SNA) communication package. that are used to select a particular station
SOLC Is actually a subset of the Interna- on the data I Ink. An address of all Is Is a
tional Standards Organization (ISO) link global address code that selects all the
control cal led High Level Data Link Control dev I ces on the Ii nk. When a pr Imary stat Ion
(HOLC), which Is used for International data sends a frame, the address fie I dis u sed to
communication. select a secondary station. When a secondary
station sends a message to the primary sta-
tion, the address field contains the secon-
SOLC Is a Bit-Oriented Protocol (BOP). It dary station address, I.e., the source of the
differs from Byte-Control Protocols (BCPs), message.
such as bisync, In having a few bit patterns
for control functions Instead of several
special character sequences. The attributes The control field follows the address field
of the SOLC protocol are position dependent and contains Information about the type of
rather than character dependent, so control frame being sent. The control field consists
Is determined by the location of the byte as of one octet and Is always present.
well as by the bl t pattern.
The Information field consists of zero or
more 8-blt octets and contains any actual
A character In SOLC I s sent as an octet, a data transferred. However, because of the
group of eight bits. Several octets combine limitations of the error-checking algorithm
to form a message frame I n such a way that used In the frame-check sequence, maximum
each octet belongs to a particular field. recommended block size Is approximately 4096
Each message frame consists of an opening octets.
flag, address, control, Information, Frame
Check Sequence (FCS), and closing flag The Frame Check Sequence (FCS) follows the
fields. The flag field contains a unique Information field or the control field, de-
binary pattern, 01111110, which Indicates the pend I ng on the type of message frame sent.
beginning and end of a message frame. This The FCS Is a 16-blt Cyc II c Redundancy Code
pattern simplifies the hardware Interface in (CRC) of the bits In the address, control,
receiving devices so that multiple devices and Information fields. The FCS Is based on
connected to a common Ii nk do not con f Ii ct the CRC-CCITT code, which uses the polynomial
with one another. The receiving devices (XI6+XI2+X5+1). The Z80 SIO contains the
respond only after a valid flag character has circuitry necessary to generate and check the
been detected. Once communication Is esta- FCS flel d.
XXXXll111110111111O
'-------'~
Abort Flag
b) Abort Condition
XXXX111111111111111
Idle
c) Idle Condition
617-1564-0001 272
PROGRAKI4I NG Implementation of the SOLC protocol with the Once the SID is Initialized and the trans-
THE 510 Z80 510 Is simplified by the design of the mitter Is enabled, It sends flag characters
510. This section discusses four areas of continuously until a message begins trans-
510 programming: Initialization, transmit mission. These flag characters consist of
operation, receive operation, and exception the ful I 8-blt pattern. Although the 510 can
condition processing. rece I ve flag characters with shared Os
(011111 101 1 I 11 101 I 11110 ) , It can on I y
Initialization defines the basic mode of
transmit flag characters without shared Os
operation for the 510. Table I shows the
(0111 I 110011 I 111001111 I 10 ).
sequence of steps used to Initialize the 510,
along with the necessary parameters. Since
vectored interrupts are used, the 510 is pro-
grammed with the status affects vector (SAV) Table I. 510 Initialization Sequence
bit (WR1, bit 2) set.
Register Data Function
Other function bits that can be Included are
the externa I Interrupt enab Ie bit (WR 1, bit 0 00011000 Channel reset
0), which results In an interrupt for each 2 (Vector) I nterrupt vector
OCO or CTS change, TX underrun or abort lower eight bits
change; address search bit (WR3, bit 2), (channel B only)
wh I ch when set, prevents the 5 I0 from res- 4 00100000 SOLC mode
ponding to data received unless the address I 00011 I I I Interrupt control
byte matches the contents of WR6 or the 6 (Address) RX address field
global (FFH) address; auto enable bit (WR3, 7 01 I I I I 10 Flag fi el d
bit 5), which causes the inactive CTS level 5 1110101 I TX character length,
to disable the transmitter and the Inactive enable, CRC enable
OCO level to disable the receiver; and OTR RTS and OTR
(WR5, bit 7) and RTS (WR5, bit 1), which can 3 11001001 RX character length,
be used to control a modem or other such enable, and CRC
device. enable
TRANSMIT After the SID has been Initialized and tion, sending a character to the SIO, and re-
<PERATION enabled, It can begin sending SOLC frames by setting the TX underrun/EOM latch In the 510.
software activation of the transmitter. Figure 3 shows the sequence for transmitting
Activating the transmitter includes resetting a typical control message frame using Inter-
the transmitter inactive semaphore (a program rupts.
indicator), resetting the Tx CRC accumula-
SOLC Tx
Control Message Frame
I
XXXXXXOllll110
I
I Address Control I CRC-l CRC-2 0111 I 110
I
Control
I
Check error conditions;
to SIO Update semaphores
SOLC RX
ContInuous
flags
I
Store data Store
(If desIred) data
I I Store Set semaphores (If character
data Check errors; Is not dIscarded
Error Reset; by SRC routIne.
Olscard thIs RCA Interrupt
Character* occurs. )
NOTES
* The SRC routIne normally reads the data character to clear the
SIO buffer. ThIs should be done after the program Issues an Error
Reset command.
617-1564-0007 275
EXCEPTION Most of the exception conditions encountered done by act i vat I ng a timer when the ESC I n-
CONDITION in the SOLC protocol have been discussed in terrupt that signals a mark I ng line occurs.
the previous sections. They Include abort I f another ESC interrupt occurs before the
CPERATION
detect and OCO or CTS change. This section timer times out, the line Is In an abort
further describes some of the more unusua I condition. If the timer times out before
conditions. another ESC interrupt occurs, then the line
I sid Ie and the program can pursue an appro-
OCO and CTS Change. The program handles OCO priate course of action. A possible mech-
and CTS change by updating Its semaphores anism for Implementing the timer function is
each time an ESC interrupt occurs. In this to use a programmable counter that Is tied to
manner, the program on the next higher level the rece I ve clock line to count bl ts. The
monitors the semaphores and determines a counter Is programmed for eight clock tran-
course of act ion based on what these sema- sitions and is started as soon as the SIO
phores indicate. Interrupts the CPU with an abort condition.
Only eight clock transitions need to be
Abort and Idle Line Detect. Abort and idle counted because by the time the SIO generates
line detect are a bit more complicated, since the ESC interrupt, at least seven Is have
they resu It in similar Interrupt operations. already passed. Figure 6 shows the abort/
An abort occurs during a valid message frame. Idle line timing and the interrupts resulting
If the abort time is greater than 14 bits, an from the line changes.
idle line is detected. This detection can be
CONCLUSION This brief describes Implementation of the rupts occur for each data byte received.
SOLC protocol using the SIO In an Interrupt-
driven environment. Descriptions for trans- The Z80 SIO enhances system performance by
mit and receive operations are given for use minimizing CPU Intervention during data
with simple control frame sequences. For transfers us I ng the SOLC protocol. Perfor-
frames that transfer data, the sequences are mance can be Improved further by us i ng the
similar except for transmit, where a data Z80 OMA with the SIO, resulting In an effi-
character Is sent to the S I 0 for a TBE I n- cient system configuration that reduces CPU
terrupt. For receive, multiple RCA Inter- Interaction to a minimum.
APPENDIX Following Is the listing of a simple SIO test sent. If the response timer expires, the
progam that uses the SOLC protocol. This program on the next higher Ieve I norma Ily
program uses vectored interrupts to send a retransmits the message frame (If the re-
short SOLC control frame consisting of Ad- transmit count has not yet expired). This
dress 9EH, Control 19H, and Data 81H. The program transmits continuously until the
response timer times the response of the processor is reset or I nterrupted by an ex-
receiving station after a message has been ternal source.
TEST SOLC
LOC OBJ CODE M STMT SOURCE STATEMENT ASM 5 9
SID SOLC TEST PROGRAM
2
3 , [0] 01--21-811MOP INITIAL CREATION
4
~
Zilog Application Note
October 1980
A popular communication protocol used to (Figure 1). The header Is made of two or
exchange Information between data processing more SYN characters (hence the name bisync),
devices has been In use for some time. This a start of header (SOH) character, and ad-
protocol, developed by IBM, Is called binary dressing and control Information for a par-
synchronous protocol, or bisync. The zao SIO ticular slave station.
provides a flexible and powerful tool for the
Implementation of the bisync protocol. How-
ever, there are some design considerations
that require special attention. This paper S S S S E B P
will discuss these design considerations and Y Y 0 T T C A
offer an approach to using bisync with the
N N H X X C D
zao SIO. Specific examples are presented and
readers who are unfaml liar with the bisync ,,--~ 'V
protocol should refer to the ANSI standard Header Body Trailer
(1) or the IBM publication (2) listed at the
end of this paper. Figure 1. Basic Message Block Format
for Bisync Protocol
Bisync Is a character-oriented protocol with
Information transmitted In blocks between two
(or more) data communication devices. The
medium through which this Information Is The body begins with a start of text (STX)
conveyed Is cal led the data link. The par- character and encompasses the entire text
ticular data link discussed In this paper Is Information. The body generally contains
a polnt-to-polnt link using the ASCII trans- ASCI I text data, although a-bit binary data
mission code. Other codes, such as EBCDIC, can be transmitted using transparent text
are not covered, but the format for bisync Is mode.
basically the same. The data link consists
of a master station (usually a computer) and The trailer contains the end of text (ETX)
a slave station (usually a terminal) with the character and the block check character
associated communication gear In between-- (BCC). The Bec Is used for detecting errors
modems, phone lines, etc. The master station through "cyc I Ic redundancy check I ng" (CRC) or
controls message flow by pol ling and select- "Iongltudal redundancy checking" (LRC).
Ing the slave station. Polling Involves send-
Ing a general request message to the slave Error detection Is essential when transfer-
statlon(s) to determine whether or not any of ring Information between data processing
the slaves have data to send (traffic). If a equipment. Since ASCII specifies only seven
slave station does have traffic, It responds bits for Its code, the eighth bit Is used for
to the poll and the master can then select vertical redundancy checking (VRC), more
that particular slave for information ex- commonly known as character parity. In syn-
change. S laves can on Iy respond to a master chronous communications, character parity Is
device and cannot Initiate communication on generally odd, whereas In asynchronous com-
the data II nk. munications It Is even. Figure 2 shows typi-
cal ASCII characters with parity. The SIO
Information Is exchanged by means of a wei 1- can be programmed for 7-bit characters with
defined block structure. Message blocks odd parity enabled to minimize software over-
consist of a header, body, and trailer head.
Since It Is assumed that Interrupts wll I be Using the 510 for the bisync protocol Is
used with the 510, an Interrupt driven re- fairly straightforward. Care should be exer-
ceiver timer count Is kept In memory and Is cised when using the 510 In transparent text
relnltlallzed each time a character Is re- mode, but the Implementation Is greatly
ceived (receive Interrupt). The same applies simplified by the SIO's flexibility, as com-
for the response timer, except that when a pared to other serial communications ICs.
timeout occurs, the transmit driver has The CRC capabilities of the 510 provide a
several options to follow. powerful means of maintaining maximum data
Integrity with minimum software overhead.
If the 510 Is set to transmit CRC on transmit Coupled with the DMA and the Interrupt capa-
underrun, then the driver could simply set bilities of the zao processor, the user will
Its flags and not fill the buffer. This find the 510 an excellent choice In serving
al lows a normal exit, since the SIO wll I then data communication needs.
send Its CRC bytes. If the 510 Is set to not
transmit CRC on transmit underrun, then It
sends sync characters (SYN SYN or DLE SYN,
Whichever was last written to WR6 and WR7) (1) American National Standards Institute.
until the transmit buffer Is fll led or trans- ANSI X3.28 - 1976.
mit data Is set to marking.
(2) "General Information - Binary Synchronous
In any event, enough time must be allowed Communications." Pub. number GA27-
after CRC Is sent so that the receiver can 3004-2.
~
Zilog Application Brief
January 1981
INTRODUCTION Serial data communication Is among the most asynchronous communication channels for a
widely used forms of exchanging Information Z8D-based system.
with and between computers. The rap Id ex- This application brief describes the use of
pansion of this form of communication has the Z80 DART In a Z80-based system. Further
created the need for low-cost, efficient, and Information on the Z80 CPU and Z80 DART Is
flexible peripheral devices that provide the available In the Zliog Data Book (document
user with a wide variety of options. The Z80 number 00-2034-A), Z8400 Z80 CPU Product
DART Is designed to fill th Is need by pro- Specification {document number 0D-2001-Al,
viding two Independently programmable, and the Z8470 Z80 DART Product Specification
(document number 0D-2044-A).
HARDWARE The hardware for this application consists of The DART-ta-CPU Interface consists of eight
a Z8400 Z80 CPU, Z8470 Z80A DART, Z8536 Cia, bidirectional data lines, seven control
4K ROM, and 4K RAM. Figure 1 shows a block lines, and three daisy chain Interrupt con-
diagram of the system. The cia supplies the trol II nes. The data II nes are used to
bit rate clock for the DART and allows the transfer data between the DART and the CPU.
baud rate for each channel to be determ I ned The direction of data flow on the data lines
by the software. Is determined through the use of the eE, RD,
4K 4K
ROM RAM
Z8400
Z80A
ADDRESS I I
CPU
DATA
I
--
IOSCILLATOR ~ 1 Z8538
CIO
w= TxCA
- -
RxCA
---
Z8470
Z80A DART
~ TxRxCB
CHANNEL A CHANNEL B
J U III IIIII
RS 232C RS 232C
INTERFACE INTERFACE
~
t ~ ~
t ~.
TO MODEM TO MODEM
FIgure 1. ZSO System Block Diagram
Aa
L 74LS139
3P
2p
Status Affects Vector (SAV) programml ng op-
tion. I nterrupts are prIoritized Internally
In the DART according to the various condi-
tions. There are four separate Interrupt
AI 1
-CE groups for each channe I. Tab I e 2 shows the
relative priorities of these Interrupts.
Op
-AlB Table 2. DART IIrterrvp1" Priority
c/o
PriorIty Function
NOTE Only the lower elght blts of the
address bus are used for I/O select Highest Ch. A Special Rx Condition
Figure 2. DART Deylce Select logIc Ch. A Rx Char. AvaIlable
Ch. A Tx Buffer Empty
External connections to the Z80 DART Include Ch. A External/Status Change
ser I a I data and contro I II nes and modem con- Ch. B Special Rx Condition
trol lines. The serial data lines are Ch. B Rx Char. Available
TransmIt Data (TxD) and ReceIve Data (RxO) Ch. B Tx Buffer Empty
for each channel. Separate transmit and Lowest Ch. B External/Status Change
~
c) DARCA-Channel A Receive
Character Interrupt Routine
SAVE REGISTERS
a) Main Program
d) DAESC-Channel A
External/Status Change
Interrupt Routine
b) DATBE-DART Channel A
Transmit Buffer Empty
Interrupt Service Routine
NOTE.DARCA,DAESC,AND
DASRC are dummy routInes.
e) DASRC-Special Receive
Condition Interrupt Routine
~
Zilog Application Brief
December 1980
INTRODUCTION There are several differences between the ture of the 8500 series peripherals In l80
8500 devices and the l80 family peripheral systems. The 8500 peripherals are general-
devices, Including interrupt handling, reset Interface versions of the l-BUS counterparts
to the device, and daisy-chain control. and are designed to interface to nonmultl-
plexed buses (such as In a zao system),
This application brief describes the hardware instead of multiplexed buses (such as In the
interface requirements and interrupt struc- l8000)
CPU HARDWARE The hardware Interface consists of three Read. RD activates chip-read cir-
INTERFACING basic groups of signals: the data bus, cuitry and gates data from chip onto
control and selection lines, and the inter- data bus (to be read by the CPU).
rupt control lines. Following is a table of
the general interface signals used by the Write. WR is used to strobe data
CPU. Additional Information can be found In from bus Into chip.
the peripherals' separate data sheets.
INTERRUPT CONTROL
DATA BUS
INTACK Interrupt acknowledge signal from
Data bus, bidirectional, 3-state. CPU. This replaces the MT and 10RQ
This bus is used to transfer data generated by the l80 CPU for Inter-
between the CPU and the peripheral rupt acknowledge. It is used In
device. conjunction with RD to gate the
Interrupt vector onto the data bus.
CONTROL SIGNALS
00, lEI Interrupt Request, Interrupt Enable
Address select Ii nes (opt ional). lEO Input and Interrupt Enable Output.
These lines are normally used to These lines are functionally equiv-
select the port and/or control alent to those In the Z80 peripheral
registers. products. TItf Is open-drain, active
Low output.
CE Ch ip Enab Ie. CE shou I d be gated
with 10RQ or MREQ to prevent spur-
ious chip selects during other *Chip reset is accomplished by activating RD
mach i ne cyc Ies. and WR simultaneously.
INTERRUPT Understanding the 8500 interrupt operation co~mand to the device or by an Implicit
OPERATION requires basic operational knowledge of the action generated by the Interrupt service
Interrupt Pending (IP) and Interrupt Under routine. The implicit action may be
Service (IUS) bits in relation to the daisy triggered by the CPU reading or writing a
chain. IP is set in the SIO by an interrupt register in the device. For example, on a
condition, such as the transmit buffer going seri al receive device II ke the SW, IP may be
empty, and is used with IUS to control the reset when the CPU reads the character from
nrr signal. IP Is not set while the CPU Is the receive buffer that caused the interrupt.
executing an interrupt acknowledge cycle. This removes the interrupt condition, allow-
Thus, ing other interrupts to occur.
IP = INT * VREAD
The Interrupt Under Service (IUS) latch Is
The IP latch is cleared either by a software used to designate the interrupt that Is
611-1809-0002 11/26/80
currently being serviced. IUS is set when conditions, only IUS Is required to control
the device receives an interrupt acknowiedge the state of the lEO pin. Therefore, the
from the CPU while lEI is High and IP is set. daisy chain used in 8500 devices is referred
If lEI is Low, the device is prevented from to as an iUS daisy chain. Since IP is not a
setting the IUS latch and thus cannot issue a part of the daisy chain, there is no "ED"
vector. In this way, the daisy chain can decoding pulling lEO High when IP is set. To
establish relative priority among peripheral allow more control over the daisy chain, the
devices. IUS is cleared on the 8500 devices 8500 devices have a "Disable Lower Chain"
by an explicit software command. (DLC) software command that unconditionally
brings lEO Low. This can be used to deacti-
The daisy chain used in the zao peripherals vate parts of the daisy chain selectively,
is referred to as an IP and IUS daisy chain, regardless of interrupt status. Figure 1
because the IP and IUS bits control the lEO shows the functions of IP and IUS and the
pin and the lower portion of the chain. If truth tables for each.
IP is set, lEO can be Low even if another
peripheral has an interrupt under service. A unique feature of the 8500 devices is the
When the CPU executes an RETI instruction INTACK pin. This pin acknowiedges a CPU
(ED-4D opcode), the peripheral monitors the interrupt service cycle to the peripheral,
bus and resets IUS. When the CPU reads the allowing the peripheral to gate its vector
"ED" part of RETI, peripherals with IP set onto the data bus. On the Z80 peripherals,
and lEI High bring lEO High momentarily. This interrupt acknowledge cycles from the CPU
enables the device in the chain with IUS set consist of a special Ml cycle where IORQ is
to clear its IUS latch when the "4D" byte is activated instead of MREQ. This limits the
read by the CPU. (IUS for a device Is not control of devices in systems using a
cleared unless lEI is High and the "ED-4D" processor other than the Z80. As a result, a
instruction Is decoded. This allows more simpler implementation has been devised,
than one device to have IUS set so that which uses additional logic to accommodate a
nested Interrupts can be implemented.) wider variety of processors. Figure 2 shows
a circuit that generates INTACK for the 8500
On the 8500 series devices, IP Is used to devices in addition to wait states. Figure 3
control the daisy chain only during the shows the timing for INTACK and wait gener-
interrupt acknowledge cycle. Under normal ation.
WArT FOR CPU
INTERRUPT ACKNOWLEDGE
CYCLE
INTERRUPT RETURN TO
CONDITION MAIN PROGRAM
b) 8500 deVIce durmg Idle slate c) 8500 devIce durmg INTACK cycle.
Figure 1. 8500 Device Inlerrupl-Proceaalng Sequence
WR------------------------------~~
RT----------------------------~
RD------------------------------~
MRIIQ-------, LS114
iii1---c[>--..-L...JI .r----------r~C>~-~
LS04
CLKO-------r---+
Figure 3. Timing for 8500 Peripheral. During Interrupt Acknowledge Without zeD Peripheral Logic
On long daisy chains, walt states may be However, on the 8500 devices, the daisy chain
necessary to allow the lEI and lEO lines time Is IUS and walt states are generated for the
to stabilize, thus avoiding conflict between iN'i'iiCK cycle onl y, nat for the return cycle.
devices and preventing IUS or IP from chang- (There Is no "ED-4D" decode.) As a result,
Ing erroneously. Because of the IP and IUS hardware Interfacing is greatly simplified
configurations, the daisy chain used In Z80 and timing Is less complicated than on the
peripherals needs to stablillze during the Z80 peripherals.
Interrupt acknowledge and RET I operations.
SOFTWARE There are several options available for peripheral Is programmed to return a vector
CONSIDERATIONS servicing Interrupts on the 8500 devices. that does not reflect the status change (SAV
Since the vector register (or IP register) or VIS not set). This al lows a simple soft-
can be read at any time, the software can ware routine to emulate the Z80 vector
emulate the Z80 CPU Interrupt response response operation, as shown In the code of
easily. The Interrupt vector reflects the Figure 4.
Interrupt status condition, even If the
AP.B500.1
~ObJ Cod. !!. Sbrt Source ~
12 'E
13
I. This rOt.ltlne emulates the ZSO vector Interrupt
15 operation by reading the device InterNpt vector,
16 forming en address fran iii vector table, end axe-
17 cutlng an Indirect Jump to the ln1"errupt service
18 routine.
I.
0000 3EOO 20 rtf)x: LD A,CIVRtG ;CURRENT INT. VECTCR REG
0002 03EO 21 DIIT (CTRl).A ;WRITE REG. PTR.
000. DBEO 22 IN A.(CTRLl ,;READ YECTCR RB3.
0006 ;VALID VECTOR?
0007
3C
CO
2'
2. ""
RET
A
Z ;NO INTERAUPT - RE1URN
0008
OODA
E60E
5f ,.
25
'""
LD
000011109
E.A
i/MSK OTHER BITS
,;FORM IN)2X VAllE:
0008
0000
0010
0011
,.
'.00
211600
7E
R
1:7
28
29
30
LD
LD
ADO
LD
0.0
Hl,VECTAB
Hl.OE
A,(HL)
;ADD VECTm TABLE ADm
E, "
'2
34
LD
LD
JP
H.{HL)
L,A
eHl)
;GET HIGH BYTE
;:PUT ROUTINE mDR IN
;:00 TO ROUTIP !
~L
,." VECTAB:
0016
0018
OOM
0010
0011
0012
",.,. DE'"
DE"
DEFW
INTI
INT2
INn
00IC
001E
0013
0014
40
41
DE'"
OE'" 'NT'
INT5
0020
0022
0015
0016 .,
.2 DE'"
OEFW
INT.
INT7
002. 0017
DE'" 'NT8
A SIMPLE The e500 dev Ices I nterf ace eas II y to the ze 0 +5.
Z80 SYSTEM CPU, providing a system of considerable +5.
flexibility. Figure 5 illustrates a simple
system using the Z80 CPU and a Z8536 cia in a iN'f fNrlNTACK
noninterrupt environment. Since INTACK Is 00-0 , 00-D7
not used, It is tied High and no additional
Rli Rli
logic is needed. Because the CIO can be used Z8D 853.
in a pol led interrupt system, the INT pin Is CPU CIO
WIi WIi
connected to the CPU. The zeo should not be
programmed for Interrupt Mode 2, because the Ao-A1 Ao-A,
vector from the cia Is never sent to the CPU. os
lORa
Instead, the CPU can be set for Interrupt
Mode 1, and a g Ioba I I nterru pt rout i ne that
reads the vector register from the cia can RE;:SET
PCLK
determine which routine to go to when an
Interrupt occurs, as previously illustrated
in Figure 4.
Z80 A ZSO system using a combination of ZSO of the chain In order to minimize propagation
PERIPHERAL~ family peripherals and 850Q-type peripherals delays during the "ED-4D" decoding. The 8500
WITH 8500 Is easily constructed, as shown In Figure 6. devices do not decode the "ED" during an
PERIPHERALS There Is no placement restriction on the 8500 opcode fetch cycle, so lEO wil I not change
devices within the daisy chain, but It Is state during this time.
recommended that they be near the beginning
T L lEI
85XX
lEO - l E I
zaD-XXX
IEOf-- lEI
zaD-XXX
IEO- lEi
zao-xxx
-lORa
RoWRI~
lORa lORa
- - -
00- 0 7 INT 00-07 Ro M1 INT 00-07 AD M1 !NT 00- 0 7 RD M1 INT
MREQ
_
M1
lORa
WAIT
AD
g WAIT &
INTACK
GENERATION
LOGIC
1
I
I
IdRQ'
I
WR
RESET
I RESET
CIRCUIT
ClK
I
OSC l~.... ClK
Figure 7 Is a diagram of the logic repre- device. The Z80 peripherals are wired to the
sented by the WAIT and INTACK logic box In Z80 as usual. The timing for the INTACK and
Figure 6. The WAIT/Signal is OR-wired to the WATT generation logic Is illustrated In
output of each peripheral device (If used). Figure 8.
The Ro and WR signal s onl y go to the 8500
RD------------------------------------~ ~o_-------------READ
TO 8&00
IORQ-----------------------------4I~~~--------~~ IORQ' PERIPHERALS
MREQ LS164
.~------------~~----_+~~_f~~INTACK)
iii1
CLK--------+---~8 C
WAIT------------------~~JP===---~~~----------------------WAIT~
lS11
Walt from penpheral devICes
IORQ' --------------------------~----~
Figure 8. Timing for 8500 and zeo Peripherals During Inlerrupl Acknowledge
~
Zilog Application Brief
February 1981
INTRODUCTION When an external clock Is not provided in a tlplexor project that used a zao SIO and a
Z80-based system. It Is often necessary to Z80 DART.
generate a bit-rate clock for serial devices.
The most efficient way to accomplish this Is This application brief describes the use of
to use a programmable counter that can change the Z8536 CIO device In a Z80-based system
the bit-rate clock under CPU control. In for generating the bit-rate clocks for asyn-
this example. the Z8536 Counter/Timer I/O chronous communications. The Z8536 CIO con-
device (CIO) was chosen to generate the blt- tains the circuitry necessary to generate the
rate clocks for a Z80-based statistical mul- clock pulses required by asynchronous com-
munication devices.
HARDWARE The Z8536 CIO is housed in a 40-pln package CIO is placed In a reset state and remains
and contains both system bus interface and there until cleared by the program. Reset can
I/O port connections. The three 16-blt coun- also be initiated by Issuing a command to
ters can be programmed to output a pulse. Register 0 with bit 0 set or by a hardware
square wave. or one-shot waveform on the condition (Ra and ~ simultaneously active).
timer's corresponding output pin. Three bits The reset state Is described In detail In the
of the output ports (two from Port B and one programming section. Once the reset state Is
from Port C) are used as the counter/timer cleared. the CIO Is placed In state O. In
outputs and provide the bit-rate pulses used which the control registers can be accessed
In this application. by writing a Register Pointer to the cia
control port. This places the CIO in state
Interfacing the cia to the Z80 CPU requires 1. after which the next CPU access (read or
eight bidirectional data lines and five con- write register data) causes the CIO to revert
trol lines. The data lines are used to to state O. The last register addressed may
transfer register address and data to or from be accessed simply by reading the CIO control
the CIO via the RD. WR. CEo and address con- port. It should be noted that the Register
trol lines. Two address lines (AO and A,) Pointer can be written only while In state O.
select the port the CPU Is accessing. Table Also. data can be written to a control reg-
1 shows the port selected by the address ister only after a Register Pointer has been
bits. written. Figure 1 shows the state diagram
for the CIO.
Table 1. Port Addressing for the CIO
Address Li ne Al AO
HARDWARE
OR _
Port C 0 0 SOFTWARE
Port B 0 1 RESET
Port A 1 0
CTRL 1 1 (BIT 0 = 11
The control port (CTRL) Is used for control Figure 1. S~a~e Diagram for Z8536 CIO
register selection and parameter transfer.
To select a particular register. a Register
Pointer Is written to the CTRL port and the The R5 and WR control lines determine the
data Is written Into or read from the data path direction into or out of the CIO.
register. When activated simultaneously. they also
perform the device's reset function. Figure
The CIO contains a state machine that con- 2 Illustrates how the reset function can be
trols the CPU interface. Upon power-up. the implemented using external circuitry.
Each counter/timer uses one or more bits on CIT Output PB4* PBO PCO
one of the paral lei ports to provide for Counter Input PB5 PBl PCl
counter Input and counter/timer output. Table Trigger Input PB6 PB2 PC2
2 shows which output port bits correspond to Gate Input PB7 PB3 PC3
particular counter/timer inputs and outputs.
*PB4 Port B, bit 4
The outputs of the counter/timers (PB4, PBO,
and PCO) are fed to the rest of the circuitry
to supply the serial clock pulses. The last hardware consideration involves the
clock input, PCLK. Since the Z8536 does not
need to be synchronized with the CPU clock,
_ LSOB
RD ___ PCLK can come from any source so long as it
RESET~SOB
READ meets the timing and interface requirements.
FROM { TO In fact, PCLK can come from a source external
Z80 } Z8536 to the system If desired. Once Inside the
CPU __ CIO
- WRITE device, PCLK is divided by two before it Is
WR sent to the counter/timer circuits. There
is no other prescal ing done and the resultinq
Figure 2. RESET Interface to the Z8536 clock Is fed to the 16-blt counters.
PROGRAMM I NG Once the hardware has been defined, the func- Time Constant= PCLK / (4 * Output Frequency)
tional operation and configuration of the
Z8536 are determined entirely by the software PCLK Is divided by four in the formula be-
programming. Several considerations concern- cause it is divided by two inside the CIO
Ing Initial izatlon must be made when using before being fed into the downcounter and by
the CIO. When the device receives a reset two again because a square wave cycle Is two
from either hardware or a software command, times the time constant value. Substituting
the reset state must be removed before any the baud rate and a multiplier of 16 for the
data can be written to the CIO. To clear the output frequency, the formula reduces to a
reset state, the user writes to register 0 simple time constant formula.
with bit 0 cleared. Once the internal reset
latch is cleared, the programmer can Initial- TC = PCLK / (4 * 16 * Baud Rate)
Ize the CIO and begin normal operations. The
program listed in the appendix shows a reset With a 3.6864 MHz PCLK Input and a desired
sequence that brings the CIO to state 0 even 9600 baud rate, the formula simplifies to:
if the previous state is undefined.
TC = 3,686,400 / (4 * 16 * 9600)
The configuration of the CIO defines the 57600 / 9600
general operating characteristics of the 6
device with respect to its internal func-
tions. The Port Mode Specification register Other 16X baud rates may be generated by
sets to output those bits in Port B that are using the above formula in a general form.
used for the counter/timer outputs. In this
example, Bit mode is used on Ports Band C to TC 57600 / Baud Rate
output the counter/timer pulses.
The user must exercise caution when choosing
The Counter/Timer mode, time constant values, values for the PCLK and baud rates since they
and trigger commands are the last parameters must result in nearly integral time constant
to be set. Finally, the Master Configuration values. For example, a 2.4576 MHz clock
Control register Is set to enable Port B, all Input with 9600 baud and a 16X clock output
the counter/timers, and Port C <Port C Is give a time constant value of 4. Greater
enabled along with the counter/timers). The flexibility is available for selecting time
CounterlTimer mode Is programmed for contin- constant values because the SIO does not
uous cycle square wave with external output require a square wave input when programmed
enabled. The square-wave cycle time Is two for 16X. 32X, or 64X clock inputs. Pulses
times the programmed time constant, which may be used with the SIO provided the user
must be taken into account when programming adheres to the SIO timing requirements.
time constant values. The downcounters In
the CIO are 16-blt counters that are decre- The last operation performed on the CIO is a
mented by one for each internal clock cycle. trigger command to "kick it off." This also
The internal clock cycle is the PCLK cycle Includes setting the gate command bit in the
divided by two, so the time constant value is Counter/Timer Command and Status registers,
determined by the following formula: which al lows the clock pulses to toggle the
CONCLUSION The designer should find the ZB536 cia a The Z8536 cia was chosen after considering
versati Ie and cost-effective component to device count, performance, and ease of use.
satisfy his or her system needs. Coupled Alternatives to the cia include discrete
with other Zilog components, the ZB536 archi- (TTL) hardware counters and gates, external
tecture enhances the performance of any Z80 clock sources, or the Z80 CTC. These methods
system by providing the essential timing, I/O are generally too parts-intensive, and power
functions, and interrupt control functions consumption is therefore higher. For appli-
necessary for efficient system operation. cations where two 8-bit ports and three
counter/timers are needed, the cia proves to
be the ideal component.
APPENDIX Fol lowing is a listing of a test program stopped, with the CIO continuously providing
written for the Z80 CPU. This program simply pulses. AI I three counter/timers are used to
initializes the cia and then loop's until generate square waves corresponding to a 16X
9600 baud clock.
TEST,CIO
LOC OBJ CODE M STMT SOURCE STATEMENT ASM 5,9
0006 18FE
27
28
29
JR . ; LOOP FOREVER
30 INIT:
31 C lOINI:
0008 DBOB 32 IN A. (CIOCTL> ; INSURE STATE 0
OOOA 3EOO 33 LD A.O ; REG 0 OR RESET
OOOC D30B 34 OUT (CIOCTL>. A ;WRlTE PTR OR CLEAR RESET
OOOE DBOB 35 IN A. (CIOCTL> ; STATE 0
0010 3EOO 36 LD A.O ; REG 0
0012 D30B 37 OUT (CIOCTL>. A ; WRITE PTR
0014 3E01 38 LD A. 1 ; WRITE RESET
0016 D30B 39 OUT (C IOCTL>. A
0018 3EOO 40 LD A.O ; CLEAR RESET
OOlA D30B 41 OUT (CIOCTL>. A
OOlC 212600 42 LD HL.CLST ; INIT CIO
OOlF 0620 43 LD B.CEND-CLST
0021 OEOB 44 LD C.CIOCTL
0023 EDB3 45 OTIR
0025 C9 46 RET
47
48
49 ; ; CONSTANTS
50
51 CLST:
0026 28 52 DEFB 28H PORT B MODE
0027 00 53 DEFB 000000008
0028 2B 54 DEF8 2BH PORT B DIRECTION
0029 EE 55 DEFB 11101110B
002A 06 56 DEFB 06H PORT C DIRECTION
0028 FE 57 DEFB 111111108
002C 1C 58 DEFB lCH Cll MODE
0020 C2 59 DEF8 11000010B
002E 10 60 DEFB lDH iCT2 MODE
002F C2 61 DEF8 11000010B
0030 lE 62 DEF8 lEH .CT3 MODE
0031 C2 63 DEF8 11000010B
0032 16 64 DEFB 16H ; CTl TC MSB
0033 00 65 DEFB 0
0034 17 66 DEFB 17H LSB
0035 06 67 DEFB CIOCNT
0036 18 68 DEFB 18H ;CT2 TC MS8
0037 00 69 DEF8 0
0038 19 70 DEFB 19H LSB
0039 06 71 DEFB CIDCNT
003A lA 72 DEFB lAH .CT3 TC MSB
0038 00 73 DEFB 0
003C lB 74 DEF8 lBH LS8
0030 06 75 DEFB CIOCNT
003E 01 76 DEFB 1 MASTER CONFIG. REG.
003F FO 77 DEF8 111100008
0040 OA 78 DEFB OAH CT1 TRIGGER
0041 06 79 DEFB 00000110B
0042 OB 80 DEFB OBH ; CT2 TRIGGER
0043 06 81 DEFB 00000110B
0044 OC 82 DEFB OCH ; CT3 TRIGGER
0045 06 83 DEFB 000001108
84 CEI\[): EGU $
85
86 i i DATA AREA
87
2000 88 ORG RAM
2000 89 DEFS 64 STACK AREA
90 STi>K: EGU $
91
92 END
~
Zilog Application Note
March 1981
I NTRODUCT ION In many computer systems, an accurate time counts or single-event Time delays can also
base Is needed so that critically timed be implemented under program conTrol. This
events do not go awry. Use of a counter or application note describes both continuous
timer to monitor time-dependent activities Is time-Interval operations and single-Interval
essential In such systems. In an Interrupt- count operat Ions us I ng the Z80 CTC I n a Z80
dr I ven system, the Z80 CTC can prov i de system.
regular program time intervals. Single-event
HARDWARE In the example used here, the hardware con- 60Hz pulses; the other Is connected to a
CONFIGURATION s Ists of a Z80 CPU with 4K bytes of RAM, 4K transmit clock line on the S I O. One of the
bytes of ROM, a Z80A SIO, and a Z80A CTC. counter/timer outputs Is connected TO the SIO
There are two eXTernal Inputs to the CTC: one transmit and receive clock Input, as shown In
is derived from The ac power line to prov Ide Figure 1.
4K 4K
RAM ROM
ADDRESS 16
DATA 8
CONTROL '7
Z80A
CPU ZCrT02 RxTxCA
+5V
>4.7K
ClKrTRIG3
CTC ... TxCB 510
RxCB
r- ClKrTRIG 1
INT f- ClK INT ClK INT
ClK
~SCILLAT01-
I RS232C
INTERFACE
60 Hz TIL
PULSES
CTC MODES There are two basic modes under which the CTC istics that enabie the eTC to be used in a
can operate: Timer mode and Counter mode. wide variety of applications.
Each mode has certain programmable character-
TIMER MODE A typical use of the CTe in Timer mode is to Another use of CTC Timer mode operaTion is to
provide regular, fixed-intervai interrupts to implement a nonretriggerable one-shot using
the CPU used as a time-base reference to external circuitry. The digital approach to
al locate the processor resources efficiently. the one-shot provides a programmable time
For example, a multitasking system might have delay under epu control and provides greater
the processor execute a task for a given noise immunity than the more common analog
length of time and then interrupt execution delay circuits provide. Figure 3 shows a
of the program at one-second intervals to circuit that uses part of a 74lS02 package in
scan the task queue for higher-priority addition to one CTC channel.
tasks. This system time interval can be pro-
vided by the CTC in Timer mode. In Timer
mode, the CTC downcounter is decremented by The trigger waveform should be positive-going
the output of the prescaler, which is toggled and shou I d meet the eTC setup time for the
by the system clock input. The prescaler has ClK/TRIG input. Also, the trigger High level
a programmable value of 16 or 256, depending time should be less than the eTC delay time
on the condition of bit 5 in the channel in order to prevent the two 74lS02s from
control word (CeW). Thus, with a 4 MHz system latch i ng in the tr i ggered state. An add 1-
clock fed into the CTC, a timer resolution of tional gate can be added to initial ize the
4us (prescaler count of 16) or 64~ (count of 7 4lS0 2 f I i p-f Iop to a def i ned state when the
256) is possible. system is reset or else the software can
pulse the timer output to set the flip-flop,
I n the example shown, the interrupt interval as is done in th i s case. A th i rd use of th e
is set TO 8.33 ms, which is provided by the Timer mode is to provide a bit rate clock for
eTC with a 3.6864 MHz input clock, 256 pre- a serial transceiver device, such as the Z80
scaler value, and a time constant value of S I O. The S I 0 can accepT a lx, 16x, 32x, or
120. The CTe interrupt service routine uses a 64x bit rate clock inpuT from an external
software count of 120 to maintain a one- source, and with a 16x, 32x, or 64x multi-
second system time Interval. Each time the plier, the SIO can accept a pulse waveform
service routine Is executed, the software input for the bit rate clocks, as long as the
count Is decremented by 1. When the count pulses meet the rise, fall, and hold time
reaches 0, a flag is set and the program requirements of the SiO. The CTC meets these
pursues an appropriate course of action. requirements and can be connected directly to
Figure 2 shows the initial ization and inter- the SIO to provide the necessary bit rate
rupt service routine coding for a CTC channei ciocks. Figure 4 shows the code needed to
using The Timer mode. generate a bit rate clock for the SIO.
lA clock driver by Hybrid House, 1615 Remuda la., San Jose, CA 95112.
TRIQGER~
INPUT A
LS02 IL.-_
C
_ ---I'
CLI<fTRIG
---1
0
L
B
ZCITO
CTC
A-Il
B--------____~rl~________
C1L..____.....J
0---1
Figure 3. Monoshble Multlvlbrator Using the 280 eTC
751-1809-0005 2-109 4/1/81
TEST CTCO
LDC ClBJ CODE M STMT S OUReE STATEMENT
71 ICTCl
72 ICTC2
73 ICTC3
003D FB 74 EI ,DUMMY ROUT INES
('O:JE ED4D 75 RET!
76
77 ICTCO
(,,)40 CD5AOO 78 CALL SAVE , SAVE REGISTERS
0043 3A4020 79 LD A, (COUNT) ,CHANGE' TIMER COUNT
0046 3D 80 DEC A
0047 324020 81 LD (COUNT>, A
004A CO 82 RET NZ , EXIT IF NOT DONe
u04B 31078 83 LD A,TIME I EL~"IE, RESET TIM!'r-' vr,Ll'l-:
(l04D a24020 84 LD (COUNT), A
1")0')0 3A4120 85 LD A, (oISP) , BI JNiI> LITES
00'53 2F 86 CPL
0054 324120 87 LD (D ISP), A
u057 D3EO 88 OUl (LITE), A
('059 C9 89 RET
90
91 SAVe, REGISTER HOUl IN~:
92
93 SA,,:
(,05A E3 94 EX (SP), HI-
005B D5 95 PUSH DE
005C C5 96 PUSH BC
(~()5D F5 97 PUSH AF
I... It) 5E CD6800 98 CALL G[)
,;.0" ] Fl 99 POP AI"
0062 Cl 100 POP BC
u(16::":J D1 101 POP DE
(\(.164 E1 102 POP Hl.
'Jtib5 FB 103 El
(J 1 hb6 ED4D 104 RETl
105
106 GO
i('1.8 E9 107 JP (HL)
108 "E
109
110 DATA AREA
111
2000 112 ORG RAM
;WOO 113 DEFS 64 ,SlACK AREA
114 STAA EGU $
2040 115 COUNT DEFS , TJMER COUNl VALVE
2041 116 DI9", DEFS ; LITE DISPLAY BY I"E
117
118 END
I
I
t
MAIN PROGRAM
TEST CTC1
LOC OBJ CODE M STMT SOURCE STATEMENT
'751-1809-0005 2-115
TEST.CTC3
LOC OBJ CODE M STMT SOURCE STATEMENT
CONCLUSION The versatility of the Z80 CTC makes It use- Interrupt capab III ties of th e Z80 CPU, the
ful In a myriad of applications. System CTC can be used to supply counter/timer func-
efficiency and throughput can be Improved tions to the CPU. This reduces software over-
through prudent use of the CTC with th e Z80 head on the CPU and significantly Increases
CPU. Coupled with the powerful, vectored system throughput.
TABLE OF CONTENTS
PAGE
INTRODUCTION . . . . . . . 2-121
16 PIN DYNAMIC RAM ADDRESSING 2-122
MEMORY REFRESH. 2-124
ACCESS TIME . . 2-125
Z80A/Z80 - CPU TIMING CONSIDERATIONS. 2-127
MEMORY CYCLE SELECTION . . . . 2-131
DYNAMIC RAM MEMORY ORGANIZATION 2-132
SLOW MEMORY INTERFACE 2-138
DESIGN EXAMPLE. 2-140
CONCLUSIONS . . 2-146
2-119
---------- .~~~~
INTERFACING 16-PIN DYNAMIC RAMS
TO THE Z80A MICROPROCESSOR
~120
INTRODUCTION
2-121
~~- ---
-~-----~~.~.
16 PIN DYNAMIC RAM ADDRESSING
~122
VBB 1 16 VSS PIN NAMES VBB 1 16 VSS
DIN 2 15 CAS ~A6 ADDRESS INPUTS DIN 2 15 CAS
COLUMN ADDRESS STROBE
WRITE 3 14 DOUT DIN DATA IN
WRITE 3 14 DOUT
RAS 4 13 CS ~T
DATA OUT RAS 4 13 A6
ROW ADDRESS STROBE
AO 5 12 A3 WRITE READ/WRITE INPUT AO 5 12 A3
VBB POWER (-5V)
A2 6 11 A4 vee POWER (+5V) A2 6 11 A4
POWER (+12V)
A1 7 10 A5 VDD
GROUND A1 7 10 A5
VSS
VDD 8 9 VCC VDD 8 9 VCC
2-123
MEMORY REFRESH
REFRESH TIME
MEMORY ZSO-CPU ZSOA-CPU NO. OF REQUIRED
SIZE 2.5 MHZ 4.0 MHZ REFRESH CYCLES/2 mS
4K 487 us (max) 304 us (max) 64
16K 974 us (max) 608 us (max) 128
~124
ACCESS TIME
~
t
RCD MAX
WINDOW
.. t
RCD MIN ..
L _
- - - - -
.... t RAH - ~tASC"""
ADDRESSES ~~
ROW COLUMN
ADDR. ADDR.
II ..... _
-~If-----------t-~-tCAc--CJ ~~~;:'
~~~--------------------tRAc--------------~r:=r-----~~~l
DATA
OUT
2-126
ZSOA/zSO - CPU TIMING CONSIDERATIONS
145
T1 T2
J 145 \ T3
J
f- , T4
J
--1 MAX
J
MAX
AO-A15 )
MEMORY READ ADDRESS REFRESH ADDRESS
--
X
-- -445MIN- _165
MIN
100 I -
MAX
- -- ... ---
I
130
MAX - ---
r-
100
MAX
- . 130
MAX
130
-,MAX
~
180 150
MAX MAX
F--
___ 400 ___
MIN
Figure 3 zao-cpu op code fetch cycle timing at 2.5 MHz clock
T1 T2 T3 \ T4
-1 110 ' I I 110 \ J J
. . MAX
MEMORY READ ADDRESS
..MA~_I
REFRESH ADDRESS
AO-A15 X I .-
X-
1-- -255MIN-
- I
105
MIN
85
MAX 1_
--- 85 MAX 35MIN--
.... - 1- 220
MIN --
95
MAX
1-
ir--- 75MIN
-~ C ~
-
--- 85
MAX
RD
_ 100 100
MAX - I MAX
.L
130
MAX
120
MAX - r-
---250 MIN--
I
r-
T2
J
, ~CPU READS DATA
T3
J
. .
MAX 135
MIN
AO-A15
100 MAX
)
-
MEMORY READ ADDRESS
640
MIN
_I MAX
100 -
-y:-
130
60 __
MIN -
I
11d
MAX
-
MAX
T1 T2 T3
J 110
\
J J
\ J
. .
MAX 75
MIN
AO-A15 ) MEMORY READ ADDRESS y-
85
MAX - 365 MIN I
i
_1 MAX
85
50
I
_
T T
85
MIN-- MAX
95 I
-
MAX
2-129
J
r-
145 - l-
MAX
,
T1
J
J- ,
-t-
T2
J
,... ,
T3
J
135 MIN
AO-A15 ) MEMORY WRITE ADDRESS x::
- __ 100
MAX
.......
..,r-
100
MAX
___ 230 _
MAX
an .
--- '100
-MAX
1
I
1-.-.1 80
________~--------_+----~I-~
-~IMAXj
WR .~~~--------~
I
NOTE: ALL TIMING IN ns ASSUME RISE/FALL TIME: 15ns
Figure a zaOA-CPU write cycle timing at 4 MHz clock
2]30
MEMORY CYCLE SELECTION
2-131
DYNAMIC RAM MEMORY ORGANIZATION
~132
4k
DYNAMIC
CONTROL 1
j,
RAM
CAS
""
,....- CS
RAS
DOUT
1>- CONTROL 2
DIN I - -
CAS
~ CS DOUT
- ....
Figure 9 Partial memory configuration in Bk byte system
2-133
All inputs on most dynamic RAMS are TTL compatible (on
some 4K devices RAS, CAS, and the WRITE line require a
2.7 volt minimum logic I level which will require a
pull-up resistor on the TTL driver). These TTL inputs,
however, do not source current; but instead, present
purely capacitive loads. This capacitance will vary
between 5pf and 10pf on most 4K and 16K devices. With a
large number of RAMS in a memory array, capacitive
loading becomes a consideration. A 16K byte memory
array made up of 4K devices will present from 150pf to
250pf of input capacitance to the input buffers. Most
TTL outputs are not specified above 50pf. Therefore, a
TTL driver must be used that can provide enough charging
and discharging current to achieve the required voltage
transition within the allotted time. A fairly accurate
calculation can be made for determing the required drive
current by using the standard relationship between the
charging current i, the capacitance C, the voltage
transition V, and the allotted time T:
b.V
i = C
b.T
2-134
The resulting current spike, which occurs when the RAS
and CAS clocks go through their negative transitions, is
coupled onto the power supply busses causing noise
throughout the system. To compensate for this noise,
high-frequency ceramic bypass capacitors should be
placed within the memory array. A good practice is to
supply a .luf capacitor every other device between +12V
and ground. Alternating between these capacitors, a
Decoupling on the +5V line to prevent noise from
affecting TTL logic should consist of a .Oluf capacitor
every 4 or 5 devices. For low frequency decoupling, a
10uf tantalum capacitor between +12 and ground should be
supplied every 16 devices with a 10uf tantalum between
-SV and ground every 32 devices.
The use of a multi-layer board with internal power and
ground planes would be beneficial in a dynamic RAM
system. However, proper routing of power lines on a
two-sided card should provide satisfactory results. It
has been found that bussing the +12 volt and ground
lines both horizontally and vertically at every device
will reduce noise and greatly improve RAM performance.
The -5 and +5 volt lines need not be bussed in this
fashion since they are less heavily loaded and are less
likely to see current spikes.
Keeping the layout as small as possible and locating the
address and data bus buffers as close to the array as
possible will also reduce potential ringing and
reflections.
Figure 10 represents a typical expandable RAM interface
for a total memory capability of either 16K using 4K
devices or 64K using 16K devices. The multiplexing of
address lines is done by "wire-oring" 8T97 drivers and
controlling the tri-state input for row to column
switching. Since the minimum voltage on any RAM input
is -1 volt, a small series resistor (about 300hms) is
inserted on each RAM address line to surpass any
undershoot that might occur. When using 4K RAMs, the
lower section of the 74Sl39 decoder selects the desired
16K quadrant by decoding address lines A14 and AIS. The
upper section of the decoder selects the desired 4K bank
in this quandrant by decoding address lines A12 and A13.
When using 16K RAMs, the lower section of the decoder is
not used and the upper section decodes the desired 16K
2-135
A15 C
B
~ D
AI2
~
8T97
)
A9
~ H
AS
./
=-.J
Z80A
I I I I f
t;..J ~~ ilMA6
~ PI ~
li MA5
IIII~ ~ MA4
A3 MA3
~ RAM ADDRESS
INPUTS
A2 MA2
-+---+--4-----~...vv__+_ MAl
MAO
/
SWI1CH RASCDNTROl
MREO~
MUX
r?--l .
RAS, SWITCH MUX.
CAS GENfRATION CAS FOR 4k RAMS CONNECT N-R, M-P, S-T, C-E, D-F
~
A-J, B-H AND Q TO W, X, V
OR Z TO SELECT THE DESIRED 16k aUANDRANT
: COO",
FOR 16k RAMS CONNECT N-M-K, P-l, S-V, A-F
B-E AND 0 TO GND
2-137
SLOW MEMORY INTERFACE
>
~>
WAIT ~>
- CK
l (
74LS109
r--o ~
PR PR
MREQ J '-- J
V
9- CK CK
-
,.--- K Q ~ ,....- -K Q t--
CLR CLR
<;> ;>
MREQ------.
WAIT - - - - - - - ,
2-139
DESIGN EXAMPLE
~140
Z80A
74S04
M1 r-o~
V 74S00 I"
74S00 0 RAS
~.~ 1
RFSH
r-~" ~ 74800
';->
:;;::
~04
! !
~[>-
PR PR PR
MREQ D Q D Q r-- '-- D
0
$ - CK r-- CK Q $ - CK Q t--
CK r-- $
2.--t?074S04
CAS
8\------
MUX
2$ / \ / '-
MREQ
-----.. 85
MAX
RAS
SWITCH
~ MUX
~
CAS
---+- 35
MIN
...--
DATAIN - - - - - - _1 _ _
130 ---+-1
"'--MAX
RFSH
112 I
152
---MIN-- - M I N -
M1\ ~
Figure 13 ZaOA dynamic ram interface timing
This basic logic structure is configured into a
microcomputer system and is seen in Figure 14. For
simplicity, only the logic pertaining to the RAM
interface is shown. Additional logic consisted of
monitor software and a serial I/O interface to a CRT
terminal.
Since the RAS to CAS interval exceeds the tRCD max value
of most access-compatible RAMs, the RAM access time is
measured from the leading edge of CAS. RAMS with CAS
access times of l50ns or less should be compatible with
this interface approach. If it is desired to keep the
RAS to CAS interval within or closer to the tRCD max
limit, a 40 clock could be applied to the clock input of
Flip-Flop B (Figure 12) instead of the 20 clock. This
would reduce the RAS to ~ interval to approximately
65ns.
2-143
~----------I
1Y1
I
I
r-+-----i A3
.,
A2 -2,3
AO
AilS
26116 26116
-2,3
26116
-2,3
26116
-2,3
}.
,--t---i:' LS157 2Y \ -_ _ _ _ _ _ _ _ _- '
.{ 26116
-2,3
26116
-2,3
26116
-2,3
26116
-2,3
"~-~-~
02
"
06
2-144
FIGURE 15 FIGURE 18
CK
~CK
MREO
RAS
RAS
SM
CAS CAS
FIGURE 16 FIGURE 19
MREO ~ CK
RAS
RAS
SM SM
CAS CAS
FIGURE 17 FIGURE 20
ADDR
2-145
The recordings also show the relation between MREQ and
RAS high time between Op Code fetch and refresh cycles.
The calculated value for RAS high time was 150ns while
the measured value was approximately 170ns. This allows
adequate RAS precharge time for all access-compatible
RAMs.
CONCLUSIONS
2-146
Controlling zao
microcomputer I/O?
An interrupt-driven program could help
A way
lthough interrupts are not necessarily the fastest
to control I/O in a microcomputer system,
Two other ways
Besides interrupts, pC-system I/O can be handled
they are often the most practical-especially when by software polling (handshaking) or by direct memo-
several asynchronous external events must be serviced ry access (DMA).
in preference to ongoing calculations. Software polling is the simplest technique-the
Interrupt processing itself is, of course, a function CPU is left idle until a peripheral is ready to transfer
of hardware architecture, but it must be supported data. Even if the inefficient processor use is accep-
by special routines in the user's software. To do that table, transfer rates under 42.3 kbytes/s for the ZSO
efficiently requires detailed knowledge of how an or 67.S kbytes/s for the ZSOA are only adequate for
interrupt functions. paper-tape or card readers, and inadequate for tape
Say a peripheral generates an interrupt condition or disk drives. Unless a separate CPU is dedicated to
I/O, the inefficiency usually makes polling unaccep-
when a character becomes available on the Z80-SIO
table.
(serial-I/O) receiver. When the connected peripheral's Worse yet, while the CPU waits for one peripheral
interrupt-enable input line is high and its internal to get ready, several others may go begging. So when
interrupt circuitry is enabled, it activates the inter- several devices need CPU access according to pre-
rupt line of the Z80 CPU. determined priorities, interrupt-controlled I/O is usu-
The processor samples the interrupt line on the last ally preferred-especially when asynchronous ex-
T state of the last machine cycle in every instruction. ternal events have to be serviced in preference to some
If the interrupt line (INT) is active, the interrupt- ongoing calculations.
enable flip-flop in the Z80 is set and the data-bus But interrupt servicing also takes time. The ZSO
request line (BUSRQ) is inactive, the CPU acknowledges needs up to 40 T cycles to detect and acknowledge the
the interrupt by entering a special Ml cycle called the interrupt, in addition to I/O processing. Compared
with polling, interrupt-driven I/O can be much slower.
interrupt-acknowledge cycle. An I/O request is then While polling can service a single-density floppy that
made during the last T state of this cycle to the device, needs data at 31.3 kbytes/s, interrupt control under
which is now able to put its vector on the data bus. a ZSO CPU would lead to the loss of some data.
This vector, together with the I register, forms a 16- When high speed is critical, DMA takes the prize.
bit pointer in the interrupt service routine's starting- By synchronizing a peripheral to the central memory
address table (ISR-SAT). The Z80 CPU then obtains rather than the CPU, the software overhead of both
a 2-byte address from the table and jumps to that polling and interrupts can be avoided. However, DMA
address. excludes the possibility of any data preprocessing
But before the interrupt can be processed properly, (field masking, character search), and tends to be
the user has to prepare the ground: expensive. Direct memory access is often combined
with interrupts; for instance, serial communications
1. An interrupt "page" must be chosen and the 1-
can be started via interrupts, and then carried on at
register programmed accordingly. high speed under DMA.
2. The device interrupt vector must be pro-
grammed.
3. An entry (or several) must be made in the ISR-
SAT.
When the interrupt has been acknowledged, the
machine state can be described as follows:
The user program has been interrupted .
Control has been passed to the proper interrupt
service routine (to which the table entry for the
7 1D C,eTel
10 10 DE,CNTMOD.SHL.8+TlME32
10 1D HL,CTRMOD.SHL.8+DELAY2
12 OUT (el,O
12 OUT (C),E ENABLE CHANNEL 1
~ FUNCTION
7 LD C,(C)
OUT CTC2
,_ ; ENABLE CHANNEL 2
12
12 OUT (C) ,L
86 TO 101 Total number of T states
NOTE: If sector pulse occurs after execution of lnput
instruction, loop is entered up to 15 T states later.
~
Zilog
Tutorial
Information
March 1981
Introduction The Zllog Z8000 CPU mICroprocessor IS a instructions and data capabihlles.
major advance in microcomputer architecture. Before discussmg these features m more
It offers many mmicomputer and mainframe detail, a word about nomenclature is in order.
features for the first time m a mICroprocessor The term Z8000 refers to the concept and
chip. This tutorial describes the Z8000 CPU architecture of a family of parts. Zllog has
with emphasis placed on those features that set adopted the typical conductor industry 4-digH
It apart from its mICroprocessor predecessors. deslgnallon for Z8000 Family parts, while also
For a detailed descnpllon of all Z8000 CPU keepmg the tradItional 3-letler acronym that
features, consult the Zllog pubhcatJons listed proved so popular for the Z-80 Family. Thus,
in the bibliography at the end of thIS tutorial. the 48-pm version of the Z8000 CPU is called
The features to be dIscussed are grouped the Z8001 CPU; the 40-pin version IS known as
mto four areas: CPU organization, handling of the Z8002 CPU.
interrupts and traps, use of memory, and new
CPU The Z8000 CPU IS orgamzed around a index. When the third index is needed, it must
Organization general-purpose register file (Figure 1). The be swapped into an index register. In contrast,
register file is a group of registers, anyone on a general-register machine three of the
of whICh can be used as an accumulator, regIsters could be dedIcated for mdex use. In
mdex register, memory pointer, stack pointer, addihon, smce the need for mdex registers
etc. The only exception is Register 0, as may vary over the course of a program, a
explained later. general-register architecture, such as the
Flexibility is the major advantage of a Z8000, can be adapted to the changmg needs
general-purpose register organization over an of the computation with respect to the number
organization that dedicates particular regIsters of accumulators, memory pointers and mdex
to each funcllon. Computallon-onented regIsters. Thus flexibility results in increased
routines can use general registers as performance and ease of use.
accumulators for intermediate results whereas In addlllon, the regIsters of the Z8000 are
data manipulation routmes can use these organized to process 8-bit bytes, 16-bit words,
registers for memory pomters. 32-blt long words and 64-blt quadruple words.
Dedicated registers, however, have a disad- ThIS readily accommodates applications that
vantage: when more registers of a given type process data of vanable sizes as well as dif-
are needed than are supplied by the machine, ferent tasks that require different data sIzes.
the performance degrades by the extra mstruc- Although all registers can-in general-be
lions to swap registers and memory locations. used for any purpose, certain instructions such
For example, a processor WIth two index as Subroutine Call and Strmg Translation
registers suffers when three are needed make use of speCific regIsters m the general
because a temporary vanable m memory (or in register file, and this must be taken mto
another register) must be used for the third account when these instrucllons are used.
3-3
~[ ,
ST,
"~J
ST,
ST, A
CPU/SYSTEM ARITHMI!TIC
ST,
NORMAL/SYSTEM
STATUS
INFORMATION 'f INSTRUCTION
REGISTER
ALU
, AND
LOGIC
UNIT
READ/WRITE
WORD/BYTE
0
CONTROL
r-----v' .. [~
~
, ~ .>'" !f.-1\
i'r-Y
~
ADDRESS ADDRESSI
DATA BUS
ptll
DATA
-( -y AEGISl ER r----\ REGISTER ADo-AD1S
--u-
BUSHEQ BUS
FILE
BUSACK
CONTROL
"Jj,. REGISTER
CONTROL -" iY'
~
, ~-A I'" SEGMENT
REGISrER
I~UMBER
W
Mi
Mo
MUL.TMICRO
CONTROL A V L!:..
CPU
CONTROL
UNIT
I-r-~
SEGMENT
ADDRESS
.h y SNo-SN7
'I
NMi
seGr
~
~
EXTERNAL
INTERRUPTI ~ iT
Vi ~
TRAP
CONTROL -V
if
INTERNAL DATA BUS
WI ~
-~
CLOCK
WAIT CPU
-t-...
CPU
CONTROL INSTRUCTION
LOOKAHEAD
-\ PROGRAM I::OUNTER OFFSET
STATE REGISTER
REFRESH COUNTER
~
LS
STOP CONTROL
REFFIESH TIMER
RESET
AND
INCREMENTER BY 2
-
~
CPU The 28000 CPU also contains a number of the Refresh Counter. These registers are
Organization special-purpose registers in addition to the accessible through software and provide some
(Continued) general-purpose ones. These include the Pro- of the interesting features of 28000 CPU
gram Counter, Program Status registers and architecture.
......, * ." .1 RO 11 AH
-l' ."... .1
."'u.... .1
I
Aoo
ARO I
AR'I R31
R111'&
R21
AH1
AH' ....
....
.1 AOO
...
AH,
... R41
AHS
'H. Al.'
.'"
...
Alit
..
."
Al.'
AO'
AR< I
..1 R11
Rsl
RII
,H'
""'
"..,
ou
A..
01.,
.1 Rain
AOO
..1 Rsl AO'
RR10
1"'0 1I
Rll
{ R121
I
RR12
R13 f
RQ12
I I
AI<R1S'
'tme!1~ e!"N!,"
RR14
Figure 2. zaOOI General Purpose Regllten Figure 3. zaOO2 General Purpose Reglsterl
20480207, 0208
3-5
Register Note that the byte register-addressing
Organization sequence (most significant bit distinguishes
I
BYJt~~~ M~DE I opcooe
I I
I_I SOURCE
I I I 1 0'F'''tA''NI
(Continued) between the two bytes in a word register) is lO~g~O~~ I MqOE 1 OPCOO'
I I I
SOURCE
I I I IllIjST"lA~K I
different from the memory addressing
sequence (least significant bit distinguishes MODE
REGISTER
I oI
between the two bytes in a word). Long-word IMMEDIATE
~ } FOR SOURCE"" 0 0 0 0
DIRECT
(32-bit) and quadruple-word (64-bit) registers
are addressed by the binary number of their
INDIRECT
INDEXED ~ } FOR SOURCE" 0 0 0 0
System/ The Z8000 CPU can run in one of two based on the frequency of disk requests and
Normal Mode modes: System or Normal. In System Mode, disk arm position) that are harder to debug
of Operation all of the Instructions can be executed and all because these errors are not easily repro-
of the CPU registers can be accessed. This duced. Thus a preferred method of program
mode is intended for use by programs that per- development would be to partition the task into
form operating system type functions. In Nor- that portion which can be performed without
mal Mode, some instructions, such as 1/0 recourse to resources accessible only in
Instructions, are not all allowed, and the con- System Mode (which will usually be the bulk of
trol registers of the CPU are inaccessible. In the task) and that portion reqUiring System
genera!, this mode of operation is intended for Mode resources. The classic example of this
use by application programs. This separation partitioning comes from current minicomputer
of CPU resources promotes the integrity of the and mainframe systems: the operating system
system since programs operating in Normal runs in System Mode and the individual users
Mode cannot access those aspects of the CPU write their programs to run in Normal Mode.
which deal with time-dependent or system To further support the SystemlNormal Mode
interface events. dichotomy, there are two copies of the stack
Normal Mode programs that have errors can pointer-one for the System Mode and another
always reproduce those errors for debug- for Normal. Although the stacks are separated,
ging purposes by simply re-executing the pro- it is possible to access the normal stack
grams with their original data. Programs using registers while in the System Mode by using
facilities available only in System Mode may the LDCTL instruction.
have errors due to timing considerations (e.g.,
Status Lines The Z8000 CPU outputs status information with 128K bytes if additional logic is used,
over ItS four status lines (STo-ST3) and the say, to select the lower 64K bytes for program
SystemiNormalllne (SIN). This information can references and the upper 64K bytes for data
be used to extend the addressing range or to references.
protect accesses to certain portions of memory. Definition
The types of status information and their codes
are listed in Table 2. 0000 Internal operahon
Status conditions are mutually exclusive and 000 I Memory refresh
can, therefore, be encoded without penalty. 0010 I/O reference
001 I Special 110 reference
Most status definitions are self-explanatory. 0100 Segment trap acknowledge
One code IS reserved for future enhancements 010 I Non-maskable mterrupt acknowledge
of the Z8000 Family. o I 10 Non-vectored mterrupt acknowledge
Extension of the addressing range is accom- oI I I Vectored interrupt acknowledge
1000 Data memory request
plished in a Z8000 system by allocating
100 I Stack memory request
physical memory to speCific usage (program 10 I 0 Data memory request (EPU)
vs. data space, for example) and using exter- 101 I Stack memory request (EPU)
nal circuitry to monitor the status lines and I 100 Instruction space access
select the appropriate memory space for each I 101 Instrucllon fetch, hrst word
I I 10 ExtenSIOn processor transfer
address. For example, the direct addressing IIII Reserved
range of the Z8002 CPU is limited to 64K
bytes; however, a system can be configured Table 2
2048-0202
3-6
Status Lines Protection of memory by access types is own dedicated status code, namely 1I0!. This
(Continued) accomplished similarly. The memory is divided allows the synchronization of external circuits
into blocks of locations and associated with to the CPU. During all subsequent fetch cycles
each block is a set of legal status signals. For wIthin the same instruction (remember, the
each access to the memory, the external circuit longest instruction requires a total of four word
checks whether the CPU status is appropriate fetches), the status is changed from 110 1 to
for the memory reference. The Z8010 Memory 1100. Load Relative and Store Relative also
Management Unit is an example of an external have a status of 1100 with the data reference,
memory-protection circuit, and it is discussed so information can be moved from program
later in this tutorial. space to data space.
The first word in an instruction fetch has its
Refresh The idea of incorporating the Refresh (n = 1 to 64), driven at one-fourth the CPU
Counter III the CPU was pioneered by the clock rate. The refresh period can be pro-
Z-80 CPU, which performs a refresh access in grammed from 1 to 64 p.s with a 4 MHz clock.
a normally unused time slot after each opcode A value of zero in the counter field indicates
fetch. The Z8000 is more straightforward (each the maximum time between refreshes; a value
refresh has its own memory-access time slot of of n indicates that refresh is to be performed
three clock cycles), and is more versatile (the every 4n clock cycles. Refresh can be disabled
refresh rate is programmable and capable of by programming the Refresh Enable Bit to
being disabled altogether). be zero.
The Refresh Register contains a 9-bit Row A memory refresh occurs as soon as possible
Counter, a 6-bit Rate Counter and an Enable after the indicated time has elapsed. Gener-
Bit (Figure 5). The row section is output on ally, this means after the T3 clock cycle of an
ADo-ADs during a refresh cycle. The Z8000 instruction if an instruction execution has com-
CPU uses word-organized memory, wherein Ao menced. When the CPU does not have control
is only employed to distinguish between the of the bus (during the bus-request/bus-
lower and upper bytes within a word during acknowledge sequence, for example), it cannot
reading or writing bytes. Ao therefore plays no issue refresh commands. Instead, it has inter-
role in refresh-it is always O. The Row nal circuitry to record "missed" refreshes;
Counter is-at least conceptually-always when the CPU regains control of the bus it
incremented by two whenever the rate counter immediately issues the "missed" refresh cycles.
passes through zero. The Row Counter cycles The Z8001 and Z8002 CPU can record up to
through 256 addresses on lines AD]-ADs, two "missed" refresh cycles.
which satisfies older and current 64- and
128-row addressing schemes, and can also be ,. 10.
used with 256-row refresh schemes for RATE
I , , I f I !
ROW
I !
64K RAMs.
The Rate Counter determines the time
FllJW'e 5. Relreah Counter
between successive refreshes. It consists of a
programmable 6-bit modulo-n prescaler
Instruction Most instructions conclude with two or three Some instructions for which the overlap is
Prefetch clock cycles being devoted to internal CPU logically impossible are the Jump instructions
(Pipelining) operations. For such instructions, the sub- (because the following instruction location has
sequent instruction-fetch machine cycle is not been determined until the instruction com-
overlapped with the concluding operations, pletes). Some instructions for which overlap is
thereby improving performance by two or physically impossible are the Memory Load
three clock cycles per instruction. instructions (because the memory is busy with
Examples of instructions for which the sub- the current instruction and cannot service the
sequent instruction is fetched while they com- fetch of the succeeding instruction).
plete are Arithmetic and Shift instructions.
20480203
3-7
Extended The Z8000 architecture has a mechanism for AD lines). If a transfer of data between the
Instruction extending the basIc mstructlon set through the CPU and EPU is indIcated, the sender places
Facility use of external devices. Special opcodes have the data on the AD lines and the receiver
been set aside to implement this feature. When reads the AD lines during the next clock
the CPU encounters mstructions with these period.
opcodes in its instruction stream, it will per- If the extended instruction Indicates an
form any indicated address calculation and internal operation to be performed by the EPU,
data transfer, but otherwise treat the "extended the EPU begins execution of that task and the
instruction" as bemg executed by the external CPU is free to continue on to the next instruc-
devICe. Fields have been set aSIde in these tion. Processing then proceeds sImultaneously
extended instructions which can be interpreted on both the CPU and the EPU until a second
by external devices (called Extended Process- extended instruction IS encountered that is
mg Umts-EPUs) as opcodes. Thus by using destined for the same EPU (if more than one
appropriate EPUs, the Instruction set of the EPU is in the system, all can be operating
Z8000 can be extended to include specialized simultaneously and independently). If an
instructions. extended instruction specifies an EPU still
In general, an EPU is dedicated to perform- executing a previous extended instruction, the
Ing complex and time consuming tasks in EPU can suspend instruction fetching by the
order to unburden the CPU. Typical tasks Z8000 CPU until it is ready to accept the next
suitable for specialized EPUs include floating- extended instruction: the mechanism for this is
point arithmehc, data base search and the STOP line, which suspends CPU actiVIty
main.!en.imc-p operations. network interfaces, during the instruction fetch cycle.
graphics support operations-a complete list There are four types of extended Instructions
would Include most areas of computing. EPUs in the Z8000 CPU instruction repertoire: EPU
are generally designed to perform their tasks internal operations; data transfers between
on data reSIdent in their internal registers. memory and EPU; data transfers between EPU
MOVing mformation into and out of the EPU's and CPU; and data transfer between EPU flag
Internal registers, as well as Instructing the registers and CPU flag and control word. The
EPU as to what operations are to be per- last type IS useful when the program must
formed, is the responsibility of the CPU. branch based on conditions determined by the
For the Z8000 CPU, control of the EPUs EPU. Six opcodes are dedIcated to extended
takes the following form. The Z8000 CPU instructions: OE, OF, 4E, 4F, 8E and 8F (in
fetches instructions, calculates the hexadecimal). The action taken by the CPU
addresses of operands residing in memory, upon encountering these Instructions is depen-
and controls the movement of data to and dent upon an EPU control bit In the CPU's
from memory. An EPU monitors this activity on FCW. When this bit is set, it Indicates that the
the CPU's AD lines. If the instructions fetched system configuration Includes EPUs; therefore,
by the CPU are extended instructions, all the instruction is executed. If this bit is clear,
EPUs and the CPU latch the instruction (there the CPU traps (extended instruction trap), so
may be several different EPUs controlled by that a trap handler in software can emulate the
one CPU). If the instruction is to be executed desired operation.
by a particular EPU, both the CPU and the In conclusion, the major features of this
indIcated EPU will be involved in executmg capablhty are, that multiple EPUs can be
the instruction. operatmg In parallel with the CPU, that the
If the extended mstruction Indicates a five main CPU addressmg modes (RegIster,
transfer of data between the EPU's internal Immediate, IndIrect RegIster, DIrect Address,
registers and the main memory, the CPU WIll Indexed) are available m accessing data for
calculate the memory address and generate the EPU; that each EPU can have more than
the appropriate timing SIgnals (AS, DS, 256 different instructions; and that data types
MREQ, etc.), but the data transfer Itself is manipulated by extended instructIOns can be
between the memory and the EPU (over the up to 16 words long.
3-8
Program The Program Status Informahon consists of Control Bits. The control bits occupy the
Status the Flag And Control Word (FCW) and the upper byte in the FCW. They are loaded and
Information Program Counter (PC). The Z8000 CPU uses read by the LDCTL instruction, which is
one byte m FCW to store flags and another privileged m that it can be executed only m
byte to store control bits. the System Mode. The control bits are:
Arithmetic Flags. Flags occupy the low byte NVIE Non-Vectored Interrupt Enable
in the FCW and are loaded, read, set and VIE Vectored Interrupt Enable
reset by the special mstruction LDCTLB,
RESFLG and SETFLG. The flags are: SIN System or Normal Mode
C Carry SEG Segmented Mode Enable (Z8001 only)
Z Zero The SEG bit is always 0 in the Z8002 even If
the programmer attempts to set It. In the
S Sign (l = negahve; two's complement Z8001, a 1 in this bit mdicates segmented
notahon IS used for all arithmehc on operation. A 0 in the Z8001 SEG bit forces
data elements) non-segmented operahon and the CPU inter-
PIV Even Parity or Overflow (the same bit IS prets all code as non-segmented. Thus, the
shared) Z8001 can execute modules of user code
D Decimal Adjust (differenhates between developed for the non-segmented Z8002.
addition and subtraction)
H Half Carry (from the low-order nibble)
Interrupt The Z8000 provides a powerful interrupt and (non-maskable, vectored and non-vectored),
and Trap trap structure. Interrupts are external asyn- three internal traps (system call, unimple-
Structure chronous events reqUiring CPU attention, and mented Instruchon, privileged mstruction) and
are generally triggered by peripherals needing a segmentahon trap. The vectored and non-
service. Traps are synchronous events vectored interrupts are maskable.
resulting from the execution of certain instruc- The descending order of priority for traps
tions. Both are processed in a similar manner and interrupts is: mternal traps, non-maskable
by the CPU. interrupts, segmentation trap, vectored inter-
The CPU supports three types of Interrupts rupts and non-vectored interrupts.
Effects of The Flag and Control Word and the Pro- The Program Status Area Pointer (PSAP)
Interrupts gram Counter are collectively called the Pro- specifies the beginning of the Program Status
on Program gram Status lnformation-a useful grouping Area. In the Z8002, the PSAP IS stored in one
Status because both the FCW and PC are affected by word, the lower byte of which is zero. The
interrupts and traps. When an interrupt or trap Z8001, however, stores its PSAP in two words.
occurs, the CPU automatically switches to the The first contains the segment number and the
System Mode and saves the Program Status second contains the offset, the lower byte of
plus an identifier word on the system stack. whiCh is again zero. The PSAP is loaded and
The Identifier supplies the reason for the inter- read by the LDCTL instruction.
rupt. (The Z8002 pushes three words on the In the Z8002, the first 14 words (28 bytes) of
stack; the Z8001 pushes four words.) the Program Status Area contain the Program
After the pre-interrupt or "old" Program Status Informahon for the followmg interrupt
Status has been stored, the "new" Program conditions:
Status is automatically loaded mto the FCW
Location
and PC. This new Program Status Information
(In Bytes) Condition
is obtained from a specified location in
memory, called the Program Status Area.
0-3 Not used (reserved for future use)
The Z8000 CPU allows the location of the
Program Status Area anywhere in the address- 4-7 Unimplemented instruchon has
able memory space, although It must be been fetched, causing a trap
aligned to a 256-byte boundary. Because the 8-11 PriVileged instruchon has been
Status Line code is 1100 (program reference) fetched in Normal Mode, causing a
when the new Program Status is loaded, the trap
Program Status must be located in program
12-15 System Call instruction
memory space If the memory uses thiS attribute
(for example, when using the Z8010 Memory 16-19 Not used
Management Unit or when separate memory 20-23 Non-maskable interrupt
modules are used for program and for data).
24-27 Non-vectored interrupt
39
Effects of Bytes 28-29 contain the FCW that is com- Bytes 56-59 contain the reserved word and
Interrupts mon to all vectored interrupts. Subsequent FCW common to all vectored interrupts.
on Program locations contain the vector jump table (new Subsequent locations contain the vector jump
Status PC for vectored interrupts). These locations table (the new segment number and offset for
(Continued) are addressed in the following way: the 8-bit all vectored interrupts). These locations are
vector that the interrupting device has put on addressed in the following way: the 8-bit vec-
the lower byte of the Address/Data bus tor that the interrupting device has put on the
(ADo-AD7) is doubled and added to lower byte of the Address/Data bus (ADo-AD7)
PSAP + 30. Thus, is doubled and added to PSAP + 60. Thus,
Vector 0 addresses PSAP + 30, Vector 0 addresses PSAP + 60,
Vector 1 addresses PSAP + 32, and Vector 2 addresses PSAP + 64, and
Vector 255 addresses PSAP + 540. Vector 254 addresses PSAP + 568.
In the segmented Z8001, the first 28 words of Care must be exercised in allocating vector
the Program Status Area (56 bytes) contain the locations to interrupting devices; always use
Program Status Information (reserved word, even vectors. Thus there are effectively only
FCW, segment number, offset), for the follow- 128 entries in the vector jump table. (Figure 6
ing interrupt conditions: illustrates the Program Status Area.)
Location
(In bytes) Condltion
~NO::rs:; 0
- o Z8D01 OFFSET
(IN lYlES)
--'
8-15 Unimplemented instruction has ~
.. --
- ..
been fetched causing a trap
"
..
-
16-23 PrIvileged instruction has been
fetched in Normal Mode causing ~,
a trap
so
: fo-.~~-
.... ..
24-31 System Call instruction to
_"0,
32-39 Segmentation trap (memory vio1a-
tion detected by the Z8010 Memory
Management Unit)
_ .. -
"}
72 VECTORED
INTERRUPT
JUMPTA8LE
40-47
48-55
Non-maskab1e interrupt
Non-vectored interrupt
.40
-'"
Figure 8. Program Stat... Area
,n
20480204
3-10
Z8000 CPU The way a processor addresses and manages These signals are also generated by the Z8002
Memory its memory is an important aspect In both the CPU and-as mentioned earlIer-can be used
Features evaluation of the processor and the design of a to increase the address range of this processor
computer system that uses the processor. Z8000 beyond its nominal 64K byte limit. It is not
architecture provides a consistent memory necessary to use a Z8010 Memory Management
address notation in combining bytes into words Unit with a Z8001. The segment number (upper
and words into long words. All three data six bIts of the address) can be used directly by
types are supported for operands in the Z8000 the memory system as part of the absolute
instruction set. 1/0 data can be either byte- or address.
word-oriented. These issues are discussed in more detail in
The Z8001 CPU provides a segmented the following sections, along WIth a descrip-
addressing space wIth 23-bit addressing. The tion of the method used to encode certain
Z8010 Memory Management Unit can Increase segmented addresses into one word. A brief
the address range of this processor. To support comment on the use of 16K Dynamic RAMs
a memory management system, the Z8001 pro- with the Z8001 concludes this group of sections
cessor generates Processor Status InformatIon. that deal with Z8000 CPU memory features.
Address In the Z8000 CPU, memory and 1/0 Ing and sorting of byte and word strings.
Notation addresses are always byte addresses. Words or Bit labeling within a byte does not follow thIs
long words are addressed by the address of order. The least significant bit In a byte, word
their most SIgnificant byte (FIgure 7). Words or long word IS called BIt 0 and occurs in the
always start on even addresses (AO = 0), so byte WIth the highest memory address. This is
both bytes of a word can be accessed simul- consistent with the convention where bit n
taneously. Long words also start on even corresponds to positIon 2n in the conventional
addresses. binary notation. This ordering of bit numbers
Within a word, the upper (or more signifi- IS also followed In the registers.
cant) byte is addressed by the lower (and
always even) address. Similarly, within a long LONG WOAD
ADDRESSES
WOAD BYTE
ADDRESSES ADDRESSES MEMORY
word, the upper (more significant) word IS ~
""[ -[
0000 AO
addressed by the lower address. Note that this 0000 [
0001 5B
format differs from the PDP-II but is identical 0010 [ 0010 C2
to the IBM convention. 0011
"
." [ ." [
There is good reason for choosing this for- 0100 [ 0100 02
0101 AB
mat. Because the Z8000 CPU can operate on
0110 [ 0110 2B
32-bit long words and also on byte and word
strings, it is important to maintain a continuity
of order when words are concatenated into
1000 I 1000 [
0111
1000
1001
FF
A2
long words and strings. Making ascending CONTENTS OF BYTE 0100 : "02"
addresses proceed from the highest byte of the CONTENTS OF WORD 0100 ::: "02AB"
CONTENTS OF LONG WORD 0100 = "02AB2BFF"
first word to the lowest byte of the last word CONTENTS OF LONG WORD 0010 = "C23502AB"
2048-0205
3-11
Memory Like most l6-bit microprocessors, the zaooo ignored and Al-A1S address the memory or
and I/O CPU uses a l6-bit parallel data bus between I/O. For byte operations in the read mode,
Addressing the CPU and memory or I/O. The CPU is B/W = High, Ao is again ignored, and a
capable of reading or writing a l6-bit word whole word (both bytes) is read, but the CPU
with every access. Words are always addressed internally selects the appropriate byte. For
with even addresses (Ao = 0). All instructions byte operations in the write mode, the CPU
are words or multiple words. outputs identical information on both the Low
The 28000 CPU can, however, also read and (ADo-AD7) and the High (ADs-AD1S) bytes of
write 8-bit bytes, so memory and I/O addresses the Address/Data bus. External TTL logic must
are always expressed in bytes. The Byte/Word be used to enable writing in one memory byte
(BM) output indicates whether a byte or word and disable writing in the other byte, as
is addressed (High = byte). Ao distinguishes defined by Ao. The replication of byte informa-
between the upper and lower byte in memory tion for writes is for the current implementation
or I/O. The most significant byte of the word is and may change for subsequent zaooo CPUs;
addressed when Ao is Low (Figure 8). therefore system designs should not depend
For word operations in both the read and upon this feature.
write modes, B/W = Low, Ao is simply
D ~ii
WORD
ADDRIISS
20480206
3-12
Long Offset When a segmented address is stored in gram size and execution time. Since 23 bits
and Short memory or in a register, it occupies two obviously don't fit into a 16-bit word, the 8
Offset 16-bit words as previously described for the most sIgnificant bits of the offset are omitted
Addressing PC and PSAP. This IS a consequence of the and Implied to be zero. The most significant
large addressmg range. When a segmented bit of the address word is made 0 to indicate
address is part of an instruction in the Direct Short Offset Mode. Short Offset addresses are
Address and Indexed Address Modes, there thus limited to the first 256 bytes at the begm-
are two representations: Long and Short Offset ning of each segment. This may appear to be a
addressing. severe restriction, but it is very useful,
In the general unrestricted case of Long Off- especially in the Index Mode, where the index
set, the segmented address occupies two register can always supply the full 16-bit range
words, as described before. The most signifi- of the offset. Short Offset saves one instruction
cant bIt in the segment word is aIm this case. word and speeds up execution by two clock
The Short Offset Mode squeezes the segment cycles in Direct Address Mode and three clock
number and offset into one word, savmg pro- cycles in Indexed Mode.
Using the The 28001 CPU can be combined wIth Multiple MMUs must be used when more
Z8010 Mem- another 48-pin LSI device-the 28010 MMU- than 64 segments are needed. Thus, to support
ory Manage- for sophisticated memory management. The the full complement of 128 segment numbers
ment Unit MMU provides address translation from the provided for each 28001 CPU address space,
logical addresses generated by the 28001 CPU two MMUs are required. The MMU has been
to the physical addresses used by the memory. designed for multiple-chIp configurations, both
An address translation table, containing start- to support 128-segment translation tables and
ing addresses and size information for each of to support multiple translation table systems.
the 64 segments, IS stored m the MMU. The Note that the memory management features
translation table can be written and read by do not interfere with the ability to directly
the CPU using Special 1/0 instructions. The address the entire memory space. Once pro-
MMU thus provides address relocation under grammed, the MMU (or MMUs) translates and
software control, making software addresses mom tors any memory address generated by
(i.e., logical addresses) independent of the the CPU.
physical memory addresses. The MMU contains status bits that deSCribe
But the MMU provIdes much more than the history of each segment. One bit for each
address relocation; it also monitors and pro- segment indicates whether the segment has
tects memory access. The MMU provides a been accessed; another bit indicates whether
Trap input to the CPU and-if necessary-an the segment has been written. This is important
mhibit signal (SUP) to the memory write logic for certain memory management schemes. For
when specific memory-access violahons occur. example, the MMU indicates which segments
The MMU provides the following types of have been updated and, therefore, must be
memory protection: saved on disk before the memory can be used
by another program.
Accesses outside the segment's alloted
When translating logIcal addresses to phys-
memory can be prevented.
ical memory addresses, the MMU must do the
Any segment can be declared invalid or followmg: access its internal 64 x 32-bit RAM,
non-accessable to the CPU. using the segment number as the address, then
Segments can be declared Read Only. add the 16 bits of RAM output to the most
SIgnificant address byte (ADs-AD1S) and final-
By deslgnatmg a segment as System Only,
ly place the result on its Address outputs. The
access can be prohIbited during the Normal
least Significant byte (ADo-AD7) bypasses the
Mode.
MMU.
Declaring a segment Execute Only means it The internal RAM access time is approxI-
can be accessed only during mstruction mately 150 ns. Throughput delay is avoided by
access cycles. Data or stack use is pro- making the segment number available early:
hibited. SNo-SN7 are output one clock period earlier
Any segment can be excluded from DMA than the address information on ADo-AD7.
access. In summary, the 28000 CPU supports
sophisticated memory management through
Segments can have a Direchon And Write
such architectural features as the Status Lmes,
Warning attribute, whICh generates a trap
the R/W and SIN lines, Segment Trap input
when a write access is made in the last 256
line, and early output of segment numbers.
bytes of its size. This mechanism can be
used to prevent stack overflow.
3-13
Using 16K 28000 systems usually implement most of requires that RAS must wait for the availability
Dynamic their memory with 16K x I-blt dynamic RAMs of the most significant address bits from the
RAMs with that have time-multiplexed addresses (2ilog MMU. During refresh, the RAS decoder must
the Z8001 also manufactures this device-the 26116). be changed to activate all memories
In 28001-based systems with MMUs, CPU simultaneously.
Address/Data lines AD1-AD7 supply row Gating CAS does not achieve lower power
addresses, MMU address outputs As-AI4 sup- consumption; however, this technique allows
ply column addresses, and MMU outputs the use of slower memories because RAS can
A15-A23 are decoded to generate Chip Select be activated as soon as the CPU address out-
signals that gate either RAS or CAS or both. puts are stable, without waiting for the MMU
Gating RAS reduces power consumption delay. Also, there is no need to change the
because all non-selected memories remain CAS decoder during refresh.
in the standby mode. But this technique
Data Types The 28000 architecture directly supports duces a number of powerful instructions that
and bits, digits, bytes, and 16- or 32-bit integers as extend the capabilities of microprocessors. The
Instructions primitive operands in its instruction set. In remaining sections of this paper describe
addition, the rich set of addressing modes sup- 28000 data types, addreSSing modes, and a
ports higher-level data constructs such as selection of novel instructions.
arrays, lists and records. The 28000 also intro-
D;::ta Typss Opcrarids a.re I, 4, 8, 16, 32, cr 64 bits, as operate on 8-. ! 6-. or 3?-bit operands: Multi-
specified by the instruction. In addition, ply instructions can operate on 16- or 32-bit
strings of 8- or 16-bit data can be manipulated multiplicands; and Divide instructions can
by single instructions. Of particular interest operate on 32- or 64-bit dividends. The Shift
are the increased precisions of the arithmetic instructions can operate on 8-, 16-, and 32-bit
instructions. Add and Subtract instructions can registers.
Addressing The rich variety of addressing modes offered is useful, for example, in accessing fields
Modes by 28000 architecture includes: Register, within a record whose format is fixed at com-
Immediate, Indirect Register, Direct Address, pile time.
Index, Relative Address, Base Address, and Base Index. The memory address in this
Base Index. Three are of particular interest addressing mode is contained in a register (the
with respect to high-level data structures: base) and is modified by the contents of
Indirect Register, Base Address, and Base another register (the index). This mode can be
Index. These modes can be used for lists, useful in accessing the components of an
records, and arrays, respectively. array, because the index of the component is
Indirect Register. In this addreSSing mode, usually calculated during execution time-as a
the contents of the register are used as a function of the index of a DO-Loop, for
memory address. This mode is needed example.
whenever special address arithmetic must be Index VB. Base Address. In the 28002 and in
performed to reference data. Essentially, the the 28001 running non-segmented, these two
address is calculated in a register and then addressing modes are functionally equivalent,
used to fetch the data. For example, this mode because the base address and dlsplacement
is useful when manipulating a linked list, are both 16-bit values.
where each entry contains a memory pointer to When the 28001 runs segmented, there is a
the memory location of the next entry. Essen- difference: in the Index mode, the base
tially, the pointer is loaded into a register and address (including the segment number) is
used to access the next item on the list. When contained in the instruction, in either Short
the list item is large or has a complex struc- Offset or Long Offset notation. The 16-bit dis-
ture, the Base Address or Base Index Modes placement stored in a register is then added to
can be used to access various components of the offset in the base address to calculate the
the item. effective address. In the Base Address Mode,
Base Address. In this addressing mode, the on the other hand, the 16-bit displacement is
memory address contained in the register (the speCified in the mstruction and is added to the
base) is modified by a displacement m the offset of the base address that is stored in a
instruction (known at compile time). This mode long-word register.
3-14
The Instruc- The 28000 offers an abundant instruction set Multiply (MULT) provides signed (two's com-
tion Set that represents a major advance over Its plement) multiplicahon of two words, generat-
predecessors. The Load and Exchange instruc- ing a long-word result; or of two long-words
hons have been expanded to support operating generatmg a quadruple word result. No byte
system functions and conversion of existing multiply exists because it is rarely used and,
microprocessor programs. The usual Arith- after sign extension, can be performed by a
metic instructions can now deal with higher- word multiply.
precision operands, and hardware Multiply Divide (DIV) prOVides signed (two's comple-
and Divide instructions have been added. The ment) diVision of a long word by another word,
Bit Manipulation mstructions can access a generating a word quotient and a remainder
calculated bit posihon within a byte or word, word; or of one quadruple-word by a long-
as well as specify the position statically in the word, generating a long-word quotient and
instruction. long-word remainder.
The Rotate and Shift instructions are con- Both Multiply and Divide use a conforming
siderably more flexible than those in previous register assignment. That IS, a multiply fol-
microprocessors. The String mstructions are lowed by a divide on the same registers IS
useful in translating between different essentially a no-op. The register designation
character codes. Special I/O instructIOns are used m the operation description must be even
mcluded to manage peripheral devices, such for word operations and must be a multiple of
as the Memory Management Unit, that do not four for long-word operations.
respond to regular I/O commands. Multiple-
processor configurations are supported by
special instructions. Logical Instructions.
The following instructions exemplify the Test Condition Code (TCC) performs the same
mnovative nature of the 28000 instruction set. test as a Jump mstruction, but affects the least
A complete list of 28000 instruchons can be significant bit of a speCified register instead of
found in the reference materials listed at the changing the PC.
end of this tutorial.
Program Control Instructions.
Load and Exchange Instructions. Call Relative (CALR) is a shorter, faster ver-
Exchange Byte (EX) is practical for converting sIOn of Call, but With a limited range.
2-80, 8080, 6800 and other microprocessor Decrement And Jump If Non-Zero (DJNZ) is a
programs into 28000 code, because the 28000 one-word basic looping instruction.
uses the opposite assignment of odd/even Jump Relative (JR) is a shorter, faster version
addresses in 16-bit words. of Jump, but with a limited range.
Load Multiple (LDM) saves n registers and is
useful for switchmg tasks. Bit Manipulation Instructions.
Load Relative (LDR) loads fixed values from Test Bit, Reset Bit, Set Bit (BIT, RES, SET) are
program space into data space. available in two forms: static and dynamic. For
the static form, any bit (the pOSition IS defined
Arithmetic Instructions. in the immediate word of the instruction)
Add With Carry and Subtract With Carry located in any byte or word in any register or
(ADC, SBC) are convenhonally used m 8-bit in memory can be set, reset or tested (mverted
microprocessors for multiprecislon arithmetic and routed into the 2 flag).
operations. These instruchons are rarely used For the dynamic form, any bit (the position
with the 28000 CPU because it has 16- and is defined by the content of a register that is,
32-bit anthmehc instructions. in turn, speCified in the instruction) located in
any byte or word in any register, but not in
Decrement By N and Increment By N (DEC, memory, can be set, reset or tested.
INC) are intended for address and pointer
manipulation, but can also be used for QUick Test And Set (T5ET) is a read/modify/wnte
Add/Subtract Immediate with 4-bit nibbles. instruction normally used to create operatmg
The flag setting is different from Add/Subtract system locks. The most Significant bit of a byte
instructions-as is conventional-in that the or word m a register or m memory is routed
Carry and Decimal adjust flags are unaffected into the S flag bit and the whole byte or word
by the Increment and Decrement instructions is then set to all Is. Durmg thiS instruchon, the
to support multiple precision arithmetic. processor does not relinquish the bus.
Decimal Adjust (DAB) automatically generates Test Multi-Micro Bit and Multi-Micro
the proper 2-digit BCD result after a byte Add Request/Set/Reset (MBIT, MREQ, MSET,
or Subtract operation, and eliminates the need MRES) are used te:> synchronize the access by
for speCial decimal arithmetic instructions. multiple microprocessors to a shared resource,
3-15
The Instruc- such as a common memory, bus, or I/O TRIB, except they repeat automatically until
tion Set device. the contents of the length register become
(Continued) Note that the instruchon MREQ (Multi- zero. They are therefore useful in straightfor-
Microprocessor Request) has nothing what- ward translation applications.
soever m common with the MREQ (Memory Translate And Test, Decrement/Increment
Request) output from the 28000 CPU. (TRTDB, TRTIB) tests a character according to
the contents of the translation table.
Rotate and Shift Instructions. Translate And Test, Decrement/Increment And
The 28000 CPU has a complete set of shIft Repeat (TRTDRB, TRTIRB) scans a strmg of
instruchons that shdt any combination of bytes characters. The first character IS tested and,
or words, right or left, arithmetically or logIC- dependmg on the contents of the translation
ally, by any meanmgful number of pOSitions as table, the process stops or skips to the next
specified either in the mstruction (static) or in character. Stopped characters can be used for
a register (dynamIc). further processing.
The CPU also has a smaller repertoire of
rotate mstructions that rotates bytes or words,
eIther nght or left, through carry or not, and 1/0 and Special I/O Instructions.
by one bit or by two bits. The 28000 CPU has two complete sets of I/O
The mstruchons Rotate DigIt Left and Rotate instructions: Standard I/O and Special I/O.
Digit Right (RLDB, RRDB) rotate 4-bit BCD The only difference is the status informahon on
dIgIts right or left, and are used m BCD arith- the STo-ST3 outputs. Standard I/O mstructions
metIc operations. ilre u<ecl In "nmmllnicate with 2-Bus compat-
ible peripherals. SpeCial I/O mstructions are
typically used for communicating with the
Block Transfer and String Manipulation Memory Management Unit.
Instructions. Both types of instruchons transfer 8 or 16
Translate And Decrement/Increment (TRDB, bits and use a type of 16-blt addreSSing
TRIB) is used for code conversion, such as analogous to the 28002 memory-addressing
ASCII to EBCDIC. These instructions translate scheme: For word operations, Ao is always
a byte string in memory by substituting one zero; in byte-input operations, Ao is used
string by Its table-lookup equivalent. TRDB internally by the CPU to select the appropriate
and TRIB execute one operation and decre- byte; in byte-output operations, the byte is
ment the contents of the length register; thus duplicated in the high and low bytes of the
they are useful as part of loop performing address/data bus, and external logic uses Ao
several actions on each character. to enable the appropriate output device.
Translate, Decrement/Increment and Repeat
(TRDRB, TRIRB) are the same as TRDB and
Biliog- Selected Publications on the Z8000 Family Z8000 PLZIASM Assembly Language
raphy Z80011Z8002 CPU Product Specification Programming Manual (03-3055-01)
(00-2045) Z8010 Z-MMU Product Specification (00-2046)
Z8000 CPU Instruction Set (03-8020-01)
00-2048-A
316
A Small
Z8000 System
B
Zilog Application Note
Component Applicahon Engmeermg
January 1980
Introduction This application note describes the hard- Module (part number 05-6101-01).
ware design Implementahon of a small com- The design uses a minimal number of TTL
puter using the 2ilog 28002 16-blt mICro- support devices and, whenever possible, gate
processor, ROMslEPROMs and dynamic RAMs functions have been combined mto MSI cir-
plus parallel and serial 1/0 devices. The mter- cuits. The result is a design that uses MSI TTL
face requirements of the 28002 to memory and circuits in a very efficient-but sometimes non-
to 280A peripherals are described and design obvious-way that mmimizes the package
alternatives are given whenever pOSSible. ThiS count. Because some of the design techniques
design is similar in structure and is software may not be self-explanatory, an effort has been
compatible with the 2ilog 28000 Development made to explam them.
General Figure 1 shows a block diagram of the relieve the processor from simple counting and
Structure design. The 28002 16-bit microprocessor is the timing tasks and generate the programmable
heart of the system. ThiS high-performance baud-rates for the serial 1/0 channels. Eight
CPU offers a regular architecture, a powerful switches can be interrogated and mterpreted
instruction set, a sophisticated interrupt struc- by the program.
ture, and high throughput at a modest 4 MHz The block diagram also indicates the various
clock rate. support functions. A crystal-controlled clock
For a description of the 28002, see the circuit generates a 28002 and 280A compahble
Z8001lZ8002 CPU Product Specification clock signal plus two complementary TTL
(03-8002-01). For a detailed description of clocks. Address buffers drive the memory and
the 28000 instruction set, refer to the Z8000 1/0 deVices; address latches demulhplex the
PLZIASM Assembly Language Manual hme-shared Address/Data bus.
(03-3055-01) . The ROM array uses a One-of-Eight Address
Fixed program and data information is Decoder and the RAMs are driven by an
stored m an array of 2K x 8 ROMs or EPROMs; address mulhplexer and a RAS/CAS
16 16K x 1 dynamiC RAMs provide 32K bytes generator. The timing for all these functions
of read/write storage. InpuVoutput is handled origmates in the bus control and timmg cir-
by five 1/0 deVices. Two 280A PIOs prOVide 4 CUlt. The 1/0 devices are selected by an 1/0
byte-Wide bidirectional ports (32 lines) with decoder and receive 280A equivalent control
handshake control. A 280A SIO prOVides two signals generated by the 28002 to 280A Con-
fully mdependent full-duplex asynchronous or trol Translator. The following sections contain
synchronous serial data communications chan- detailed descriptions of these circuits.
nels. Four counterltimers in the 280A CTC
3-17
WAIT
WAIT
~j.,
STATE
GENERATOR
ROM CE RAS
DECODER
2K x 8
IV' RAS ICAS EVE~
--
ROMs CAS 16K DYNAMIC
CASODD RAMs
OR
EPROMs (32K BYTES)
--y ADDRESS g
1
MUX
7 LINES
WAIT
A iI.
(
A ~
BlolR
A iI. 11 LA,-LA"
1
~ 0
ADo-AD15 BUFFERS ) 16-81T BIDIRECTIONAL DATA BUS
'(--y 'I V
16BIT LATCHED ADDRESS BUS
I
J
LATCHES lAo-LA1S
Z8002
iI.
I A LA
'- lO
'f'
CONTROL
V
BUS CONTROL AND TIMING
rl 110
DECODER
00
,-----. Vi STATUS
1 iI.
::>I
STATUS
L - ._ _
DECODER
Z80A PERIPHERALS
I 1
L
WITH DAISYCHAINED INTERRUPT PRIORITY 3 STATE BUFFER
~
CLOCK zaOO2 M1
+ TO
Z80A
lORa
zaOA
~I19<19<191
0-- CONTROL RD Z80A. Z80A ZSOA
PIO PIO 510
SWITCHE~
TRANSLATOR CTC
MOS CLOCK EIGHT
C
-=c.-
CLOCK
GENERATOR I<>--CLOCK
I---CLOCK
CLOCK
INTERRUPT
iC~~r4r tHffil t t
4 BYTE POFtTS 4 COUNTER! TWO FULL DUPLEX SERIAL
WITH HANDSI>iAKE TIMERS CHANNELS WITH HANDSHAKES
~
~
w Figure 1. Block Diagram
Clock The 28002 requires a continuously running safest way to insure it is to start with a crystal
Generation clock with a frequency between 500 kHz and oscillator frequency that is twice the clock
4 MHz. Most 28002 applications are perfor- rate, and divide it with a toggling flip-flop.
mance oriented and the clock rate is therefore The Z8002 clock mput is not TTL compati-
usually set close to the maximum limit of ble. It requires a High level within 400 mV of
4 MHz. At this frequency, the speCified Vee. A resistive pull-up can achieve this level,
requirements for clock width (minimum of but cannot guarantee the required rise-time
105 ns High or Low) and clock transition times (20 ns from 0.8 to 4.0 V) when driving the
(maximum of 20 ns rise or fall) require careful ",,30 pF clock input capacitance. The strin-
attention. At 4 MHz, a 50% clock duty cycle is gent rise time reqUIrements dictate the use of
indirectly implied by this specification and the an active pull-up as shown in Figure 2.
Vee
O.01/tF
R2 OPTIONAL
O.01~F I
L...f-~:a
12<l BYPASS
01
2N57710R
A1 2N3546
470 AS
22
MOS CLOCK
1/6504
L...f><~---CLOCK
1/6504
C80600054
3-19
CPU Output The 28002 outputs can sink 2 rnA while Very small systems can be built without TTL
Buffering maintaining TTL noise margins and can thus buffering of the CPU outputs, but most systems
drive five LS-TTL inputs. All output delays require TTL buffering of the Address/Data
are specified for a capacitive load of up to lines and major control outputs, like AS, DS,
50 pF. They increase by approximately MREQ and R/W.
0.1 ns/pF of additional capacitive load.
Bidirectional buffering of the AID lines. The The bus transceivers are controlled by three
Address/Data lines require Bus Transceivers, CPU control outputs as shown in the following
such as the LS243 Quad Non-Inverting Bus truth table.
Transceiver with separate Enable inputs for the
BUSACK R/W DS
two directions (one active High; the other
active Low), or the LS245 Octal Non-Inverting H H L Enable Receiver
Bus Transceiver with a Direction Control input (input Data into CPU)
and an active Low Enable input. H H H } Enable Transmitter
Figure 3 shows the logic that controls four H L H (output Address or Data
LS243 Quad Transceivers; Figure 4 shows the H L L from CPU)
even simpler logic that controls two LS245 L X X Disable Transceiver
Octal Tranceivers.
ADo-AD1S (TO/FROM CPU)
DS~ I I I
888
R/W-----'"
'824.
LS10
ADO-AD1S (TO/FROM SYSTEM)
R/W-----'
Unidirectional Buffering of CPU Control shared, BUSACK must be used to control the
Outputs. The following CPU control outputs latches and transceivers, as shown in Figures 4
may require unidirectional buffering: AS, DS, through 6.
MREQ, R/W, NiS, B/W.
The buffered signals must be 3-stated when FROM CPU
'"~'~:~ :~~~I
3-State Buffer can perform this function as
shown in Figure 5. The LS244 Octal 3-State
Buffer buffers eight Signals, but uses a 20-pm
package.
In a simple system, such as the one
described here, BUSREQ is not used, so AS MREQ Nt" Bli'
os RIW
BUSACK is therefore always High. In a more TO SYSTEM
complex system with direct memory access, a
Low on BUSACK indICates that the CPU has Figure 5. Control Signal Buffering
relinquished the bus. If the buffered bus IS
ROM Most microprocessors use novolatile memory When driven with a 4 MHz clock, the za002
Addressing for part of their program memory. Since the requires a read access time (address valid from
program status information for the Z8002 is the CPU to data required into the CPU) of
read after Reset from locations 0002 and 0004, 400 ns. After subtracting a 27 ns propagation
it is natural to use the lower half of the delay through the LS373 address latches and
addressing space for ROM or EPROM. an 18 ns propagation delay through the LS243
This application uses 2716-type 2K x 8 transceivers, the ROM or EPROM must have
EPROMs addressed by the latched addresses an access time (address in to data out) of
LAI-LAII. Pairs of 2716s store the low and belter than 355 ns. Some ROMs and EPROMs
high byte of each word. Ao is ignored since have a longer access time and therefore
the za002 always reads a full word from require an additional wait state that relaxes the
memory. LAI5 must be used as a Chip Select access time requirement by an additional
input to separate the ROM and RAM areas. 250 ns. Figure 8 shows a 2-input NAND gate
When more than 2K words of ROM or EPROM that generates a Wait signal whenever LAI5 is
are used, an LSl38 one-of-eight decoder Low and Q2 is High, thereby adding a wait
selects between the ROM and EPROM pairs. state to every ROM/EPROM access.
RAM Address Dynamic 16K X 1 RAMs such as the Z6116 Address Multiplexing. Two LS157 Quad Two-
Multiplexing provide read/write random-access storage. Input Multiplexers route the 14 address outputs
and RAS CAS Sixteen of these devices populate the upper LAI-LAI4 into the seven RAM address inputs.
Generation half of the addressable memory space MREQ synchronized with the rising clock edge
(LAI5 = High). Dynamic 16K RAMs use is a convenient signal to control this multi-
address multiplexing to reduce the package plexer (Figure 7).
pin count, thus requiring only seven address
inputs plus strobe inputs RAS and CAS.
FROM ADDRESS LATCHES
LA 8 1 9 2 10 3 11 4 12 6 13 8 14 7
CLOCK
COO6000SS CSOOOOQS9
3-21
RAM Address HAS and CAS Generation. The address falling edge of CLOCK during AS clocks Q 1
Multiplexing strobes RAS and CAS must be timed carefully Low. The next falling clock edge leaves Q 1
(Continued) with respect to the address information and the unaffected, but clocks Q2 Low. The next fall-
multiplexer control. Concee!!:!ally, MREQ ing edge clocks Ql High and leaves Q2 unaf-
might be used as RAS and DS as CAS. This fected. The next falling clock edge clocks Q2
would, however, require a memory read High and leaves Ql High unless AS is Low, in
access time from the falling edge of CAS of which case the cycle is repeated. Ql is Low
approximately 120 ns (parameter 33 in the from the center of the first to the center of the
Z80011Z8002 Product Specification Composite third T state. Q2 is Low from the center of the
AC Timing Diagram, minus the 30 to 40 ns second to the center of the fourth T state.
used by the CAS drivers and bus trans- The left half of the LS139 Dual One-of-Four
ceivers). Only the fastest 16K dynamic RAMs Decoder generates CAS by ANDing three
(the 2ilog 26116-2, for example) meet this signals: LAI5, MUX-S, and an auxilliary signal
requirement. Consequently, it is more prac- active during Read or DS.
tical to use a small amount of clocked TTL During a read operation, CAS becomes
logic to generate earlier RAS and CAS signals active at the beginning of T2; that is, on the
and thus relieve the access time requirements rising edge of CLOCK after MREQ has gone
so that even slow 16K RAMs (26116-3 and -4) Low. During a write operation, CAS is delayed
can be used. Figure 8 shows the circuit that until the beginning of DS, when output data is
generates RAS and CAS. guaranteed valid. The flip-flop stretches the
RAS is a 2-clock period (500 ns at 4 MHz) width of DS, thus stretching CAS (during write
wide active-Low s.!5Elal starting on the falling operations) from 160 to 200 ns, as required by
clock edge when AS IS Low. The address mior- slower memories.
mation is valid and stable during the specified The right half of the LS139 decoder controls
hold time 50 ns) immediately after the fall- the routing of CAS to the two memory byte
ing edge of RAS. RAS is generated by an banks. The 28002 addresses memory as bytes,
LSI09 edge-triggered dual JK flip-flop, but usually accesses words, ignoring Ao. It
clocked by CLOCK (that is, of a polarity oppo- uses Ao only when writing a byte, in which
site to the 28002 clock). At the end of a case it suppresses CAS to the byte bank that is
machine cycle both Ql and Q2 are High. The not being written.
r-------------t----------RAS
D Q
CLOCK
MUXS - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
C8060-0060
3-22
RAM Address T, T, T,
Multiplexing
(Continued)
~.-l
CLO CK
- l I
AIT
\ LA15
V
0
INSERTS WAIT STATE
STAT US
(BIW. N/S.
STo- ST,)
Ai
IIQ
HAS
Qa
/
MU x-s
1\ V
CAS REAO\ \WRITE
V
I 1
Figure 9. BAS and CAS Generation
C8060-0068
3-23
RAM Address Dynamic Memory Refresh. No external hard- refresh requirements of typical 16K dynamic
Multiplexing ware is required for memory refresh. The RAMs.
(Continued) Z8002 provides automatic memory refresh if Figure 11 shows the relationship between
properly initiated through a LDCTL instruc- the upper byte of the refresh control register
tion into the Refresh Control Register (Figure and the refresh period expressed in clock
10). Loading a 9EOO generates a refresh oper- cycles. (Refer to the Z8000 PLZIASM Assembly
ation every 60 clock cycles (15 p.s with a Language Programing Manual, 03-3055-01 for
4 MHz clock). This satisfies the worst-case further information.)
I
RATe
l I I
:
I ROW
i ADDRESS
I I l I I I
.
3
w 4 NO REFRESH
~ 5
a:
w 6
o.
o.
:>
u. 7
o
..
~
8
9
256
32
4
36
8
40
12
44
16
48
20
52
24
56
28
60
Z
a: A 64 68 72 76 80 84 88 92
w
o. B 96 100 104 108 112 116 120 124
o.
:>
C 128 132 136 140 144 148 152 156
0 160 164 168 172 176 180 184 188
E 192 196 200 204 208 212 216 220
F 224 228 232 236 240 244 248 252
Status The Z8002 provides encoded status informa- word of an instruction fetch. Two LSI38
Decoding tion on four outputs (STo-ST3). which dis- One-of-Eight Decoders can generate all the
tinguish between three different interrupt individual Status signals. For a simple system,
acknowledge cycles; memory refresh; I/O only the first ten status codes have to be
reference; internal operation; data memory, decoded. A single LS42 One-of-Ten Decoder is
stack or program memory access; and the first sufficient for this purpose (Figure 12).
INTERNAL OPERATION
MEMORY REFRESH
FROM
CPU
I :~~
512
ST,
a
If REQUEST
SPECIAL 110
RESERVED
NMI
NVI
I ~Nri:~~~~DGE
l
VI
DATA MEMORY
STACK ACCESS
LA,
r- -UI". -
Q,
YO
Y1
YO
.3
.4
LS08
LA, A YO "ET'
=::J....- TO
-l- zaOA
PERIPHERALS
iii -!!: ~
-
J
AS ~SO.
LAo ... LO,.
FROM
zaooo
BUS
....
_
T oj
PAl PRI
-r:::::j
LS10
)0-
~
IORQ
CLOCK
D
LK
1.81'
11 0----
-r- D
' - - ~Cl.K
LS74
0
i1
7,;;
...,I~
CUI CUI
r -c...=r
.5V
RlW
VIACK
C8060-0064
3-25
Interfacing The first four I/O devices addressed when IORQ is Low, the highest priority interrupt
Peripheral LAs is Low are four Z80A peripheral com- requestor (the one with IEI High) places its
Devices ponents. The fifth peripheral is a set of eight interrupt vector on the data bus and sets
(Continued) switches that can be read by the CPU, which its internal interrupt-under-service latch.
addresses them as a peripheral device. The Figure 14 shows the Interrupt Acknowledge
user can thus specify anyone of 256 different timing.
conditions (for example, choosing between 16 The circuit shown in Figure 13 generates the
different baud rates for each of the two serial MI, IORQ, and RD signals required by the
I/O channels). The sixth CE output addresses a Z80A peripherals during an interrupt
phuiltom peripheral called RET!, which is acknowledge cycle.
activated at the end of an interrupt service Return From Interrupt. At the end of an inter-
operation. rupt service routine the interrupt-under-ser-
The mterrupt operation requires some extra vice latch in the Z80A peripheral that has been
logic and software to make the Z80A per- serviced must be reset. The zaOA CPU
lpherals compatible with the Z8002. zaOA accomplishes this by executing a special
peripherals request a vectored interrupt by 2-byte instruction with the opcode sequence
pulling the VI input of the CPU Low. The CPU ED-4D (RETI) appearmg on the data bus. All
(Z80A or Z8002) samples this input at a peripherals monitor this sequence and
specified time prior to the end of any instruc- manipulate the daisy cham to reset the
tion execution. The Z8002 then acknowledges appropriate internal interrupt-under-service
the interrupt with a specific Status code latch. The normal daisy-chain operation can
(VIACK). The Z80A, whICh has no dedicated be used to detect a pending interrupt;
Interrupt Acknowledge output, acknowledges however, it cannot distinguish between an
interrupts by issuing a unique combination of interrupt under service and a pending
control signals: IORQ active during an MI unacknowledged interrupt of a higher priority.
cycle (MI normally indicates the opcode fetch Whenever "ED" is decoded, the daisy chain is
cycle of an instruction execution). Z80A modified by forcing High the IEO of any inter-
peripherals resolve potential conflicts between rupt that has not yet been acknowledged. Thus
overlapping interrupt requests from different the daisy chain identifies the device presently
interrupting devices by means of a daisy-chain under service as the only one with an IEI High
arrangement between the IEO outputs and the and an lEO Low. If the new opcode byte is
IEI inputs of the peripheral components. The "4D," the interrupt-under-service latch is reset
highest-order peripheral has ltS IEI perma- (Figure 15).
nently tied High. For any peripheral that has The Z8002 does not have the equivalent RET!
no interrupt pending or under service, instruction and must therefore simulate it with
lEO = IEI. Any peripheral that has an interrupt a combination of hardware and software. A
pending or under service forces its lEO Low. software sequence at the end of every interrupt
To insure stable conditions in the daisy service routine writes two consecutive bytes
chain, all interrupt status slgnals are pre-
vented from changing while MI is Low. When
T, T, TWA T, T, T, TWA T,
CLOCK
iS~ U
Di \ r
iii1~\._ _ _ _ _ _ _ _---, iii1
IORQ (zao)
IORQ (zao) HIGH
AD--~H~'G~H--------------------------- AD
Do-D7 -----< VECTOR l-- - -- DO-D7-O-< "ED"
>-e:>-< "4D"
>-
Figure 14. Interrupt Acknowledge Cycle Figure 15. Return from Interrupt Cycle
C8060-0066 C8060-0065
3-26
Interfacing (ED followed by 4D) into the phantom per- Driving Z80A Peripherals. The 280A PIa,
Peripheral ipheral called RETI. The recommended soft- CTC and SIO are directly connected to the
Devices ware sequence IS as follows: appropriate lines, as follows. The bidirectional
(Continued) ADo-AD7 buffers are connected to the Do-D7
DI Disable Interrupts data inputs/outputs on the peripherals.
LDB RLl, #%ED Load FIrSt Byte The address bits LAj and LA2 are used as
OUTB RET!, RLl Output First Byte
Port Select (AlB) and Control Data select
LDB RLl, #%4D Load Second Byte
(C/D) on the PIa and SIO, and as Channel
OUTB RET!, RLl Output Second Byte
Enable Interrupts
Select (CSo, CSj) on the CTC.
EI
RET Return From Interrupt The Interrupt outputs of all peripherals are
interconnected (pulled up with a 4.7kO resistor
To prevent the two byte simulated RET! to Vee and connected to the VI input of the
instruction from being mterrupted, interrupts 28002). The lEI-lEO mterrupt daisy chain of
must be disabled. If NMIs can occur at any the 280A peripheral devices must be con-
time, then interrupts must remam disabled nected appropriately to establish the desired
throughout the NMI service routine. This hierarchy of mterrupt priorities.
allows the 280A peripheral devices to decode The 280A PIa requires a Ml to enable the
correctly a RET! instruction. During the two peripheral circUit's internal interrupts. This
OUTB operations, each four clock cycles long, can easily be accomplished by wrltmg a
RETI is Low, VIACK is High and the 280A dummy byte (OOH) to the RETI port after PIa
control signals MT and RD are Low. interrupts have been enabled.
Reset The 28000 Reset input requires a minimum more than adequate margin for noise Immun-
High level of 2.4 V. While TTL High levels are ity. If an open collector gate is not readily
guaranteed to be at least 2.4 V, this does not available, a standard TTL gate may be used
leave margin for noise Immunity. If an open with an output pullup resistor. In this case, the
collector buffer (such as a 7407) is available, value of the pullup resistor should not be less
an output pullup resistor to + 5 V will provide than 300 O.
Conclusion This Application Note demonstrates that a also shows how the readily-available 280A
small, but powerful computer can be bUilt peripheral circuits interface easily to the
around the 28002 l6-blt microprocessor usmg 28002, taking advantage of the similarity in
very few standard TTL support packages. It the 280A and 28000 interrupt structures.
3-27
An Introduction to the
Z8010 MMU Memory
Management Unit
~
Zilog
Tutorial
Information
March 1981
Introduction The declming cost of memory, coupled wIth Preventmg one user from unauthorized
the mcreasmg power of mIcroprocessors, has access to memory resources or data
accelerated the trend in mIcrocomputer Protectmg the operatmg system from unex-
systems to the use of hIgh-level languages, pected access by the users.
sophisticated operatmg systems, complex pro-
grams and large data bases. The Z8001 mICro- The Z8010 provIdes all these features plus
processor supports these advances by offering addItional features that permIt a variety of
multiple 8M byte address spaces as well as a system hardware configurations and system
rich and powerful mstructlon set. The Z8010 deSIgns.
Memory Management Umt (MMU) supports the ThIs paper exammes the various uses of
Z8001 processor in the effIcient and flexIble memory management m computer systems and
use of its large address space. how memory management techmques gen-
Support for managing a large memory can erally meet these reqUIrements. The major
take many forms: features of the Z8010 MMU illustrate how
memory management functions can be sup-
Providmg a logIcal structure to the memory
ported by hardware. A few examples demon-
space that IS largely independent of the
strate how this LSI CIrcuIt can be used to
actual physical location of the data
configure several different memory man-
Protecting the user from madvertent agement systems.
mistakes such as attemptmg to execute data
Motivations The primary memory of a computer IS one of procedure or as complex as a set of related
for Memory ItS major resources. As such, the management routmes.) If the populahon of memory-resIdent
Management of thIs resource becomes a major concern as tasks can vary over hme, a useful feature of a
demands on It mcrease. These demands can system would be the abIlity for a task to re:lde
arise from dIfferent sources, three of whIch are anywhere m memory, and perhaps m several
of mterest m the present context. The hrst dIfferent locations durmg ItS lifetime. Such
stems from multiple users (or multiple tasks tasks are called reiocaiabie, and a system m
wlthm a dedICated application) contendmg for whICh all tasks are relocatable generally offers
a limIted amount of physIcal memory. The greater flexIbIlity m respondmg to changmg
second comes from the deSire to mcrease the system envIronments than a system m whICh
mtegrlty of the system by lImltmg access to each task must resIde m a hxed location.
variOUs portions of the memory. The fmal A second Issue that arises m multi-task
source arises from Issues surroundmg the envIronments IS that of sharmg. Separate tasks
development of large, complex programs or may execute the same program on dIfferent
systems. Each of these three sources mvolves a data, and may therefore share common code.
multifaceted group of related Issues. For example, several users compllmg FOR-
When multiple tasks constitute a gIven TRAN programs may WISh to share the com-
system (for example, multiple users of a system piler rather than each user having a separate
or multiple sub-tasks of a dedIcated applica- copy m memory. Alternatively, several tasks
tion), the possIbIlity eXIsts that not all tasks may WIsh to execute dIfferent programs using
may be m primary memory at the same time. the same data as mput, and It may be possIble
(A task IS the action of executmg a program on for these tasks to access the same copy of the
!Is data; a task may be as sImple as a smgle
3-29
Motivations mput. For example, a user may wish to print a Protecting a task from itself obviously helps in
for Memory PASCAL program while it is being compiled; debugging a large program, but there are
Management the print process and the compiler process other system features that can aid in develop-
(Continued) could access the same copy of the text hIe. ing complex systems. Modern methodology for
A third issue in mulh-task systems is protect- developing large systems dictates partitioning
ing one task from unwanted interactions with a task into a number of small, simple, self-
another. The classic example of unwanted contained sub-tasks with well defined inter-
interaction IS one user's unauthorized readmg faces. Each sub-task generally interacts with
of another user's data. Prohibiting all such only a few other sub-tasks and thIs commumca-
interachons conflicts with the goal of sharing tion is carefully controlled. This methodology
and so thIs issue is usually one of selectively promotes a systems design that can be readJly
prohIbiting certam types of mterachons. The modified, but It also tends to promote the crea-
Issue of protectmg memory resources from tion of a large number of nearly mdependent
unauthorized access IS usually included m the sub-tasks and many data structures accessible
larger set of issues relating to system integrity. to only one or a few of these sub-tasks.
System integrity takes many forms in addI- Because modern systems are mcreasingly
tion to protecting a task's data from unwanted driven to support many interacting tasks,
access. Another aspect is preventing user tasks possibly written and compiled separately, they
from performing operatmg system functions must also enforce some communicahon pro-
and thereby mterruphng the orderly dispatch tocol wIthout sacrificing efficIent operation.
of these tasks. For example, most large systems Modern memory management systems can
prevent a user task from dIrectly inihatmg I/O offer effective tools for implementing large
operahons because thIs can disrupt the correct systems designed uSIng thlS rnethuuuluy y.
funchonmg of the system. In summary, the major goals of memory
Another aspect of separatmg users from management systems are to:
system functions relates to separating system ProvIde flexible and efficient allocation of
I/O transfers from user tasks, especIally wIth memory resources during the execuhon of
respect to error condlhons. For example, an tasks
error durmg a direct memory access, say to a
Support mulhple, independent tasks that
nonexistant memory location, should not cause
can share access to common resources
an error in the program that is currently
executing. ProvIde protechon from unauthorized or
A final example of mcreasmg the system unmtentional access to data or other
integrity is protecting a user task from Itself. memory resources
Obvious errors, such as trying to execute data Detect obvIOusly mcorrect use of memory by
or overflowing an area set aSIde for a stack, an executmg task
can be detected while a program IS executmg
Separate users from system functions.
and handled appropriately, provIded the
system is given sufficient information. Most of today's memory management systems
The nohon of protecting an executmg task support these functions to some degree. The
from performing certain types of achons known extent of thIs support IS largely a queshon of
to be erroneous mtroduces a third general resources to be devoted to these functions and
motivahon for memory management, namely the understood demands of the mtended
support for the deSIgn and correct implementa- applications for these systems.
hon of large, complex programs and systems.
The Funda- Memory management has two functions: access It and what types of access can be made
mentals of the allocation and the protectiOn of memory. by each task. Each memory reference is
Memory DynamIC relocation of tasks during theIr checked to insure that the task has the right to
Management execution IS accomplished by an address access that locahon m the gIven fashIOn (for
translahon mechamsm. The restrlchon of example, to read the contents of the locahon or
memory access is accomplished by memory to write data to that location).
attribute checking. Both operations occur wIth Instead of a Imear address space, more
each memory request during the execution of a elaborate memory management systems have a
program and both are transparent to the user. hIerarchIcal structure in whICh the memory
Address translation simply means treating conSIsts of a collechon of memory areas, called
the memory addresses generated by the pro- segments. Access to thIs structured memory
gram as logical addresses to be mterpreted or reqUIres the speclflcahon of a segment and an
translated into actual physICal memory loca- offset withm that segment. Thus, mstead of
tions before dIspatching the memory access specIfying memory location 1050 m a linear
requests to the memory unit. Memory attribute address space, a task speclflCes memory loca-
checkmg means that each area of memory has tion 5 m segment number 23, for example.
assocIated with it Information as to who can
3-30
The Funda- Generally, segments can be of variable SIze, of Segment 5 he gets an error message from
mentals of within limits, and a user can specify the size of the system indicatmg that he has exceeded the
Memory each segment to be used. Thus one user may allocation limit for Segment 5. Note that he
Management have two segments of two thousand and ten does not access word 50 of Segment 6. That is,
(Continued) thousand words for hIS FORTRAN program and segments are logIcally dIstinct and unordered,
data, respectively, whIle another user might A reference to one segment cannot inadvert-
have three segments of three thousand, six ently result in access to another segment.
thousand and two thousand words for her Thus, in thIS example, User A is prevented
PASCAL program, data, and run-time stack. If from accIdentally (or deliberately) accessing
the Irst user called his data segment number hIS program as though It were part of hIS data
5, then the Irst word m hIS data set would be segment.
accessed by the logical address (5,0) mdlCat- FIgure 2 illustrates one way that these
ing segment 5, offset 0. The memory man- segments could be arranged in the phYSICal
agement system translates thIS symbolic name memory. The dotted Imes mdlcate the
mto the correct phYSIcal memory address. memory-mappmg funchon from the logical
FIgure I gives a conceptual realization of address space of the user to the physi-
these two users' logIcal program spaces. The cal memory locahons allocated to hIm.
Irst user, User A, has hIS program segment The figure also indicates the access attri-
called "Segment 6" and his data segment butes associated WIth each user's segments.
called "Segment 5." The second user, User B, For example, program segments are "exe-
has her program segment called "Segment 5," cute only" and data segments are "read!
her data segment called "Segment 12" and her WrIte." Thus a user IS prevented from exe-
stack segment called "Segment 2." Nohce that cuting a data segment or writmg into a
both users have named one of theIr segments code segment.
"Segment 5," but they refer to dIfferent enti-
tIes. ThIS causes no problem smce the system LOGICAL ADDRESS SPACE PHYSICAL
keeps the two memory areas separate. The EXECUTE
MEMORY
----------
ONLY
situahon is analogous to both users havmg an
integer variable called "I" in theIr programs:
The system realIzes that these are two separate
1~'~1
variables stored in different memory locations. READ/WRITE - - - - - __
" I
\ I
\ I
USER A , I
\ I
rEo..
p_M
.1 ''/
I ' 1/
4
I ')"
I 1/
I 1/
I 1/
I I /
/ / I
\ / / /
$EO,6
\
EXECUTE/
, /
/
/
/
/
/
/
/
~DAtA
......nFlll:"
"
"-'-,
/
//
I 1"-
I I '\
'\'-co,
J
8,.5E012 RI!AD/WRITE!
OATA 'i-.
USERB B.$6Ca I "
STACK I "
...
SEG. $
PROGRAM
sm.,.
DATA
~
~
Figure I. Two User's Logical Address Space Figure 2. Mapping Logical Segments to Physical Memory
2049-0075, 0076
3-31
The Funda- Figure 3 Illustrates what happens when area may not actually reSIde in physICal
mentals of both users have access to the same data memory until a task actually tries to access It.
Memory set in pnmary memory, say the results of a At the time an access IS made to a segment
Management questionnaire that both intend to analyze. missmg from physical memory, the mstruction
(Continued) Each user has a logICal name assocIated execution IS held in abeyance until the logical
with that data set to specIfy the segment m memory can be brought into the physical
whICh the data set is to resIde. Note that the memory and then the mstruction is allowed to
two users have chosen to put the data set m proceed wIth the memory access. The address
dIfferent segments of their personal address translation is performed, access protection is
spaces. The system-mapping function trans- checked and the instruction proceeds as if the
lates these dIfferent segment names to the logIcal memory area had been m the physical
same physical memory locations. Thus User memory at the beginning of the mstruction.
A's access to address (2, 17) references the The mstructions in the Z8001 must run to com-
same physical memory locatIOn as User B's pletion before the CPU can perform any
access to address (7, 17). In the figure, note action, such as respondmg to a missmg seg-
that two of B's segments have been moved in ment trap. But with the conjunction of hard-
physICal memory to create a space large ware and software to SImulate the above func-
enough to hold the questionnaire data. tions, a segmented VIrtual memory scheme can
Another topic m memory management that IS be implemented.
supported by Z8001-Z8010 architecture but A final topic in memory management is
reqUIres additional support hardware is paging, whICh IS another method for partitlon-
demand swapping, or segmented virtual mg a user address space and mappmg it onto
memory, whIch means that the logICal memory the physIcal memory. Paging is most effective
when demand swapping can be supported.
Essentially, pagmg dIvides the logical memory
into fixed-size blocks, called pages. Like
segments, the mdividual pages can be located
anywhere in the physIcal memory and a
translation mechamsm maps logIcal addresses
READ/WRITE
to physICal memory locations. There are two
',READ ONLY _---::::;;/
differences between paging and segmentmg a
" I
"'" [~N I logical memory. First, pages are of fixed size
SHARED
SEGMENT whereas segments are of various sIzes. Second,
I
I
under paging, the logical memory IS still
I linear, that IS, a task accesses memory using a
I
" I
single number, rather than a pair as m
~/",,- segmentation. The major advantage of pagmg
- I "
I I" is in treating memory as blocks of fixed sizes,
I I
I I whICh slmphfles allocating memory to users
I I
I I and deCIding where to place the logical pages
, I
I
I
I in physical memory. The major disadvantage
'8, '-
of paging is in assigning different protection
EJ'"
" I I
EXECUTE,
" READ ONLY ,I ~ _::'
'
' attributes to different areas in a user address
ONLY"" c:u:.::o~. I space because a paged memory appears
8,SE$, $
'NAIRE
.... "\. I
! homogeneous to the user and the operating
READ/WRITE PROQRAM ...., ~ ~ "'" I system. Paging can be combmed with segmen-
I tation to produce a memory management
............. ::t:-.,
............ I'~ system WIth the advantages of both paging and
.......................... , I
segmentation. The implementation of pagmg
B $EO. i~
DATA J\ ,',
READIWRITE..........
B.$G.2
STACK
\
\\
' .....'-
I
2046-0077
3-32
The Funda- with logical addresses and hence is mdepen- ment systems separates user functions from
mentals of dent of the addresses of the physICal memory system functions. For processors that dis-
Memory locatIons It accesses. Movmg the task to dIf- tinguish between System mode and User mode
Management ferent physical memory 10calIons requires that of operation, thIS goal can be accomp-
(Continued) the address mappmg function be changed to lIshed by associating a system-only attribute
reflect the change m memory location, but the with system segments so users cannot directly
task's code need not be modIfied. Of course, access system tables and tasks.
thIS flexIbilIty does incur the price of manag- As a final point, It should be noted how
mg the varIOUs system tables reqUIred to segmentatIon can be used to support the
Implement memory management. development and execution of large, complex
The second goal supports sharmg of com- programs and systems. The concept of segmen-
mon memory areas by different tasks. ThIs IS tation corresponds to the concept of partition-
accomplIshed by mappmg different logical ing a large system mto procedures and data
areas m different tasks to the same physical structures where each procedure and data
memory locations. structure can be associated with a separate
The thIrd provIdes protection against certam segment. A task can then invoke a procedure
types of memory accesses. ThIs is accomp- or sub-task or access a data structure by refer-
lIshed by assoclatmg accessing attributes WIth rmg to ItS logical segment name. Access to
each logIcal segment and checkmg the type of these objects can be indIvidually restrIcted by
access to see If each access IS permItted. using the protectIon-checkmg mechamsm of
The fourth goal detects obvIOus execution the memory management system.
errors related to memory accessmg. ThIs can As a speCIfic example of how segmentatIon
be accomplished by checkmg each access to a could be used m the deSIgn of a large system,
segment to see whether the address falls withm conSIder a multI-user mteractIve BASIC system
the allocated phYSIcal memory for that seg- WIth a large data base shared by all users.
ment. It could also mclude afhxmg a Such a system could be designed with
reacl/write attrIbute to data to prevent a task segments a through 15 reserved for system
from trymg to execute a data segment, and use, segments 16 through 31 reserved for the
afhxmg an execute-only attrIbute to code BASIC interpreter and ItS mternal tables,
segments to prevent a task from trying to read segments 32 through 63 allocated to user tasks
or WrIte data to this segment. Additionally, if a and segments 64 through 127 reserved for por-
segment IS used for a stack, the system could tions of the data base when they are m primary
Issue a warning to a task when the stack memory bemg accessed by users. For thIS
approaches the allocated limIt of the segment. system, segments a through 31 would probably
The task could then request more memory for always be m memory; the other segments
the stack before the stack overflows and would be assIgned as needed and the memory
creates a fatal error. they require allocated dynamically.
The fmal goal lIsted for memory manage-
The Mechan- Essentially there are four Issues m Imple- reduced traffic between the memory and the
ics of Memory mentmg a memory management system: how processor for fetchmg shorter mstruclIons, a
Management addresses are specified, how these addresses program may execute faster.
are translated, what attributes are checked for On the other hand, these speCIal registers
each access, and how the protection mech- must be manipulated to access more segments
anism is Implemented. Some of the major alter- than there are regIsters, and this manipulation
natIves m each of these Issues are brIefly adds to the number of mstructIons, the pro-
discussed here, prImarily from the pomt of gram size and the execution tIme. In practice,
vIew of a segmented memory. these can destroy the advantages deSCrIbed
Two approaches have tradllIonally been above. If the special registers contain phYSIcal
taken for specIfymg addresses m a segmented memory locations, then these must be pro-
memory. For SimpliCIty, only addresses in tected from user access to maintam the integ-
instructIons are dIscussed. The first way rIty of the system, and changing segments
puts all the addressmg mformatIon m the reqUIres system calls which can be time con-
mstruction itself. That IS, each memory address suming If too few regIsters are supplied. The
m an instructIon contams both the segment 28001 archItecture specIfIes the complete
name and the offset wlthm the segment. The logical address m the instructIon.
alternative sets aSIde speCIal registers that con- Address translatIon is performed by adding
tam some of thIS mformation, for example the the logical segment offset to the memory loca-
segment name or the address in physical mem- tion where the segment begins. Thus, when an
ory where the segment resides. address of the form (a, b) is presented to the
The advantage of the latter approach lIes in translation mechamsm, the segment name "au
the fact that fewer bits are needed in an IS used to determme where segment "au
mstructIon to specify addresses. Thus pro- reSIdes m memory. Assume that It reSIdes in
grams may be shorter. Also, because there is locations 10000 to 25000. Then the actual
333
The Meehan- memory location of (a, b) is memory location tions. The other Issue wIth respect to attributes
ics of Memory 10000 + b. The major option in implementing is whether they are permissive or prohIbitive.
Management thIs type of address translation IS m determin- That is, whether the attrIbute IS in the form of
(Continued) ing the segment location in physical memory. "wrIte to thIS segment is permitted" or of the
When specIal registers have been set aSIde to form "write to thIS segment IS prohIbited." The
contain the starting location of the segment 28010 adopts the approach of specifying attri-
instead of putting all address mformatIon in butes that prohibIt certain types of accessing.
the instruction, the addressing mechanIsm IS The fmal Issue m the mechanIcs of memory
sImilar to using the segment regIster as an management systems IS the ImplementatIon of
mdex register or a base regIster. the protection attributes. These may be
When logical addresses are eIther complete- aSSOCIated either with the logical address
ly speCIfIed in the instruction or when the space or wIth the physical memory Itself. The
speCIal regIster contains the symbolic segment IBM 360 serIes, for example, places the
name, a table must be used to translate the memory protection informatIon wIth the
logIcal segment name mto a physical memory phYSICal memory itself. Thus the processor
locatIon. The table may have an assocIatIve generates a memory address and the memory
capabIlity, that IS, the segment name is module checks to see If the access IS permit-
presented to the table and the device returns ted. The mam diffIculty wIth thIS approach IS
the physical memory location where the seg- in the lack of fleXIbIlIty, because protection IS
ment begins. Alternatively, the table could associated wIth fIxed memory partItions. Also,
have one entry for every possible segment sharing memory IS cumbersome because each
name. The Z8010 implementation of the user IS given a protectIon key to match thp
address translation table sets aside a specific memory key; thus both users must have the
table entry for each logical segment name. same access key or a universal access key.
A number of attrIbutes can be associated ASSOCIatIng access attributes WIth the logIcal
wIth a segment and checked durmg each segment permits a versatile memory manage-
access. One of these is the allocated length of ment scheme because different users can
the segment, and each access is checked to access the same segment and have different
see if it falls within the bounds of the segment. access attributes associated with their access-
The 28010 prOVIdes lImit checkmg. ing. The 28010 implements access attributes
Another type of attribute deals with owner- usmg the segment mapping information.
ship or class of ownershIp: tasks are grouped Other information assocIated with each seg-
into classes and ol1,ly those in certam classes ment does not pertam to the protection
are permitted access. The simplest example is mechanism but can be of use to the memory
the system versus user claSSIficatIon, where management system. ThIS informatIon gener-
tasks are eIther one or the other and this deter- ally relates to the history of the segment; for
mmes whether or not any type of access can example, whether a segment has been
be made to the segment. The 28010 has thIS modified whIle resident m primary memory. If
feature-users are prevented from accessmg it has not been modifIed and the system
system segments. requIres the memory for another segment, the
Other types of attributes that can be memory can be freed immediately; otherwIse,
associated with a segment involve modes of the updated versIOn of the segment must be
accessing, for example read only, read/wrIte stored m secondary memory and the primary
or execute only. For these attrIbutes, the pro- memory IS not available untIl the segment has
cessor must mdicate the type of access to be been saved. Although not strictly necessary,
made, be it code fetch, read from memory, such information can improve the performance
wrIte to memory, etc. The 28001 mdicates of the memory management system. The 28010
when it IS fetching code, reading or wrItmg collects information on segment usage, and
data, or performing stack operatIons, and thus this informatIon can be used to enhance per-
the 28010 can offer protection for these opera- formance of systems that use this deVIce.
The Z8010 The 28001 CPU generates segmented some detail, begmnIng WIth the translation
Memory addresses consistmg of a 7-blt segment number procedure and continuing WIth a description of
Management and a 16-blt segment offset address. In addi- the internal registers of the chip. The sectIon
Unit tIon, the CPU generates status signals mdi- concludes with a deSCrIption of the system
catmg ItS current mode of operatIon (such as commands that alter the contents of these
InstructIon Fetch, Data Memory Reference, regIsters.
Stack Memory Reference, and Internal Opera- The 28010 MMU has three functional states.
tion), whether it is performmg a Read or a The first IS the memory management state:
Write Memory Reference and whether It is m when a logIcal address IS presented to the unit,
Normal (User) or System Mode. The 28010 the MMU checks the access to msure ItS valId-
Memory Management Unit uses thIS informa- Ity and translates the logIcal address to a
tion to perform its memory management func- phYSIcal memory location. The second state is
tions. This section deSCrIbes the 28010 MMU in a command state: when a speCIal I/O instruc-
3-34
The Z8010 tlon is issued to the MMU, such as readmg or
Memory writing one of its internal registers, the MMU
Management responds to the command as appropriate. The
Unit
(Continued)
third state is a quiescent state: when the CPU
Issues an I/O mstructlon or a refresh cycle, the
MMU address lines remain 3-stated.
ADDRESSJ
DATA BUS 1
The mputs to the MMU are the Address/Data
PHYSICAL
lines (A/D hnes), Segment Number hnes, Bus ADDRESS
Status and Timing Lines, and special control
lines for chIp selection and DMA. The outputs
from the MMU are Address lines, a Segment
SEGMENTj
NUMBER
Trap line and a Suppress lme (Figure 4). Dur-
mg address translation and access protection,
logical addresses are presented to the MMU on
the Segment Number and Address/Data lInes; SEGMENT
the MMU puts the translated physical memory TRAP
6 15 a
I SEGMENT NUMBER I'--________ ~S_ET I
O_F... _ _ _ _ _ _ _ _.... LOGICAL ADDRESS
~123_______________ I
BASE ADDRESS
.,87_ - - ____________ ~ ?:STARTING ADDRESS
2046-005 I 2049-0079
3-35
The Z8010 MMU base-address field: 15 is added to 2311
I bJ tj~
" 0
I
I
\
I
I
\
1,a,",,1
a) FULL ADDITION
0
,.
+
23
I
~
I
.. ,......,
I
8 ~
I
o~
.L..:..J...:J
I
MMU There are three groups of registers m the trol Registers contam information used to con-
Internal MMU: Segment DeSCriptor Registers, Control trol the various functions of the MMU, mclud-
Registers Registers and Status Registers. The Segment ing how to mterpret various signals generated
DeSCriptor Registers contam all the mformation by the CPU. The Status Registers contain all
relatmg to the address translation and access the mformatlon the MMU generates when it
protection of a particular segment. The Con- detects an access violation.
Segment Because there.are 64 Segment DeSCriptor segment descriptors are used in address
Descriptor Registers m the MMU, two MMUs are required translation.
Registers to handle all 128 segments that the 28001 can The Base Field speCifies the starting location
manipulate directly. An MMU is programmed in memory of fhe segment.
to handle either segments 0 through 63 or The Limit Field speCifies the segment size in
segments 64 through 127; the particular set of blocks of 256 bytes. The address offset is com-
64 segments in an MMU can be changed uSing pared against the segment limit and a size
speCial operating system commands. Each Seg- VIOlation occurs If the offset falls outside the
ment DeSCriptor contams three fields, a 16-bit segment boundaries. A write warning occurs if
Base Field, an 8-bit Limit Field and an 8-blt the destination is in the last block of a segment
Attribute Field (Figure 7). The segment being used as a stack.
number of a logICal address determines which
20490080
3-36
Segment
Descriptor "
Registers A
V'
,
The Attribute Field contains eight flags. Five prohibited. This flag IS useful in preventing a
flags protect the segment against certain types program from making a copy of a proprietary
of access, one indicates a special orientation of program. For example, if this flag is set for a
the segment, and two indicate the types of segment containing code that a user can
accesses that have been made to the segment. access, that code is protected from being read
The following brief description explains how and hence from being copied.
these flags are used. The DMA-Inhibit Flag (DMAI) indicates that
The Read-Only Flag (RD) indicates that the the segment is not to be referenced by a DMA
only accesses to this segment are reads. Writes Channel. When this flag is set, only the CPU
are prohibited when this flag is set. Thus this has access to the segment. This flag is useful
flag is a write-inhibIt flag; in particular, code In preventing a DMA device from modifying a
can be executed from a read-only segment. segment being used by an executing task. For
This flag is useful in protecting data from example, segments with valid data should have
being written by unauthorIzed users. For this flag set to protect them from modIfication
example, if one user wants to gIve another
access to a document that he has created, but
does not want this user to be able to modify it,
by a DMA deVIce.
The Direction And Warning Flag (DIRW) 2
Indicates that memory accesses are to be
the system can set the Read-Only Flag when it monitored and certain accesses are to be
copIes the hIe into the user's address space. If signaled, although allowed to proceed. When
the data is already in memory (in a read-only this flag is set, any write to the lowest 256
mode), then this same memory area can be bytes of the segment generates a write warn-
made accessible to that user without another ing. This flag is useful for segments that are
copy of the document being required. used as stacks since the Z8001 has special
The System-Only Flag (SYS) indicates that stack instructions to manipulate stacks that
only accesses made in System Mode are to be grow toward lower memory locations. Thus a
permitted. When this flag is set, accesses in write warning for a stack indicates that the
the Normal Mode are prohibited. This attribute stack may soon overflow its allotted memory
is useful in protecting system tables and tasks space and that more phYSIcal memory should
from being accessed by users. For example, be obtained. For example, if a segment serves
system 1/0 routines can be left in the memory as a run-time stack for a block-structured pro-
with this flag set and a user is unable to call gramming language such as PASCAL, memory
them directly. This feature is useful if a system can be allocated to this segment only as a pro-
is designed so that users are given certain seg- gram requires during its execution. The alter-
ment names and other segment names are native in a fixed allocation emvlronment is to
reserved for system use. This flag prevents allocate as much memory for the stack as the
users from accessing system segments, even system expects the program to need, whether
though they can generate the logical or not it IS actually used by the program.
addresses. The Changed Flag (CHG) indicates that a
The CPU-Inhibit Flag (CPUI) indIcates that write has occurred to this segment. This flag is
the segment is not to be referenced by the set automatically whenever a program or DMA
CPU. When this flag is set, CPU access to this device writes into the segment. This flag is
segment is prohibited, but DMA channels can useful in indicating which segments have been
access the segment. This flag is useful in modified in the case where the segment must
preventing a program from accessing a seg- be written to a secondary storage device.
ment whose data resides on secondary storage Segments that have not been updated need not
and has not been brought into primary be copied back to disk if a copy already exists.
memory. For example, a user may request the For example, when a user task is suspended in
operating system to read a file from disk into a multiple-user environment and his task is to
segment number 19; if the operating system be swapped out of memory temporarily to
returns control to the user before the file has make room for another task, only those
been read, this flag should be set in Segment segments that have been changed need to be
Descriptor Register 19. updated on the disk.
The Execute-Only Flag (EXC) indicates that The Referenced Flag (REF) indicates that a
the segment is to be referenced only during memory access has been made to a segment.
the instruction fetch cycle of the processor. This flag is set automaticaly whenever a pro-
When this flag is set, access to the segment gram or DMA device accesses the segment.
during any other cycle of an instruction, for This flag IS useful in indICating which segments
example during the memory request cycle, is are active in the case that a segment must be
2049-0081
3-37
Segment selected to be swapped out of primary memory out to make room for users with large memory
Descriptor to make room for another task. For example, requirements. This flag is a way of ascertaining
Registers seldom-used operating-system tasks that usual- which segments contain seldom used tasks. '
(Continued) ly reside in primary memory may be swapped
Control Three user-accessible 8-bit registers in the 127; when the flag is reset, the MMU contains
Registers MMU control the functioning of the MMU descriptors 0 through 63.
(Figure 8). The Mode Register provides a When multiple-MMU devices keep separate
sophisticated method for selectively enabling tables for system descriptors and user descrip-
MMUs in a multiple-MMU configuration. The tors, the Multiple Segment Table Flag (MST)
Segment Address Register (SAR) selects a par- and the Normal Mode Select Flag (NMS) in the
ticular segment descriptor to be accessed by a Mode Register distinguish which MMUs con-
system routine when it is changing the tain system descriptors and which contain user
organization of primary memory. The Descrip- descriptors. When the MST flag is set, multiple
tor Selection Counter Register selects the par- tables are present In the configuration, and
ticular byte in the Segment Descriptor Register each MMU is dedicated to one of the tables. In
that is accessed. this case the MMU translates addresses only
Two flags in the Mode Register govern the when the Nis signal matches the NMS flag.
functioning of the MMU. The Master Enable Thus, if there are two tables In the memory
Flag (MSEN) indicates whether the device will management system (one for the system and
perform address translation. When this flag is one for users), the NMS flag IS set in those
set, addresses translated by the MMIJ are MMUs containinq the users' segment descrip-
placed on its Address lines; when this flag is tors, and is not s~t in the remaming MMUs. All
clear, the Address lines are 3-stated. Thus, MMUs in the system have the MST flag set to
once this flag is reset, no memory request can indicate more than one table In the system.
pass through the MMU. In a single-MMU con- The final piece of control information In the
figuration, MSEN set to zero requires that the Mode Register is a 3-bit Identificahon Field
CPU must have access to a special memory, (10) that Indicates a logical name for the
since it will not be able to fetch an instruction MMU. When a segment trap is acknowledged
from the primary memory. This flag can be set by the CPU, the MMU uses this field to select
during hardware reset (this is discussed later). one of the ND lines; each enabled MMU
The second flag in the mode register that should select a different line. If an MMU
governs the functioning of the MMU is the requested a segment trap, it outputs a I on its
Translate Flag (TRNS). This flag indicates assigned ND line; otherwise it outputs a O.
whether the MMU is to translate the addresses Since the 10 field is three bits, up to eight
presented to it. When the flag is set, the MMU MMUs can be uniquely identified. One
translates logical addresses to physical memory instruction might result in mulhple violations
locations and checks to see if a violation will in different MMUs, so that the segment trap
occur on that access. When the flag is clear, software might have to deal with several MMUs
addresses presented to the MMU are passed to to process the trap.
the output Address lines without change, and The other two control registers in the MMU
no protection checking is done. are the Segment Address Register (SAR) ,
When multiple-MMUs are used in a memory- which points to one of the 64 segment descrip-
management system, some mechanism must be tors, and the Descriptor Selection Counter
present to select those deVices that are to be Register. Commands to read or write a seg-
active during the memory translation process. ment descriptor use the SAR pointer to select
More specifically, if two MMUs are employed which descriptor is to be accessed. This
so that all 128 segments can be used at random register has an auto-incrementing capability
by an executing process, then some way must for accessing consecutive descriptors in suc-
eXist for each of the MMUs to know which 64 cession without having to reload the SAR. Thus
Segment DeSCriptors are located in its Segment if descriptors 0 through 4 are to be modified,
Descriptor Registers. The Upper Range Select the SAR is initialized to 0 and then auto-
Flag (URS) indicates which set of 64 descrip- incremented to point to descriptors, I, 2, 3
tors IS stored in the MMU. When the flag is and 4 in succession.
set, the MMU contains'descnptors 64 through The Segment Descriptor Number is a 6-bit
field that contains the address of the descriptor
7 32 0
within the MMU. If the MMU holds segments
F3~'~I~I~1 ,,)11\':' " " MODE
64 through 127 (that is, if the URS flag is set),
7 65 0 the segment named 64 is accessed when the
F'' :""1~~"'~1
h'( ";';'" t , "';>",' r'~ i ' t .. '
SEGMENT
ADDRESS SAR number field is O. This is a result of the
6-bit limit of the descriptor number field. The
t", ' :"08C,A'1
21 0
:~, DESCRIPTOR
SELECTION field indicates the 6 least-significant bits of the
1.............._ ...........--'_.1:-'..' .......' ... COUNTER
t
20460031
338
Control Segment Descriptors consist of four bytes; This counter is used by MMU commands that
Registers the Descriptor Selection Counter indicates access multiple bytes within a descriptor. In
(Continued) which byte is being accessed during a com- general, the counter is handled automatically
mand (commands to the MMU can read or by the MMU commands. Only when a com-
write only one byte at a time). A counter value mand could be interrupted-and intervening
of 0 indicates the high-order byte of the base MMU commands issued-should this register
address is being accessed, I indicates the low- be saved and later restored by the interrupting
order byte of the base address, 2 indicates the program.
limit field, and 3 mdicates the attribute field.
Status Six 8-bit registers contain informahon useful that the system stack is in danger of overflow-
Registers in recovermg from memory trap conditions ing its allotted memory. Once the SWW flag IS
(Figure 9). The Violation Type Register set, further write warnings are suppressed.
describes the conditions that generated the This prevents the system from repeatedly
segment trap. The Violation Segment Number being interrupted for the same warning while
and Offset Registers contain the segment it is in the process of eliminating the cause
number and upper byte of the segment address of the warning.
offset for the logical address that caused The final violation-type register flag to be
the segment trap. The Instruction Segment discussed is the Fatal Condition Flag (FATL).
Number and Offset Registers contain the seg- This flag is set when any other flag m the
ment number and uper byte of the segment violation type register is set and either a viola-
address offset for the last mstructJon before the tion IS detected or a write-warning condition
segment trap was issued. The Bus Cycle Status occurs in normal mode. This flag is not set
Register records the status of the bus at the durmg a stack push in system mode that
time the trap condition was detected. results m a warning condition. This flag
Only VIOlations caused by CPU access have indicates that a memory access error has
trap mformation stored in the status registers; occurred in the trap processing routine. Once
DMA violations cause Suppress to be asserted, this flag has been set, no Trap Request signals
but the Status Registers are not altered. Thus if are generated on subsequent violations.
a DMA violation occurs between a CPU viola- However, Suppress signals are generated on
tion and entry to the trap service routine, the this and subsequent CPU violahons until the
service routine still has the CPU trap mforma- FATL flag has been reset.
tion available to process the trap. It is the The Bus Cycle Status Register contams infor-
responsibility of the DMA device to save mation pertaining to the status of the bus when
enough information in the event of a violation a trap condition is detected. This includes
so that a software DMA violation service CPU Status (STo-ST3), plus flags indicating
routine can process the violation correctly. whether a read or a write was bemg performed
Eight flags in the Violation Type Register and whether or not the Nis line was asserted.
describe the cause of the segment trap. Four The Violation Segment Number and Offset
flags correspond to access protechon modes in Registers record the first logical address to
the segment descriptor attribute mode. A read- cause a trap. Only the high-order byte of the
only violation sets the RDV flag, a system-only offset is saved, however, so that external sup-
violation sets the SYSV flag, a CPU access to a port circuitry is needed to save the low-order
CPU-Inhibit segment sets the CPUIV flag, an eight bits of the logICal address offset. If the
execute-only violation sets the EXCV flag. trap occurred during the instruction fetch
Three flags correspond to addressing viola- cycle, this mformation is the logical address of
tion or warnings. The Segment Length Viola- the instruction; otherwise it indicates the
tion Flag (SL V) is set whenever the offset of the
logical address falls outside the memory space
allocated to the segment. The Primary Write
Warning Flag (PWW) is set whenever a write 7 0
occurs in the last 256 bytes of a segment whose IL.._" I
..I_J-...J~'-M_Efl....
.. ~ __
I ~~~~~:T
-'"~E_"u..........--'.
VIOLATION
2046-0032
3-39
Status logIcal address of a data item whIch was to be registers mdlcate the logICal address of the
Registers accessed. prevIOus mstruction. Such information is useful
(Continued) The Instruction Segment Number and Offset If the preceding instruction was a branch
Registers record the logical address of the last mstructlon to an invahd address smce-in thIs
instruction fetch that occurred before the trap. case-these registers indicate which branch
Only the hIgh-order byte of the offset IS saved, instruction led to the erroneous sItuation. If a
however, so external support circUItry IS need- data reference caused the segment trap, then
ed to save the low-order eight bits of the offset. these registers indIcate the logical address of
If an mstructlon fetch caused the trap, these the instruction that speCIfied the illegal access.
Stack Segments are speclhed by a base address the limIt of ItS allocated segment, additional
Segments and a range of legal offsets to thIS base memory can be allocated on the correct end of
address. On each access to a segment, the off- the segment. As an aid in maintaining stacks,
set is checked agamst thIS range to msure that the MMU detects when a wnte IS performed to
the access falls wlthm the allowed range. If an the lowest allocated 256 bytes of these
access outSIde the segment IS attempted, a segments and generates a Trap Request. No
Trap Request and a Suppress SIgnal are Suppress signal IS generated so the write IS
generated. allowed to proceed. ThIS write warning can
Normally the legal range of offsets WIthin a then be used to mdICate that more memory
segment is from 0 to 256N + 255 bytes, where should be allocated to the segment.
0:5 N :5 255. (N IS the value in the hmlt held of The DIRW flag indicates that a segment is to
the segment deSCrIptor.) However, a '3eC}mp.nt be treated m this speCIal way by the MMU.
may be speCIfied so that legal offsets range When the DIRW flag is set, the range of
from 256N to 65,535 bytes, where 0:5N:5255. allowed offsets IS from 256N to 65,535 bytes
The latter type of segment IS useful for stacks and wntes mto the range 256N to 256N + 255
because the Z8001 stack-manipulation instruc- generate Segment Trap but not Suppress,
tions cause stacks to grow toward lower mdICatmg a wnte warnmg.
memory locations. Thus, when a stack grows to
Segment The Z8010 MMU generates a Segment Trap on the AID lme assocIated WIth the number in
Trap and whenever It detects an access VIOlation or a ItS ID field. An MMU that has not generated a
Acknowledge wnte warnmg condllion. In the case of an segment trap request outputs a 0 on its
access VIOlation, the MMU also activates Sup- assocIated AID lme. AID lines for whICh no
press. Suppress can be used to mhlblt memory MMU IS assocIated remain 3-stated. During a
wntes and to request that speCIal data be segment trap acknowledge cycle, an MMU
returned on a read access. Segment Trap uses ND lme 8 + 1 If the content of its ID
remams Low until a Trap Acknowledge SIgnal held IS 1.
IS receIved. If a violallon occurs, Suppress IS Following the acknowledge cycle, the CPU
asserted for that cycle and all subsequent CPU automatically pushes the program status words
memory references until the end of the mstruc- and program counter onto the system stack,
tlon. Intervemng DMA cycles are not sup- and loads a new program status word and pro-
pressed, however, unless they generate a gram counter from the program status area.
vlOlallon. VlOlallons detected durmg DMA The Segment Trap Ime is reset during the seg-
cycles cause Suppress to be asserted durmg ment trap acknowledge cycle, and no Suppress
that cycle only; no segment trap requests are SIgnal IS generated during the stack push. If
ever generated durmg DMA cycles. ThIS IS the store creates a wnte warnmg condl11on, a
because the CPU would not be able to respond segment trap request IS generated and is ser-
to these traps until the conclUSIOn of the DMA VIced at the end of the context swap; the SWW
cycle. flag IS also set. ServICmg thIS second Segment
Segment traps to the Z8001 CPU are handled Trap request also creates a wnte warnmg con-
SImIlarly to other types of mterrupts. To ser- dIllon, but-because the SWW flag IS set-no
vIce a segment trap, the CPU enters a segment Segment Trap request IS generated. If a VIOla-
trap acknowledge cycle. The acknowledge tion rather than a wnte warnmg condItion
cycle IS always preceded by an mstructlon occurs during the context swap, the FATL flag
fetch cycle that IS aborted. The MMU has been IS set rather than the SWW flag. In thIS case,
deSIgned so that thIS dummy instruction fetch subsequent vlOlahons cause the Suppress to be
cycle IS Ignored. Durmg the acknowledge asserted but not Trap Request. WIthout the
cycle, all enabled MMUs use the Address/Data SWW and FATL flags, trap processmg routmes
lmes to mdICate theIr status. An MMU that has that generate memory VIOlations would
generated a Segment Trap request outputs a 1 repeatedly be mterrupted and called to pro-
340
Segment cess the violations they create. SWW flag should be checked to determine if
Trap and The CPU routine to process a trap request more memory is required for the system stack.
Acknowledge should first check the FA TL flag to determine Finally, the trap Itself should be processed and
(Continued) if a fatal system error has occurred. If not, the the violation type register reset.
Commands When a memory management system must deSCriptors in the MMU to have the CPU I or
to the MMU read or change information m the MMU to DMAI flags set, respechvely. These two set
respond to a segment trap or to re-orgamze the commands can be useful m initiahzmg address
physical memory, it can Issue control com- translation tables or when swappmg between
mands to the MMU. These commands fall mto tasks. For example, when swappmg between
two genenc categones: reset commands and tasks the Set All CPU! Flags command
read/write commands. Reset commands are automatically makes the prevIOus task's
simply orders to the MMU to set or clear segments maccesslble to the next task, unless
specihed helds. For these commands, the the system expliCItly mlhahzes the segment
Z8001 SpeCIal I/O output command can be attribute held m these segments.
used with the destination field set to be the As an example of usmg the SpeCIal Output
MMU command code correspondmg to the mstructlon SOUT to control an MMU, conSIder
desIred action. resettmg the fatal flag of MMU # 1. The MMU
Read and wnte commands are shghtly more command opcode for thIs IS "%14" (% denotes
comphcated because they consIst of both com- hexadecImal). The assembler syntax for the
mands and data. Such commands to the MMU SOUT mstruchon IS "SOUT destmahon held,
are Issued using the Z8001 SpeCIal I/O mstruc- source held" so that the mstruchon to reset the
tlons. These instructions have a source and a fatal flag of MMU #1 IS "SOUT %1402, RO."
destmatlOn held. For an input mstructlon, the Specifymg register 0 m thIs instruchon IS an
source held contains an MMU command code arbItrary chOIce-the content of this regIster IS
and the destinahon field indlCates where m placed on the A/D lmes durmg the data phase
primary memory the data is placed. For an of the SOUT mstruction, but It IS Ignored by
output instruction, the destination field con- the MMU. The low-order byte of the command
tams an MMU command and the source held (the destination held of the mstruchon) en-
mdlCates where the data to be written into the codes which MMU IS to reset its fatal flag. The
MMU resIdes m memory. convenhon followed m thIs paper IS that MMU
The hIgh-order byte of the command con- I IS speclhed by settmg bit i in the low order
tams the opcode for that command; the low- byte of the command. (BIt I set IS hex "%02.")
order byte of the command can be used to The rest of the MMU commands consISt of
speCify the parhcular MMU to be accessed. both operahon and data. The follOWing mternal
The MMU does not receIve mformahon on registers can be read or written: the Mode
ADo-AD7, so external circUItry must decode RegISter, the Segment Address RegIster, the
mformahon on these lines durmg the SpeCIal Descriptor RegIsters and the DeSCriptor Selec-
I/O commands and then select a particular hon Counter RegIster. A Descnptor Reqlster
MMU. The encodmg of the low-order byte is can be read or written as a whole, or selected
dependent upon the system Implementation. subfields can be accessed. In addItion, by
ThIs paper always uses the convention that using the auto-increment feature of the Seg-
bIt I specihes MMU number 1. ment Address RegIster, successIve Descnptor
The reset commands to the MMU are: Reset RegISters can be accessed, or a selected field
Violation Type RegIster, Reset SWW Flag In withm succesSIve Descriptor Registers can be
VlOlahon Type RegIster, and Reset Fatal Flag accessed. For example, one SpecIal 110 com-
In Violation Type RegIster. Resetting the Viola- mand m block mode could read a number of
tion Type RegIster IS sImIlar to a hardware segment attribute fields. ThIs IS useful m deter-
reset m that It clears thIs regIster and returns ming whlCh segments have been modlfi()d.
the mternal control of the MMU to an mlhal As an example of usmg the Special Output
state (as if no VIOlation had occurred since instruction SOUT to write data mto an MMU,
system mltlahzation). Resettmg the SWW flag conSIder wntmg the contents of ReglstN 6 mto
or the FATL flag m the Violation Type RegIster the Mode RegIster of MMU #2. The opcode for
clears these flags. thIs command is "%00" and so the command IS
Two other commands are sImIlar to reset "SOUT %0004, R6." Here the hIgh-order byte
commands m that they have no data associated of the destmahon held contams the Opt 'ode
WIth them. These are Set All CPU-InhIbIt Flags and the low-order byte has bIt 2 set (hl'x
in the segment attribute fields and Set All adecimal4 If 0100 m bHlary) mdlCahn'l
DMA-Inhlblt Flags m the segment attribute MMU #2.
helds, both of whlCh cause all segment
3-41
Commands Certain MMU internal registers can only be the Instruction Segment Number Register, the
to the MMU read-there is no corresponding write instruc- Instruction Offset Register and the Violation
(Continued) tion. This is because these registers contain Bus Status Register. Although the Violation
information relating to a detected violation and Type Register cannot be written, it should be
thus it is not necessary to be able to write into noted that it can be cleared and that two of its
these registers. These registers are the Viola- flags can be indiVidually cleared: the SWW
tion Type Register, the Violation Segment flag and the FATL flag.
Number Register, the Violation OffsetRegister,
Direct DMA operations may occur between 28001 At the start of a DMA cycle, the DMASYNC
Memory machine cycles and can be handled through line must go Low, indicating to the MMU the
Access the MMU. The MMU permits DMA in either beginning of a DMA cycle. A Low DMASYNC
the System or Normal Mode of operation. For inhibits the MMU 'from using an indeterminate
each memory access, segment attributes are segment number on lines SNo-SNs. When the
checked and-if a Violation is detected"':"'a DMA logical memory address is valid,
Suppress signal is generated. Unlike a CPU DMASYNC must be High on one rising edge of
Violation, which automatically causes Suppress Clock and the MMU then performs its address-
signals to be generated on subsequent memory translation and access-protection functions.
accesses until the next instruction, DMA viola- Upon the release of the bus at the termination
tions generate a Suppress only on a per- of the DMA cycle, DMASYNC must again be
memory-access basis. The DMA device should High. After two clock cycles of DMASYNC
note the Suppress signal and record sufficient High, the MMU assumes that the CPU has con-
information to enable the system to recover trol of the bus and that subsequent memory
from the access violation. No Segment Trap references are CPU accesses. The first instruc-
Request is ever generated during DMA (hence . tion fetch occurs at least two clock cycles after
warning conditions are not signaled). There the CPU regains bus control. During CPU
are no trap requests because the CPU would cycles, DMASYNC should always be High.
not acknowledge the request until the end of
the DMA cycle.
Hardware The MMU can be reset by either hardware open-drain outputs are not driven .. If the
and or software mechanisms but aote that they Master Enable Flag is not set during reset,
Software have different effects. A hardware reset occurs the MMU does not respond to subsequent
Reset on the falling edge of the Reset input; a soft- addresses on its AID lines. To enable an MMU
ware reset is performed by an MMU oommand. after a hardware reset, an MMU command
A hardware reset' clears the Mode Register, must be used in conjunction with Chip Select.
Violation Type Register and Descriptor Selec- A software reset occurs when the Reset
tion Counter. If the Chip Select line is Low Violation Type Register command is issued.
while Reset is Low the Master Enable Flag in This command clears the Violation Type
the Mode Register is set to 1. All other Register and returns the MMU to its initial
registers are undefined. After reset, the AJD state as if no violations or warnings had
and A lines are 3-stated. The SUP and SEGT occurred.
Multlpl..MMU 28010 MMU architecture supports system lating only 64 logical segment names. These
Configur- configurations that use more than one names must either be 0 through 63 or 64
aUoDS MMU. Multiple MMU devices can be used through 127. If the MMU in a single-MMU
either to manage 128 CPU segments rather configuration is set to translate segment names
than the 64 supported by one MMU, or to in one range and the CPU generates a logical
manage multiple translation tables. segment name in the other range, the MMU
The 28001 CPU generates logical address- does not perform address translation 'and no
eS that can specify up to 128 different seg- physical memory location is output. In this
ment names. Because the MMU contains case, no request is made to memory. There-
only 64 Segment Descriptor ~egisters, two fore, a single-MMU configuration should have
MMUs are needed to perform address trans- additional external logic to detect erro-
l,ation for 128 logical segments. Systems neous segment names and generate a Segment
designed with only one MMU device still Trap and Suppress signal.
have the powel"' and flexibility offered by The Upper Range Select flag (URS) is
memory management, although tasks in used in multiple MMU configurations to
such a system are restricted to manipu- indicate which group of logical segment names
3-42
Multiple-MMU are to be translated by an MMU. When this name). If the Nis line fails to match the state
Configur- flag is set, the Segment Descriptor Registers in of the NMS flag, no translated address is
ations the MMU are used in translating logical generated by the MMU. The MST flag and the
(Continued) addresses In the range 64 through 127. When NMS flag are under program control and can
the flag IS clear, the range is 0 through 63. be changed in System Mode.
Thus the URS flag corresponds to the most The simplest multiple translation table con-
significant bit (bit 6) in the logical segment figuration has one table for Normal Mode
names that the MMU translates. Because this access and one for System Mode access. In
flag is under program control, the range of such a configuration, the Multiple Table Flag
logical segment names can be changed dUring IS set in all MMUs and the Nis line\of each
execution in System Mode. MMU receives its input from the Nis output of
MMU architecture also supports multiple the 28001 CPU. MMUs containing descriptors
segment translation tables. This feature is of system segments have the NMS flag clear,
useful when separate tables are maintained for and those containing descriptors to be used in
different tasks. Each task has ItS own table and Normal Mode have the flag set. When the
SWitching between tasks requires enabling the 28001 IS in System Mode, the Nis line is Low
appropriate MMU devices. In contrast, systems and it matches the NMS flag in those MMUs
with only one translation table must either whose Descriptor Registers contain system seg-
restrict the logICal segment names that an ment information. Therefore, these MMUs are
individual task can use, or change the used in address translation for system
Descriptor Register entries whenever tasks are references.
swapped. Two flags in the Mode Register, When the 28001 is in Normal Mode, the Nis
together with the Nis signal, are used in multi- line is High and it matches the NMS flag in
ple table conhgurations. those MMUs whose Descriptor Registers con-
The Mulhple Segment Table (MST) flag tain user segment information. Consequently,
indicates whether the configuration is being these MMUs are used in address translation for
used to support multiple tables. When this flag user segments. In this configuration, system
is set, the MMU will compare the Nis line segments are separated from user segments.
against the Normal Mode Select Flag (NMS) When the 28001 changes from Normal to
before generating a physical memory location System Mode of operation, the appropriate
on its Address lines. When the line and the translation table is automatically selected. A
flag match (both asserted or both de-asserted), more elaborate example of a configuration with
the MMU IS enabled and an address translation mulhple translation tables is g'iven in the next
IS performed (assuming the URS flag matches section.
the most significant bit in the logical segment
Examples This section describes two 28001-28010 con- bined with the Reset line. This allows the
figurations: one contains two MMUs and one Master Enable Flag to be set upon system
address translation table; the other contains initialization, so the logical addresses gen-
seven MMUs and four address translation erated by the CPU are passed to the physical
tables. These examples are given in suf- memory. This is done because-upon reset-
fiCient detail to illustrate some of the major the mode register is otherwise cleared, the
ideas in constructing memory-management Translate Flag is clear and addresses pass
systems around the 28010 MMU. High-level through the MMUs untranslated. The bootstrap
block diagrams Illustrate some of the major program can therefore reside in absolute
features of typical hardware configurahons memory locations in the physical memory. If
and short programs illustrate software tech- the Reset line is not an input to the Chip
niques for using the MMU. Select line, the Master Enable Flag would not
The hrst example system is the two- MMU be set during system initialization and the CPU
configuration illustrated in Figure 10. The two would not be able to address memory through
MMUs are called MMU #1 and #2, and they the MMUs.
are selected during a command cycle by AD j Note that there is a direct path from the
and AD2 being Low, respectively. Since a CPU and DMA to the system bus. This path
Special I/O instruction is being used bit 0 must is used during I/O and memory refresh
always be zero. Thus, when a low-order byte of because the MMUs are quiescent during these
a command is "%02," MMU #1 responds; cycles. It is also used for data on memory
when it is "%04," MMU #2 responds; and reads and writes. Also, note that the Suppress
when it is "%06," both MMUs respond. (Note line goes both to the memory, where it can be
that AD, is inverted before attachment to the used to protect the memory from erroneous
CS pin.)
The A/Dj line, which controls MMU #1
through the Chip Select input, is first com-
3-43
Examples writes, and back to the DMA device to save To write this descriptor into the MMU, a
(Continued) information upon the event of a DMA access copy of the descriptor should be created in
error. primary memory and a Special IIO block
Of further interest in the example, address transfer instruction used. The SOTIRB instruc-
latches are used to buffer addresses between tion can be used for this.
the Z8001 and a demultiplexed bus. This is This instruction has the assembler syntax
required to demultiplex the address and data "SOTIRB destination, source, count register"
onto the bus. The address latch for ADs-ADJ5 where both the destination and source are
may not be needed if the IIO device does not registers. The destination register contains the
use separate address and data lines. command to the MMU, the memory location
A detailed example indicates how such a pointed to by the source register contains the
system could be used. First, consider setting first byte of the data to be transferred, and the
Segment Descriptor Register 65 to point to a Count Register contains the number of bytes to
read-only segment of 768 bytes starting at be transferred.
memory location % 115200. The segment is to The opcode to load the Descriptor Register
be accessed in Normal Mode. The Descriptor IS "%OB". Segment Descriptor Register 65 is
RegIster should be % 115202 01. The first two Segment DeSCriptor Register I of MMU #2, so
bytes, % 1152, indIcate the starting location of the MMU command is "%OB04".
the segment (note that the low-order byte of To specify which Segment Descriptor
the memory address is all zeros and is not Register to write, it is necessary to load the
stored in the Descriptor RegIster). The third Segment Address Register of MMU #2 with I.
byte, %02, mdicates that three blocks of 256 The MMU opcode to do this is "%01" and so
bytes have been allocated to this segment. The the command is "%0104." The segment
fourth byte, %01, indicates that only the read- number (in this case 65) is a parameter to the
only segment flag has been set. example routine, passed in register O. The
ZBUS
tz
.....
16 1 ... 1" ~
iIHEf 24
lili&WK
16 ADo-AD15 8 A08-A015 t:Z BAa-B81s
- 7 SNo-SNa
.....
-
zaOO1
4 8To-8T3
CNTL
,- 4
-
4 STo-8T3
110"
MM\I$YNC 4 CNTL
r- ljjI
AD,
i1II
RESET
"L>- t--
iIHEf
DMASYNe
- >--- 8 ADa-AD1s
ZOOiD
7 SNo-SNe MMU
#1 f+ I-
:-
4 8To-8T3
4 CNTl.
ljjI
AD,
i1II -
I iIHEf
I f)MASYNC
2049-0084
3-44
Examples BIT RO, #6 !Test to see if DescrIptor RegIster is in MMU # I!
(Continued) JR Z, OVER lor MMU #2!
SOUTB %0104, RHO !Set SAR m MMU #2!
LD RI, #%OB04 !Prepare to write descriptor!
JR NEXT
3-45
Examples
(Continued) -;z
>-au
I ;.
DMASYNC
- 10 ADo-AD'5
'"'
10 BAo-8A"
t- ~
10 ADa-AD1S
j 8 ADi-AD"
-;z ''''- BA15
-- - 1Il001
~~-
IiiJlIl;i(l
mIlT
4
4
7 8No-SNI
STo-Sf3
CNfL 8 ADo-AD1
1 AD1-AD7
-;;z BAo-BAr
....
1=1 1O}
~
8
...,...
LATCH
J
e- m
1_.
IiiJlIl;i(l
10
7
ADo-ADa
SNo-SN, 8 ADI-AD1S
~~
.
'"';:/ 8,..-8A15
D...
-~~
STo-Sf3
CNTL
7
SNo-SNs
STo-STs
."'1D
JlMU
,11'
10
..
;;Z BA,.-BAn
-..-
eNTL
r- mJ ~1IIIi'
mIlT
t:::::n- ~ m I-
L.." m
,Mm 16 ADo-AD1S
....
7 SH<I-SNe
ADa-ADu
8N,-SN, _tOe 10
,lI
STo-8T3 7
_0'"
_0 ~;~- frt- r-
CNTL 4 S10-ST3 ~ ~
CNTL
-
---
f-- IIiIJI IIIIi'
'8 m;
AD,-ADus
SNo-SN,
STa-STa
- .-
_'0 rrt-
10
t-
-
CNTL
r-
CII m
3-46 2049-0085
Examples The routine performs the selective enabling ADo-AD. MMU S.lect.d
(Contmued) of MMUs required by a task swap. This routine System: 02 III ID=O, URS=O
disables all user MMUs (thus disabling the cur- 04 112 ID=l, URS=l
rently enabled user MMUs) , then enables the User 0: 08 113, ID=2, URS=O
appropriate pair. (The system pair is always 10 114, ID=3, URS=l
User 1: 18 115, ID=2, URS=O
enabled.) The code selecting the new task is 20 116, ID=3, URS=l
passed in register RI; it contains 'lion, if task n User 2: 28 117, ID=2, URS=O
is to be dispatched. 30 118, ID=3, URS=l
Two peculiarities of this example are worth
noting. First, each user 10 number cor-
responds to seven MMUs (for example, all User 6: 68 1115, ID=2, URS=O
upper-range user MMUs). The Segment Trap 70 1116, ID=3, URS=l
processing routine has to take this into
account. Second, the Chip Select code is It is also assumed that %F8 will select all
assumed to be as follows: user MMUs.
CLR RO !Clear RO!
SOUT %00F8,RO !Disable all user MMUs by clearing their mode registers!
SLA Rl,#l !Multiply Rl by 2-the number of bytes in a memory word!
LD Rl,TABLE(Rl) !Get the command word (opcode always %00) for user n,
URS=O!
LDA RR2,DATA !Get the new mode register bit pattern (%DA)!
SOUTIB @Rl,@RR2,RO !Send %DA to lower-range MMU and increment RR2 to
DATA + l!
INC Rl, #8 !Command word for URS = I!
SOUTIB @Rl,@RR2,RO !Send %FB to upper range MMU!
END:
DATA: BYTES(%DA, %FB) !Mode register bit patterns!
TABLE: WORDS (%8, %18, %28, %38, %48,%58, %68)
Program to Switch Tabl
OO2049-A
3-47
---- ---~-------.-----
ELECTRONICS & POWER APRIL 1980
An introduction to
memory management
Once used only on the largest computer systems,
memory-management techniques will soon be used on a
variety of high-level microprocessor-based systems
by D. Stevenson
The declImng cost per bit of memory has execuhon of a program, and both are management systems sImulate a hIerar-
led to systems with even larger transparent to the user. chIcal memory structure In which the
memones, and the declinmg cost of Address translatlOn simply means memory conSIsts of a collechan of
10glC has led to more powerful pro- treall'ng the memory addresses dIstmct memory areas, called segments.
cessors. Together, these two trends pro- generated by the program as logICal or Access to thIS structured memory re-
mote the sophlsllcated use of large vlrtual addresses to be translated into qUIres the specIfICation of a segment and
memones, based on techmques com- actual phYSical-memory addresses of an offset wtlhm that segment. Thus, m
monly referred to as memory manage- before dlspatchmg the memory-access stead of speclfymg, say, memory loea-
ment. Automated memory-management requests to the memory umt. Memory- han 1050 m a lmear address space, a
systems date back to the Atlas computer attnbute checkmg means that each area task mIght speCify memory locahon 5 m
project at Mqnchester Umverslty m the of memory has assoClated with It mfor- segment number 23. The actual locallon
late 1950s. Dunng the 1960s the concept mahon as to WhICh tasks can access It of the segment m the physlCal memory
was explOIted In a number of time- and what types of access can be made by does not concern the task - the actual
shanng machines (e.g. the SClephhc each task. Each memory reference IS access IS earned out VIa the address-
Data Systems 940, General Electric 645, checked to ensure that the task has the translation mechamsm, WhICh IS mform-
Dlgllal Equipment Co. PDP-IO), and nght to access that locahon m the given ed of the actual locallon of the segment
dunng the 1970s was highly publIcised fashlOn (for example, to read the con- by the operatmg software.
In Its manifestahon as virtual memory tents of the locahon or to wnte data to Generally, segments can be of
(IBM 370). Unhl fairly recently, memory that locahon). vanable SIze, wlthm hmIts, and a user
management has been associated only Instead of a convenllonal lInear ad- can speCIfy the SIze of each segment to
with large mamframe computers, but dress space, more elaborate memory- be used. Thus one user may be allocated
with the 1978 mtroduchon of Digital
EqUlpment's VAX 11 'super mim', the
concept has Invaded the mIniCOmputer userAs personal
market. Now, with the advent of smgle- memory spacE'
ChIP memory-management unlts such as
USE'r 8's personal
that available with the 2110g 28000 pro- memory space
cessor the concept IS about to arrlve In
I
mICroprocessor-based systems.
Memory management has two func-
lions: the efhclent allocahon and
reallocahon of memory space to ex- segment 5
(program)
ecuhng tasks so as to optimIse overall
memory usage; and the protechon of
memory contents from un::.ntended or
unauthQrlsed accesses by executmg
tasks. To keep overall memory usage op-
hmised as demands on memory con-
I segment 12
(data)
.segment 2
(stock)
stantly change, dynamlC relocahon of
tasl\:s durmg their execuhon may be
necessary, and thiS 18 accomplIshed by
an address-translahon mechamsm. The
restrIchon of memory access to prevent
umntended or unauthorised accesses is
accomphshed by memory-attribute 1 In a multiuser system. each user is aware of only those memory segments in his own
checking. Both operations occur with 'personcd' logical-memory space. and does not know where the segments are located in
each memory access made durmg the the system's physical memory
0013-5127/801040317 + 07 $01'50 IEE.198Q 3-49 Reprinted with permiss~on of Electronics and Power.
ELECTRONICS & POWER APRIL 1980
OPE"ratlng
software>
physical phYSical
memory memory
systE'm code system code
(systE'm E"XE'cute (systE'm executE'
only) only)
segmlmt 6
(program) USE'r A's data
(read/writE')
~--------------- USE'r A's program
(execute only)
user B's program
USE"r B's program (execute only)
5 (executE' only)
~ .- - - - - - -
pgm."t
~,~,1. (data) USE"r Bs stack
(stack rpod /wrlte)
'- (:xE':c~;~ p~~fm
,,;~, USE'r Bs data
user A's data (read IWrltE" )
(read/writE') user S's stack
(5 tack read I writE'
a b
2 T......par.atly 10 !be u ..... I'" oys!em. operatla; aoltwar. 'mope' each ........ (aadlte owa) loglcalm.mory apace lalo !be pb",1cal
_iDory. alao applyl"gmemory-proleclloa attrlbul lo each ~al.1f chaagIag clemoncla oa _mory apace m..... l ... original map-
pia; (a) 110 longer opllmum. !be .yetem CaD dynamically relocate _e"te (b). again IraDllpareatly 10 I'" u....
two segments, one 01 2000 words lor h,s these two users' logIcal program spaces. realIses that these are two separate
Fortran program. and the other 01 The hrst user, user A. has h,s program varIables stored In dIfferent memory
10 000 words lor h,s data. Another user segment called 'segment 6' and h,s data locahons.
mIght be allocated three segments. 01 segment called 'segment 5'. The second User A's data segment. 'segment 5', IS
3000,6000 and 2000 words. respecbvely. user, user B. has her program segment 10 000 words long. II he trIes to
lor her Pascal program. data. and run- called 'segment 5', her data segment relerence word 10 050 01 segment 5, he
hme stack. II the hrst user called h,s data called 'segment 12' and her stack seg- gets an error message Irom the
segment 'segment 5'. then the hrst word ment called 'segment 2'. Nohce that both operatmg software mdICatmg that he has
In h,s data set would be accessed by the users have named one 01 their segments exceeded the allocahon hmlt lor seg-
logICal address (5,0). mdICahng seg- 'segment 5', but they reler to dlllerent ment 5. Note that he does not aCCIdental-
ment 5, 011 set O. The memory- enhhes. Th,s causes no problem smce ly access word 50 01 segment 6; I.e.
management system then translates th,s the system keeps the two memory areas segments are logICally d,stmct and
symbolIc name mto the correct physlcal- separate. The situahon IS analogous to unordered. A relerence to one segment
memory address. both users havmg an mteger varIable cannot madvertently result in access to
Fig. I gIves a conceptual realIsation 01 called 'f m theIr programs: the system another segment. Thus, m th,s example.
3-50
ELECTRONICS & POWER APRIL 1980
operating
software physical
memory
D DsYstE"m
cod. (system E"XE"cuteo only)
syst.m tabl.s
code
systt"m code
(system execute only)
shored dala
O segment 6
(program)
user 8's pe>rsonol
_ - - - _ mE"mory spacE> (,.ad OI1ly)
D segm.nt
(data)
D segmE"nt 5
(progra~)_ -
USE'r /!4.s program
(execute only)
user Bs lYogram
(E'XE'cutE' only)
user B's stack
D~~Et- ------ O
, (stack re-ad I wnte)
segment 12 /
(data) / us(;,r A's data
Dsogm.nt 2/ (read/Write)
(stack /
D /
segment 7
(data)
USE'( 8's data
(re-od Iwntp)
3 The memory-manag.mentsyat.m can alao allow gm.nt.to bhared between ".......uch as a shared data segment meant for in-
put to mor.than one user program. To pr.v.nt any on. us.r from alt.ring th. shar.d data. the system marks th. . .gmentread only'
user A IS prevented from aCCIdentally logIcal-address space of the users to the the segment In whIch the data set is to
(or dehberately) aCceSSIng hts program phYSIcal-memory locations allocated to reside. Note that the two users have
as though It were part of hIS data seg- them. The Ftgure also IndICates the ac- chosen to put the data set In dIfferent
ment. cess attributes assocIated WIth each segments of theIr personal address
FIg. 20 Illustrates one way that the user's segments. For example, program spaces. The memory-mappIng system
operating software could arrange these segments are execute only' and data translates these dIfferent segment names
segments In the phYSIcal memory. If segments are 'read/wrIte'. Thus a user IS to the same phYSIcal memory locations.
demands on phYSICal-memory space prevented from executIng a data seg- Thus user A's access to address (2,17)
were to change. however. the operatIng ment or wrItIng mto a code segment. references the same physical memory
software could dynamIcally relocate the Flg.3 Illustrates what happens when locatIon as user B's access to address
segments (e.g. as shown in Flg.2b). the both users have access to the same data (7,17). The shared data segment IS mark-
relocatIon beIng completely transparent set In primary memory, say the results of ed 'read only' to prevent eIther user from
to the two tasks. In each case, the arrows a questIonnaIre that both Intend to delIberately or aCCidentally changing
indicate the address-translatIon or analyse. Each user has a logIcal name the data.
memory-mappmg functions from the assocIated WIth that data set to specIfy Before proceedIng to the mechanism
the system's memory-management unit ChdCks to see associative storage for active address-translation
if the desired page is in the primary memory, and if so tables within its internal memory, using a cache ap-
translates the logical address to the appropriate proach to ensure that only:; % of accesses require
physical address. If the page is not in primary reference to the full translation tables stored in
memory, it is 'swapped in' from the disc. All this is primary memory. On detecting that a require6page Is
relatively straigiitforward - the complication comes not in primary memory, it will send an 'abort' message
in during the design of the 'paging algorithm' by which to the main processor, which is equipped with a
the operating software decides which page currently special hardware mechanism to 'roli back' its state to
in primary memory can most readily be 'swapped out' what it was at the start of the aborted instruction. Na-
to free space for the incoming page. The efficiency of tional Semicondt)ctor claims that, with these featues,
the whole system depends critically on the choice of and with an appropriate operating system to control
the correct swapping algorithm, and in computer- them, the design of a full virtual-memory system
science terms this choice is 'non-trivial', or in other should not be significantly more difficult than Ihe
words extremely difficult. design of any other microprocessor-based system.
With the forthcoming announcement of the Na- Will such virtual-memory microprocessor systems
tional Semiconductor 16000 'super micro' range, ever become widely used, however? One develop-
virtual,memory operation of this kind will become ment that may make them extremely attractive is that
feasible in microprocessor systems for the first time. of denser, less expensive, magnetic',bubble stores. A
The NS16082 memory-management unit (m.m.u.), relatively inexpensive system could then be based on
which will act as a coprocessor to the NS16000 main a 'super micro', a relatively small (say 128 kbyte)
processor, will support a paged system of virtual- primary memory, and ,,2 Mbyte of fast non.volatlle
memory operation rather like that used on the VAX-11. bubble storage. Such a system, occupying a single
Because of the NS16000's use of 24-bit addresses, board, might well exhibit a performance approaching
each virtual-memory space will be initially limited to that of traditional mainframe systems.
only 16 Mbytes, but later expansion should increase
thiS substantially. The m.m.U. will prOVide fast DENNIS MORALEE
3-51
ELECTRONICS & POWER APRIL 1980
of memory management, It IS InstructIve the sharmg of common memory areas by when the stack approaches the allocated
to reVlew the advantages of usmg thIS dlfferent tasks ThIS IS accomphshed by limIt of the segment. The task could then
form of segmented address translatlOn mappmg dIfferent logIcal areas m dIf- request the operahng software to
and attrIbute-based memory protectIon. ferent tasks to the same phYSiCal-memory allocate more memory to the stack
The hrst advantage IS that It permIts the locahons before the stack overflows and creates a
dynamic allocahon of memory dUring The thlfd advantage lS that It provIdes fatal error.
the execuhon of tasks, 1 e tasks can be protechon agamst certam types of The fmal advantage of such memory-
located anywhere In memory and can I memory access ThIS IS accomplIshed by management systems IS that they
be relocated as demed whJie thelf ex- assoclabng accessmg attrIbutes WIth separate user funchons from system
ecutIon IS suspended The address- each logICal segment, and by checkmg functIons For processors that dIstmguish
translatIon mechamsm provIdes thIS the type of access to see If each access IS between a 'system' mode and a 'user'
f1exlbllity because the task deals ex- permltted mode of operatIon, thIS goal can be ac-
cluslvely WIth logIcal addresses, and The fourth advantage IS that It detects complished by assoclatmg a system-only
hence IS mdependent of the addresses of ObVlOUS executIon errors related to attrIbute WIth operatmg -system segments
the phYSIcal-memory locatIons It ac- memory accessmg ThIS can be ac- so users cannot dIrectly access the
cesses Movmg the task to dIfferent complished by checking each access to operatmg software and ItS data tables.
physlcai-memory locatIons reqUlres that a segment to see whether the address As a fmal pomt, It should be noted
the address-rneppwg fllnrt\on hp "hang- f",ll<- wdhm the ohvslcal-memorv area how seamentahon can be used to sup-
ed to reflect the change m phYSICal ~li;cated to that ~egment. It couid also port th~ devslopment and execuhon of
memory locahon, but the task's code mclude afhxmg a read/wnte attnbute to large, complex programs and systems.
need not be modlfled Of course, thls data to prevent a task from trYing to ex- The concept of segmentatlon cor-
flexlbliity does mcur the overheads m- ecute a data segment, and affixmg an responds to the concept of parhhonmg a
volved m managmg the VarIOUS address- execute-only attribute to code segments large system mto procedures and data
transl.hon tables reqUlred by the to prevent a task from trymg to read or structures, each procedure and data
operatmg software, but these are nor- wnte data to thIS segment Addlhonally, structure bemg assocIated WIth a
mally outweIghed by the advantages If a segment IS used to hold a stack, the separate segment. A task can then In-
The second advantage lS that It allows system could Issue a warmng to a task voke a procedure or subtask, or access a
3-52
ELECTRONICS & POWER APRIL 1980
3 22 15 0
. bit status
word from
procE'ssor
D 'illE'gol aCCE"5S'
warning to processor
1
,-_S_"_9_n_O---,-_O_ff_s_"_t 1
23- bit IOQlcai cadre-55
_---!. from proccE'ssor
'--r---'~
precesser te put the 7-bIt segment number en Its .out- 'Ieng werd' eperatlens Fer mere effiCient manlpula-
put lines .one cycle ahead .of the rest .of the address tlen .of shert (up te 256 byte) segments, shertened
This gives the m m u addltlenal time te retneve the leglcal addresses censisting .of 7-blt segment
apprepriate segment-starting address and te check numbers and 8-bIt .offsets can alse be used, these
the apprepriate segment attnbutes shertened addresses fitting Within an .ordinary 16-bit
Frem thiS acceunt .of the m m u 's actlen, It will be werd
seen that the Z8000 precesser handles 23-bit leglcal Very Similar memery-management facilities are
addresses directly, each legical address cempnsing a said te be planned for Meterola's 68000 'super micre'
segment number and apprepnate .offset These 23-blt The Metorela deVice, hewever, uses 24-bIt legical
addresses can be stered as 32-blt 'Ieng werds' In pairs mem.ones te give a larger 16 Mbyte addreSSing range
.of 16-blt registers.or in adjacent 16-blt memery werds,
and can be manipulated by all the Z8000's built-In DENNIS MORALEE
data structure, by referrmg to its logical- lmks to a rouhne formmg part of the memary into fIxed-SIzed blacks, called
segment name, Access to these .objects operating software and capable of fet- pages. LIke segments, the mdividual
can be indiVidually restricted by using chmg the segment from secondary pages can be lacated anywhere In the
the protection-checking mechamsm of memory when needed. phYSIcal memory, and a translation
the memory-management syslem. Whenever an access IS made to a seg- mechamsm maps laglCal addresses ta
ment mlssmg from physlCal memory, the physICal lacahons. There are twa dIf-
Virtual memory instruction executIon is held In ferences between pagmg and segmen-
With the memory-management abeyance unhl the segment can be hng a laglCal memary. First, pages are
systems consIdered so far, It has been brought mto the physical memory, and .of fIxed SIze whereas segments are .of
assumed that the actual physical then the instruction IS allowed to pro- various SIzes. Second, under pagIng, the
memory available is always large ceed WIth the memory access. The ad- logical memary 18 shll lmear, I.e. a task
enough for all the users' 10glCal-address dress translation IS then performed, ac- accesses memory USIng a sIngle number,
space to be simultaneausly mapped anta cess protection IS checked, and the m- rather than a pair as In segmentahan.
it. In fact, further advantages can result struction proceeds as If the segment had The maJar advantage of paging is in
fram making even this physical-memary been in the phYSIcal memory at the treating memory as blacks of fIxed sizes,
space 'virtual', and fram mapping it m begmillng of the mstruchon. Thus th,s which sImplIfies allacahng memary ta
turn inta a two-level memary space, part techmque of demand swapping, or users and decldmg where ta place the
.of which is held in a relatively small segmented virtual memory, means that 10glCal pages in physical memary. The
'true' physical memary, and part of the segments WIll not m general reside m major d,sadvantage .of paging IS the dif-
which is held an a secandary-memory physica,l memory unhl a task actually fIculty of asslgnmg dIfferent pratectian
device such as a magnetic d,SC (F,g.4), trIes to access it. attrIbutes ta dIfferent areas In a user ad-
In aperatian, this vIrtual-memory ar- Another techmque of vIrtual-memory dress space, because a paged memary
rangement relies on a,n extensIOn .of the management IS pagmg, which IS also a appears hamageneous ta the user and
address-translahan scheme cansidered method of parhtionmg a user's logical- the operating system. Paging can,
abave, If a given segment IS nat current- address space and mapping It onto a hawever, be cambmed WIth segmenta-
ly in physical memary, the address- two-level phYSIcal memory. Essentially, hon to produce a memory-management
translation table indicates the fact, and a paging system diVIdes the logical system WIth the advantages .of bath pag-
3-53
ELECTRONICS & POWER APRIL 1980
operattng
softwarE'
matn mE"mory
(random access)
systE"m code-
D segment
(data)
D spgment 5
(program)
O U5er B~
D spgment 12
(data)
O spgment 2
(stack)
data
R
system
codE" U
disc
storE'
4 In CIt vlrtuCltI-memory syatem, the system'. 'phYJlcal memory' I. split betw..n CIt relatively small rcmo:\om-acceas 'main' memory and a
secoDdary-",emory disc 8tore, If CIt program attempt. to acee.. a ..gment not currently stored In main memory, the operating software
retrieves II from the disc, and proc..llng continues transparently to the user
ing and segmentahon, but at the cost of deSCrIbed above. If the specIal regIsters could have one entry for every poss.ble
considerable extra complexity. contam phys.cal memory locahons, segment name, w.th the starhng address
these must be protected from user access of each segment m use stored as part of
Mechanics 01 memory to mamtaIn the integrity of the system, the table entry.
management and changIng segments reqUIres system A number of other segment attrIbutes
Essenbally there are four Issues In Im- calls whIch can be hme consummg .f too can also be stored In the address-
plemenbng a memory management few regIsters are supplIed. translahon table and checked durIng
system: how addresses are speCIfIed, In e.ther case, address translahon .s each access. One of these .s the
how these addresses are translated, what performed by addmg the log.cal- allocated length of the segment, and
attributes are checked for each access, segment offset to the address of the each access IS checked to see .f It falls
and how the protection mechanIsm IS Im- phYSIcal-memory locabon where the w.thIn the bounds of the segment.
plemented. segment begInS. Thus, when an address Another type of attrIbute deals WIth
Two approaches have tradlhonally of the form (a,b) IS presented to the ownersh.p or class of ownershIp: tasks
been taken for speCIfYIng addresses In a translahon mechanIsm, the segment are grouped Into classes, and only those
segmented memory (for SImplICIty, only name 'a' .s used to determIne where seg- In certaIn classes are permItted to own
addresses In Instrucbons are dIscussed ment 'a' res.des In memory. Assume that and therefore access a g. ven segment.
here). The hrst way puts all the address- .t reSIdes In locahons 10000 to 25000. The s.mplest example .s the 'system' ver-
ing Informabon In the instruchon Itself; Then the actual memory locahon (a,b) .s sus 'user' claSSIfIcation, where tasks are
i.e. each memory address in an instruc- memory locahon 10000 .,.. b. The major e.ther one or the other, and wh.ch they
tion contains both the segment name and ophon m Implemenhng th.s type of ad- are determInes whether or not they can
the offset wlthm the segment. The aller- dress translahon IS m determInIng the access a given segment.
native sets aSIde special regIsters that segment's location In phYSIcal memory. Other types of attnbutes that can be
contain some of this information, for ex- When speCIal reg.sters have been set assoc.ated WIth a segment Involve modes
ample, the segment name or Ihe address aSIde to contain the startIng locahon of of accessmg, for example 'read-only',
In phYSical memory where the segment the segment instead of puthng all ad- 'read/wnte' or 'execute-only' _ AttrIbutes
resides. dress informabon In the Instruchon, the can be eIther perm.sslve or prohlblbve;
The advantage of the latter approach addreSSing mechanIsm .s s.mllar to us- for example the 'wnte' attrIbute can
lies in the fact that fewer bits are needed Ing the segment regIster as an index mean 'wrlbng to th.s segment .s permIt-
in an Instrucbon to specify addresses. reg.ster or a base register. ted' or 'wr.bng to thIS segment IS pro-
Thus programs may be shorter. Also, When log.cal addresses are e.ther hlb.ted'.
because there is reduced trafhc between completely speCified In the Instruchon or A fInal Issue m the mechanICS of
the memory and the processor for fet- when the speCIal regIster contaInS the memory-management systems .s the Im-
ching shorter instrucbons, " program segment's symbolIc name rather than .ts plementalton of the protechon at-
may be executed faster. phYSIcal-memory localton, a table must trIbutes. These may be assoc.ated eIther
On the other hand, these special be used to translate the segment's name WIth the logIcal-address space or WIth
registers must be manIpulated to access Into Its phYSIcal-memory locahon. The the phys.cal memory .tself. Assoc.ahng
more segments than there are regIsters, table may have an assoc.abve capab.lI- access attrIbutes w.th the log.cal seg-
and thIS manIpulabon adds to the ty, I.e. the segment name IS presented to ment permIts a more versable memory-
number of Instrucbons, the program SIze the table and It automabcally returns the management scheme because dIfferent
and the execubon time. In pracbce, phys.cal-memory locabon where the users can access the same physical seg-
these can de;troy the advantages segment begins. Alternahvely, the table ment and have d.fferent access attrIbutes
3-54
ELECTRONICS & POWER APRIL 1980
assoCIated with their accessing. stored in secondary memory, and the not strictly necessary, such information
Other mformahon that can be primary memory is not available until can improve the performance of the
assocIated with each segment is the segment has been saved. Although overall memory-management system.
assocIated not with the protection
mechanism, but with other functIons of
the memory-management system. Th,s
informahon generally relates to the Re/erene
hIstory of the segment; for example, I CORBATO, F.J.. , and VYSSOTSKY, V.A.: 'Introduction and overview 01 the mulllcs system',
whether a segment has been modified AFIPS Coni. Proe .. Fall Jomt Computer Coni .. 1965,27, pp.I85-196
while resident in primary memory. If It 2 GLASER, E.L., el al.: 'System deSIgn 01 a computer lor IImesharmg apphcallons', AFIPS
has not been modified, and the system Coni. Prec., Fall Joint Computer ConI., 1965,27, pp.297-302
temporarily requires the memory space 3 WATSON, R.W.: 'Timesharing system deSIgn concepts', (McGraw-HIll, New York, 1970)
for another segment, the memory can be
freed immedIately; otherwise, the up-
dated versIon of the segment must be David Stevenson is WIth ZUog Inc., 10460 Bubb Road, Cuperllno, Cahl. 95014, USA
, 'I'
3-55
Z8000 vs. 68000
Concept Papers
~
Zilog Introduction
July 1981
Memory Addressing The l8000 and 68000 CPUs are SImIlar In theIr
reglster archItectures, bul they dlffer ln Slg-
There lS a sharp contrast between the segmented nlflcant detalls. POl nts that should be consI-
addreSSIng model of the l8000 CPU and the purely dered are:
l,near addresslng model of the 68000 CPU. In
eXamlning these approaches, lhe followlng deslra- General vs. speCIal-purpose use of reglsters
ble attrlbutes for a memory addresslnq scheme Avallablllty of reglsters of all necessary
should be recalled: Slzes
Addressabillty of subreqlsters
An addreSSIng model that murors proqram 01'- ExtenslbIllty of the regIster set
qan Izat lOn
PrOV1S11Jn for access protect lOn
ProvIslon for memory mappIng
3-57 7/2/81
~
Zilog Concept Paper
May 1981
The ZBOOO and the 6BOOO take quite different data register or an index register. (There are
approaches to register architecture. The prin- restrictions on the use of RO imposed by the cur-
cipal points of difference are: rent instruction encoding.) The 6BOOO has two
sets of 32-bit registers: eight address registers
General purpose vs. special purpose registers and eight data registers; either type can be used
Pairing vs. telescoping of subregisters for indexing.
Extensibility of the register sets
This difference in register architecture results
DO in generally simpler programming of the ZBOOO than
of the 6BOOO. Several aspects of this are:
01
02 Information in a ZBOOO register never has
to be moved before being used as an address
RO
03 or in arithmetic operations.
R1 The ZB 000 uses the same op codes for argu-
04 ments in any of the registers. This is in
R2 contrast with the 68000's separate op codes
05
R3 (e.g., ADD and ADDA for operations on the
06 two register sets).
R4
07 The ZBOOO uses the same addressing modes
R5 for all of the registers. This is in con-
68000 Data trast with separate 6BOOO addressing modes
R6 like "data register direct" and "address
Registers
R7 register direct."
AO RS The net effect of these di fferences is that with
regard to register handling the job of the com-
A1 R9 piler writer is easier with the Z8000 than with
A2 Rl0 the 6BOOO and that compiled code for the ZBOOO is
likely to be more efficient than code for the
A3 Rll 6BOOO.
A4 R12
PAIRING VS. TELESCOPING Of SUBREGISTERS
AS R13
The ZBOOO instructions refer to byte registers,
A6 R14
16-bit registers, 32-bit registers and (occasion-
A7 R15 ally) 64-bit registers. The 6BOOO refers to
16-bit and 32-bit address registers and to B-bit,
6BOOO Address ZBOOO General Purpose 16-bit and 32-bit data registers. On both
Registers Registers machines, every register, except for those of the
largest size, is contained in a register of the
Z8000 and 68000 Registers next larger size. Thus, every byte register is
contained within a 32-bit register, and so on. On
the 6BOOO, this is a one-to-one relationship.
Each 32-bit register contains exactly one 16-bit
GENERAL PURPOSE VS. SPECIAL PURPOSE REGISTERS register, each 16-bit data register contains
exactly one byte register. In each case, the
The ZBOOO has a set of 16 16-bit general purpose sub register is the rightmost half of the larger
registers. Each can be an address register, a register.
r
8-bit version
RRO RHO RLO ~
o
Rl RHl RLl RQO DO
RR2
{: RH2
RHJ
RL2
RL3
01
RR4
{: RH4
RH5
RL4
RL5 >RQ4
02
RH6 RL6 OJ
RR6 { R6
R7 RH7 RL7
D4
RRB
{: ~ RQB 05
RRl0 { Rl0
D6
Rll
RR12 { R12 07
R1J
>RQ12
RR14 {R14
R15 6BOOO Oata Registers
B, 16 and 32-bit versions
Z8000 General Purpose Registers all have same name; each is
Smaller registers are paired rightmost subset of the
to form larger registers. 32-bit version
28000 Register Hierarchy 6BOOD Regiater Hierarchy
~
Zilog
Z8000 vs. 68000
Concept Paper
October 1980
The Z8000 and 68000 take very different The MOVEP Instruction and the missing block
approaches to the addressing of I/O trans- I/O Instruction also demolish the simplicity
actions. In the 68000, I/O addresses and argument. Separate Instructions are necessary
memory addresses share the same address because the two kinds of operation are dif-
range. This Is called memory-mapped I/O. ferent, and If the separation Is not made
References to I/O addresses are made exactly explicit, an additional Instruction wll I be
like references to memory addresses, using necessary, as was done on the 68000.
the same Instructions and addressing modes.
The processor does not know, when It engages In regard to the ease of Implementation argu-
In a read or write, whether It Is talking to ment, I/O and memory transactions on the
memory or to an I/O device. Z-Bus are only trivially different (I/O has
an added cycle). The difference between the
In the Z8000, there Is a separate address Z8000 and the 68000 bus protocols Is not In
range for I/O transactions, and separate ease of Implementation. The difference Is
Instructions are used. The processor always that the 68000 Is locked Into a single bus,
knows which kind of transaction Is being while the Z8000 has the potential for future
conducted. The same physical address/data separation to Improve performance.
lines are used for the two kinds of refer-
ence; the status lines ST3-STO distinguish Upon closer Inspection, memory-mapped I/O
between them. has, In fact, many disadvantages.
Several advantages have been claimed for It makes protection of I/O references Im-
memory-mapped I/O: possible at the Instruction level--I/O In-
structions can't be privileged, because
Regularity - the same Instructions and there are no I/O Instructions.
addressing modes are available for I/O as It creates "holes" In the memory address
for memory. space, so that certain addresses--posslbly
Simplicity - the size of the Instruction localized, but potentially anywhere--
set Is reduced, since there are no I/O cannot be used for memory addresses by any
Instructions. program.
Ease of Implementation - there Is no need It prevents a compatible separation of I/O
to design separate I/O bus protocols. and memory buses--blocklng an Important
path to performance Improvement.
As to regularity, the kinds of operation
performed on I/O ports are limited, as are The question of protection Is Important In
the kinds of addressing that are useful In the design of operating systems. The I/O
I/O operations. Furthermore, there are function Is usually control led by the system
special needs of I/O operations that are and prohibited to users, so It makes sense to
different from those of memory operations make I/O Instructions privileged. On the
(e.g., block transfers to a fixed address). 68000, there are no I/O Instructions (except
for MOVEP, which Is not privileged), so I/O
The 68000 design recognizes the fal lacy of Instructions cannot be privileged. The only
the regularity argument by Introducing the way to achieve this kind of protection on the
MOVEP Instructlon--a block transfer of the 68000 Is to assign to an external device the
bytes of a word or longword to consecutive job of recognizing I/O addresses and prevent-
even-addressed or consecutive odd-addressed Ing access to these addresses when the
bytes of memory. No 68000 Instruction Is processor Is executing In user mode.
provided for block transfers to a fixed
address In memory.
~
Zilog
Z8000 versus 68000
Concept Paper
October 1980
The l8000 and 68000 address/data buses are similar allow the data bus to be turned around at
1n that both use asynchronous protocols. They the beginning and at the end of each
d1ffer in that the l8000 time multiplexes one set write.
of lines for address and data, while the 68000
Considering the other side of th1s trade-off, the
uses two separate sets of lines. The trade-off
use of separate address and data lines results in
involves the h1gher potent1al performance of
separate, dedicated hnes versus the more effec- the need for 16 (and, in the future, 32) pins that
could be utilized to greater advantage. Looking
t i ve use of the limited numbers of pins ava11able
just at the CPU, the 68000 faces all of the price,
for chip packages.
power and reliability problems of a 64-pin chip
Dedicated lines have a potential for improved with no more capabilit1es than are provided by the
l8000's 48-pin package. When improved manufac-
performance when one device has access to both
tur1ng technology allows economical and reliable
the address and the data and can send them out
expansion of the l8000 to a 64-pin package, the 16
simultaneously. The principal occurrence of this
additional pins will provide greatly increased
situation is a write to memory. There are several
capabilities.
reasons why this potential advantage is of little
consequence in a comparison of the l8000 and the In add1t10n to the more effective use of CPU pins,
68000. the multiplexing of address and data lines pro-
vides a means of addressing directly the internal
Reads from memory (includ1ng instruction registers of peripheral chips without the need to
fetches) occur roughly eight times as ded1cate pins of the peripheral ch1p to separate
often as writes. A read from memory does address lines. Since at least eight data lines
not benefit from the separation of lines, must generally go to a peripheral chip, these can
S1nce the address must be sent from the be used during the addressing phase of an instruc-
CPU to the memory before the memory can tion to address a chip's internal registers (with
retrieve the data or instruction in the remaining eight I/O address lines possibly
question and send it back to the CPU. being decoded by external chip-select logic).
In the case of writes to memory, most This simplifiesthe programming of and access to
memory chips are incapab Ie of s imult a- peripheral chips by eliminat1ng the separate
neously accept ing both the address and address setup cycle required by an unmultiplexed
the data to be stored. peripheral interface.
Even with a memory chip that is capable
of accepting addresses and data simul- In summary, the use of separate address and data
taneously, the 68000 still achieves no lines gains little in performance, especially on
performance benefit, since 68000 write the 68000 with its extra-long memory write
instructions are two cycles longer than instructions. It is wasteful of hard-to-come-by
read instructions (six cycles for writes CPU pins and encourages a cumbersome interface for
vs. four cycles for reads) in order to addressing peripheral chips.
611-1790-0004 3-63
Z8oo0 vs. 68000
Segmeated vs. Liaear
Addressiag
~
Zilog Coaeept Paper
November 1980
3-65
INmRODUCTION The Z8000 and the 68000 use fundamentally The tradItIonal approach to dealIng wIth
dIfferent models for memory addressIng. The these objects Is to allocate portIons of the
Z8000 uses segmented addressIng. The 68000 computer's memory to each of them. A relo-
uses lInear addressIng. We shall defIne these catIng loader mIght pack the programs to-
terms and explaIn why segmented addressIng Is gether end to end and then allocate the data
a superIor method. areas (of fIxed sIzes) end to end In the
portIon of memory not occupIed by the pro-
Segmented addressIng Is a "hIgher-level grams. SInce the only addressIng model
language" for memory addressIng. That Is, It avaIlable wIth the earlIest computers was
Is a way for the programmer to thInk about lInear addressIng, each of the objects would
and refer to the computer's memory In terms receIve an address dIrectly related to
that are natural to programmIng rather than (usually the same as) the actual memory
In terms of the memory's physIcal Implementa- address at whIch It was stored. These ad-
tIon. LInear addressIng Is the "machIne dresses were all numbers In the range 0 to
language" of memory addressIng. That Is, N-I, where N was the total number of memory
wIth lInear addressIng, the programmer uses a locatIons avaIlable. Every program that
model for the computer's memory that Is very referred to any of these objects had to do so
close to Its actual hardware ImplementatIon. usIng thIs address.
Before we state more specIfIcally exactly
what segmented addressIng Is and how It
works, let's look at some of the memory ad- PROGRAM PROGRAM ARRAY STACK
dressing tasks that programmers face and see 1 2 1
what kInd of addressIng model these tasks
suggest.
Figure 2. A Traditional Invalid Access For the stack example. a sImIlar envelope
would be placed around pushes and pops.
Rather than usIng the machIne's push and pop
Another example of thIs problem concerns the InstructIons. the program would call sub-
use of stacks. A common approach to stack routInes for these operatIons. Nllturally.
use In a sIngle-user system Is to allocate thIs approach entaIls a large software over-
the "beg I nn I ng" of memory to programs lind helld.
data and the "end" to a stack. sInce the push
lind pop InstructIons on most computers are Another type of Invlllld access occurs In even
desIgned In such a way that stacks grow the most elementary systems. but It presents
"backwards" In memory; that Is. the fIrst an urgent problem when several programs or
Item plilced on the stack Is at the hlghest- sets of data--not necessarIly related to one
numbered address. and the "top" of the stack another--share memory slmultllneously. ThIs
Is at the lowest-numbered address. If often problem concerns the restrIctIon of a pro-
happens that program changes cause the pro- gram's accesses to those portIons of the
grllm and data areas to expand. so that less memory contaInIng Its bwn subroutInes and
and less remalHs for the stack. Sooner or data or--even more dlfflcult--to portIons of
later. II stack push causes the stack to over- memory contlllnlng data or subroutInes that It
flow the allotted area and eradIcate the end shares wIth another program lind to whIch It
of the area assIgned to progrllms and dllta. Is allowed only certaIn kInds of access (such
liS "relld only" or "execute only").
A frequently used approach to problems of the
sort descrIbed above Is to create an The software envelopes dIscussed above can be
"envelope" around the accesses In questIon. extended to accommodate shared access to
Thus. for example. Instead of usIng the c0m- dllta. but It Is dIffIcult to place such
puter's IndexIng capabIlIty to access arrays envelopes around program accesses. Further-
dIrectly. the program mIght Insteed call a more. these envelopes are voluntary; that Is.
subroutIne thllt accepts the Index and the a programmer who wIshes to avoId them can
3-67
usually discover enough Information to be and Irrelevant to the program using the
able to make the accesses directly. For stack. Unfortunately, the way that stacks are
situations of this sort hardware solutions ordinarily used does not lend itself to this
were I ntroduced. One such so I ut Ion was the approach. Frequently a program Is allocated
use of II mit reg Isters. For examp Ie, the a block of stack space, which It then
operating system might set registers that accesses using based addressing. That Is,
defined the limits of the program about to the actual memory address of the first loca-
run to be locations 10000 through 19999. In tion of a block of stack space Is kept In a
this case, the program Is free to make register, and accesses Into the block are
references of any sort so long as the ad- made by adding an Index (from a register or
dress used lies within the given range. An from an Instruction) to the base addresses In
attempt, for example, to call a subroutine at the register. This common practice Is Incom-
address 20000 resu Its In a "trap," and con- patible with the existence of gaps In the set
trol Is returned to the operatl ng system. of addresses assigned to the stack.
These examples are an Indication of some of The solution to this problem (before segmen-
the ways In which the problem of Invalid tation was Invented) was to al locate a larger
accesses can manifest Itself, and they show contiguous block of memory to the enlarged
how early system designers attempted to solve stack--elther by moving the stack to another
them. Shortly we shall see how segmentation part of memory or by moving something else
provides a complete solution to this problem. out of Its way so that It could be expanded
where It was. This approach has two Inherent
Objects of Varying Sizes problems: the processing overhead to move
objects around In memory and keep the unused
In our stack example above, we saw the kind memory all In one place and the "relocation"
of problem that can arise when an object problem of changing all of the base addresses
varies In size. We showed how an envelope of blocks of stack space that the program has
around pushes and pops can detect Invalid In registers or In storage. The second
accesses before they occur, but we are stll I problem Is almost Insurmountable, except In
faced with the problem of what to do about the most elementary cases.
them. In the example given above, there was
only one stack, and It didn't run out of The problem of accommodating objects whose
STACK
SEG
3
PROGRAM PUSH/POP
USING ENVELOPE
PUSH/POP
- ~ I BASED ADDRESSING
L _ ....J-REFERENCES TO HERE
ARE
MEANT FOR HERE
STACK
"LOGICAL SEG
STACK" 1
PROGRAM
USING
BASED PHYSICAL
ADDRESSING STACK
I
2ND
OBJECT stack pointer or other address register.
(ABANDONED) Relocation effected through based addressing
Is called uuser-controlled" relocation, since
the setting of the stack pointer or other
address register Is under control of the
running program. A better approach from the
3RD standpo I nt of re II ab III ty Is "system-
OBJECT HARDTo-USE
FRAGMENT
controlled" relocation. This kind of relo-
cation can be provided using memory mapping.
-- --
MAPPING
the creation and deletion of objects Is USING
simply treated as part of the "algorithm" BASE
REGISTER
that the program Implements. Soon we shall
see how segmentation allows system control of
this function.
Ml
I K -- K
Rei ocatl 011 "LOGICAL"
BASE REGISTER
ADDRESSES
Segmentation Is the organization of the ad- These ~xamples show how segmented addressing
dress space Into a collection of Independent helps to allevIate our fIrst major problem
Objects. As we noted ear II er, In each pro- wIth lInear addressIng: InvalId aceesses.
gramming situation there can usually be Suppose. for example. that we had made a
Identified a set of largely separate but programming error that caused us to address
Interrelated objects. The segmented address- the current posItion representatIon array by
Ing model assigns to each of these objects a usIng an Index value of 257. WIth a lInear
is;-T
SEG
3 the linear address space of the segment. It
Is called en offset because In the Interpre-
tation of segmented addresses, the offset Is
LJK.1 added to the physical memory address of the
"base" of "the segmen"t to obtai n the phys Ica I
address of the element In ques"tlon. For
L-_ _-IIN1 example, If segment 5 has a base address In
23BIT LOGICAL ADDRESS
A
TOP OF STACK
It Is a matter for subjective judgment to
MEMORY
decide where to draw the lines between sys-
ACTUAllY tems that are too small for segmentation.
ASSIGNED
NONFATAl systems In which segmentation Is desirable
STACK WARNING
OCCURS ON REFERENCE but Inessential. and systems that are so
64K TO THIS 256BYTE large that segmentation Is mandatory. The
BYTES AREA
, / j256 Z8000 architecture provides for a 16-blt
BYTE S linear address space but demands segmentation
I for any size above 16 bits. In Its 23-blt
I address space. It Is possible that clever.
I well disciplined programmers could manage to
I
handle unrestricted linear addressing. In
Its ultimate 32-blt address space. there Is
I no doubt that segmentation Is the only viable
I
approach.
I I
OF:~~ENT_L __ ---1 This concern for the future expansion to
Figure 9. Stack Segments 32-blt address spaces greatly Influenced the
decision to use segmented addressing In the
23-blt version. The Z8000 represents a break
COM::lUS ION from the architecture of the Z80; It seems
short-Sighted to ask designers moving from
This concludes our discussion of the specific
8-blt to 16-blt or 23-blt systems to face one
details of the Implementation of segmented architectural break today and another In a
addressing and memory mapping on the Z8000.
few years. This Is In contrast with the
We have discussed the many problems associ- situation of designers who adopt the 68000
ated with linear addressing. the solution
provided to these problems by the segmented today and who will have to face another
architectural upheaval If true segmentation
addressing model and the details of segmenta- Is Introduced--that occurrence seems Inevi-
tion on the Z8000. We have shown that seg-
table If the address space Increases In size
mented addressing is clearly superior to
to 32 bits.
linear addressing.
~
Zilog
Z8000 vs. 68000
Concept Paper
May 1881
One of the most striking differences between the sources among these processes and resolVIng con-
arch itectures of the Z8000 and 68000 is the pro- flIcts accordIng to an externally selected polICY.
vision for operating system support. This area Duectlng traffIC entaIls:
received careful consideration in the Z8000
design. The designers of the 68000 addressed most Protection of the operating system and of each
of their careful attention to other issues. This process from damage or invasion of privacy
paper shows the importance of operating system arising from the actions of any other proc-
support features, even in relatively small appli- ess.
cations, and contrasts the designs of the Z8000 Establishment, support, and enforcement, of
and the 68000 in regard to operating system sup- protocols and conventions for the interactions
port. of system elements.
Facilitation of interprocess communication and
sharing.
OPERATING SYSTEMS
Thus, the responsibilities of an operating system
Every computer application contains an operating are:
system--either explicitly or implicitly. For the
purpose of this paper the following definition of Allocation and protection of processing and
an operating system is used: storage elements, external interfaces, and
programs.
The portion (hardware and software) of a Defi nit ion, fac i li taUon, .and enforcement of
computer application that is devoted to protocols and conventions.
managing hardware and software re- Communication and sharing.
sources. Policy enforcement.
Most definitions of "operating system" are similar ARCHITECTURAl SUPPORT FOR OPERATING
to this one. The idea of resource management is SYSTEM RESPONSIBILITIES
central to everyone's idea of an operating system.
The resources of a computer application can be The operating system responsibilities listed above
divided (approximately) into the following cate- differ from system to system. For example, the
gories: work of a small application may be carried on by a
single process, although the system process that
Processing elements (e.g., CPUs, floating handles external device interrupts will share the
point chips, "intelligent" disk controllers) CPU with the application process. There are
Storage elements (e.g., ROM, RAM, disks, several kinds of architectural support that facil-
tape) itate the operating system's task in a wide range
External interfaces (e.g., I/O ports, modems) of applications:
Programs (e.g., compilers, application pro-
grams) Restriction of access to CPU facilities
Restriction of memory use
A process (also called a task) is the ongoing Memory mapping
execution of a program by one or more processing Sharing of programs and data
elements. For example, a compilation is a proc- Program relocation
ess. The goals of a computer application can be Stacks
viewed as the completion of processes. From this Context switching
point of view, the job of the operating system is I/O system and interrupts
to "direct traffic" for as many processes as it Distributed control
makes sense to run concurrently, allocating re- Support for conventions
Stacks are used by the operating system (explicit- One of the di f f icult ies of running several proc-
ly or impliCitly) to allocate memory in a flexible esses concurrently is the overhead associated
way that, in connection with based addressing, wi th context switching. The context of a process
allows programs that need nonregister storage to is the portion of its state that occupies shared
remain position independent. Special cases of this resources. For example, since most CPU architec-
are the storage of return addresses for subroutine tures call for only a single Program Counter (PC),
calls and machine state for interrupt processing. all processes must share this register, so the PC
value of each process is part of its context. Most
Stacks provide an important application of dynamic architectures also call for a single set of
physical relocation, because the way they are used general-purpose registers, control registers, CPU
makes logical relocation of stacks almost impos- status registers, and so forth. Thus, when the
sible. In order to provide flexible allocation of same CPU is allocated to more than one proces s,
stack space, the operating system must be able the pr ocess contexts must include the contents of
to expand a stack upon demand. This sometimes any of these registers used by the processes.
entails physical relocation of the stack to a lar-
Context switching is the saving of the context of
ger area of physical memory, since with based
addressing, a stack must consist of contiguous one process and the recalling of the stored con-
text of another process. Some architectural
logical addresses and since most memory-mapping
features for the support of context switching are
schemes require contiguous logical address blocks
desirable. These include automatic saving of CPU
(below a minimum size) to map into contiguous
state on interrupts, single-instruction block
physical addresses.
register saving and restoring, and access to all
necessary control registers.
Other architectural features desirable for stack
support inClude: All modern CPUs provide automatic saving of a
portion of the CPU state on inter rupts and ac c es s
The ability to designate one or more stacks to all control registers that can form part of a
for program use. process context. Block saving and restoring of
Single- and multiple-argument push and pop registers is available with some CPUs. Either a
instructions. starting register and the number of registers to
The ability to address items at locations be saved or a bi t-encoded select ion of registers
defined relative to the top of a stack. to be saved provides some flexibiUty--not all
Automatic warning (traps) of impending stack registers need to be saved in every case. In most
overflow or underflow. cases, the operating system saves registers on a
stack.
Most architectures call for the implementation of
stacks as linear arrays in memory with an address
register marking the top of the stack and provid- I/O System and Interrupts
ing (through based addressing) access to items at
other locations in the stack. The stack register The operating system responsibilities pertaining
is a dedicated (special-purpose) register in some to the I/O system and interrupts vary greatly with
architectures. In other architectures, any ad- the type of application. The architecture of a
dress register can be used as a stack register, general-purpose CPU must provide the flexibility
although the program usually cannot specify which necessary to accommodate the I/O requirements of a
stack register is to be used for saving returns wide range of application types.
from a subroutine or the machine state on inter-
rupts. One of the operating system's most difficult tasks
in this area is the control of access to I/O
The implementation of stacks as arrays in memory resources. Unlike memory, which can be divided
and the use of general-purpose address registers into large, relatively homogeneous blocks, the
for stack registers make the provision of overflow elements of the I/O space require specisl-purpose
and underflow protection difficult. Architectures management, protection, and access techniques. In
that provide stack limit protection usually do so addition, device timing requirements and exter-
through the use of the attribute specification nally set policles for confllct resolut lon make
associated with memory protection. Several arch i- hardware support of I/O mechanlsms mandatory.
Conflict resolution is controlled by a policy that One of the issues that must be considered in the
is set by the system designer and enforced by the design of a CPU is whether its architecture should
system. The usual approach is to provide a small support all conventions equally, favoring none, or
number of priority levels to which device inter- whether it should encourage, through special fea-
rupts can be assigned, by virtue of either the tures, specific conventions. For example, should a
means of connection to the CPU or the setting of a CPU be designed with general support for high-
priority level in the "vector" for each device. level languages, or should it be designed to op-
Then, when the CPU is processing a device inter- timize Pascal, say, at the expense of making
rupt of a given priority level, only higher-level FORTRAN programming less efficient? Should it
interrupts can occur. provide special features that make a subroutine
The ZCI Z-BUS Component Interconnect provides The Z8000 archItecture prOVIdes ways to synchron-
the signal lines and protocols requ~red to tie Ize processes that share memory and those that do
members of the Z8000 family together and provides not. The Test and Set InstructlOn prOVIdes the
the necessary ~nterface spec~fication for family baSIS for synchronlZatlOn of processes that share
members st~ll to be developed. memory. For nonmemory synchromzatlOn, the Z-BUS
has a set of hnes and a protocol for resolving
An even wider environment for the CPU is defined s lmult aneou s req ues ts for shared resources, and
by the ZBI Z-BUS 8ackplane Interconnect, which the CPU provldes InstructlOns to support the bus
connectIon and protocol.
is compatible w~th the ZCI and prov~des for expan-
s~on of the Z8000 to a full 32-bit arch~tecture.
In the Z8000 I/O ~nstructmns are privileged, Context Switching in the 68000
while in the 68000 ordinary memory reference
~nstruct~ons double as I/O ~nstructions and There is very little d~fference between the Z8000
thus cannot be priv~leged. and the 68000 ~n their approaches to context
The Z8000 has one System Call (SC) instructIon switching.
with 8 programmable bits, while the 68000 has
16 separate System Call instruchons, none of
which has any programmable bits. The 68000 Ca.ponent Fllllily and Bus
The 68000 operating system designer is forced to The idea of a family of components des1gned to
use an external memory management system to imple- work together, wh~ch ~s so fundamental to the
ment the protection of I/O operations. The Z8000 Z8000 phllosophy, is not clearly eVIdent ~n the
operating system designer can work with pr~vileged 68000 des~gn. While the Z-BUS forms the framework
instruct10ns--a tool that 1S consistent with the for the entire, expanding Z8000 Family, the 68000
tools used for protection of other key ZBOOO func- seems to have been deSIgned with an eye toward
t~ons. (For a detailed dIscussion see the Z8000 compatibih ty with the older 6800 family per iph-
vs. 68000 concept paper "Memory-Mapped vs. erals and w~th existing bus structures.
Explic~ t I/O.)
While the Z8000 is designed to include features to
Ths second pOlnt boils down to the nunber of d~s facih tate its integration into a family of com-
hnct ~nstruchons available for system calls and ponents, the 68000 seems to have been designed
the number of separate traps over Wh1Ch these before there was a clear conception of what its
~nstructions are dIstributed. The 68000 architec- environment would be. For example, the Z8000 has
ture prov 1des for a total of 16 system calls and prov ision for memory management integrated ~nto
ties them all to separate traps. The Z8000 archi- the CPU; the 68000 memory management mechanIsm is
tecture provides for 256 system calls and ties entuely external to the CPU. The Z8000 has a
them all to one trap, so that dispatch software is nonmemory synchronization facility; no bus or
required to route the calls to the proper rou- processor prov~s~on for nonmemory synchronization
tines, but obv~ously, the Z8000 des~gn can accom- exists in the 68000. The ZBOOO was des1gned w~th
modate the add~ hon of a hardware dispatch a mult~plexed address/data bus to accommodate the
mechan~sm in the future with no change to user advanced programmable peripherals designed with
programs. Furthermore, the 68000 approach forces it; the 68000 was designed with a nonmultlplexed
dupl1cahon of context-saving operations (e.g., address/bus (See the Z8000 vs. 68000 Concept
reg~ster saVlng). Paper "Multiplexed vs. Non-Multiplexed Address/
Data Bus"). The ZBOOO was designed with block I/O
The key difference 1S that the Z8000 has 256 ins truct ions to fac~ li tate the message passing
System Call instructions, while the 68000 has only protocols to be used with the Universal Peripheral
16. The Z8000' s 256 calls will accommodate the Controller and, via the FIFO ~nterface, w~th other
procedure LISTINSER'l' (LISTeD, NEWBNTRY) 1 PRESENT.PREV .. 0 and NEW.KEY < PRESENT. KEY
'lithe notatIon POINTERe FIELD is used to access a then
part1cular field of the structure pOInted to by POINTER" It new list head It
Memory limitations surface nately, this trick only works because the records are
A major feature of the new 16-bit processors is their exactly 16 bytes long. Because the 8086 addressing
ability to address large memories. Unfortunately, many system internally multiplies each segment by 16,
of the benchmark programs were coded in a way that putting a record number in the segment register
limits them to a 64k-byte range; only the Motorola automatically points to the appropriate address.
68000 programs are truly usable over the machine's full Executing Quicksort for records of any other length,
addressing range. though, would require rewriting the Intel program.
The LSI-ll123 and Z8000 benchmarks assume a 64k Modification of this routine for general record lengths
data space, because they use only 16-bit addressing. would increase code size by an estimated 25% worst
For example, in Benchmark E, the character-string case (this also allows records extending over segment
search, neither of these machines can (with the coding boundaries) while affecting performance by no more
shown) deal with the case where the search substring than an estimated 5%. The performance degradation
and the data string are not in the same 64k space. In occurs only for segment-boundary checks, record-
that case, you'd require additional coding to handle the length incrementing through the array (rather than
segment information, necessary to extend the pro- segment-register incrementing) and segment-boundary
grams to the processor's full addressing range. transitions. The code expansion arises from segment-
In the same vein, the 8086 benchmark programs boundary-transition logic that's infrequently-if ever-
frequently assume that the calling program and the invoked.
subroutine share data and stack segments-an assump- Note that the Zilog benchmarks shown are coded for
tion that also limits the subroutine's addressing range. the Z8002 (unsegmented) version of the Z8000. On the
For example, the character-string-search Benchmark segmented (Z8001) version, these programs would be
(E) assumes that the string to be searched is in the virtually identical: Except for the I/O-interrupt-kernel
extra segment (ES). This must be the case to make the benchmarks, all of the programs use exactly the same
compare-string (CMPS) instruction work properly; if number of bytes for both devices. (The I/O-interrupt-
the string were not already in the extra segment, you kernel routines use direct addressing for some varia-
would need code to change the segment addressing. bles.) Execution times for the Z8001 benchmarks would
The 8086 coding of the Quicksort (Benchmark I) uses tend to be longer than the Z8002 times, though,
a clever trick involving the 8086 segment registers to because of such factors as
gain efficient indexing of the data records. Unfortu- 32-bit Load instructions for address moving
EDN APRIL 1, 1981 3-89
Tests attempt to measure fLPS, (or in Motorola's case, calculated). We do include data
not programmers' skills on the processors' clock rates, as well as on how the
timings were obtained. And we also performed spot
checks on the timing figures provided, using our
experience in working with these processors to ensure
More registers to save and restore that the times were reasonable.
The longer execution time of the RET instruction Execution times for the 8086-, Z8000- and 68000-
The longer time required for direct addressing. based single-board computers assume on-board mem-
ory-access operations. By contrast, results for the
What did we measure? LSI-1l/23 are based on the use of standard off-board
Two statistics are important in computer bench- dynamic-RAM systems and an asynchronous bus for
marks: program size and speed. A program's size is instruction and data transfers--a configuration dictat-
easy to measure-just add up the bytes. Our ground ing the use of processor Wait states, which slowed
rule in this regard was "If you placed the program in speeds somewhat. DEC points out, however, that the
ROM, how much ROM would be used?" We didn't count LSI-ll123's performance figures reflect the actual
stack space. (There are no local variables, because the operation of current board-level product offerings and
benchmarks are re-entrant.) that the data doesn't necessarily reflect a limitation of
Speed values, on the other hand, are very difficult to the board's processor chip set.
get a handle on: It seems that the chip makers produce Finally, note that we list the clock speeds of the
faster /LPS weekly. The memory you use can also affect fastest boards currently available; ie, we have lO-MHz
the execution speed, thanks to such factors as units from Intel and Motorola running in our lab.
dynamic-memory refresh. Therefore, because it wasn't However, we expect that the manufacturers will build
possible to obtain a consistent timing mechanism for all even faster machines in the future. For example, Zilog
of the benchmarks, the timing information provided is plans to introduce a lO-MHz version of the Z8000 within
merely what the programmers themselves measured the next 3 months. Because faster processors obviously
Benchmark I-Quicksort
The test data for this benchmark consists of 102 Note that only the key values (bytes 3 to 9 in each
(N=100) records, each 16 bytes long. Parameter M record) are significant. All data values are hexadeci-
is set to nine. The records are initialized as follows: mal bytes. As in the previous benchmarks, the
RecordO ---0000000000 00 00------ 68000 times are hand computations; the others are
Record 1 - - - FF 00 00 00 00 00 00 - - - - - - the results of program runs. No data is available for
Record2 ---FE 00 00 00 00 00 00------ the LSI-11/23 on this benchmark.
Record3 ---FD 00 00 00 00 00 00------ Proce8sor Clock Speed Code Bytes Execution
(MHz) Time (fJSIlC)
LSI-11 123 3.33
8086 10.00 347 115,669
68000 10.00 266 33,527
Record 100 - - - 9C 00 00 00 00 00 00 - - - - -- zeooo 6.00 386 115,500
Record 101 - - - FF FF FF FF FF FF FF - - - - - -
BENCHMARK A-LSI-11/23
1 TITLE. BlNCHMAHK A
2 .IDENT /OCT.221
3 .ENABL LC
4
5 110 IfliTERRUPT KERNEL, FOUR PRIORITY LEVELS
6
7 services interrupts trom four levels, prOduces a count of interrupts
8 by level.
9
10
11 The following "ASECT" or absolute program section will load up
12 tour 1nterrupt vectors.
13
14 000000 .ASECT ; absolute
15
16 000300 = 300
17 000300 000000' INTI
18 000302 000200 200 execute at priority 4
19
20 000302 = 302
21 000302 000006' INT2
22 000304 000240 240 I execute at priority 5
23
24 000304 = 304
25 000304 000014' IhT3
26 000306 000300 300 , execute at priority 6
27
28 000306 :: 306
29 000306 000022 ' INN
30 000310 000340 340 execute at priority 7
31
32 000000 .PSECT , relocatable
33
34 Hardware saves context: program counter and processor status.
35 Herawere masks out lower level interrupts.
36 Hardware vectors to one of the four interrupt service routines.
37 , Interrupt service routine increments counter.
38 RTI instruction re&tores procressor status and program counter,
39 , lower level interrupts are re-enabled.
40
41 Note: If ROMabl1lty was a requirement, this program would be four words
42 , longerl
43 I
44 000000 INTI.
45 000000 005227 INC (PC).
46 000002 000000 COUNTI. 0 Continued on pg 186
BENCHMARK A-Z8000
lExample AI I/O Interrupt Kernel, Four Priority Levels!
REASON := Rl
QUEPTR := R2 IRR2 for segmented
QUENXT :- REASON
ADRLEN ,- 2 ! 4 for segmented 1
JUMP :- ADRLEN +
ENTeFF E= ADRLEN
1 The four routines that follow are the processing routines for
the four priority levels. VIO is the highest priority routine,
VI3 the lowest. Each of these routines is reached in response
to an interrupt on the vectored interrupt (VI) line. Priority
resolution is through a hardware protocol def ined as part of the
Z8000 family architecture. Each of the four devices assumed to
be attached to the VI line places its own identifier on the bus
when it interrupts, and this identifier is used by the CPU for
automatic vectoring to the appropriate routine. The addresses
of the routines appear in the program status area (see below).
The flag/control word (FCW) value assembled into the PSA has the
vectored interrupt enable (VIE) bit set, so that each processing
routine is interruptible by other vectored interrupt devices.
The hardware interconnection protocol aSBures that interrupts
come only from higher priority devices.
I
BENCHMARK B-LSI-11/23
1 .TJTLE BENChMARK 8
2 .10ENT IOCT.221
3 .ENABL LC
4
5 1/0 INTERRUPT KlRNE.L, FifO PROCESSING
6
7 Services interrupts from four levels, using a fIfO queue ..
8 Each of the four devices has an interrupt vector set up as follows
9
10 .. = vector address
11 .WORD ROUTINE, 340
12
13 The vectored interrupt capability ot the LSI-ii hardware 1s used
14 here to implIcitly identify the device causln9 the interrupt.
15 Each interrupt wIll vector to a different service routine.
16 Hardware w111 save context (pr09ram counter - PC, and processor
17 , status'" PS) at the interrupt.
18
19 000000 .ASECT
20
21 Set up a vector for each device.
22
23 000300 = 300
24
25 000300 000000 ' DEVI new PC
26 000302 000340 340 new PS
27
28 000304 000006' DEV2
29 000306 000340 340
30
31 000310 000014' DEV]
32 000312 000340 340
33
34 000314 000022 ' DEV4
35 00031. 000340 340
36
37 Each device operates at priority seven (340 octal in the PS) to disable
38 other interrupts.
39
40 The queue contains e power of two number of words. It must be'lin on
41 an even multiple of the Queue size, such that for all addresses in
42 the queue, (address AfoID queue size) is zero, and (Queue start +
43 queue size) AND Queue size) 15 nonzero. QEND points to where the
44 next new entry w11l be made in the queue. QSTAR1' points to where the
45 next entry w111 be removed from the queue. When they pOint to the
46 same place, the queue is empty. _e assume the queue never overflows.
47
48 000000 .PSECT DATA
49
50 000040 QSIZE 40 sixteen elements
51 QUEUE: will be relocated to
52 address 1000 (8) at LINK tIme
53 000000 QUEUE: .BLKB QSIZE
54 000040 000000' QSTART: QUEUE
55 000042 000000 ' QEHD: QU'UE
56 000044 000000 RUNFLG: 0
57
58 000000 .PS~ C1 CLJDf
59
60 , lach of tne four devices nas an interrulJt routine as follows:
61
62 ;RCJUTINE.:
63 any immediate processing
64 CALL CClMMuN
65 ;CIR: .WORD 0
66
67 ; eTR is the counter that will be incremented by the fIfO processor.
68 ; In a real example, it would !:Ie the first instruction of the
69 ; interrupt service routine.
10 ;
11 000000 DEVI:
12 000000 0047.1 000024 CALL COM~ON
73 000004 000000 CrRI: wORD 0
74
75 000006 DEV2 :
76 000006 0047.7 000016 CALL COMMON
77 000012 000000 CTR2 : ORO 0
78
19 000014 DEV3, Continued on pg 200
BENCHMARK B-Z8000
! Example B: I/O Inter rupt Kernel, FIFO Processing J
0000 2DFI FIFO: EX REASON,@SP ISave the context!
0002 93F2 POSH @SP,QUEPTR ISave registers 1
0004 6102 LD QUEPTR,QUEIN !Queue the request
0006 OOOE'
OOOS 3321 LD QUEPTR(tENTOFF) ,REASON
OOOA 0002
OOOC 2121 LD QUENXT, @QUEPTR
OOOE 6FOI LD QUEIN,QUENXT ISet pointer to next slot
0010 OOOE'
0012 4C06 TSETB FLAG lean it be processed now?
0014 003e'
0016 E50C JR HI, RESTOR I No I
OOIS 7C06 LOOP: EI NVI lYes, let more happen 1
OOIA 3121 LD REASON,QUEPTR(tENTOFF) lSimulate proceSSing by
ODIC 0002
ODIE 6S10 INCB COUNTS(REASON) bumping count
0020 ODDS'
0022 7C02 DI NVI IDisable before dequeing
0024 2122 LD QUEPTR, @QUEPTR leheck on next I
0026 4B02 CP QUEPTR, QUE IN lAnythlng else in queue ? I
002S OOOE'
002A EEF6 JR NE,LOOP 1 Yes, do it I
002C 4COS CLRB FLAG I No, clear flag J
002E 003C'
0030 97F2 RESTOR: POI> QUEPTR,@SP 1Restore registers
0032 2DFl EX REASON,@SP
0034 7BOO IRET lAnd return
lCounters for FIFO interrupt processing!
ODDS COUNTS ar ray [5 byte 1
BENCHMARK E-Z8000
IExample E: Character Searchl
IArguments: 1
SRCHLNGTH _ RO lLength (In bytes) of SRCHSTRI
ARGLNGTH _ R1 !Length (In bytes) of SRCHARG I
SRCHSTR _ R2 IAddress of the strIng to be searchedl
SRCHOFF _ R2 !offset port1on of address I
SRCHARG _ R4 IAddress of str1ng soughtl
ARGDFF _ R4 JOffset port1on of address I
LOC _ R6 IReturn arg: char pOSItion ();O) or
FAILCDDE _ -1 I negative (FAILCODE) If no matchl
IWorkspace for the routIne: I
G - RH6 IFIrst char of sought strIng I
LCT ._ R7 !Substr1ng counter J
SCH ._ R8 IAddress reg1ster used WIth ARCHARGI
ARG ._ R10 [Address regIster used WIth SRCHARGJ
OFFSAVE ._ R12 !Remembers or1g1nal SRCHOFF value!
CT ._ R13 rCount (bytes in srch str1ng)!
WK1 - R7
NW1 - 7
0000 ABFD SEARCH: DEC SP, #2*NW1
0002 1CF9 LDM @SP,WK1,#NW1 ISave reg1sters used J
0004 0706
0006 A107 LD LCT, SRCHLNGTH ICompute number of substr1ngs I
0008 8317 SUB LCT, ARGLNGTH I long enough to match 1
BENCHMARK F-LSI-11/23
1 .TITLE BENCHMARK f
2 .IDENT /OCT.221
3 .ENABL LC
4
5 BI T TEST, SET, OR RESET
6
7 Find D bit, CheCk it, Change it, bash it, smash it
8
9 Assumes that bits are numbered from 0 from tne right-hand end ot a word.
10 Th1& 1s the way a PDP-ll views words. l..uCklly left-to-right ordering
11 "as- not a benchmark requirement 1 Arguments are passed on the stack..
12 Naturally, performance improvements could be made by passing tne arguments
13 in registers.
14 Stack offsets assume 4 bytes for saved reQisters:
15
16
17
000006
000010
f
N
10
function code
, relative bit number
18 000012 AI 12 address of bit string
19 000014 RC 14 address of return code _ord
20 000016 oORK I. not used
21
22 000000 ONTRACE
23 000000 BTSR
24 000000 01004. MOV RO, -(SP) save reg1sters
25 000002 010146 MOV Rl, -(SP)
26 000004 005076 0000\4 CL. iORC(bP) assume bi t is zero
'l7 000010 016600 000010 MOV N(SP), ~o HO = b1t offset
28 000014 042700 177770 BIC ."C<7>, NO HO = bit wit!')in byte
29 000020 012701 00000 I MOV .1, J( 1 kl = i
30 000024 072100 ASH ftO, Rl shift the 1 1n Hi lett RO times
31 000026 016600 000010 MOV N(SP), itO RO = bit offset
32 000032 072027 177775 ASH .-3, (0 RO = byte otfset into r"lt string
3J 000036 066600 000012 ADD Al(SP), KU RO -) the byte address
34 000042 130110 SnB kl, (fl:O) cheCK out the bit
35 000044 001402 Bfi'::Q lOS branch 1 f zero
36 000046 005276 000014 INC @HC(SP) else return code b@comes one
37 000052 026627 000006 000002 lOS: eMF F tSP), .2 1t functlon cOde i5 two,
38 000060 001002 8NE ~OS
39 000062 150\10 BISB kl, (kO) set tne oit
40 000064 000405 BR 30$
41
42 000066 026627 000006 UOOO03 20S. CMP f{!)P), .3 it function coae 1s three,
43 000074 001001 ~~E JO$
44 00007b 140110 tileS HI, (PO) clear the t-it
45 000100 012001 30S: MO\' restore r~~!st:rs
46 000102 012600 fIInll (SP)+, kO
47 000104 lJH'IkACt.: :
48 000 I 04 000207 kf.1UHt.
49
50
51 OOOUOI
BENCHMARK F-Z8000
IE ....ple p, Bit array manipulation routines I
IArgument.,
p
PL
....,. RO I Function code - po . . i~l. vaues are: 1
aLO
PH
TS'l'CODE ,.
,.
RHO
1 ITest the bitl
SETCODE
RESCODE
II ....,.,. 2
3
ISet the bit to 11
IReset the bit to 01
Rl IInclex (from lero) of desired bitl
Al
A10PP
RC ..
Illorkapece for the routine. I
R2 IAddre . . of bit array (RR2 for seg)
R2 IR3 for .egmented I
R3 IReturn arg' sat to value of cI.dred bitl
BENCHMARK H-Z8000
IElample H: Insertion in a Doubly Linked listl
(Format of an entry
KEYF := 0 IKey portion of entry I
LICE! ._ 4 I Number of bytes 1 n a key I
NEXTF : = LICEY IPointer to "next" entry I
PREYF := NEXTF+AOLEN IPointer to "previous" entry.
IWorking storage for routine: I
KEY := RRO
PTRS := R2 IFirst of registers for NEXT and PREYI
NUTAO := R2 (RR2 for segmented) I
PREYAO := R3 I (RR4 for segmented)1
NPTRS : = AOLEN IRegisters in the block (2*AOLEN/2) I
NUM := R4 I "Number of entries from LISTCB I
I (R6 for segmented) I
WK3 := HO
NW3 := MPTHS+3
0000 ABF9 LISTINI DEC SP,I2*NW3
0002 1CF9 LOM @SP,WK3,INW3 ISave registers used I
0004 0004
0006 14!0 LOL ICEY,@NEWENTRY IGet the new entry' 8 key
0008 31C4 LO NUM,LISTCB(lNUMF) I Count the new entry 1
OOOA 0004
OOOC 1940 INC NUM
OOOE 33C4 LO LISTCB(lNUMF), NUM
0010 0004
0012 B030 LOK PREYAO,IO IZap PBEYAO pOinter I
0014 OB04 CP NUM,I1 IFirst entry?1
0016 0001
0018 EEOS JR NE, NOTFRST no - go scan list I
001A B020 LOK KEITAO, '0 1 yes - zap Itnext ptr I
001C 2FC! LO @LISTCB,NEWENTRY ISet LISTCB "head" ptrl
001 E 33C! LO LISTCB( #TAILF), NEWENTRY ISet LISTCB "tail" ptr I
0020 0002
0022 E817 JR UPIIEW IUpdate new entry's ptrs
0024 21C2 NOTFRST: LO NEX!!D,@LISTCB Unit -next- for scanl
0026 1020 SCANLP: CPL KEY,@NEXTAO I Compare key s I
0028 E906 JR GE, TRYNEIT I not the place I
002A 8034 TEST PREYAO IInsert here. Head?1
002C EEOE JR NZ,UPMIO I no - update and exit
002E 2FC! LO @LISTCB,NEWENTRY I yes - adjust LISTCBI
0030 332A LO NEXTAO(lPREYF), NEWENTRY IUpdate prev's "next-.
0032 0006
0034 E80E JR UPNEW lUpdate new entry's ptrs
0036 A123 TRYNEXT:LO PREVAO,NEXTAO IN. . t in list I
0038 3132 LO NEXTAD, PREYAO(tNEXTF)
003A 0004
003C 8024 TEST NEXTAO INew tail?1
003E EEF3 JR NZ,SCANLP I no - keep looking I
0040 333A LO PR EVAO (lNEXTF) , NEW ENTRY I yes - set prevs "nxt a
0042 0004
0044 33CA LO LISTCB(#TAILF), NEWENTRY ISet LISTCB "tail" ptrl
0046 0002
0048 E804 JR UPNEW IUpdate new entry's ptrs
004A 332A UPMID: LD NEXTAD{#PREVF) ,NEVENTRY IUpd.ate next' ~ prev!
004C 0006
004E 333A LO PHEYAO(#NEXTF),NEWENTRY IUpdate prev's -next".
0050 0004
0052 A9A3 UPNEW: INC NEWENTRY,ILKEY IWri te entry pointer I
0054 1CA9 LOM @NEWENTRY,PTRS,INPTRS
0056 0201
0058 1 CF1 LOM WK3,@SP,'NW3
005A 0004
OOSC A9F9 INC SP,I2*NW3 lRestore registers J
005E 9E08 RET
BENCHMARK I-Z8000
fExample I: Quicksort/Insertion Sort I
IArguments I
N .- RO I Number of records
H : = Rl f Changeover point
REC := RR2 fArray base I
RECOFF := R3
RECSEG := RH2
IWorking registers I
SCRL : = RRO I Sera teh borrowed from argument registers I
SCRl _ HO
SCR2 ._ Rl
BIGH _ SCRL
AOR := RR4; ADRHH ._ RH4; ADRHL .- RL4; ADRL := R5
I
J
:= RR6; IHI
._ RR8; JHI
R6 ; ILO
R8 ; JLO
.-.- R?R9
L ._ RR10;LHI := R10; LLO := Rl1
U ._ RR12;UHI : = R12; ULO .- R13
ITAD := AORL IAddress of I-item
IOther constants I
ESIZE ._ 16 IByt per record I
KEYOFF :: 3 IIndex in record of first byte of key I
KEYBYTES:: 7 IBytes per key I
0000 ABFF SORT: DEC SP, #16
0002 ABFB DEC SP,112
0004 1 CF9 LDM @SP,RO,#14 ISave all registers
0006 OOOD
0008 Al0D LD ULO, N INumber of records I
OOOA B1CA EXTS U
OOOC 190C HULT U,IESIZE JMult by size of records
OOOE 0010
0010 140A LDL L,IO IZero lower limit to start
0012 0000
0014 0000
0016 91FC PUSHL @SP,U
0018 1900 HULT BIGH,IESIZE IAdjust cutoff for record size
001A 0010
001C 91FO PUSHL @SP,BIGM
001 E DFB7 CALR QUICK
0020 95FO POPL BIGH,@SP
0022 95F6 POPL I,@SP
0024 1206 SUBL I,#ESIZE
0026 0000
0028 0010
002A 9464 INSORT: LDL ADR,I
002C 1604 ADDL ADR, IESIZE
002E 0000
0030 0010
I CALR ADCOMP I
0032 8135 ADD ADRL, RECOH
0034 1604 ADDL ADR, IKEYOFF
0036 0000
0038 0003
003A 9440 LDL PIVOT, ADR IPIVOT i. adr of key of A(I+1)
003C DF7D CALR CPPI
003E EF2F JR UGE, ENOl IIf A(I+l):A(I), end block I
0040 ABH DEC SP, IESIZE
0042 8D08 CLR PIVHI
0044 A1Fl LD PIVLO, SP IPIVLO has adr of V on stack
0040 1600 ADDL PIVOT, #KEYOFF I PIVOT point. to key in V I
0048 0000
OOH 0003
004C A1FB LD DEST, SP
004 E 9464 LDL ADR,I
I CALR ADCOMP I IADRL is source address
0050 8135 ADD ADRL, RECOFF
0052 BDA8 LDK Rl0,#(ESIZE/2)
0054 BB51 LDIR @DEST,@SRCE, Rl 0 ISave a(l) on stack I
0056 OABO
0058 9468 LDL J, I
005A 1608 ADDL J,IESIZE IJ : I + 1
005C 0000
005E 0010
0060 9484 AGN2: LDL ADR,J
0062 1204 SUBL ADR, IESIZE IADR J - 1
0064 0000
0066 0010
I CALR ADCOHP I
006~ 8135
006A 94H tgr t~!~h RECOH IL addre of A(J-l) I
006C 9484 LDL ADR,J
ICALR ADCOMPI
006E 8135 ADD ADRL, RECOFF
0070 BDA8 LDK Rl0,#(ESIZE/2)
0072 8B51 LDIR @DEST,@SRCE,Rl0 IA(J-1) : A(J)
0074 OABO
007.6 1608 ADDL J,IESIZE IJ : J + 1
0078 0000
007A 0010
007C DF9B CALR CPPJ
001 E401 JR OV, ENDLAST
0080 EFEF JR UGE, AGN2
0082 9484 ENDLAST :LDL ADR, J
0084 1204 SUBL ADR,IESIZE IADR J - 1
0086 0000
0088 0010
I CALR ADCOMP I
008A 8135 ADD ADRL,RECOFF
008C 944A LDL L, ADR
008E 9404 LDL ADR, PIVOT
0090 1204 SUBL ADR, #KEYOH IADR address of V again I
0092 0000
0094 0003
0096 BDA8 LDK Rl0,#(ESIZE/2)
0098 BB51 LDIR @DEST,@SRCE, Rl0 IA(J-1) V
3-100
EDN APRIL 1, 1981
BENCHMARK I-Z8000
009A OABO
009C A9FF INC SP,IESIZE
009E 1206 ENOl. SUBL I, IESIZE
OOAO 0000
0012 0010
00A4 9C68 TESTL I
LD~RRg~I!~~~m
00A6 EECI
00A8 1 CFl
OOAA OOOD
OOAC A9FF INC SP,II6
OOAE A9FB INC SP,II2 IRestore registers
OOBO 9E08 RET
ISubroutine Quicksort - after C. A. R. Hoare
CALL QUICK wi th BASE = array address
U = offset of upper limit
L = offset of lower 11mi t
Semi-sorts e1 ements at offsets between Land U (inol usi ve).
The 23-bit integers Land U are in the range 0 to 8,388,607.
I
0082 94C4 QUICK. LDL ADR, U
0011'1 92A4 SUBL ADR,L Icompute subfile size
00B6 9004 CPL ADR,BIGH
00B8 9E02 RET LE IReturn i f subfile is <= H long I
OOBA 91FO PUSHL @SP,BIGH
r Partition array segment between offsets Land U (inclusive)
around a pivot element with index J. Returns the ranges:
eL,J-l) in L,U
eJ+l,U) in I,J
I
OOBC 94A4 PART. IADR = L I
IADR = actual address of aeL) I
OOBE 8135
OOCO 1604 ladd in offset of key within record
00C2 0000
00C4 0003
00C6 9440 LDL PIVOT,ADR IPIVOT = actual address of pivot I
00c8 9416 LDL I,L
OOCA 94C8 LDL J, U
OOCC 1608 !DDL J, IESIZE IJ = J+l
OOCE 0000
OODO 0010
00D2 91FA PUSHL @SP,L
0004 91FC PUSRL @SP,U ISAVE L,U I
0006 DF07 LPII CALR UPI IInc I until aeI) >= pivot valuel
00D8 DFOI CALR DOWNJ IDeo J until aeJ) =< pivot value or J=<I
OOOA 9484 LDL ADR, J
I CALR ADCOHP I
OODC 8135 ADD ADRL, RECOFF
OODE 944A LDL L,AOR IL = aotual address of aeJ) I
OOEO 9068 CPL J, I ICompare J and I I
00E2 E202 JR LE, HOVPIV IJ <= I, exchange aeJ) and pivot
00E4 DFC5 CALR EXCHIJ IExohange aeI) and aeJ) valuesl
00E6 E8F7 JR LPI
00E8 DFC4 HOVPIV. CALR EXCHJP IExohange aU) and pivot valuesl
OOE! 95FC POPL U,@SP
OOEC 95FA POPL L,@SP IRestore L, U
OOEE 9486 LDL I,J IPut in RR4 I
OOFO 94C8 LDL J, U IPut U in RR6 I
00F2 946C LDL U,I ICopy of J into U alsol
00F4 120C SUBL U,IESIZE I L,U eL,J-1)
00F6 0000
00F8 0010
OOFA 1606 ADDL I,IESIZE I,J
OOFC 0000
OOFE 0010
I Put shorter range in LtU, longer in I,d I
0100 9480 SHORT. LDL SCRL,J ISCRL = U-L for first rangel
0102 9260 SUBL SCRL,I
0104 9404 LDL ADR, SCRL ISave first U-L I
0106 94CO LDL SCRL,U ISCRL = U-L for second range I
010H 92AO SUBL SCRL,L
010A 9040 CPL SCRL,ADR ICompare lengthsl
010C 204 JR LE,Ql IDone if second U-L =< first U-L
010E ADA6 EX IHI,LHI
0110 ADB7 EX ILO,LLO
0112 ADC8 EX JHI,UHI
0114 ADD9 EX JLO,ULO
0116 95FO Ql , POPL BIGH,@SP
0118 ABFT DEC SPOFF, 18 ISave I,J = longer e L, U) range I
01U lCF9 I.DM 'SP, IHI, 14
011C 0603
011E 0037 CALR QUICK IRecursive call to sort shorter range I
0120 lCFl LDM LHI,'SP,14 'Restore longer range into L,D I
0122 OA03
0124 A9F7 INC SPOFF,18
0126 D03B CALR QUICK IRecursive call to sort longer range I
0128 9E08 RET
~~~~-~------- ----~-
BENCHMARK I-Z8000
012C 0000
012E 0010
0130 DF" CALR CPPI ICOIIIpare pivot value with a(Ili
0132 9E04 RET OY lOY = 1 says pivot aU) = I
Q134 9EOT RET ULT IReturn if pivot value =< aU) I
0136 E8F9 JR UPI
0138 1208 DOWRJ: SUBL J ,IESIZ E IDecr . . ent J I
'013A 0000
013C 0010
013E DFFC CALR CPPJ
0140 9EOF RET UGE IReturn i f pivot >= A(J) I
0142 E8FA JR DOWRJ
IPlvot and exchange subroutines
CALL CPPI - cOlllpare pivot v.lue and .(0. Set FLAGS.
CALL EXCHJP - . .change a(J) and pivot value.
CALL EXCHIJ - elohange a(I) and a(J) valu
Regiater use I 8S for PART
U scratch
ADR calling arg for and addreas returned by &DCO"P
~ actual address of a(J) for exchange routines.
BENCHMARK K-LSI-11/23
1 .TITLL BENCHMARK
2 .IDENT IOCT.2ll
3 .ENUL LC
4
5 BOOLEAN MATRIX TRANSPOS~
6
7 Transpole a tightly-packed bit matrix
8
9 Arguments are passed on the stack.
10 Offsets assume 14(8) bytes used for saving registers on stack.
11
12 000016 N 16 lize of matrix
1~ 000020 AI 20 pointer to a word of storage
14 000022 A2 22 b1 t offset of _tart of matr 1x
15
16 000000 ONTRACE. :
17 000000 8NTI;
Ii
19 save reg1sters
20
21 000000 010046 MOV RO, -(SP)
22 000002 010146 MOV Rl, -(SP)
23 000004 010246 MOV R2, -(SP)
24 000006 010346 MOV R3, -(SP)
25 000010 010446 MOV R4, -(SP)
26 000012 010546 MOV R5, -(SP)
27 Continued on pg 256
73
74 90900044 4COF0738 MOVEM.L (SP) +,03-05/A9-A2 RESTORE REGISTERS
75 00999048 4E75 RTS RETURN TO CALLER
76
77 END
BENCHMARK K-Z8000
lExample K: Boolean Matrix TransposeJ
IArguments: I
NX := RO JDimension of Matrix!
A2 := Rl IBit (0<=A2<-15) at which matrix begins in All
AIX := R2 IAddress of first word of Matrixl
~------- ---~-"~--
------------------
Architectural Concepts
for Microprocessor
Peripheral Families
~
Zilog Concept Paper
December 1980
Some fundamental constraints on micro- combinations, and can be used to link mul-
processor peripheral families have always tiple local buses to a main system bus at
existed, but some of the more severe con- high speed and with little overhead.
straints In the present 16-blt environment
will be worse In future 32-blt environments. Local buses are, In general, a very effec-
One of these restrictions Is the number of tive way to Improve overal I system per-
signal lines avallable--usually correspond- formance. They allow significant paral lei
Ing to the number of pins on a package. processing to occur and can Improve system
Present packaging technology for mass- reliability by partitioning the tasks to
produced parts al lows up to 64 pins, which make Interference between processes less
Is sufficient for a 16-blt microprocessor likely. Many of the problems with linking
with an unmultlplexed address/data bus or a multiple buses can be avoided by adding
32-blt microprocessor with a multiplexed buffer memory between the buses. In many of
address/data bus. Unfortunately, control of the new-generation I/O devices, this buffer
these wide buses uses most of the pins memory can be Included on the Integrated
available with current packaging, so any circuit Itself.
device controlling the bus cannot have a
wide, Independent data path. An example of the power of these techniques
Is the construction of a high-speed
The key word here Is "Independent." It Is para I lei/serial front-end processor for a
certainly possible to design a device that high-end microcomputer system (Figure I).
could operate a local bus and, when neces-
sary, switch modes to control a global bus.
This mode of operation for multiple The key element In this system Is the Z8038
processor-type devices Is Inferior for FlO (FIFO Input/Output) device. This Is a
several reasons. First, when the buses are 128x8 FIFO buffer that has the necessary
linked, other processes experience longer Intelligence and flexibility to Interface to
delays In being serviced. Second, an archi- a wide variety of microprocessors. It also
tecture that al lows multiple-processor has the ability to Interrupt under a variety
devices access to most memory In the system of conditions and can bypass the data FIFO
Is a difficult one In which to assure data by a separate path to pass control and
and system Integrity. A third difficulty Is status Information from one processor to
anOTher.
simply the number of devices necessary to
link the buses. Typical Implementations Information Is passed from one processor TO
require six to eight packages. the other on a message basis. A typical
transfer begins with the main sysTem
A significant observation Is that the only processor sending a control byTe through the
commercially available I/O devices that FlO to the local processor via the bypass
Incorporate a DMA-type function are serial regiSTer. This control communication typi-
Input/output devices and CRT controllers. cally Includes InformaTion about the daTa
Only these applications allow enough pins to block lengTh, the Intended destination, and
properly Implement the DMA function. any OTher relevant parameters. At the same
time, The main system DMA can be set up to
Fortunately, the same technology that begin transferlng data Into the FlO. Either
enables the Integration of 16- and 32-blt of the two DMA controllers In This system
microprocessors also allows the Integration can be eliminated with little loss in per-
of considerable Intelligence and some buffer formance If the CPU has block memorY-To-l/O
memory In the peripheral device. This Is a move Instructions available, as In The Z80
very powerful combination, especially In or Z8000. AfTer Initial setup of the FlO,
conjunction with highly Integrated CPU/DMA the main sysTem DMA Is activated and quickly
3105 11/12/80
fIlls the FlO's data buffer, If the local data through the FlO. If the Interrupt
system DMA has not yet been actIvated. ThIs routIne Is short, the other system may not
Is of lIttle consequence, sInce the maIn even notIce that the FlO was not beIng
system DMA wIll sImply stop transfers when servIced for a short Interval. If the
the ROY sIgnal from the FlO goes InactIve. Interrupt Is longer, the fact that the FIFO
SImIlarly, If a block move InstructIon Is may go empty Is of lIttle consequence. An
beIng used Instead of a OMA, the FlO Interrupt on empty or an InactIve ROY lIne
provIdes an "Interrupt-on-full" Interrupt, wIll serve to temporarIly suspend servIce of
WhIch allows the CPU to do other tasks untIl the FlO at the local end.
next Interrupted by the FlO. ThIs second
Interrupt occurs only when the contents of
the FlO have been emptIed to a predetermIned The FlO Is suffIcIently flexIble to Inter-
programmable level. face In four dIstInct applIcatIons:
To a multIplexed address/data bus mIcro-
processor.
SImIlarly, on the local bus sIde of the FlO, To an unmultlplexed address/data bus
the DMA wIll be actIve only when there Is mIcroprocessor.
data remaInIng In the FlO. To reduce the WIth handshake lInes to most types of
number of bus' request cycles (or Interrupts paral leI-Interface I/O devIces.
In the case of a block move InstructIon), As a "hIgh byte portIon" of a 16- or
the FlO can be programmed to request servIce 32-blt lInk between buses.
from the local OMA only when the FIFO con-
taIns more than a certaIn programmable
number of bytes. It wll I then transfer FIgure 1 also shows the use of the FlO in
untIl the FIFO Is empty and contInue thIs a handshake applIcatIon. One of the prInci-
burst cyclIng untIl the end of the block. pal advantages of the FlO in this configur-
ation is its ability to decrease interrupt
The combInatIon of the block move Instruc- handling overhead by more than two orders of
tIons and the FlO Is more powerful than the magnitude, compared to the typical Interrupt
replacement of the OMA functIon. UnlIke the hand II ng with a para I leI 1/0 dey ice. For
OMA, whIch, by requestIng the system bus, example, If interfaced to a line prInter,
places Itself at a hIgher prIorIty than any the CPU wou Id be i nterru pted once per II ne
Interrupt In the system, the block move rather than once per character. Another
InstructIons can be Interrupted. ThIs means capabIlIty of the FlO is its abIlIty to
that a hIgh-prIorIty Interrupt In eIther the recognize special characters (or bIts in a
local system or the maIn system can be character). It can interrupt or stop OMA
servIced ImmedIately, even though the CPU Is transfers when a specIal character comes
Involved In a very hIgh speed transfer of through the FIFO, such as End of File.
ACK
MAIN
MEMORY
ACK
8IDIRECTIONAL
} HIGH SPEED
PARALLEL
PORT
7;1",.
Zilog
Interfacing to the
Z6132 Intelligent MelDory
~
Zilog Application Note
April 1981
Introduction In memory applIcations where the requIre- that mIght be useful are referenced throughout
ments for byte-wIde buffer storage are modest the applIcalIon note.
(2K to 32K bytes), the 26132 offers a new con- The applIcatIon note is dIvIded Into four sec-
cept In Intelligent memory. The 26132 features tions. The Irst section provIdes a general
4K bytes of RAM in a byte-wIde, 28-pIn descnplIon of the 26132 along with funclIonal
package that conforms to the 2716/2732 JEDEC descriptions of each avaIlable type of memory
standard. operation. The self-refresh operallon IS
ThIs application note dIscusses the basIc dIscussed WIth the various refresh options
features and operatIng modes of the 26132, avaIlable WIth the 26132. The second sectIon
WIth applIcation examples gIven for each of begIns the application examples by provIdIng
2ilog's mICroprocessors. In addition to a interface CIrcuitry for the 280A CPU. The third
discussIOn of the Interface requIrements for the and fourth sectIons prOVIde interface circuitry
28, zao and 28000 CPUs, an applIcation and timIng for the 28002 and 28 mIcro-
example describes the desIgn requIrements for processors. The section that dIscusses the 28
interchangIng the 26132 WIth 2716/2732-type memory Interface also treats the deSIgn criterIa
EPROMs. Each interface desIgn Includes logic for interchangIng the 26132 WIth either 2716-
and tImIng dIagrams. Other 2110g documents or 2732-type EPROMs.
General The 2110g 26132 IS a +5 V, IntellIgent, MOS compallble with the proposed JEDEC standard.
Description dynamic RAM organIzed Into 4096 8-bit words. The 26132 conforms with the 2-BUS specifica-
of the Z6132 The 26132 uses high-performance, depletion- lIon used by the new generation of 2110g
load, double-poly, n-channel, SIlIcon-gate mICroprocessors, the 28 and 28000.
MOS technology WIth a mixture of static and The 26132 4K x 8 quasl-stallc RAM is
dynamIC cIrcUItry that provides a small organIzed as two separate memory-bIt blocks.
memory cell and low power consumplIon. Each block has 128 sense amplIIers WIth 64
Internally, the 26132 uses dynamIC storage rows of memory bIts on each SIde. Both blocks
cells, but externally, the 26132 functions as a have separate row address buffers and
statIc RAM because It controls and performs ItS decoders. The two sets of row address.
own refresh. This elimInates the need for exter- decoders are addressed either by the address
nal refresh support cIrcuItry and combines the inputs AJ-A7 or by the Internal 7-bit refresh
convenience of a static RAM WIth the hIgh counter. The least signiIcant address input
density and low power consumption normally (Ao) selects one of the two blocks for external
assocIated WIth dynamic RAMs. access. While the selected block performs a
The 26132 is partIcularly well SUIted for read or write opera lIon , the other memory
mICroprocessor and mInIComputer applIcations block uses the refresh counter address to
where its byte-WIde organIzation, self-refresh, refresh one row. Details of the self-refresh
and SIngle power-supply voltage result in a mechanIsm are discussed In the next section.
reduced parts count and a slmplIIed design. A memory cycle starts when the rising edge
The 26132 supports both multiplexed and non- of Address Clock (AC) clocks in Chip Select
multIplexed address and data lInes using the (CS), Ao, and WrIte Enable (WE). If the chip
control ~nals Address Strobe (AS) and Data is not selected (CS is HIgh), all other Inputs
Strobe (DS) to latch address and data internal are ignored unlIl the next riSIng edge of AC. If
to the memorychlp. The circuit IS packaged in the chIp is selected (CS is Low), the 12
an Industry-standard, 28-pIn DIP and IS PIn address bits and the WrIte Enable bit are
4-3
General clocked Into their respective internal registers. on the DS input activates the data outputs after
Description The block addressed by AI-All is determined ~eclfied delay. During a read operation,
of the Z6132 by Ao; the other block is refreshed by the 7-bit DS is only a static Output Enable signal.
(Continued) refresh counter. Write cycle is initiated by the riSing ed~of
The Chip Select and address inputs must be AC while both CS and WE are Low. The WE
held valid for only a short time after the rising '!!!put is checked again on the falling edge of
edge of AC. This supports the multiplexing of DS. If WE is still Low, the falling edge of DS
address and data and allows enough setup time strobes the data on the Do-D7 inputs into the
for the multiplexed data lines to settle with addressed memory location. Data must be
respect to the input control signal Data Strobe. valid for only a short hold time after the falling
A read cycle is initiated brthe rising edge edge of DS.
of AC while CS is Low and WE is High. A Low
REFRESH
.-
ADDRESS
COUNTER II. .
INPUT
ADDRESS
ROW
DECODER
(10F128t
MEMORY ARRAY
IIUX
INPUT
ADIIIIEII8
D~D I-
~J1i.~.~EN~.E~~~PU~F~IE~~=}-l---------1
(10f'12111
BUFFE~
MEMORY ARRAY
Self-Refresh The 26132 stores data in a single-transistor mode consists of a memory operation followed
Operation dynamiC cells that must be refreshed at least by a refresh operation on both blocks, after
every 2 ms. Each of the two memory blocks which the refresh counter is incremented.
contains 16,384 cells and requires 128 refresh Internally, the complete cycle consists of a
cycles to completely refresh the array. The four-phase sequence:
26132 operates in one of two user-selectable 1. Memory read, write, or write inhibit
self-refresh modes, each satisfying the refresh 2. Precharge
time requirements. On the basis of the 3. Refresh
available memory cycle time, the user can 4. Precharge
decide to use either the Long Cycle-Time
Refresh mode or the Short Cycle-Time Refresh These internal operations are automatic and
mode. The Long Cycle-Time Refresh mode is transparent to the user. When the chip is not
the simplest self-refresh mode and is enabled selected (CS is High when AC goes High), the
by permanently grounding the BUSY output first two phases are omitted. There are two
pin of the 26132. Every memory cycle in thiS important requirements: the memory cycle
4-4 2028-148
Self-Refresh times must always be longer than the TC cycle. Hence, the addressing of PROM or I/O
Operation (mimmum memory cycle time) value speCIfied can also be used to refresh the Z6132 by allow-
(Continued) when BUSY is Low, and there must be at least mg It to receive Address Clocks wIthout Chip
128 Address Clocks in any 2 ms period. Select.
The Long Cycle-Time Refresh mode is most Under normal conditions, the deselected and
practical for microprocessor applications odd/even self-refresh mechamsms step through
where the read and write cycle times are in the 128 refresh addresses m less than 2 ms. To
range of 650-750 ns. The Short Cycle-TIme guarantee proper refresh operahon, even in
Refresh mode is a more sophIsticated self- the exceptional case of the memory bemg con-
refresh mode that is activated by pulling the tmually selected and addressed by a long
BUSY output pin High through a pul~ string of all even or all odd addresses, a bUIlt-
resistor (typically I kO) to Vee. The BUSYout- in cycle counter activates the BUSY output and
puts of several Z6132 chips can be OR-wIred requests a lengthened memory cycle to append
together. In this mode, the Z6132 always per- a refresh operation. ThIs mternal cycle counter
forms a refresh operation on the memory block IS reset whenever the refresh counter is incre-
that is not being addressed from the outside. mented. The cycle counter then counts
If the chIp is selected (CS is Low when AC memory cycles and activates the BUSY output
goes High), the refresh counter refreshes the when it reaches a count of 17.
block that is not addressed by A<J. The refresh BUSY is fed mto the WAIT input of most
counter is incremented after both an even and mICroprocessors and IS a request to the CPU
an odd address have occurred. This self- for a longer memory cycle. The BUSY line IS
refresh scheme takes advantage of the sequen- held Low by the Z6132 until the refresh cycle
tial nature of most memory addressing. If the has started. BUSY becomes active only when
chIp is deselected (CS is High when AC goes the Z6132 has been selected and addressed
HIgh), both blocks are refreshed and the wIth all odd or all even addresses for 17 con-
refresh counter is mcremented after every secutive Address Clocks.
Interfacing The Z6132 was designed to interface with address stable time (! 10 ns in TI), the max-
the Z6132 to Z-BUSTM-compatible microporcessors such as imum access time available for a memory fetch
the Z80A CPU the Z8 and Z8000. Although the Z80 does not is reduced to 355 ns.
directly produce Z-BUS-compatible memory To keep the interface logIC for the Z6132 to a
signals, only three commonly available inte- minimum and still use commonly avaIlable
grated circuits are required to interface the parts, the Z6132-5 (300 ns access time) is
Z6132 with the Z80A CPU. The interface logic, exemplified. Timing edges prOVided by the
circuit description, and timing diagrams for Z80A CPU clock are used to activate the Z6132
each important processor cycle are dIscussed Address Clock (signal AC shown in Figures 2,
later. Further information on the Z6132 and 3, 4, and 5). Figure 7 shows the logic for the
Z80A CPU can be obtained from the Z6132 zaOA-to-Z6132 interface. The 74S00 NAND
Product SpeCification (document number gate has a maximum delay of 5 ns, the 74LS04
00-2028-A) and the Z80B CPU AC mverter has a maximum delay of 15 ns, and
Characteristics (document number 00-2005-A). the 74S74 has a maxImum clock to output
The Ml or opcode fetch cycle of the Z80A delay of 9 ns. The clear-to-Q output Low delay
CPU represents the shortest memory cycle and is 8 ns for the 74S74. These numbers are
must be given careful consideration when displayed in the timing d~rams l2!:. the Z6132
designing memory interface logic. Figure 2 control signals CS, AC, DS, and WE
shows the Z80A CPU Ml cycle in detail along (FIgures 2-6).
with worst-case delay timings for the important The following description of a memory fetch
control signals. The maximum access time cycle illustrates how each of the important
allowed for an opcode fetch (under ideal con- Z6132 timing parameters is met. The Ml cycle
ditions) is 500 ns in clock cycles TI and T2. begins with the activation of Z80A CPU control
Considering worst-case zaOA CPU data setup signal Ml in clock cycle TI. Since the max-
time (35 ns in T2) and worst-case opcode imum delay for Ml is 100 ns (Figure 2) and the
4-5
Interfacing maximum delay from the rising edge of T I As a reminder, the MI machine cycle is a
the Z6132 to until addresses are stable is 110 ns, the control 2-clock-cycle instruction fetch, which requires
the Z80A CPU path that gates MI and CLK to clear the 74S74 the data fetched to meet the specified setup
(Continued) flip-flop is used to force AC High. time (35 ns) before the rising edge of clock
The delay of 33 ns shown in Figure 2 for AC cycle T3. With 35 ns required for worst-case
from the falling edge of T I was derived from data setup time, the remaining time in TI and
the collective delays of the 74LS04 (15 ns), the T2 for memory access is:
74S00 (5 ns), the 74S74 clear (8 ns), and the 500 ns - (158 ns + 35 ns) = 307 ns
final 74S00 gate (5 ns). Thus, under the worst
conditions possible, a memory cycle begins This allows the use of 300 ns access time RAMs
with the rising edge of AC 158 ns after the even under worst-case conditions.
rising edge of clock cycle TI. The Z6132-5 has a guaranteed access time of
T, T, T,
CLOCK
I I I I
-4---100----'1 -4---100----'j
I I
_85_1~"o~1
220
1_85_1 1_ ----:1
85
I I I I I I
1_.5_1 --------85~1
I I I
""'--110-----+-1 -4---110 ------'1
ADDRESS I PC ADDRESS STABLE I REFRESH ADDRESS STABLE
DATA
I
_I 1__ '5 1..,..- -4----110 -----+-\
II
OPCODE
DATA SETU~ TIME I REFRESH CHIP SELECT (IGNORED)
........1.....-111+-..1~1
14 33
307 . 1_. _1
0
AC
I I I I I
1~115- ~I ....---105 ------+-1
I I I
-+----105~1 .......--105----1
I I
NOTE:
Two walt states automahcally mserted here
by CPU. Each walt state IS one clock cycle long.
2102-001
4-6
Interfacing 300 ns and is recommended for use with the cycle Ml generates an MREQ signal that
the Z6132 to 280A CPU to simplify interface circuitry. This violates the AC timing requirements of the
the Z80A CPU mode takes advantage of the self-refresh 26132. The second purpose of the 74S74 is
(Continued) feature of the 26132 so that interfacing the realized during an interrupt acknowledge
280A CPU refresh control signals is not cycle. The 280A CPU uses the simultaneous
required. occurrence of Ml active with IORQ active to
The 74S74 flip-flop IS useful for two reasons. indicate that an interrupt acknowledge cycle is
The 280A CPU refresh cycle, with its accom- in progress. If the 74S74 flip-flop is removed,
panying MREQ, is effectively blocked by the the Address Clock becomes active during
74S74 during an Ml cycle. This is required every clock cycle time (425 ns) for the
because the refresh cycle during machine 26132-5. Figure 3 illustrates memory timmg for
T,
CLOCK
I I I
1_85~1 1_85~1
I I I I
1_. _1 5 1_85_1
I I I I
1_.0__1 1_80_1
I I I I
""'-110---+-1
ADDRESS
I MEMORY ADDRESS STABLE
1-+-- 150 -
-I I~I
DATA
I I WRITE DATA VALID
I I
__I 1_ 15
READ
DATA SETUP TIME
II
1.... 14
1_.0_1
AC
I I
1_"5 -_1 1--- '05 ----1 I
iii
READ I I r 1
1_'00 ----0 I 1_'00 ----0 I
iii
WRITE I I
1"-100--"1
WE
READ I I
Figure 3. Z8DA Memory Cycle Timing
2102-002 4-7
Interfacing the Z80A CPU memory read or write cycle. In other memory control signals (such as CS and
the Z6132 to this cycle, MREQ is issued by the Z80A CPU to DS) do not affect operation of the Z6132.
the Z80A CPU imtiate a memory operation. The Z80A CPU Figure 5 shows a Z80A CPU interrupt
(Continued) control signals, MREQ and RD, closely track acknowledge cycle. Although AC makes a
each other over the guaranteed temperature positive transItion and CS could be true
range. Were this not the case, DS could poten- (depending on the Z80A CPU's current PC),
tially become active before AC becomes true. the memory control signal DS never becomes
The three 74LS04 inverters in the DS path help active during an interrupt acknowledge cycle.
to insure that DS will become active only after This cycle appears to be an aborted read cycle
AC has become true. Figure 3 shows WE in a to the Z6132 and has no harmful effect.
memory read cycle. Only the occurrence of Thus, with only three commonly available
Ml (Indicating an opcode fetch or an interrupt 14-pin packages, a simple interface between
acknowledge) or the occurrence of RD the Z80A CPU and the Z6132 can be con-
(Indicating Ml or memory read) inhibit WE structed. The Z80A was chosen for this appli-
from becoming active. During a memory read, cahon example because it allows 4 MHz opera-
the close tracking of MREQ and RD insures tion while uSing relatively Inexpensive (300 ns)
that WE setup time to AC High ( - 10 ns) memory. Operation of the Z80B CPU (6 MHz)
is met. provides for a maximum memory access time
Figure 4 shows a Z80A CPU I/O cycle along of 210 ns in the opcode fetch cycle (not
with the corresponding active Z6132 memory Including memory interface logic) under worst-
control signals. Since AC never makes a case condihons. Figure 6 shows the hming for
positive transitIOn during this I/O cycle, the the Z80B opcode fetch cycle with its associated
T, T, Tw
CLOCK
I I I I
.....--85~1 1___ "_1
I I J
-+-65----'1 1'-"_1
I I I
....--110-----+-)
DS
WRITE I I
....--90--+-1 1_90_1
WE
WRITE I I I
Figure 4. Z80A 1/0 Cycle Timing
4-8 2102-003
Interfacing maximum delays. In this configuration, one fetch cyeles) can increase processor execution
the Z6132 to wait state can be mserted to increase the effiCIency. The Z80 CPU (2.5 MHz) IS also
the Z80A CPU available access time to 375 ns. In systems that easdy interfaced with the Z6132 famdy. Here,
(Continued) require higher performance, the Z80B CPU as with the Z80A CPU, no additional wait
(even with one wait state meluded m opcode states need to be added.
T
1 2 W 3
CLOCK
I I I I
-4---100 -----+-1 ~100~
I I
-+--110----.[ 4----110----+-[
I
AC
1_ 1
"
--I
I I
1-4-33
~105----..1
-+--105-----+1
I 1
Figure 5. ZSDA Interrupt Acknowledge Cycle Timing
[-+--- 82 5------.
CLOCK I I I
""""--80-------'1 ~8------+-1
I I
1__ 70-1
I I
1__ _1 70
I
......--7____ 1~65 ______ 1~
I 1
-135_1
"--100-------'1 _ _ 110-------+-1
I I
1__ _1 80 .30 ....
_______ 70 ______ 1
I I I
+ - - - - 9 0 - - ' - ' .. AVAILABLE ACCESS TIME~ -+----90----+-1
210
ADDRESS
I PC ADDRESS
I REFRESH ADDRESS
the Z6132 to
the Z80A CPU
16MHz
OSC
v"
OUT 10
i-=- .....-:!::-
GNDCP Vee -+SV
eLR
5V GND
(Continued) +5V 9318 ENP
CLOCK ~ LK
4.7K -=- DRIVER 6 13
+i~1 BENT
+i~8
.
~.+5V
V"
"0: -=- ---- ,. V"
A, 32 A,
~
8
iNT A2 33 A,
7
NMI A. A.
'"*"
~ BUSREQ ",34
.. 35
As:
8
5
..
A
A,
: : 38
As:
3
25
2'
21
A,
..
A,
:~~ 1
23 A"
Al1
2 11~4 2 2.
A" OS
4 ..........500 V-
5 6 27
21 WE
"0
. F'
~
1.
MREQ 26 AC
Z80A
CPU
27
~"
PR Vee Z81325
Mi 'D Or'-
6 3 C. S7.
CLOCK
3 5
tn "LS..
6 1_~O
CLR GND
1 7
'
- 3
-=- ~oo
l
13.';..504 8
-
8 22
ViR V-
4.7K 13 1.
D, D,
26 1. 18
RESET D, D,
D,
7
17
16
D,
5V D. D.
8 15
D. 13 03
12
D, 12 02
lK
A WAIT
D,
Do
,.
15 D,
11 Do
GND
~29
i YOB
BUSY
~tf4
011'F
Vss
-=
Figure 7. Z80A/Z6132 Interface Logic
Interfacing Two Z6132s are interfaced to a Z8002 (non- CPU Technical Manual (document number
the Z6132 to segmented Z8000) in this example to provide 00-201O-C). A Z8002 running at 4 MHz was
the Z8002 CPU 4K words (16 bits wide) of buffer storage. chosen to provide high throughput while still
Three external TTL packages provide all providing a generous memory access time of
address chip select and byte/word decoding to 360 ns for the Z6132s (Figures 8-10). The
the Z6132s. The timing diagrams (Figures Z6132-6 chosen for this example has a max-
8-10), the mterface logic (Figure 11), and the imum access time of 350 ns. All Z8002 memory
circuit description are discussed later. Infor- transactions are three clock cycles long and
mation on the Z8002 CPU can be obtained conform to the Zilog Z-BUS timing specifica-
from the Z8000 CPU Product Specification tions. More information on the Zilog Z-BUS can
(document number 00-2045-A), the be found in the Z-BUS Summary (document
Z80011Z8002 CPU AC Characteristics (docu- number 00-2031-A).
ment number 00-2004-A) and from the Z8000
4-10 2102-006
Interfacing The Z8002 uses a multiplexed address/data enable signals for the even and odd banks of
the Z6132 to bus to provide for memory addressing and Z6132s. The truth table for this multiplexer
the Z8002 CPU data transfer. The rising edge of Address follows. Both even and odd banks are enabled
(Continued) Strobe (AS) guarantees that addresses from the except durmg byte operations. During byte
Z8002 are stable. This signal (AS) is fed write operations, only one bank of Z6132s is
directly to the Z6132s as the Address Clock enabled. This bank is determined by ADo.
(AC) input clocks in memory addresses and
initiates a memory cycle. The Z6132 samples INPUTS OUTPUTS
its Chip Select (CS) pm with the rising edge of RfW BfW
ADo
AC to determine whether the bus transaction is (Enable) (BfA Select) (lA, 2B) EVEN ODD
intended for it. If CS is found Low on the rIS'
0 X 0 0 0
ing edge of AC, the Z6132 begms a read or 0 0 I 0 1
write operation, depending on the state of its 0 I 1 I 0
Write Enable (WE) pin. The Z6132 samples WE I X X 0 0
again on the falling edge of Data Strobe (DS).
If WE is still Low, the Write cycle is continued. x = don't care
If WE has returned to the High state, the
memory write cycle to the Z6132 is aborted. When the Z8002 performs a read operation,
This feature of the Z6132 allows memory Write 16 bits of memory data are returned to the
cycles to be suppressed if determined CPU. For byte read transactions, the appro
undesirable, without paying an access-time priate (odd or even) byte is selected internally
penalty. The R/W signal is fed directly from to the Z8002. The enable input for the 74LSI57
the Z8002 to the Z6132 WE pin. The signal DS is active Low. When the R/W output of the
from the Z8002 indicates when valid data is Z8002 is High (indicating a read operation),
available on the multiplexed adress/data bus. the 74LSI57 IS disabled, forcing the even and
This signal indicates if valid CPU data is odd outputs Low. During a write operation, the
available to the Z6132 during a write cycle and 74LSI57 IS enabled and the even and odd out
enables the Z6132 output buffers during a CPU puts are determined by the states of the B/W
read cycle. The DS signal from the CPU is fed and ADo CPU outputs. During a word-write
directly to the DS input of the Z6132. The only operation, both even and odd outputs are
interface circuitry between the Z8002 and the enabled. During a byte-write operation, the
Z6132 is the decoding of required byte/word, enabled even or odd bank is determined by
read/write, and high-byte/low-byte Z8002 the least sigmficant address bit (ADo). A byte-
memory control functions (Figure II). A write to an even address (ADo is 0) cor
74LSI57 dual multiplexer is used to prOVide responds to an even enable. When this byte IS
165 .
CLOCK
l l
- 4 - - 85--------"1
STATUS
I
-4--60------'1 1_. _1 0 AVAILABLE ACCESS TIME
230 I __ '0
J L
1__ 70 _ _1J
I I
'--75-----"'1
ADDRESS
I
Figure S. ZSOOO Memory Transaction (6.0 MHz)
2102007 411
Interfacing read back from the 26132, the 28002 expects it as a data bit). It is used instead in the selection
the Z6132 to to appear on the upper eight data bits of even or odd 26132 banks. A 74LSI38 is used
the Z8002 CPU (ADs-AD15). The lower eight data bits are con- to further decode even and odd addresses into
(Continued) nected to the odd bank, and the upper eJght mdividual even and odd Chip Selects for the
data bIts are connected to the even bank. The 26132s. Memory transachons (excluding
least sIgnificant address bit (ADo) is not con- refresh operations) are reflected by status bit
nected to the 26132 (although it still functions 03 (HIgh) of the 28002 CPU. This bit is fed to
. 250 .
CLOCK
I I
""'--110--'1
STATUS
I
""'-80----+-1 1_'0_1
I I I
I_SO_II 360 .-50-.
I I
"'-100------"'1 ....--100~
ADDRESS
I I DATA (WRITE)
~120------+-1 "-7~1
DS
READ 1 I
1_ _1 95 '-7~ ______ 1
DS
WAITE I I T
Figure 9. 2:8000 Memory Transaction (4.0 MHz)
.
-+----163-------'1_
250 ..
I
""'-80----+-1 1_ _190
AC
I I I
"""-100-----'1
ADDRESS
I
............... 110 ------+-1
I -4----120 _______ 1 1_ _1 70
DS
READ I I I
1_ _1 95 1_'0_1
OS
WRITE WAIT
SETUP
I I I T
~190-------+-1
1- 1-110---+-1.50 . . 1
II I
Figure 10. 2:6132-6 Interlace Timing (4.0 MHz)
+5V
128
u
g
~I~
Z61328 (ODD)
~47K 1~11'~~'~llll"i8~88a&&B
+5V
L' ~
v., re
~
23
~ ~~ ~
~~ ~ ~ ~ M
~ ~ ;; ~ ~ ~ ~ ~
~ ~ ~~
WAIT
- 29
AS
17
55
R/W 25
ADo 40
ACt 32
AD2 33
AD3 34
AD4 36
AD5 ::
AD,
AD7 38
ADs 39
ADg !
:~~~ 3
Z8002 AD12 :
CPU AD13 9
:~~: 8
./A G ~ ~ ~ ~
~o
~ ~ ~~ ~ ~ ~ ~ M ~ ~ N ~ +j:a
U 74LS1S7 I> I" II~ W
~~O~4<~~COOOOOCO
0 ~ " M , 0 - 0 - " M ,
u
g
2' lA
~ODD
BIW
~~
12A ~
I~
2. rl>- ~
GND
sT,
~
~ G2A Vee
'-!-5 G1
+~,V6
Yo 0-15
V1 0-14
Y20-13
Ie
4 G2A Vee
~ G1
5
'1: Yo 0-15
Vi 0-14
Y20-- 13
~8
0---;-
2102-0]0 4-13
Interfacing In the following example, a 26132-5 (300 ns) multiplexed address/data bus and Port 0 as the
the Z6132 is interfaced to a 28 operating at 7.3728 MHz. upper byte of a 16-bit address bus. Before
to the Z8 Timing for interfacing the 28 to a 26132-4 external memory references to the 26132 can
(250 ns) is discussed for 8-MHz 28 operation. be made by any instruction, the user must con-
In addition, the example describes 2716 and figure Ports 0 and I appropriately. Instruction
2732 EPROM interchangeability with the pipehning mandates that after setting the
26132. Timmg diagrams and circuit drawings modes of Ports 0 and I for external memory
have been included for 28 memory mterface operahon, the next two bytes are fetched from
timing and are discussed in this section. internal program memory. Two single-byte
The 28 is an 8-bit, general-purpose micro- instructions, such as NOPs, can be used to
computer chip that can be configured under accomphsh this. On-board ROM in the 28 is
software control. The 28 features regular archI- avaIlable from 0000-07FF (Hex). This applica-
tecture with 144 on-chip registers, 2K bytes of tion locates the external 26132 in the 28
on-chip ROM, and 32 I/O lines configured for address space from 1000-IFFF (Hex).
conventional I/O or for external memory. All 28 timmg references are made with
Detailed information on the 28 can be found m respect to the output signals AS and DS. The
the Z8 Microcomputer Technical Manual control signal AS indicates when the 28
(document number 03-3047-02) and the address bus is valid, while the control signal
Z86011213 MCU Microcomputer Product DS controls the flow of data. The 28 status
Specification (document number 00-2037-A). signal R/W (Read/Write) indicates the direc-
The 28 uses Port I (eight bIts wide) as a hon of data flow. The 28 indICates when a
+5V
! 2716
.~
+jV J1 2732
26 AC
73728 MHz Vo< 22
DS 8 08(0)
(SERIES 20
RESONANT) 2 CS(CE)
27
WE
~
XTAL2 RW 7
Pi0 ;~
11
Do
12
~
P2, D,
P12 23 13
XTAL1 D,
Pi3 24
P14 25
,.
15
17
D,
D,
Pi5 26 Ds
Pi6 27 18
D.
Pi7 28 19
D,
RESET
DEBOUNCED +i~o
SWITCH
RESET
Z8132 *
6 RESET
~Do 00 ~ '0
~D1 a,
+s-----i "
~ 02
~ "
02
,. Oa 74LS373 Q3 ~ A,
~
04 Q4 A,
Z8601 7
MCU 13
Ds
D.
as
O.
~ As
A.
8
01 Q7 : 9 3 A,
74LS04 G GND OE
As
po,
9
13
...
11~""" 10 1110~
25 Aa
,. ~~
po, 14
15 Ag
po, A10
po, 23 A11
+~1~
P04~A Y1~
4K-8K
J2
2716 i, BUSY
U
Vee V
~~.
~
POe
~
P07
C
G2A
"~)
~
745138 Ya
~
Y4 OTHER SYSTEM
ONO Vee ~ +5V
011'F
5 G2B Ys?- DECODING
Y.~
OND (01 OND 1 ol-
Y
~" ~ '7K
+5V
4-14 2102-011
Interfacing hardware reset operation IS m progress by The basic memory cycle of the Z8 is six
the Z6132 activatmg DS whIle outputting AS at the inter- clock cycles (810 ns at 7.3728 MHz). An
to the Z8 nal clock rate. Since the internal clock has a extended cycle mode is available under soft-
(Continued) cycle time period of 250 ns, it is necessary to ware control that lengthens memory access by
inhibIt AS during hardware reset operations so one clock cycle. At 8 MHz, thIs cycle is reduc-
that the mimmum memory cycle time for the ed to 750 ns. In eIther case, the Z6132 timing
Z6132 IS not vlOlated. This IS easily accom- parameters TC (read or Wrlte cycle time),
phshed by using the reset line to the Z8 as an TwACh (AC width HIgh), and TdDS(AC) (DS
inhibit Ime to the AC mput of the Z6132 Low to AC High) all allow the Z6132 to be
(Figure 12). The 74LS32 OR gate delays the used in the Long Cycle-Time Refresh mode.
Address Clock to the Z6132 a maximum For thIs reason, the Z6132 BUSY line IS per-
of 22 ns. manently grounded.
Theory of FIgure 12 shows the circUlt diagram for a (Low) and retams the addresses after AS has
Operation small Z8 system. In thIs configuration, a serles returned High. The Z6132 does not require
resonant crystal (7.3728 MHz) provIdes all addresses to be stable throughout the entire
system hmmg. Port I is conflgured for memory cycle, so this latch is used only with
mulhplexed address and data, and Port 0 is systems that provlde the option of usmg the
conhgured to provIde the upper address byte 2716 and 2732 EPROMs. Addresses are latched
to complete the 12-blt address bus required by internally to the Z6132 on the rismg edge of
the Z6132 and to provIde four bits of address AC. Jumpers 11 and J2 are connected as shown
decodmg. The upper bits of Port 0 (P04 to P07) for Z6132 operation. To substitute a 2732 for
are decoded by a 74S138 to provIde eight the Z6132, the existing Jumper OJ) must be cut
blocks, each 4K bytes long. The flrst block is from the Z6132 pm 26 to the Z8 pm 9, and
dIscarded because It overlaps with internal Z8 Z6132 pm 26 IS connected to Vee. To
ROM. The second segment IS used to generate subshtute a 2716, one addihonal Jumper
CS for the Z6132, and the last SIX segments are change must be made. Jumper J2 is shown
free for other system chip select decodmg, connected for Z6132 and 2732 operation. To
such as additional memory or external I/O substitute a 2716, the existmg Jumper IS cut
ports. A 74LS373 IS used to latch addresses from the Z6132 pm 23 to the Z8 pin 16, and the
from the multiplexed address/data bus of Port Jumper at J2 from the Z8 pm 23 IS connected to
I. ThIS latch is enabled when AS is active the 4.7K pullup resIstor.
4-15
Timing The important control signals for memory calculate the timmg value for a clock input of
interface to the Z8 have been reproduced in 7.3728 MHz, the difference in clock periods
Figures 13-16. In this design example, a (135.6 ns - 125.0 ns = 10.6 ns) must be
crystal frequency of 7.3728 MHz was selected added to the value given in the Z8 product
for overall system timing. The Z8 product specifications. Hence, the delay time for
specifications provide timing specifications at TdA(AS) with a 7.3728 MHz clock is 40.6 ns
8 MHz. To calculate the timing parameters for (30 ns + 10.6 ns = 40.6 ns). The AS signal
frequencies other than 8 MHz, the timing has a guaranteed minimum width of 70.6 ns at
parameters are derated by a factor based on 7.3728 MHz. The Z8 guarantees that addresses
the dIfference in clock period. For instance, will be stable 40.6 ns before the rising edge of
the timing parameter TdA(AS) is given as AS. With the additional maximum delay of
30 ns (mm) for a clock input of 8 MHz. To 22 ns for the 74LS32, the resultant signal (AS)
L
I"-J~---IO- . . - 6 0 MIN------'-I
PORT 1
ADDRESS I VALID ADDRESS
I
I- 230 MIN 1-+--50 MIN-----+-
Di
READ I r
I...JI~-+-I" 150 MIN .
Di
WRITE I
,
- 280 MIN
AC
I I L
12tMrx1
ADDRESS LATCHED ADDRESS
T
I- 230 MIN I"'--SOMIN----"'-
Di
I
.
READ
Di
WRITE I
...J~...... 250 MIN
'I
DATA VALID (WRITE) I VALID READ DATA
.- 1. . . . 12 MAX
Cs ~I~I ______________________~____
4-16 2102-012,013
Timing is fed directly to the Address Clock input of access time begins wIth the rising edge of AC
(Continued) the Z6132. The low-byte address encounters a and includes the data setup time to the Z8
maximum delay of 30 ns through the 74LS373 CPU. ThIS access time allows the use of low-
latch. The status signal R/W and the data bus speed Z6132-5 (300 ns) RAMs. For systems that
control signal DS are fed directly to the Z6132. requIre hIgher performance, the Z6132-4 can
The status signal R/W is available to the Z6132 be used with an 8-MHz Z8 CPU. Timing for the
40.6 ns before the rismg edge of AC. The Z8 at 8 MHz has been included in Figure 13.
maximum delay for CS through the 74S138 is The maximum access time allowed for external
12 ns. This still leaves 27.4 ns setup time for RAM by the Z8 when operatmg at 8 MHz is
CS to AC, although a ns is the mmimum 280 ns. The Z6132-4 has an access lime of
reqUirement. The maximum access time for an 250 ns, making it directly compallble with
external memory operation at 7.3728 MHz is an 8-MHz Z8.
calculated to be 322.4 ns (FIgure 14). This
-106 MIN_I
fi I~----------------~L~
'
I"--~~'~--+- -+---70 6 MIN~I -+--------606MIN _ _ 1
PORT 1
ADDRESS
I VALID
I
I" 2619 MIN 1""---606 MIN------+-
READ
Dli
l I
I-+-~~~---.I . 1819 MIN .
r-
WRITE
Dli
I
. 3224 ,
AC I ""-1- + - 1 - - - - - - - - - - - - -
.......-
22 MAX
ADDRESS
I LATCHED ADDRESS
READ
Dli
I
'-~~----'I II
1819 MIN
'I
WRITE
Dli
I
...--~~~----- 300 MAX
'I
DATA VALID (WRITE)
I VALID READ DATA
-- 1-+-12 MAX
11
+1 V
26 AC
73728 MHz
(SERIES
V"
os
22 os
(OE)
20 CS (CE)
RESONANT) 2 7 27 WE
~
XTAl2 RW
21 11
P1, 0,
22 12
P2, 0,
"'E2 XTAl.1 P12 23 13
15
0,
Ph 24 0,
P1, 25 1.
0,
," 2.
P16 27
17
18
0,
0,
P17 28 19
0,
DEBOUNCED
SWITCH
RESET Z6132"
6 REseT 10 . .
: A1
A,
~ A3
A,
Z8801 : A5
MCU A,
3 A,
j\S9
~:
13
PDo As
PO, 14
15 21 A9
po, 23 A10
1.
PO, A"
po, ~
-=-
i, BUSY
ff
V"
PO, ~ GND vcc~ +5V
Po. t-!L
po, ~.
011'F
GND
..1..11
Summary The 26132 is a versatile, intelligent byte- memory systems. The 26132 is an industry-
wide RAM, which provides an attractive solu- standard, 28-pin DIP that conforms to the
tion for primary buffer storage. Because the JEDEC recommended pinout and is inter-
26132 provides two modes of self-refresh, the changeable with 2716/2732-type EPROMs. The
user can select between executing a refresh 26132 is 2-BUS compatible and interfaces
after each memory access or taking advantage easily with the 28, 280, and 28000 Families of
of the inherent sequential access of most microprocessors.
4-18 2102016
Z-Bus 5
0-
ZBUSTM
Component Interconnect
~
Zilog Sammary
March 1981
ADO'AD"~S
of shared resources (including the bus itself)
is supported by a daisy-chain priority EXTENDED ADDMS$ DlOO
. DE
STATUS / ~
mechanism.
The heart of the Z-BUS is a set of multi- ........--CLOCK-----.
plexed address/data lines and the signals that - - - - - B U S REOUEST SIONALS,-----
control these lines. Multiplexing data and -4--BUSREQ----+-
- - BUSACK-----" REQUESTER
addresses onto the same lines makes more effi-
cient use of pins and facilitates expansion of
the number of data and address bits. Multi-
CPU
C=e:==
-----INTERRUPT S I O N A L S - - - - - -
...--iNf--
plexing also allows straightforward addressing
of a peripheral's internal registers, which
greatly simplifies I/O programming. PERIPHERAL
A daisy-chained priority mechanism resolves
interrupt and resource requests, thus allowing
distributed control of the bus and eliminating C=lr:~==
the need for separate priority controllers. The ----RESOURCE REQUEST SIONALS----
--MMRQ---..
resource-control daisy chain allows wide MULTIMICRO
ZBUS ...---MMSf--
physical separation of components. COMPONENT ...--MMAI----,
REOUEST
NETWORK
The Z-BUS is asynchronous in the sense that -----... MMAO----.J
Operation Two kinds of operations can occur on the at a time, and it must be initiated by the bus
Z-BUS: transactions and requests. At any given master. A request, however, may be ini-
time, one device (either the CPU or a bus tiated by a component that does not have con-
requester) has control of the Z-BUS and is trol of the bus. There are three kinds of
known as the bus master. A transaction is requests:
initiated by a bus master and is responded to Interrupt. Requests the attention of the
by some other device on the bus. Four kinds of Z-BUS CPU.
transactions occur in Z-BUS systems:
Bus. Requests control of the Z-BUS to ini-
Memory. Transfers 8 or 16 bits of data to or tiate transactions.
from a memory location.
Resource. Requests control of a particular
I/O. Transfers 8 or 16 bits of data to or from resource.
a peripheral.
When a request is made, it is answered
Interrupt Acknowledge. Acknowledges according to its type: for interrupt requests an
an interrupt and transfers an identi- interrupt-acknowledge transaction is initiated;
fication/status vector from the interrupting for bus and resource requests an acknowledge
peripheral. signal is sent. In all cases a daisy-chain pri-
Null. Does not transfer data. Typically used ority mechanism provides arbitration between
for refreshing memory. simultaneous requests.
Only one transaction can proceed on the bus
5-4
Signal The Z-BUS consists of a set of common signal be transmitted on a 16-bit bus. This signal is
Lines lines that interconnect bus components (Figure not present on an 8-bit bus.
I). The signals on these lines can be grouped WAIT. (active Low). A Low on this line indi-
into four catagories, depending on how they cates that the responding device needs more
are used in transactions and requests. hme to complete a transaction.
RESET. (active Low). A Low on this line resets
Primary Signals. These signals provide the CPU and bus users. Peripherals may be
hming, control, and data transfer for Z-BUS reset by RESET or by holding AS and DS Low
transactions. simultaneously.
ADo-AD1S. Address/Data (active High). These CS. Chip Select (active Low}~ach peripheral
multiplexed data and address lines carry 1/0 or memory component has a CS line that is
addresses, memory addresses, and data during decoded from the address and status lines. A
Z-BUS transactions. A Z-BUS may have 8 or 16 Low on this line indicates that the peripheral
bits of data depending on the type of CPU. In or memory component is being addressed by a
the case of an 8-bit Z-BUS, data IS transferred transaction. The Chip Select information is
on ADo-AD7' latched on the rising edge of AS.
Extended Address. (active High). These CLOCK. This signal provides basic timing for
lines extend ADo-ADI5 to support memory bus transactions. Bus masters must provide all
addresses greater than 16 bits. The number of signals synchronouly to the clock. Peripherals
lines and the type of address mformation and memories do not need to be synchronized
carried is dependent on the CPU. to the clock.
Status. (active High). These lines designate
the kind of transaction occurring on the bus Bus Request Signals. These signals make
and certain additional information about the bus requests and establish which component
transaction (such as program or data memory should obtain control of the bus.
access or System versus Normal Mode).
BUSREQ. Bus Request (active Low). This line
AS. Address Strobe (active Low). The rising is driven by all bus requesters. A Low indi-
edge of AS indicates the beginning of ~trans cates that a bus requester has or is trying to
action and that the Address, Status, R/W, and obtain control of the bus.
B/W signals are valid.
BUSACK. Bus Acknowledge (active Low). A
DS. Data Strobe (active Low). DS provides Low on this line indicates that the Z-BUS CPU
timing for data movement to or from the bus has relmquished control of the bus in response
master. to a bus request.
R/W. Read/Write (Low = write). This signal BAI, BAa. Bus Acknowledge In, Bus
determines the direction of data transfer for Acknowledge Out (active Low). These signals
memory or I/O transactions. form the bus-request daisy chain.
B/W. Byte/Word (Low = word). This signal
indicates whether a byte or word of data is to
5-5
Z-BUS Signal CPU Requester Peripheral Memory
Connections
Bldlrectional2 Bidirectional 2 Bidirectional! BidlrectionaJ2
ADo-AD15 3-state 3-state 3-state
3-state
Extended Output Output
0 Input
Addlesss 3-state 3-state
Output Output Input lO 0
Status
3-state 3-state
Output Output Input Input
R/W
3-state 3-state
B/W9 Output Output Input3 Input
OutputS OutputS
WAIT Input Input Open Dram
Open Drain
Output Output
AS Input Input
3-state 3-state
Output Output
DS Input Input
3-state 3-state
CS4 0 0 Input Input
RESET Input Input13 InputS D
CLOCK14 Input Input InputS Inputs
Bidirectional
BUSREQ Input 0 D
Open Dram
BUSACK Output 0 0 D
BAP 0 Input 0 D
BA07 0 Output 0 D
Input Output
INT 0 Open Drain D
INTACK6 0 0 Input! I D
IEP 0 0 Input D
IE07 0 0 Output D
MMRQ12--- Output.
Open Dram
MMST12 Input
MMAF,12 Input
MMA07,12 Output
I. Only ADO-AD7' unless perlpheral1s 16-B11. 10. OptIonal-usually only mput on perIpherals that are also
2, For an 8blt bus, only ADO-AD7 are bIdIrectIonal. requesters.
3. Only for a 16-M peripheral. 11, May be omItted 1 perlpheral mputs status lmes.
4. Derived sIgnal, one for each perIpheral or memory; decoded 12. OptIonal sIgnal; any component may attach to the resource
from status and address Imeso request hnes.
5. OptIonal-perIpherals are tYPIcally reset by AS and DS bemg 13. OptIonal sIgnal; a bus requestor may also be reset by AS and
Low sImultaneously; however they can have a reset mput.
I DS gOing Low and BAI being HIgh sImultaneously.
6. DerIved sIgnal; decoded from status lmes. 14. ThIS sIgnal IS ophonallf there are no requesters on the bus.
7. Dalsycham hnes. CPU tIming can be provIded by alternate means such as
S. Ophonal slgnal(s). crystal oscIllator mputs.
9. For 16-b1t data bus only.
D No Connechon
5-6
Signal Interrupt Signals. These signals are used for Resource Request Signals. These signals are
Lines interrupt requests and for determining whICh used for resource requests. To manage more
(Continued) mterrupting component is to respond to an than one resource, the lines carrying these
acknowledge. To support more than one type signals can be replicated. (The 28000 supports
of interrupt, the lines carrying these signals one set of resource request lines.)
can be rephcated. (The 28000 CPU supports MMRQ. Multi-Micro Request (active
three types of interrupts: non-maskable, vec- Low). ThIS line is driven by any device that
tored, and non-vectored.)
can use the shared resource. A Low indicates
INT. Interrupt (active Low). This signal can that a request for the resource has been made
be driven by any peripheral capable of gener- or granted.
ating an interrupt. A Low on INT indicates that MMST. Multi-Micro Status (active Low). This
an interrupt request is being made. pin allows a devICe to observe the value of the
INTACK. Interrupt Acknowledge (active MMRQ line. An input pin other than MMRQ
Low). ThIS signal is decoded from the status fac!litates the use of line drivers for MMRQ.
hnes. A Low indicates an interrupt acknowl- MMAI, MMAO. Multi-Micro Acknowledge In,
edge transaction is in progress. This signal Multi-Micro Acknowledge Out (active
is latched by the peripheral on the rising Low). These lines form the resource-request
edge of AS. daISY chain.
lEI, lEO. Interrupt Enable In, Interrupt Enable
Out (active High). These signals form the
interrupt daisy chain.
Transactions All transactions start with Address Strobe bus master makes ADo-ADI5 mactive before
bemg driven Low and then raised High by the drIving Data Strobe Low so that the
bus master (Figure 2).The Status lines are addressed memory or peripheral can put its
valid on the rising edge of Address Strobe and data on the bus. The bus master samples this
indicate the type of transactions being initi- data just before raising Data Strobe High. For
ated. If the transaction requires an address, a write (R/W = Low), the bus master puts the
it must also be valid on the rising edge data to be written on ADo-ADI5 before forcing
of Address Strobe. Data Strobe Low.
For all transactions except null transactions For an 8-bit 2-BUS, data is transferred on
(which do nothing beyond this paint), data IS ADo-AD7' Address !::its may remain on
then transferred to or from the bus master. The ADs-ADI5 while DS is Low.
bus master uses Data Strobe to time the move-
ment of data. For a read (R/W = High), the
)O( K
~
CLOCK
- }
I
BUS MASTER
SAMPLES WAIT
~ BUS MASTER
SAMPLES
INPUT DATA
I
STo-ST3
RiW,BIW
'\
ADo-AD15
ADDRESS FROM
BUS MASTER
DATA TO
BUS MASTER -{
\ \
ADo-AD15 DATA FROM BUS MASTER
20310181 5-7
Memory For a memory transaction, the Status lines bytes of all the addressable 16-bit words. The
Transactions distinguish among various address spaces, other bank contains all the lower bytes. When
such as program and data or system and nor- a single byte is written (R/W = Low,
mal, as well as indicating the type of trans- B/W = High), only the bank mdicated by
action. The memory address is put on address bit Ao is enabled for writing.
ADo-ADI5 and on the extended address lines. For a Z-BUS with 8-bit data, the memory is
For a Z-BUS with 16-bit data, the memory is organized as one bank which contains all
organized as two banks of eight bits each bytes. This bank always inputs and outputs its
(Figure 3). One bank contains all the upper data on ADO-AD?
D D,
Ao-Au
EXTENDED
ADDRESS
LOWER
BANK
_-l::===L/_________. . . . ENABlE
I/O 1/0 transactions are sImilar to memory mltted on ADo-AD7, regardless of the I/O
Transactions transactions wIth two Important dIfferences. address. (ADs-ADI5 contam arbItrary data in
The first IS that 1/0 transactions take an extra thIS case.) For an I/O transaction, the address
clock cycle to allow for slow penpheral oper- mdicates a peripheral and a particular regIster
ation. The second IS that byte data (indIcated or function wlthm that peripheral.
by B/W HIgh on a 16-blt bus) IS always trans-
Null The two kmds of null transactions are dIS- operation (to support memories whICh generate
Transactions tinguished by the Status lmes: internal oper- refresh cycles from Address Strobe).
ation and memory refresh. Both transactions For a memory refresh transaction, the
look like a memory read transaction except Address lmes con tam a refresh address when
that Data Strobe remains HIgh and no data IS Address Strobe goes High. ThIS transaction IS
transferred. used to refresh a row of a dynamIC memory.
For an mternal operation transaction, the Any memory or I/O transaction can be sup-
Address lmes contam arbItrary data when pressed (effechvely turnmg It mto a null trans-
Address Strobe goes HIgh. ThIS transactIOn is achon) by keepmg Data Strobe HIgh through-
imtlated to maintain a mmlmum transactIOn out the transachon.
rate when a bus master is doing a long internal
Interrupts A complete mterrupt cycle consIsts of an bIts that control how It generates mterrupts.
interrupt request followed by an interrupt- These bits are an Interrupt Pendmg bit (IP),
acknowledge transaction. The request, which and Interrupt Enable bit (IE), and an Interrupt
consists of INT pulled Low by a peripheral, Under ServICe bIt (IUS).
notifies the CPU that an interrupt is pending. A peripheral may also have one or more
The mterrupt-acknowledge transactIOn, whICh vectors for identifying the source of an lnter-
is mihated by the CPU as a result of the rupt dunng an interrupt-acknowledge trans-
request, performs two funchons: It selects the achon. Each mterrupt source IS associated WIth
peripheral whose interrupt IS to be acknowl- one mterrupt vector and each interrupt vector
edged, and It obtams a vector that Identifies can have one or more mterrupt sources assocI-
the selected deVICe and cause of interrupt. ated with It. Each vector has a Vector Includes
A peripheral can have one or more sources Status bIt (VIS) controlling ItS use.
of interrupt. Each interrupt source has three Finally, each peripheral has three bits for
20310182
386 5-8
Interrupts controlling interrupt behavior for the whole transaction (indICated by INTACK Low).
(Continued) device. These are a Master Interrupt Enable Between the rising edge of AS and the falling
bit (MIE), a Disable Lower Chain bit (DLC), edge of DS, the lEI/IEO daisy chain settles.
and a No Vector bit (NV). Any interrupt source with an interrupt pending
Peripherals are connected together via an (IP = 1, IE = 1, MlE = 1) or under service
interrupt daisy chain formed with their IEI and (IUS = I) holds its lEO line Low; all other
IEO pins (Figure 4). The interrupt sources interrupt sources make IEO follow IEI. When
within a device are similarly connected into DS falls, only the highest priority interrupt
this chain with the overall effect being a daisy source with a pending interrupt (IP = 1) has
chain connecting the interrupt sources. The its IEI input High, its IE bit set to 1, and its
daisy chain has two functions: during an IUS bit set to O. This is the interrupt source
interrupt-acknowledge transaction, it deter- being acknowledged, and at this point it sets
mines which interrupt source is being its IUS bit to 1, and, if the peripheral's NV bit
acknowledged; at all other times it determines is 0, identifies itself by placing the vector on
which interrupt sources can initiate an inter- ADo-AD7' If the NV bit is 1, then the periph-
rupt request. eral's ADo - AD7 pins remain floating, thus
Figure 5 is a state diagram for interrupt allowing external circuitry to supply the vec-
processing for an interrupt source (assuming tor. (All interrupts, including the 28000's non-
its IE bit is I). An interrupt source with an vectored interrupt, need a vector for identify-
interrupt pending (IP = 1) makes an interrupt ing the source of an mterrupt.) If the vector's
request (by pulling INT Low) if, and only if, it VIS bit is 1, the vector will also contain status
is enabled (IE = 1, MIE = 1), it does not have information further identifying the source of
an interrupt under service (IUS = 0), no the interrupt. If the VIS bit is 0, the vector
higher priority interrupt is being serviced held in the peripheral will be output without
(IEI = High), and no interrupt-acknowledge modification.
transaction is in progress (as indicated by While an interrupt source has an interrupt
INTACK at the last rising edge of AS). IEO is under service (IUS = 1), it prevents all lower
not pulled down by the interrupt source at this priority interrupt sources from requesting
time; lEO continues to follow IEI until an interrupts by forcing lEO Low. When interrupt
interrupt-acknowledge transaction occurs. servicing is complete, the CPU must reset the
Some time after INT has been pulled Low, IUS bit and, in most cases, the IP bit (by
the CPU initiates an interrupt-acknowledge means of an 1/0 transaction).
,"1'CIIRUPT __
I'~d'*.. I'~'l
I I I
I .
~~A~~~'A~O'~______-.rF
~
I
J o . . - - . : . . ..
l
I I
., '
"
I
,..
HIQH.~~
PRIORI~~ LOWEST
PRIORITY
T~Ttf ri rnTACK
lEO lEI ADo-ADr AS
II rr I
os fNf i'N"fACi( lEO lEI ADo-AD7
-:~ IlJ
AS os iNf MACK lEO
t
I
ADo-ADr
AS
ZBUS
DO
CPU
iNf
WAIT I-
STATUS
F=>[ STATUS
DECODER rL
AOe-AD15 [<::=J FROM '.BIT PERIPHERALS
20310189
5-9 387
- - - - - - - - - _.._ - - - - ._---
Interrupts ANY ANY
(Continued)
IP IUS IE
I I I, I
0 0
STATE0D.
HIGH~
IP IUS
i' 1 I, I0
STATE'D.
HIGH LOW
IP IU$ IE lP 1US IE
i' i I' I
0 ~
~
STATE 3D. STATE 4
ANY ANY
I
IP WS IE
I I' I' I < IP IUS IE.
G:E:EJ
0
STATE 5
G
> STATE 6
STATE 7 STATE 8
Figure 5. State Diagram for an Interrupt Source
1. ThIS dIagram assumes MIE = 1. The effect of MIE = a IS the 3. Transltion I to state 6 or 7 can occur from any state except 3 or
same as that of settmg IE = o. 4 (whIch only occur durmg mterrupt acknowledge).
2. The DLC bIt does not affect the states of mdlvidual mterrupt 4. TranSItIon J from state 6 or 7 can be to any state except 3 or 4,
sources. Its only effect IS on the lEO output of a whole perIpheral. dependmg on the value of lEI, IP, and IUS.
2031-0185
Interrupts A peripheral's Master Interrupt Enable bit requests.
(Continued) (MIE) and Disable Lower Chain bit (DLC) can Polling can be done by disabling interrupts
modify the behavior of the peripheral's inter- (using MIE and DLC) and by reading per-
rupt sources in the following way: if the MlE ipherals to detect pending interrupts. Each
bit is 0, the effect is as if every Interrupt Z-BUS peripheral has a single directly
Enable bit (IE) in the peripheral were 0; thus addressable register that can be read to deter-
all interrupts from the peripheral are disabled. mine if there is an interrupt pending in the
If the DLC bit is I, the effect is to force the device and, if so, what interrupt source
peripheral's lEO output Low, thus disabling all it is from.
lower priority devices from initiating interrupt
Bus To generate transactions on the bus, a bus its BAO High, thereby locking out all lower
Requests requester must gain control of the bus by priority users.
making a bus request. This is done by forcing A bus requester gains control of the bus
BUSREQ Low (Figure 6). A bus request can be when its BAI input goes Low. When it is ready
made only if BUSREQ is initially High (and has to relinquish the bus, it stops pulling BUSREQ
been for two clock cycles), indicating that the Low and allows BAO to follow BAI. This per-
bus is controlled by the CPU and no other mits lower priority devices that made simul-
device is requesting it. taneous requests to gain control of the bus.
After BUSREQ is pulled Low, the Z-BUS When all simultaneously requesting devices
CPU relinquishes the bus and indicates this have relinquished the bus, BUSREQ goes
condition by making BUSACK Low. The Low High, returning control of the bus to the CPU
on BUSACK is propagated through the and allowing other devices to request it.
BAIIBAO daisy chain (Figure 6). BAI follows The protocol to be followed in making a bus
BAO for components not requesting the bus, request is shown in Figure 7.
and any component requesting the bus holds
'-CPU
+5Y
2031-0193.0194
511
Resource Resource requests are used to obtain control The four unidirectional lines of the resource
Requests of a resource that is shared between several request chain allow the use of line drivers,
users. The resource can be a common bus, a thus faCilitating connection of components
common memory or any other resource. The separated by some distance. In the case of the
requestor can be any component capable of 28000 CPU, the four resource request lines
implementing the request protocol. may be mapped into the CPU MI and MO pins
Unlike the Z-BUS itself, no component has using the logic shown in Figure 10. With this
control of a general resource by default; every configuration, the Multi-Micro Request Instruc-
device must acquire the resource before using tion (MREQ) performs a resource request.
it. All devices sharing the general resource
drive the MMRQ line (Figure 8). When Low,
the MMRQ line indicates that the resource is
being acquired or used by some device. The
MMST pin allows each device to observe the
state of the MMRQ line. YES
When MMRQ is High, a device may initiate
a resource request by pulling MMRQ Low
(Figure 9). The resulting Low on MMRQ is
propagated through the MMAIIMMAO daisy
chain. If a device is not requesting the
resource, its MMAO output follows its MMAI
input. Any device making a resource
request forces its MMAO output High to deny
use of the resource to lower priority devices.
A device gains control of the resource if its
MMAI input is Low (and its MMAO output is
High) after a sufficient delay to let the daisy
chain settle. If the device does not obtain the
resource after this short delay, it must stop
pulling MMRQ Low and make another request
at some later time when MMRQ is again High.
When a device that has gained control of a
resource is finished, it releases the resource by
allowing MMRQ to go High.
+5.
-
ria
iIIIIIiT
IIfmI
ria
iIIIIIiT
r,....-------iiIiII'I'
!iiliIIIII iii---~
nmi
H-"i>---1IiIlRl
L.::::::JLp---- iiiiili
Figure 8. Resource Requatli CcmDeclioll8 Figure 10. a... Requa! Logic 1M Z8000
2031-0196, 0238
512
Test The hming characterishcs given in this +5V DC
DC The folloWing table states the dc character- components. All voltages are relative to
Charac- ishcs for the input and output pins of Z-BUS ground.
teristics Symbol Parameter Min Max Unit Test Condition
Capacitance The follOWing table gives maximum pin Symbol Parameter Max (pF)
capacitance for Z-BUS components. Capaci-
tance is speCified at a frequency of I MHz CIN Input Capacitance 10
over the temperature range of the component. COUT Output CapaCitance IS
Unused pins are returned to ground.
CliO Bidirectional CapaCitance IS
Timing The follOWing diagrams and tables give the delays and for signal skew. The timing given
Diagrams timing for each kind of transaction (except null for memories is a constraint on bus-compatible
transactions). Timings are given separately for memories (like the Z6132 Quasi-Static RAM)
bus masters and for peripherals and memories and is not intended to constrain memory sub-
and are intended to give the minimum timing systems constructed from conventional com-
requirements which a Z-BUS component must ponents.
meet. An individual component will have more Besides these timings, there is a requirement
detailed and sometimes more stringent hming that at least 128 transactions be initiated in any
specifications. The differences between bus 2 ms period. This accommodates memories that
master timing and peripheral and memory tim- generate refresh cycles from Address Strobe.
ing allow for buffer and decoding circuit
8085004,005 5-13
Bus Master "I!~
Timing
CLOCK
~
g I~~
------<D---
2
4 -
3
,~)~ ~
f-
~ ~.'1 ~
tPLED
5
.~."'"
ADDEO
~ r-<D
STo-STa
RlW. alii )( }(
~
~
Q)-- ~ :-....
1\
~I I
~
~~
18 13
~ ..... 14
Di
(READ) M "
-@t--
I-I- ~
EXTENDED
ADDRESS X
Qt
11
" ~
ADo-ADHi )( ADDRESS FROM
8US MASTER
DATA TO
BUS MASTER ~
" ~
J2
"
~
~
DI
(WRITE)
23
35
"
ADo-ADu
X M DATA FROM BUS MASTER
I/O Transaction
Timing
Interrupt
CLOCK
Acknowledge
Timing
STATUS
ADo-ADU __ )(UI'o.""N'o)-------------+--------i
20310240,0187,0191
5-14
Bus Master Number Symbol Parameter Min (ns) Max (ns) Notes
Timing
Parameters All Transactions
I TpC Clock Period 250 2000
2 TwCh Clock High Width 105 1895
3 TwCl Clock Low Width 105 1895
4 TfC Clock Fall Time 20
5 --TrC Clock Rise Time - - - - - - - - - - - - - - - - - - 2 0 - - - -
6 TdC(S) Clock I To Status Vahd Delay 100
7 TdC(ASr) Clock I To AS I Delay 90
8 TdC(ASf) Clock I To AS I Delay 80
9 TdS(AS) Status Valid To AS I Delay 50
1O--TwAS---AS Low W i d t h - - - - - - - - - - - - - - 8 0 - - - - - - -
II TdDS(S) DS I To Status Not Valid Delay 80
12 TdAS(DS) AS I To DS I Delay 70 2095 3
13 TsDR(C) Read Data To Clock I Setup Time 50
14 TdC(DS) Clock I To DS I Delay 70
15--TdDS(AS)-DS I To AS I D e l a y - - - - - - - - - - - 7 0 - - - - - -
16 TdC(Az) Clock I To Address Float Delay 65
17 TdC(A) Clock I To Address Valid Delay 90
18 TdA(AS) Address Vahd To AS I Delay 50
19 TdAS(A) AS I To Address Not Valid Delay 60
20--TwA Address Valid W i d t h - - - - - - - - - - - - - 1 5 0 - - - - - - -
21 ThDR(DS) Read Data To DS I Hold Time 0
22 TdDS(A) DS I To Address Active Delay 80
23 TdDS(DW) DS I To Write Data Not Valid Delay 80
24 TsW(C) WAIT To Clock I Setup Time 50 2,5
25--ThW(C)--WAIT To Clock 1 Hold Time 0-----2,5-
Memory Trcmsactions
26 TdAS(W) AS I To WAIT Required Valid 90
27 TdC(DSR) Clock I To DS (Read) I Delay 120
28 TdDSR(DR) DS (Read) I To Read Data Required Valid 185
29 TwDSR DS (Read) Low Width 250
30--TdAz(DSR)-Addrass Float to DS (Read) 1 D e l a y - - - - - - - - O - - - - - - -
31 TdAS(DR) AS I To Read Data Required Valid 320
32 TdA(DR) Address Valid To Read Data Required Valid 400
33 TdC(DSW) Clock 1 To DS (Write) 1 Delay 95
34 TwDSW DS (Write) Low Width 160
35--TdDW(DSWf)-Write Data Valid To i5S (Write) 1 D e l a y - - - - - - 5 0 - - - - - - -
36 TdDW(DSWr) Write Data Valid To DS (Write) I Delay 230
1/0 Transactions
37 TdAS(DR) AS I To Read Data ReqUired Valid 570
38 TdA(DR) Address Valid To Read Data Required Valid 650
39 TdAz(DSI) Address Float To DS (VO) I o
40--TdC(DSI)-Clock 1 To DS (I/O) 1 - - - - - - - - - - - - - 1 2 0 - - -
41 TdDSI(DR) DS (I/O) 1 To Read Data Required Valid 320
42 TwDSI DS (I/O) Low Width 400
43 TdDW(DSIf) Write Data To DS (I/O) I Delay 50
44 TdDW(DSlr) Write Data To DS (I/O) I Delay 480
45--TdAS(W)--AS I To WAIT Required Valid - - - - - - - - - - - - 3 4 0 - - - -
Interrupt-Acknowledge Trcmsactions
46 TdAS(DSA) AS I To DS (Acknowledge) I Delay 960
47 TdC(DSA) Clock I To DS (Acknowledge) I Delay 120
48 TdDSA(DR) DS (Acknowledge) I To Read Data Required Valid 420
49 TwDSA DS (Acknowledge) Low Width 485
5O--TdAS(W)--AS I To Wait Required Valid - - - - - - - - - - - - 8 4 0 - - - -
51 TdDSA(W) DS (Acknowledge) I To Wait Required Valid 130
1. Timing for extended addresses IS CPU dependent; however, extended addresses must be valId at least as soon as addresses are vahd on
ADo-ADIS and must remam vahd at least .s long as addresses are vahd on ADO-ADIS.
2. The exact clock cycle that waIt IS sampled on depends on the type of transactIon; however, walt always has the given setup and hold hmes to
the clock.
3. The maxImum value for TdAS(DS) does not apply to Interrupt-Acknowledge TransactIons.
4. Except where otheI'Wlse stated, maximum rIse and fall bmes for mputs are 200 ns.
5. The setup and hold times for WAIT to the clock must be met. 11 WAIT IS generated .synchronously to the clock, It must be synchromzed
before mput to a bus master.
5-15
Memory and
Peripheral
Timing Ci
----~~~~~~------------------------------
ITo-STa. -----, J:++-----------------------~,,_--
8M.NW ________J~++------------------------------------_f'----
.XT.NDED-------...~~---~-,.--------------~---------
ADDR..S____--'~~---~-'---------------~---------
DATA TO
BUS MASTER
ADo-AD18
------.I
lIS
(READ)
lIS
(WRITE)
---------------------------'r~--~~--~~------------
ADO-AD1'
1/0 TransactioE
Timing
Ci ____~X8K~ ____ .X8K~ ______________________________
.iiii _ _ _ ---JX\..____________________________-JX\..________
@
.1l-
.
ADo-ADti )[ ADDRESS FROM
BUS MASTER
OATATO
BUS MASTER
" .1l-
J ~
~
Ji
~
l-
Niii
(WRITE) I
RM
(READ)
J~ \
~
)[ DATA FROM BUS MASTER
X
~
X
Interrupt
Acknowledge
Timing
00-203J-A
5-17
ggslug EgUlgggrlgu
T terconnections
he Z-bus logically and efficiently organizes in-
and transactions between Zilog's
Z8000 microprocessors and their peripherals. The
signals in transactions between microprocessors and
peripherals inherently provide all the necessary tim-
ing, allowing asynchronous operation, so that the
peripheral devices can be independent of the
processor's speed and clock frequencies. In addition,
the bus has a simple scheme-the daisy chain-for
establishing sequential priority, as when a common
system resource must be shared by several processors
and peripherals.
Processors and peripherals engage in five types of
transactions through the Z-bus:
Memory transfers.
I/O transfers
Interrupts requests, to interrupt the Z-bus proc-
essor.
Bus requests, to gain control of the bus for both
memory and I/O transfers
Resource requests, to gain access to a general
resource.
Although memory and I/O transfers are usually
between the Z-bus processor and the memory or a 1. Bus-request signals to the master processor from all
requestors are OR-wired to the BRQ line, and their BAI/BAO
peripheral, some Z-bus-system peripherals, such as a lines are daisy chained to provide a priority sequence (a)_
direct-memory-access controller can initiate transfers The daisy-chain signal is derived from the BUsAcKsignal
after making a successful bus request. delivered by the master processor (b).
The Z-bus system depends on strobe, request and
acknowledge signals to provide the timing information
5-19
D~ta can be formatted in 8 or l6-bit groups, with the resource is busy. A low MMST line indicates busy
memory and I/O addresses that are l6-bits long and additionallnmQs" are blocked. No requestor ca~
(memory addresses in the Z8001 segmented version preempt another, but when simultaneous requests are
can be as long as 24 bits). made for the same resource, the requestor highest on
th~ daisy chain will seize the resource first, all else
An equal-opportunity protocol
,
, ,~,
, " .
\ \ :,",,'1 "", ,I ","''
r.::'b---"":'_-,Q!n'
Unlike the bus-request protocol, the resource-re-
r.;;JH._---c Wm
quest chain is not dominated by a single system ,'i,' .",'
component. To acquire a resource, a component must .....,..... .,.---Ii&ili
issue a request signal, MMRQ low. All MMRQ signals " ",' ' ,vq,...
, , , ".'';","""':::~";":"'~
for a given resource are wire-ORed to a common bus ',: :'(~,.. "i \ ' " :iiiiIiO
line (Fig. 2a). Nevertheless, the resource-requesting , ,: ~:, '\\:;, ,~~,\\f\,<, ;:,:1':
devices are daisy-chain connected, so that a low on 2. The resource-request chain,lIke the bus-request, also
the -mmQ line propagates through the chain-into OR-,,!ires the request signals, in this case MMRQ,and daisy-
each MMAI and out of each MMAO. However, the MMAO chains for priority (a). Several gates, however are needed
of the requesting device remains high. Thus, the to interface a Z8000, which has just two resou~ce-request
ports, Moand M I , with the daisy chain (b).
combination oflYiMRQ low and MMAO high in a device
identifies it as the temporary controller of the re-
source.
Before a component makes a resource request it
first checks the MMST (resource-status) line to se; if
5-20
Z8001/8002 processors: MMAI passes through gate G. Although more than one peripheral may have issued
to MMAO as long as MO is high (not requesting the an interrupt request simultaneously, the request
resource). While MO is high (before making a request), highest on the daisy chain prevails: Its lEO remains
the state of the MMST line passes through G1 and G2 low, aborting any other interrupt requests further
to MT With M, high (MMST is not busy), Mo can issue a down the chain, until lEO drops low.
request. But if another requestor higher had seized Three Wait cycles occur after the leading edge of
the resource first, MMAI would be low and would pass INTACK to allow the daisy chain to settle (or more,
through G1 and G2 to MI to abort the IlP'S request, if a peripheral device asks for it via the WAIT line).
until it could try again. Then, a DS from the IlP stimulates the interrupting
peripheral to place its data on the bus. INTACK returns
Interrupts also are daisy chained high two (or more) Wait cycles later, after completion
of the transaction for which the interrupt was ini-
In the interrupt protocol (as in both the bus-request tiated.
scheme and the resource-request scheme), the device's After INTACK returns high, any requestor on the
physical position in the daisy-chain-in at lEI, out at daisy chain can issue an interrupt; lower-priority
IEO-determines its priority. Also, like bus requests, devices are locked out until higher priority interrupts
interrupt requests are directed to the processor-in have been serviced.
this case, to one of its three interrupt input ports-
NMI, VI, or NVI. A separate set of interrupt-protocol
I/O is main transaction
signals-INT, INTACK, lEI and lEO -control each IlP
interrupt mode that is used. The peripherallN'F ports The main purpose of an interrupt request is to
receive the same treatment as BRQ -the INT lines for perform a transfer of information in or out of the
one of a processor's interrupt modes are all wire-ORed processor. This 1/0 transaction is distinquished from
together (Fig. 3a). The appropriate acknowledgement, every other by the IlP'S status-lines code 0010, desig-
decoded from the four status lines of the IlP (Fig. 3b), nated 1/0 Reference.
returns via the Z-bus' INTACK line to all the daisy- The bus R/W line determines the direction in which
chained peripheral requestors. This procedure tem- the information flows: The processor reads from the
porarily inhibits further interrupt requests. requestor device when R/W is high or writes into the
device when R/W is low. Information flows via the
ADo to AD15 lines of the IlP.
When AS is low, the information being transferred
is addresses; when TIS is low, the information is data.
Word or byte formats are identified by the B/W line
-word format, when low-allowing 16 or 8-bit data
elements (Fig. 4).
This early-status information, which defines the
transaction ahead of the actual process, allows the
enabling of bidirectional drivers and other interface
hardware elements. The enabling action is a distinct
benefit, which simplifies interfacing peripherals.
3. Microprocessor Interrupts from peripherals also use of interrupt (a). The properly decoded status line ofthat
an OR-wired line (iNT) for initiating the sequence and a daisy interrupt from the processor then becomes the INTACK
chain to establish peripheral priorities for a given type signal on the line (b).
5-21
Indeed, the Z8000 processors distinguish between
I/O-transaction and memory/processor-interchange, Z-Bus signal descriptions
modes only by using different status-line codes; other-
wise, the two modes work almost the same way. The
address/data bus, strobe lines AS andM. and theR/W,
MEMORY OR
B/W, and N/S lines are shared by both I/O and ~Rl'HERAL
memory transactions; therefore the interface buffers
_ _ _ _) EXTENlED ADDRESS
can be shared by substantially fewer processor pins.
One difference in the modes-an extended address
capability to 23 bits-applies only to memory, when
<
-----
)
.. lIi
ADo-ADI5
MIm'
to keep up with the processor. .~
}~R
Help for the busy processor
. .. mAli
MMAi
TYPE
5-22
overall system efficiency and speed. It generates into the Z-bus's daisy-chain priority system. As an
almost any control signal that a peripheral device alternative, the controller can be programmed to
might need. Operating on the same 4-MHz clock as operate with a polled system-a concept that is also
the Z8000 !lPS, it executes instructions in an average compatible with the Z-bus.
of just 2 !lS. Not all peripheral interfacing tasks need all the
Not only speed, but flexibility is attained. An intelligence and flexibility that the Z-UPC possesses.
extensive register file of 256 byte-registers, organized Zilog's Counter/Timer and Parallel I/O (Z-CIO), with
into 16 groups of 16 working registers each make the its two independent 8-bit bidirectional I/O ports and
Z-UPC very versatile. Short-format instructions ex- special-purpose 4-bit I/O port, can satisfy most or-
pedite the access to any group. The file includes 234 dinary needs for parallel I/O interfacing and
general-purpose, 19 status-and-control (including two counting/timing (Fig. 6).
16-bit counter/timer) and three I/O-port registers. Either of the Z-CIO's two identical 8-bit I/O ports
Add six levels of priority interrupts and the Z-UPC can operate in a handshake-byte or bit-by-bit mode.
is indeed a flexible support package.
Any general-purpose register can be used as an
accumulator, address pointer, index register or
stack for the the Z-UPC's program. All unused
general-purpose registers can then act as data buffers
between the master processor and the peripheral
device. In addition, communications between the mas-
ter processor and the Z-UPC takes place via one of the
groups of 16 registers, which are accessed directly by
the master processor over the Z-bus Address/Data
(ADx) lines.
Examining the I/O ports
The Z-UPC's three I/O ports also allow great flex-
ibility. Two of the I/O ports are 8-bits each; the third
has 8 bits for I/O that can be shared between I/O and
control lines, as determined by the program. In fact,
all the I/O ports can be programmed in many combina-
tions as input, output or bidirectional lines, with or
6. By taking care of parallel I/O interfacing and counting,
without a handshake protocol. the Z-CIO peripheral-interfacing circuit chip can remove
When its p3 o, p3 z, Pas and P 37 pins are programmed a heavy burden from the processor in a com plex Z8000
as lEI/lEO, lNTACK and lNT lines, the Z-UPC fits easily system.
5. A universal peripheral controller (Z-UPC) can take a when the processor is interfacing peripheral devices that
great amount of the load off a microprocessor, especially demand a lot of detailed attention.
5-23
In the later mode, the direction of each bit can be provides the full complement of bus control signals
individually programmed. Like the universal con- and daisy-chain priority pins (lEI/lEO).
troller, the two ports can perform in the handshake
mode, as inputs, outputs or bidirectional lines; also,
Serial unit supports many protocols
they can be linked into one 16-bit port. In addition,
each of the 8-bit ports includes pattern-recognition Also supporting the Z-bus family is the Z-SCC,
logic to generate an interrupt when a specified pattern Serial Communications Controller, a peripheral-in-
is detected. terfacing package for serial communications or data-
Four handshake protocols are available: the transfer applications (for example, with disks and
IEEE-488, an interlocked (with another Z-CIO or Z- cassettes). The package contains two independent full-
UPC), a strobed and a pulsed. duplex channels, each with its own quartz-crystal
The pulsed handshake connects one of the Z-CIO's oscillator, baud-rate generator and digital phase-
counters with logic, to interface a mechanical device locked loop for clock recovery (to 1 Mbit/s). Each
such as a printer. The special-purpose 4-bit I/O port channel also provides facilities for modem/control
provides the handshake controls: a Wait/Request line (Fig. 7a).
for high-speed data transfer or general-purpose I/O. The Z-SCC is programmable for NRZ, NRZI or FM-
The programming and status for all the control data encoding. A channel in an asynchronous mode
features reside in 12 registers provided for each port. can operate with 5 to 8-bit codes per character plus
The Z-CIO's three, independent, identical 16-bit 1,1-1/2 or 2 bits per character as stop bits. In addition
counter/timers (two of the counters can be pro- the package provides such features as break detection
grammed to form a 32-bit counter/timer) can help to and generation, and parity, overrun and framing error
control a device. Each counter/timer consists of a 16- detection.
bit down-counter and four registers as follows: a 16- In the synchronous mode, the Z-SCC handles such
bit register, to hold the initial value (called the Time protocols as IBM Bisync or bit-oriented HDLC and
Constant), which is loaded into the down-counter;
another 16-bit register, to hold a current down-count
output, when strobed; and two 8-bit registers to hold
mode, control and status information.
Either the counting or the timing function can be
programmed for single-cycle (one-shot) or continuous
operation with a pulse or square-wave output. Up to
four control lines-for gach counter/timer-can act
as the counter input, enable input, trigger input and
counter/timer output, as required.
Whether counting or parallel interfacing, the Z-CIO
can substantially unburden the master processor in
8. The Z-FIO general-purpose bidirectional buffer can
a computer system, especialiy when complex per- interconnect devices operating at different speeds. It is
ipherals demanding high service must be handled. The not limited to Z8000 configurations, butcan handle
Z-CIO is also fully compatible with the Z-bus and almost any general-purpose "p system.
5-24
SDLC with frame-level control, automatic zero-inser-
tion and deletion, I-field residue handling, abort
generation and detection, CRC generation and check-
ing and loop-mode operation. Parity and overrun
features also apply to synchronous operation
Fig. 7b shows one of the Z-SCC's channels connected
as a synchronous data-link-the loop (SDLC) mode.
Note the absence of clock lines. With NRZI or FM
data, no clock lines are needed, since the clock can
be recovered at the receive end from the bit stream
by the Z-SCC's digital phase-locked loop. The other
channel, via a modem under control of the Z-SCC, is
shown servicing an asynchronous serial port.
Basically the Z-SCC functions as a parallel-to-serial
and serial-to-parallel converter, but it does more: Its
sophisticated repertoire of internal functions greatly
reduces the amount of external supporting logic
needed for a wide variety of serial-communications
applications in distributed-processing systems.
Another great saver of external assorted logic in
distributed-processor operation is the Z-FIO general-
purpose bidirectional buffer.
First-in, first-out
The Z-FIO can interconnect components or sub-
systems (of almc.st any ILP including the Z8000)
operating at different speeds. It can accept 128 bytes
of data, which it then holds until they are called for
by another device in the system. In this way, interrupt
servicing time can be cut two orders of magnitude in
most I/O transactions. Moreover, the capability of
moving variable-sized blocks under either direct-
memory access or interrupt control greatly facilitates
system throughput, which is especially important
with fast peripheral circuits.
The internal functions of the Z-FIO are shown in
Fig. 8. Its two sets of Address/Data ports are identical
except for programming. The A set (programmed by
pins Mo and MJ and the B set (programmed by bits
SLo and SL 1) have in common a 128 X 128 RAM for
data storage, two 7-bit counters and several registers.
The RAM can read and write both simultaneously
and independently: The A set can write a byte of data
into the RAM without disturbing a simultaneous read
operation at the B set. The counters address the RAM
and, by means of a subtractor, determine the number
of bytes remaining in the memory. This number can
be read from a status register dedicated to each set.
When compared internally with the memory-status
register, a programmable register generates an inter-
rupt for starting aild stopping DMA transfers. Anoth-
er pair of registers permits direct communication
between the ports by bypassing the main buffer
memory .
5-25
GeDel'a1 6
Zilog
pplication note
SOF'rwARE SERIES
AN OPTIMISING DRIVER
FOR NEe SPINWRITER
AND DIABLO PRINTERS
6-3
An Oplindsing Driver Revision 2. 1
For NEC Splnwriler
And Diablo Prinlen
COIIDIITS
Page
1 INTRODUCTION ~-6
6-5
-----,----~
Spinwriter/Diablo driver Revision 2.1
DlTRODUCTIOR
The features provided by the driver ensure that the printer operates
at its maximum possible speed under all circumstances. Adjacent
spaces and tabs are merged into single head movements, and the
printing direction is fully optimised to minimise unnecessary head
travel. This has the effect not only of raising print speeds, but of
considerably reducing noise and vibration, although this effect will
not be obvious unless two printers are operating near to each other
under different control algorithms.
6-6
Spinwriter/Diablo driver Revision 2.1
In either case, the operation involves the use of the RIO command
ACTIVATE.
Assuming that a NEG Spinwriter is in use, and the files of the disc
supplied have been used without modification, the actual device
driver will be known as $NEC. The command is therefore
%ACTIVATE $NEC
A RIO prompt
AAAAAAAAAAAAA Operator command
%DEFINE 3 $NEC
A RIO prompt
AAAAAAAAAAAAA Operator command
There are several RIO utilities, such as PRINT, and CAT, which
automatically send their output to whatever device has been
associated with LUN=3, and it is recommended that the procedure given
above be used. This adds significantly to the general convenience of
using the system.
6-7
Spinwriter/Diablo driver Revision 2.1
%I $NEC
RIO prompt
Operator command
%ACTIVATE $NEC
Cut sheets ? Y
Auto form feed ? Y
In the above example, the two responses for Yes are shown. Any other
character response apart from Y is interpreted as NO.
%PRINT PRINTER.DRIVER.MANUAL
and the contents of that file will be printed. Obviously the text
actually appearing on the paper will largely reflect exactly what is
contained in the file, but pagenation can be affected by whether the
operator has selected automatic formfeed. The use of cut sheets does
6-8
Spinwriter/Diablo driver Revision 2.1
not affect the printed output, merely the type of paper stock which
can conveniently be used.
ZFORM outputs its formatted text to the system console unless the
operator specifies an alternative. This is particularly convenient,
as most operators would require to view the fully formatted text on
their VDU more frequently than actually printing it.
6-9
Spinwriter/Diablo driver Revision 2.1
such as input files for use by ZFORM for example, and it is then that
the auto formfeed option is likely to be used.
This technique ensures that text files which contain the necessary
control codes for these functions can be printed by printers such as
TALLY, CENTRONICS etc. and by conventional Visual Display Units when
handled by standard" Zilog drivers, with total compatibility.
Obviously these peripherals cannot produce the effects obtainable
when using a Spinwriter, but the text format and content would be the
same. It would perhaps be regarded as a draft quality output which
can be prepared at very high speed.
6-10
Spinwriter/Diablo driver Revision 2.1
The editor can be told to pass the code from the ESCAPE key into its
output file by preceding it with the key labeled '\'. This prevents
the editor from interpreting the code from ESCAPE for its special
function.
Now, let's see exactly what keystroke sequences would have to be used
in order to print the following line of text:-
Notice that that there must not be any character between the <ESC>
and the following attribute control code.
6-11
The printer is interfaced to the host system by the use of one of the
four serial channels provided by an SIB (Serial Interface Board).
SIB modules have a great many link areas enabling the characteristics
of each channel to be tailored to precisely suit the user's needs.
The following link definitions are specific to channel 2, and the
printer driver when operating with either a NEC Spinwriter model
5510/5520, or a DIABLO model 1610/1620.
Clock distribution:-
J3-6 to J3-12
J2-3 to J2-15
J2-3 to J2-16
J7-1 to J7-13
J7-2 to J7-14
J7-3 to J7-11
J7-4 to J7-12
J7-5 to J7-10
J7-6 to J7-9
6-12
Spinwriter/Diablo driver Revision 2.1
J102-7 Ground
J102-B 'spare'
J102-5 Clear To Send -> To printer
J102-6 Data Set Ready -> To printer
J102-20 Data Terminal Ready <- From printer
J102-4 Request To Send <- From printer
Jl02-3 Received data <- From printer
J102-2 Transmitted data -> To printer
The printer driver assumes that a rate of 1200 bauds will be used,
and switches in the printer must be appropriately set. As those
settings depend upon the exact printer model number, it is
impracticable to give them here.
All other links on the SIB are either to be left as when delivered,
or set as required for defining the characteristics of the channels
which are not used by the printer driver
6-13
Spinwriter/Diablo driver Revision 2.1
The tab bits are defined after a call is made to determine the
current tab locations in use by the system console driver. This is
done each time an initialisation request is received by the printer
driver.
After the line and attribute buffers have been loaded, the driver
decides whether the current printhead position is nearer to the left
or right end of the line about to be printed, and is therefore able
to perform an absolute tab to the nearer end, and output the line in
the appropriate direction.
Notice that the driver never issues a carriage-return code to the
printer. It always sends absolute tabs and 1inefeeds. This is due
to the danger of accidently locking the "Auto Linefeed" switch of
some printers, which is sometimes located near to frequently used
controls. Its use would destroy carefully defined formats.
It is expected that any programmer who wishes to understand, or
modify, the driver will be able to do so easily after reading the
module listings. Therefore a blow-by-blow descriptions of the
operation is considered unnecessary.
6-14
Spinwriter/Diablo driver Revision 2.1
MODULE FUNCTION
PRINTER.DRIVER.O ( PLZSYS )
PRINTER.DRIVER.1 ( PLZSYS )
6-15
RIO.IO.INTERFACE ( ASSEMBLER )
SIB ( ASSEMBLER )
CALL.SYSTEM ( ASSEMBLER )
PLZ.INTERFACE.MACROS ( ASSEMBLER
6-16
Spinwriter/Diablo driver Revision 2.1
4 CONCLUSION
Hopefully this note will have given the reader a few ideas about the
use of PLZSYS in association with Assembly Language for 1/0 driver
writing. The author cannot realistically recommend its use if memory
space is at a premium, but certainly does recommend it wholeheartedly
if an objective is to produce intelligible, easily adaptable code
quickly. The entire driver described herein took less than 30
man-hours to design, implement and test.
The source code files for all modules are available from Zilog's
franchised distributors as part of the software library.
6-17
Spinwriter/Diablo driver Revision 2.1
PLZSYS 2.02
1 PRINTER_DRIVER 0 MODULE
2
3 Extended 3/3/79 to allow for subscripting and super scripting
4 Also for operator controlled page-waits and auto formfeed I
5
6
7 TYPE
8
9 RECORD [ LUN BYTE
10 REQ BYTE
11 DTA ~BYTE
12 DTL WORD
13 CRA WORD
14 ERA WORD
15 CCOD BYTE
16 SPV_ADD WORD
17
18 CONSTANT
19
20 INITIALISE .- 0
21 ASSIGN .- %02
22 OPEN .- %04
23 CLOSE .- %06
24 WRITE_BINARY .- %OE
25 WRITE_LINE .- %10
26 READ_LINE .- %OC
27 READ_STATUS .- %40
28 WRITE_STATUS .- %42
29 DEACTIVATE .- %44
30 INVALID_OPERATION_REQUEST .- %C1
31 PROGRAMME_ABORT .- %49
32 GOOD~ETURN .- %80
33 CONIN .- 1
34 CONOUT .- 2
35 ASCII_SPACE .- , ,
36 ASCII_CR .- '%R'
37 ASCII_LF .- '%L'
38 ASCII_FF .- '%P'
39 ASCII_BELL .- %07
40 BLACK .- %01
41 TRUE .- 1
42 FALSE .- 0
43 INTERRUPT_REQUEST_MASK .- %FE
44 TAB_BIT .- %80
45
46 EXTERNAL
47
48 REQUEST_BLACK PROCEDURE
49 GET_CODE PROCEDURE
50 SETCH2 PROCEDURE
51 ABSOLUTE_TAB PROCEDURE ( BYTE
52 FORMFEED PROCEDURE
53 PRINT_LINE_BUFFER PROCEDURE
54 CALRIO PROCEDURE ( BYTE )
A
55 RETURNS ( BYTE )
56 PROCEDURE
57
58 LINE CONTAINS PRINTABLE_CHAR BYTE
59 CODE BYTE
60 ATTRIBUTE_SEQUENCE_FLAG BYTE
61 NEXT_ATTRIBUTE BYTE
62 LINE_FINISHED_FLAG BYTE
63 EOF_FLAG BYTE
64 BYTES_TAKEN_FROM_SOURCE WORD
65 BYTE_COUNT BYTE
66 CONSOLE_STATUS_BUFFER ARRAY 5 BYTE ]
67 LINE_BUFFER ARRAY 163 BYTE
68 LINE_BUFFER_PTR A
BYTE
69
70
71 INTERNAL
72
73 BYTE
74
75 date_code ARRAY [* BYTE .- '%RPrinter Driver rev. 2.1%R'
76 NEW_SHEET_MSG ARRAY [* BYTE ._ 'Load new sheet, hit a key:'
77 BELL_STRING ARRAY [1 BYTE [ ASCII_BELL ]
78 CUT_SHT_QUES ARRAY [* BYTE .- '%RCut sheets?
79 AUTO_FM_FEED_QUES ARRAY [* BYTE .- 'Auto form feed ? '
80 NL_ARRAY ARRAY [* BYTE .- '%R'
81
82
83
84 GLOBAL
85
86 REQUEST_CODE BYTE
87 SOURCE_PTR A
BYTE
88 DATA_LENGTH WORD
89 ABORT_FLAG BYTE
90 AUTO_FF_FLAG BYTE
91 PAGE_WAlT_FLAG BYTE
92
93
94 PROCEDURE UNIT BYTE
95 REQUEST BYTE
96 DATA_ADDRESS ABYTE
97 DATA_LENGTH WORD
98
99 LOCAL RETURN_CODE BYTE
100
101 ENTRY
102 GENERAL_RIO_CALL_VECTOR.LUN := UNIT
103 GENERAL_RIO_CALL_VECTOR.REQ := REQUEST
104 GENERAL_RIO_CALL_VECTOR.DTA := DATA_ADDRESS
105 GENERAL_RIO_CALL_VECTOR.DTL .- DATA_LENGTH
106 GENERAL_RIO_CALL_VECTOR.CRA .- 0
107 GENERAL_RIO_CALL_VECTOR.ERA .- 0
108 GENERAL_RIO_CALL_VECTOR.CCOD .- 0
109 GENERAL_RIO_CALL_VECTOR.SPV_ADD .- 0
110
111 RETURN_CODE := CALRIO ( HGENERAL_RIO_CALL_VECTOR.LUN
112
113 IF RETURN_CODE <> GOOD_RETURN
114 THEN
115 ABORT_FLAG := TRUE
116 FI
117
118
119
120
121 MAYBE3BORT PROCEDURE
122
123 ENTRY
124
125 CONIN
126 READ_STATUS
127 #CONSOLE_STATUS~UFFER[O]
128 1 )
129
130 IF ( CONSOLE_STATUS_BUFFER[O] AND %20 =0
131 THEN
132 ABORT_FLAG : = TRUE
133 FI
134
135 END MAYBE_ABORT
136
137
138 NEWLINE PROCEDURE
139
140 ENTRY
141 CALL_RIO CONOUT
142 WRITE_BINARY
143 iINL_ARRA Y[ 0 ]
144 SIZEOF NL_ARRAY
145
146 END NEWLINE
147
148
149 PROCEDURE
150
151 ENTRY
152 CALLJIO CONIN
153 READ_LINE
154 UNPUT_CHAR
155 1 )
156
157 IF INPUT_CHAR <> '%R' THEN NEWLINE FI
158
159
160
161
162 PROCEDURE
163
164 ENTRY
165 CALL_RIO CONOUT
166 WRITE_BINARY
167 #NEW_SHEET_MSG[O]
168 SIZEOF NEW_SHEET_MSG + SIZEOF BELL_STRING
169 GET_CHAR
170 IF INPUT_CHAR
171 CASE 'C' 'c'
172 THEN
173 PAGE_WAlT_FLAG .- FALSE
174 NEWLINE
175 FI
176
177
178
179
180 PROCEDURE
181
182 ENTRY
183 CALL_RIO CON OUT
184 WRITE BINARY
185 Ifdate=code[O]
186 SIZEOF date_code
187
188 CON OUT
189 WRITE_BINARY
190 #CUT_SHT_QUES[O]
191 SIZEOF CUT_SHT_QUES
192
193 GET_CHAR
194 PAGE_WAlT_FLAG := FALSE
195 IF INPUT_CHAR
196 CASE 'Y' 'y'
197 THEN PAGE_WAIT FLAG ._ TRUE
198 FI
199 CONOUT
200 WRITE_BINARY
201 #AUTO_FM_FEED_QUES[O]
202 SIZEOF AUTO_FM_FEED_QUES
203
204 GET_CHAR
205 AUTO_FF_FLAG := FALSE
206 IF INPUT_CHAR
207 CASE 'Y' 'y'
208 THEN AUTO_FF_FLAG := TRUE
209 FI
210 NEWLINE
211 NEWLINE
212
213
214
215
216 GET_TAB_LOCATIONS PROCEDURE
217
218 LOCAL COUNTER BYTE
219
220 ENTRY
221 CALL_RIO ( CONIN
222 READ_STATUS
223 #CONSOLE_STATUS_BUFFER[O]
224 139 )
225
226 COUNTER := 0
227 LINE_BUFFER_PTR := # LINE_BUFFER [0]
228 DO
229 IF COUNTER = 163 THEN EXIT FI
230 IF COUNTER < 134
231 THEN
232 IF LINE_BUFFER_PTR <> 0 A
233 THEN
234 LINE_BUFFER_PTR A
._ TAB_BIT
235 ELSE
236 LINE_BUFFER_PTR A
.- 0
237 FI
238
239 ELSE
240 LINE_BUFFER_PTR A
:= TAB_BIT
241 FI
242
243 LINE~UFFER_PTR := INC LINE_BUFFER_PTR
244 COUNTER += 1
245 OD
246
247 CLEAR_LINE~UFFER
248
249 END GET_TAB_LOCATIONS
250
251
252 PROCEDURE
253
254 ENTRY
255 IF PAGE_WAlT_FLAG = TRUE
256 THEN
257 PAGE_WAlT_FLAG := FALSE
258 FORMFEED
259 PAGE_WAlT_FLAG := TRUE
260 ELSE
261 FORMFEED
262 FI
263
264
265
266
267 PLZDVR
268
269 ENTRY
270 REQUEST_CODE := VECTOR_PTRA.REQ AND INTERRUPT_REQUEST_MASK
271 SOURCE_PTR := VECTOR-fTRA.DTA
272 DATA_LENGTH := VECTOR-fTRA.DTL
273
274 VECTOR_PTRA.CCOD := GOOD_RETURN
275 VECTOR_PTRA.DTL := 0
276
277 BYTES_TAKEN_FROM_SOURCE := 0
278 EOF_FLAG := FALSE
279 ABORT_FLAG := FALSE
280
281
282
283 CASE INITIALISE
284 THEN
285 SETCH2
286 BYTE_COUNT : = 0
287 ABSOLUTE_TAB (1)
288 EJECT_PAGE
289 ATTRIBUTE~EQUENCE_FLAG := FALSE
290 NEXT_ATTRIBUTE := BLACK
291 REQUEST..J3LACK
292 GET_TAB_LOCATIONS
293 GETJLAGS
294
295 RETURN
296
297 CASE ASSIGN
298 THEN
299 RETURN
300
301 CASE OPEN
302 THEN
303 GET_TAB-LOCATIONS
304 RETURN
305
306 CASE CLOSE,DEACTIVATE
307 THEN
308 ABSOLUTE_TAB (1)
309 EJECT_PAGE
310 RETURN
311
312 CASE WRITE..J3INARY
313 THEN
314 DO
315 IF DATA-LENGTH = BYTES_TAKENJROM-SOURCE
316 THEN
317 EXIT
318 FI
319 GET_CODE
320 IF EOF-fLAG = TRUE
321 THEN
322 EXIT
323 FI
324 IF ABORT-fLAG = TRUE
325 THEN
326 VECTOR-fTRA.CCOD
327 EJECT-fAGE
328 EXIT
329 FI
330 OD
331
332 VECTOR-fTRA.DTL := BYTES_TAKEN-fRO~SOURCE
333 RETURN
334
335 CASE WRITEJ.INE
336 THEN
337 LINE_CONTAINS-fRINTABLE_CHAR := FALSE
338 DO
339 IF DATAJ.ENGTH = BYTES_TAKEN-fROM_SOURCE
340 THEN
341 PRINT_LINE~UFFER
342 EXIT
343 FI
344
345 GET_CODE
346 IF CODE = ASCII_CR THEN EXIT FI
347 IF ABORT_FLAG = TRUE
348 THEN
349 VECTOR-fTRA.CCOD := PROGRAMM&-ABORT
350 EJECT_PAGE
351 EXIT
352 FI
353 OD
354
355 VECTOR-fTRA.DTL := BYTES_TAKEN-fRO~SOURCE
356
357 RETURN
358
359 ELSE
360
361
362
363 FI
364
365 END PLZDVR
366
367 END PRINTER_DRIVER_O
END OF ZCODE GENERATION
o ERROR(S) 0 WARNING(S)
PLZSYS 2.02
1 PRINTER-DRIVER_1 MODULE
2
3 Extended 3/3/79 to allow for subscripting and super scripting
4
5
6 CONSTANT
7
8 TRUE .- 1
9 FALSE .- 0
10
11 ASCII_SPACE .- , ,
12 ASCII_TAB .- %09
13 ASCII_BS ..-- %08
14 ASCII_ESC %1B
15 ASCII_FF .- %OC
16 ASCII_CR .- '%R'
17 ASCICLF .- '%L'
18 ASCII_CONTROL_R .- %12 COLOUR CHANGE
19 ASCICCONTROL_B ' - %02 BOLD !
20 ASCII_CONTROL_U .- %15 UNDERLINE I
21 ASCII_CONTROL_N .- %OE SUPERSCRIPT
22 ASCII_CONTROL_F .- %06 SUBSCRIPT !
23
24 BLACK .- %01
25 RED := NOT BLACK
26 BOLD .- %02
27 NOT_BOLD ._ NOT BOLD
28 UNDERLINE .- %04
29 NOT_UNDERLINE .- NOT UNDERLINE
30 SUPERSCRIPT .- %08
31 NOT---SUPERSCRIPT ._ NOT SUPERSCRIPT
32 SUBSCRIPT .- %10
33 NOT_SUBSCRIPT ._ NOT SUBSCRIPT
34
35 TAB_MASK .- %80
36 PARITY_MASK .- %7F
37
38 EXTERNAL
39
40 PRINTER_WIDTH BYTE
41 PRINT_LINE_BUFFER PROCEDURE
42 FORMFEED PROCEDURE
43 LINEFEED PROCEDURE
44 MAYBE_ABORT PROCEDURE
45
46 ~BYTE
47
48
49 GLOBAL
50
51 CODE BYTE
52 BYTES_TAKEN FROM SOURCE WORD
88 OR ASCICSPACE
89 LINE_BUFFER_PTR := INC LINE_BUFFER_PTR
90 COLUMN_NO += 1
91 OD
92
93
94
95
96 PROCEDURE
97
98 ENTRY
99 LINE_BUFFER_PTR A
:= ( LINE_BUFFER_PTR AND TAB_MASK
A
100 OR CODE
101 ATTRIBUTE BUFFER_PTR A
:= NEXT_ATTRIBUTE
102
103 IF LINE_CONTAINS_PRINTABLE_CHAR = FALSE
104 THEN
105 LEFTMOST_PRINTABLE_COLUMN .- COLUMN_NO
106
107 FI
108
109 RIGHTMOST_PRINTABLE_COLUMN := COLUM~O
110 COLUMNJO += 1
111 LINE~UFFER-?TR := INC LINE_BUFFER_PTR
112 ATTRIBUTE_BUFFE~PTR := INC ATTRIBUTE~UFFER_PTR
113
114 END PUT_COD~INTO~INE~UFFER
115
116
117 PROCEDURE
118
119 ENTRY
120 DO
121 LINE~UFFER_PTR := INC LINE~UFFER_PTR
122 ATTRIBUTE_BUFFER_PTR A := NEXT_ATTRIBUTE
123 ATTRIBUTE~UFFER-?TR := INC ATTRIBUTE~UFFER_PTR
124 COLUMNJO += 1
125 IF ( LINE~UFFER_PTRA AND TAB_MASK ) <> 0
126 THEN
127 RETURN
128 FI
129 OD
130
131
132
133
134 FETCUTTRIBUTE PROCEDURE
135
136 ENTRY
137 ATTRIBUTE_SEQUENCE-fLAG := FALSE
138
139 IF CODE
140
141 CASE ASCII_CONTROL~
142 THEN
143 IF NEXT~TTRIBUTE AND BLACK <> 0
144 THEN
145 NEXT~TTRIBUTE := NEXT~TTRIBUTE AND RED
146 ELSE
147 NEXT_ATTRIBUTE := NEXT~TTRIBUTE OR BLACK
148 FI
149
150 CASE ASCII_CONTROL~
151 THEN
152 IF NEXT~TTRIBUTE AND BOLD <> 0
153 THEN
154 NEXT_ATTRIBUTE := NEXT~TTRIBUTE AND NOT~OLD
155 ELSE
156 NEXT~TTRIBUTE := NEXT~TTRIBUTE OR BOLD
157 FI
158
201
202 IF CODE = %FF
203 THEN
204 EOF_FLAG . - TRUE
205 RETURN
206 FI
207
208 CODE := CODE AND PARITY MASK
209 SOURCE_PTR := INC SOURCE_PTR
210 BYTES_TAKEN_FROM_SOURCE +=
211 IF ATTRIBUTE_SEQUENCE_FLAG = TRUE
212 THEN
213 FETCH_ATTRIBUTE
214 RETURN
215 FI
216 IF CODE > ASCII_SPACE
217 THEN
218 PUT_CODE_INTO_LINE_BUFFER
219 RETURN
220 FI
221 IF CODE
222
223 CASE ASCII_SPACE
224 THEN
225 LINE~UFFER_PTR := INC LINE~UFFER~TR
226 ATTRIBUTE_BUFFER_PTR~ := NEXT~TTRIBUTE
227 ATTRIBUTE_BUFFER_PTR := INC ATTRIBUTE_BUFFER_PTR
228 COLUMN_NO += 1
229
230 CASE ASCII_CR
231 THEN
232 PRINT_LINE_BUFFER
233 LINEFEED
234 MAYBE~BORT
235
236 CASE ASCIIJ'F
237 THEN
238 PRINT~INE_BUFFER
239 FORMFEED
240 MAYBE_ABORT
241
242 CASE ASCII_LF
243 THEN
244 PRINT_LINE~UFFER
245 LINEFEED
246 MAYBE_ABORT
247
248 CASE ASCII_TAB
249 THEN
250 GOT_TAB
251
252 CASE ASCIIJ;SC
253 THEN
254 ATTRIBUTE_SEQUENCE_FLAG := TRUE
255
256 FI
257
258
259
260
261 END PRINTER-PRIVER_1
END OF ZCODE GENERATION
o ERROR(S) 0 WARNING(S)
PLZSYS 2.02
1 PRINTER_DRIVER_2 MODULE
2
3 CONSTANT
4
5 ASCICSPACE := ' ,
6
7 PARITY_MASK := %7F
8 FORWARD := 1
9 BACKWARD := 0
10
11 TRUE := 1
12 FALSE := 0
13
14 := %10
15
16 EXTERNAL
17
18 LEFTMOST-YRINTABLE_COLUMN BYTE
19 RIGHTMOST-YRINTABLE_COLUMN BYTE
20 PRESENT_COLUMN BYTE
21 DIRECTION BYTE
22 CHARS_IN_LINE_BUFFER BYTE
23 LINE_BUFFER_PTR ABYTE
24 ATTRIBUTE~UFFER_PTR
ABYTE
25 ATTRIBUTE BYTE
26 REQUEST_CODE BYTE
27 LINE_CONTAINS_PRINTABLE_CHAR BYTE
28
29
30 LINE_BUFFER ARRAY 163 BYTE ]
31 ATTRIBUTE~~FFER ARRAY 163 BYTE ]
32
33
34 ABSOLUTE_TAB PROCEDURE BYTE)
35 SEND PROCEDURE BYTE )
36 PRINT PROCEDURE BYTE BYTE
37 ! CHAR, ATTRIBUTE
38
39 REQUESTJORWARD PROCEDURE
40 REQUEST_BACKWARD PROCEDURE
41 WAIT_FORJCK PROCEDURE
42 CLEAR_LINE_BUFFER PROCEDURE
43
44
45 INTERNAL
46
47 CHAR BYTE
48 COLUMN_NO BYTE
49 NEXT_COLUMN_NO BYTE
50 SPACE_COUNT BYTE
51 SPACE_SKIP_FLAG BYTE
52
53
54 PROCEDURE
55
56 ENTRY
57
58 IF LEFTMOST-YRINTABL~COLUMN > PRESENT_COLUMN
59 THEN
60 ABSOLUTE_TAB ( LEFTMOST-YRINTABL~COLUMN
61 REQUEST_FORWARD
62 RETURN
63 FI
64
65 IF PRESENT_COLUMN > RIGHTMOST-YRINTABLE_COLUMN
66 THEN
67 ABSOLUTE_TAB ( RIGHTMOST-YRINTABLE_COLUMN
68 REQUEST~ACKWARD
69 RETURN
70 FI
71
72 IF (RIGHTMOST-YRINTABL~COLUMN - PRESENT_COLUMN
73 > ( PRESENT_COLUMN - LEFTMOST_PRINTABL~COLUMN
74 THEN
75 ABSOLUTE_TAB ( LEFTMOST_PRINT ABLE_COLUMN
76 REQUEST_FORWARD
77 RETURN
78 FI
79
80 ABSOLUTE_TAB ( RIGHTMOST_PRINT ABLE_COLUMN
81 REQUEST~ACKWARD
82
83
84
85
86 GLOBAL
87
88
89 PRINT~INE~UFFER PROCEDURE
90
91 ENTRY
92
93 IF LINE_CONTAINS-YRINTABLE_CHAR = FALSE
94 THEN
95 CLEAR~INE_BUFFER RETURN
96 ELSE
97 CHARS-lN~INE~UFFER .- RIGHTMOST_PRINTABL~COLUMN
98 - LEFTMOST-YRINTABL~COLUMN + 1
99 FI
100
101 SET_UP-PIRECTION
102 LINE_BUFFER_PTR := HLINE~UFFER [ PRESENT_COLUMN-1 ]
103 ATTRIBUTE_BUFFER_PTR := HATTRIBUTE_BUFFER [ PRESENT_COLUMN-1
104 NEXT_COLUMN_NO := PRESENT_COLUMN
105 SPACE_SKIP_FLAG := FALSE
6-31 PRINTER.DRIVER.2
Spinwriter/Diablo driver Revision 2.1
106 SPACE_COUNT := 0
107 DO
108
109 IF CHARS-lN~INE~UFFER =0
110 THEN
111 CLEAR~INE~UFFER
112 RETURN
113 FI
114
115
116 COLU~O := NEXT_COLUMN_NO
117 CHAR := LINE_BUFFER_PTR A AND PARITY_MASK
118 ATTRIBUTE := ATTRIBUTE~UFFE~TRA
119 IF DIRECTION = BACKWARD
120 THEN
121 LINE_BUFFER-fTR := DEC LINE_BUFFER_PTR
122 ATTRIBUTE_BUFFE~TR := DEC ATTRIBUTE~UFFER-PTR
123 NEXT_COLUMN~O -= 1
124 ELSE
125 LINE~UFFER-fTR := INC LINE~UFFER_PTR /
126 ATTRIBUTE_BUFFER_PTR := INC ATTRIBUTE_BUFFER_PTR
127 NEXT_COLUMN~O += 1
128 FI
129
130 CHARS-lN~INE~UFFER -=
131
132 IF CHAR = ASCII_SPACE
133 THEN
134 IF SPACE_SKIP_FLAG = FALSE
135 THEN
136 SPACE_SKIP-1LAG := TRUE
137 SPACE_COUNT := 1
138 REPEAT
139 FI
140
141 SPACE_COUNT +=
142 REPEAT
143 FI
144
145 IF SPACE~KIP-1LAG = TRUE
146 THEN
147 SPACE_SKIP-1LAG := FALSE
148 IF SPACE_COUNT >= 3
149 THEN
150 ABSOLUTE_TAB ( COLUMN_NO
151 ELSE
152 DO
153 IF SPACE_COUNT = 0 THEN EXIT FI
154 PRINT ( ASCII_SPACE ATTRIBUTE )
155
156
157 OD
158 FI
159 FI
160
161 PRINT ( CHAR ATTRIBUTE )
162
163 OD
164
165 END PRINT_LINE_BUFFER
166
167
168
169 END PRINTER_DRIVER_2
END OF ZCODE GENERATION
o ERROR(S) 0 WARNING(S)
PLZSYS 2.02
1 SPINWRITER MODULE
2
3 Extended 3/3/79 to allow for subscripting and super scripting
4 Also for page-waits and controllable auto-form feed !
5
6
7 CONSTANT
8
9
10 PRINTER_BUFFER_SIZE := 256
11 PITCH _ 12
12 SS - 120/PITCH
13
14 ASCII_ETX .- %03
15 ASCII_ACK .- %06
16 ASCII_ESC .- %1B
17 ASCICFF .- %OC
18 ASCICBS .- %08
19 ASCICUL .- f f
20 ASCII_SPACE .- f f
21
22 PARITY_MASK .- %7F
23
24 FORWARD .- 1
25 BACKWARD .- 0
26
27 BLACK ._ %01
28 BOLD .- %02
29 UNDERLINE .- %04
30 SUPERSCRIPT ._ %08
31 NOT_SUPERSCRIPT := NOT SUPERSCRIPT
32 SUBSCRIPT := %10
33 NOT_SUBSCRIPT := NOT SUBSCRIPT
34
35 TRUE - 1
36 FALSE .- 0
37
38
39 INTERNAL
40
41 LINE_COUNT BYTE
42 COLOUR BYTE
43 HMI BYTE
44 SUBSCRIPT_FLAG BYTE
45 SUPERSCRIPT_FLAG BYTE
46
47 LAST_SCRIPT_STATE BYTE
48
49
50 EXTERNAL
51
52 OUTCH2 PROCEDURE ( BYTE )
159 RETURN
160 FI
161 FI
162
163 SEND ( '%L' )
164 LINE_COUNT +=
165 END LINEFEED
166
167
168 REQUEST_FORWARD PROCEDURE
169 ENTRY
170 IF DIRECTION = FORWARD THEN RETURN FI
171 SEND ( ASCII_ESC ) .
172 SEND ( ,>, )
173 DIRECTION := FORWARD
174 END REQUEST_FORWARD
175
176
177 REQUEST_BACKWARD PROCEDURE
178 ENTRY
179 IF DIRECTION = BACKWARD THEN RETURN FI
180 SEND ( ASCII_ESC )
181 SEND ( ,<, )
182 DIRECTION := BACKWARD
183 END REQUEST~ACKWARD
184
185
186 REQUEST~LACK PROCEDURE
187 ENTRY
188 SEND ( ASCII_ESC
189 SEND ( '4' )
190 COLOUR : = BLACK
191 END REQUEST_BLACK
192
193
194 REQUEST_RED PROCEDURE
195 ENTRY
196 SEND ( ASCII_ESC
197 SEND ( '3' )
198 COLOUR := 0
199 END REQUEST_RED
200
201
202 DEFINE_HMI PROCEDURE ( SPACING BYTE )
203 ENTRY
204 SEND ( ASCII~SC )
205 SEND ( 'l' )
206 SEND ( SPACING + %40
207 END DEFINE_HMI
208
209
210 SEND_BOLD_CHAR PROCEDURE ( CHAR BYTE ATTRIBUTE BYTE )
211 ENTRY
~~~~-------- ---
Spinwriter/Diablo driver Revision 2.1
PLZSYS 2.02
1 DIABLO MODULE
2
3 Extended 3/3/79 to allow for subscripting and super scripting I
4 Also for operator controlled page_waits, and auto formfeeds. I
5
6 CONSTANT
7
8
9 PRINTER~UFFER-SIZE .- 158
10 PITCH .- 12
11 SS .- 120/PITCH
12
13
14
ASCIIJ;TX
ASCIIJ,CK
- %06
.-
%03
15 ASCIIJ;SC .- %1B
16 ASCIIJ'F .- %OC
17 ASCII~S .- %08
18 ASCII_UL .- ,, ,,
19 ASCII-SPACE .-
20 ASCII_US .- %1F
21 ASCII_TAB .- %09
22
23 PARITY_MASK .- %7F
24
25 FORWARD .- 1
26 BACKWARD .- 0
27
28 BLACK .- %01
29 BOLD .- %02
30 UNDERLINE .- %04
31
32
33
SUPERSCRIPT
NOT_SUPERSCRIPT
- %08
:= NOT SUPERSCRIPT
34 SUBSCRIPT := %10
35 NOT_SUBSCRIPT := NOT SUBSCRIPT
36
37
38
TRUE
FALSE
-
:= 0
1
39
40 INTERNAL
41
42 LINE_COUNT BYTE
43 COLOUR BYTE
44 HMI BYTE
45
46 SUPERSCRIPTJ'LAG BYTE
47 SUBSCRIPT_FLAG BYTE
48
49 LAST-SCRIPT-STATE BYTE
50
51
52 EXTERNAL
53
54 OUTCH2 PROCEDURE ( BYTE )
55 INCH2 PROCEDURE RETURNS ( BYTE )
56
57 PROCEDURE
58
59 PAGE_WAlT_FLAG BYTE
60 AUTO]F]LAG BYTE
61
62 GLOBAL
63
64 PRINTER_WIDTH BYTE .- 158
65 DIRECTION BYTE
66 PRESENT_COLUMN BYTE
67 AUTO_FF_LINE_COUNT BYTE .- 63
68 BYTE_COUNT BYTE
69
70
71
72 SEND_ETX PROCEDURE
73 ENTRY
74 OUTCH2 ( ASCII_ETX
75 BYTE_COUNT : = 0
76 END SEND_ETX
77
78
79 WAIT_FOR_ACK PROCEDURE
80 ENTRY
81 DO
82 IF ( INCH2 AND PARITY_MASK = ASCII_ACK
83 THEN
84 RETURN
85 FI
86 OD
87 END WAIT_FOR_ACK
88
89
90 SYNCH PROCEDURE
91 ENTRY
92 IF BYTE_COUNT < PRINTER_BUFFER_SIZE - 10 THEN RETURN FI
93 SEND_ETX
94 WAIT_FORj,CK
95 END SYNCH
96
97
98 SEND PROCEDURE ( CODE BYTE
99 ENTRY
100 IF BYTE_COUNT > PRINTER_BUFFER_SIZE - 10
101 THEN
102 SEND_ETX
103 WAIT_FOR_ACK
104 FI
105 BYTE_COUNT += 1
265 RESIDUE -=
266 OD
267
268 END ABSOLUTE_TAB
269
270
271 PRINT PROCEDURE ( CHAR BYTE ATTRIBUTE BYTE )
272 ENTRY
273
274
275 DO
276 IF ATTRIBUTE AND (SUBSCRIPT OR SUPERSCRIPT)
277 = LAST_SCRIPT_STATE
278 THEN
279 EXIT
280 FI
281
282 IF ATTRIBUTE AND SUPERSCRIPT <> 0
283 THEN
284 IF SUBSCRIPT_FLAG = TRUE
285 THEN
286 REQUEST-NEG_HALF~INE
287 SUBSCRIPT_FLAG := FALSE
288 FI
289 REQUEST_NEG_HALF_LINE
290 SUPERSCRIPT_FLAG := TRUE
291 EXIT
292 FI
293
294 IF ATTRIBUTE AND SUBSCRIPT <> 0
295 THEN
296 IF SUPERSCRIPT_FLAG = TRUE
297 THEN
298 REQUEST-?OS_HALF_LINE
299 SUPERSCRIPT_FLAG := FALSE
300 FI
301 REQUEST_POS_HALF_LINE
302 SUBSCRIPT_FLAG := TRUE
303 EXIT
304 FI
305
306 IF SUPERSCRIPT-fLAG = TRUE
307 THEN
308 REQUEST_POS_HALF_LINE
309 SUPERSCRIPT-fLAG := FALSE
310 EXIT
311 FI
312
313 REQUEST_NEG_HALF~INE
314 SUBSCRIPT_FLAG := FALSE
315 EXIT
316
317 00
318
319 LAST_SCRIPT-STATE
320 := ATTRIBUTE AND ( SUPERSCRIPT OR SUBSCRIPT
321 IF ( ATTRIBUTE AND BLACK ) <> COLOUR
322 THEN
323 IF ( ATTRIBUTE AND BLACK ) = BLACK
324 THEN
325 REQUEST_BLACK
326 ELSE
327 REQUESTJ!ED
328 FI
329 FI
330
331 IF CHAR > ASCII_SPACE
332 THEN
333 IF ATTRIBUTE AND BOLD <> 0
334 THEN
335 SEND_BOLD_CHAR ( CHAR ATTRIBUTE
336 ELSE
337 IF ( ATTRIBUTE AND UNDERLINE ) <> 0
338 THEN
339 DEFINE~I ( 0 )
340 SEND ( CHAR )
341 DEFINEJlMI ( SS
342 SEND ( ASCICUL
343 ELSE
344 SEND ( CHAR )
345 FI
346
347 FI
348 ELSE
349 SEND ( CHAR) I SPACES WILL NOT BE UNDERLINED I
350 FI
351
352 IF DIRECTION = BACKWARD
353 THEN
354 PRESENT_COLUMN -=
355 ELSE
356 PRESENT_COLUMN +=
357 FI
358
359 IF PRESENT_COLUMN = 0 THEN PRESENT_COLUMN += 1 FI
360
361
362 END PRINT
363
364
365
366 END DIABLO
END OF ZCODE GENERATION
o ERROR(S) 0 WARNING(S)
145
146 global CALRIO calrio
147
148 SYSTEM EQU 1403H
149
150
151 CALRIO
152 calrio
0000 153 ENT 0 no locals
154
0008 155 LDHL 4 put RIO vector address into hI
OOOE E5 156 push hI
OOOF FDE1 157 pop iy and then where it should be
158
0011 DDE5 159 push ix save it
0013 CD0314 160 call SYSTEM go and do the necessary
0016 DDE1 161 pop ix restore it
162
0018 FD7EOA 163 ld a,(iy+10) j get the completion code
001B 164 STA 6 and place it as return parameter
165
001E 166 RTN 0 2 return to caller. 0 locals,2 liP param bytes
167
168
169 END
1 *H RIO.IO.INTERFACE
2
3
4 Date_code:- October 31st. 1978
5
6 This interface module receives 1/0 calls from RIO, and
7 passes the IY register value to the called programme
8 as a single parameter.
9
10 The intention of the module is to act as an interface
11 to enable 1/0 drivers to be written largely in PLZ.
12
13
14 EXTERNAL PLZDVR
15
16 GLOBAL ENTRY entry
17
18 ENTRY
19 entry
20
0000 FDE5 21 push iy the actual parameter
22
0002 FD223000 R 23 save iy
24
0006 CDOOOO X 25 call PLZDVR pass control to the driver proper
26
0009 FD2A3000 R 27 restore iy
28
OOOD FDCB0146 29 bit O,(iy+1) was it int.req ?
0011 FD7EOA 30 Id a,(iy+10) get c_code
0014 200E 31 jr nz,intreq
0016 FE80 32 cp 80h was it good?
0018 C8 33 ret z if so, go back quietly
34 getera
0019 FD6609 35 Id h, (iy+9)
001C FD6E08 36 Id 1, (iy+8)
37 jmpret
001F 7C 38 Id a,h
0020 B5 39 or 1
0021 C8 40 ret z rtn add field was zero
0022 C1 41 pop bc balance stack
0023 E9 42 jp (hl)
0024 FE80 43 intreq cp 80h
0026 20F1 44 jr nz,getera
0028 FD6607 45 Id h, (iy+7)
002B FD6E06 46 Id 1, (iy+6)
002E 18EF 47 jr jmpret check cra field
48
49
50
0030 51 defs 2
52
53 end
174 *E
175
176 SETCH2
177 setch2
0000 178 ENT 0
179
0008 CD9400 R 180 call BAUDR set up the baud rate
OOOB CD7BOO R 181 call SUART2 set up USART-2
182
OOOE 183 RTN 0 0 no locals, no IN parameters
184
185
186 OUTCH2
187 outch2
0011 188 ENT 0
189
0019 190 LDA 4 get the code for issuing
001C CDA600 R 191 call OUSIB2 send it with wait ready
192
001F 193 RTN 0 2 no locals, 2 bytes IN
194
195
196 INCH2
197 inch2
0024 198 ENT 0
199
002C CD9DOO R 200 call INSIB2 get the code, with wait ready
002F 201 STA 4 place it as return parameter
202
0032 203 RTN 0 0 no locals, no IN parameters
204
205
206 INCH2E
207 inch2e
0035 208 ENT 0
209
003D CD9DOO R 210 call INSIB2 get the code, with wait ready
0040 CDA600 R 211 call OUSIB2 echo it, with wait ready
0043 212 STA 4 place code as return parameter
213
0046 214 RTN 0 0 no locals, no IN parameters
215
216
217 STACH2
218 stach2
0049 219 ENT 0
220
0051 DB91 221 in a,(USART2+1) get the status reg contents
0053 222 STA 4 place it as return parameter
223
297
298 TIMMOD EQU 07H TIMER MODE, PRESCALER=16
299 INT.DISABLED, RESET
300
301 RATEO EQU 4 FOR 1200 BAUDS
302
303
304
305 ,
306 , ELEMENTARY CHARACTER LEVEL 1/0
307 ,. * * *.** *.
308
009D DB91 309 INSIB2 IN A,(USART2+1) GET STATUS REGISTER
009F CB4F 310 BIT RXRDY,A IS THE RECEIVER FLAG SET
OOAl 28FA 311 JR Z,INSIB2 IF NOT, WAIT FOR IT
00A3 DB90 312 IN A, (USART2) GET CONTENT OF DATA REGISTER
00A5 C9 313 RET
314
315
00A6 F5 316 OUSIB2 PUSH AF SAVE CHARACTER
00A7 DB91 317 BZY IN A, (USART2+1) GET STATUS REGISTER
00A9 CB47 318 BIT TXRDY,A TEST THE TRANSMITTER READY FLAG
OOAB 28FA 319 JR Z,BZY IF UNREADY THEN WAIT
OOAD Fl 320 POP AF RESTORE CHARACTER CODE
OOAE D390 321 OUT (USART2) ,A SEND IT
OOBO C9 322 RET
323
324
325 RXRDY EQU 1 RECEIVER READY BIT
326 TXRDY EQU 0 TRANSMITTER READY BIT
327
PLZ.INTERFACE.MACROS PAGE 1
LOC OBJ CODE M STMT SOURCE STATEMENT ASM 5.8
1 ;-LIST OFF
2
3
4 Mark-stack macro:
5
6 Allocate room on stack for out parameters
7 before a procedure call.
8
9 Optimise the code when 0,1,or 2 parameters
10 ie. 0,2 or 4 bytes.
11
12 MST macro In ; In is in BYTES _..
13 cond (/n=2).or.(/n=4)
14 push hl
15 cond In=4
16 push hl
17 endc
18 cond .not. (/n=O) . and . not. (/n=2) and not. (In=4)
19 ld hl,-/n
20 add hl,sp
21 ld sp,hl
22 endc
23 endm
PLZ.INTERFACE.MACROS PAGE 2
LOC OBJ CODE M STMT SOURCE STATEMENT ASM 5.8
24 *E
25
26 Procedure entry:
27
28 Allocate locals on stack ( No. of bytes)
29
30 Optimise when 0,2,or 4 bytes.
31
32 ENT macro lin ; #n is in BYTES ***
33 push ix
34 ld ix,O
35 add ix,sp
36 cond (#n=2).or.(#n=4)
37 push hI
38 cond Iln=4
39 push hI
40 endc
41 cond . not. (#n=O) . and .. not. (l/n=2) . and .. not. (lln=4)
42 ld hl,-Iln
43 add hl,sp
44 ld sp,hl
45 endc
46 endm
PLZ.INTERFACE.MACROS PAGE 3
LOC OBJ CODE M STMT SOURCE STATEMENT ASM 5.8
47 *E
48
49 Procedure return:
50
51 Deallocate locals ( bytes) and IN parameters.
52
53 Optimise when 0,2,or 4 bytes.
54
55 RTN macro IL, In ; fL, In are in BYTES ***
56
57 cond #L
58 ld sp,ix
59 endc
60
61 pop ix
62
63 cond I#n=O
64 ret
65 endc
66
67 cond (I#n=2).or.(fln=4)
68 pop hl
69 pop de
70
71 cond fn=4
72 pop de
73 endc
74
75 cond (In=2) .or.(fn=4)
76 jp (hl)
77 endc
78
79 cond .not.(ln=O) .and . not.(fln=2) .and not.(fln=4)
80 pop de
81 ld hl,fln
82 add hl,sp
83 ld sp,hl
84 ex de,hl
85 jp (hl)
86 endc
87
88 endm
- - - - - - - - .. ~. ~~.~-.-
Spinwriter/Diablo driver Revision 2.1
PLZ.INTERFACE.MACROS PAGE 4
LOC OBJ CODE M STHT SOURCE STATEMENT ASH 5.8
89
90
91 Macros for accessing locals and parameters
92 from the stack.
93
94 This is only a small selection.
95
96
91
98 ; Load hI from In ( offset of word variable from ix )
99
100 LDHL macro In
101 ld l,(ix+ln)
102 ld h, (ix+ln+1)
103 endm
104
105
106
107 ; Store hI into In ( offset of word variable from ix )
108
109 STHL macro In
110 ld (ix+#n),l
111 ld (ix+ln+1),h
112 endm
113
114
115
116 ; Load A from In ( offset of byte variable from ix
117
118 LDA macro In
119 ld a,(ix+ln)
120 endm
121
122
123
124 ;Store A into In ( offset of byte variable from ix )
125
126 STA macro In
121 ld (ix+#n),a
128 endm
129
130 *LIST ON
~
Zilog
Product
Description
Preliminary
June 1981
6-61
FUNCTIONAL DESCRIPTION TABLE I.
The Concepts. ZRTS is both easy-to- TASK MANAGEMENT
learn and easy-to-use. Only a few sim- I_Census PrOVides the status of tasks 1n the
ple concepts need to be understood system.
before designmg begins. I_Create Creates a task dynamically
Tasks. Tasks are the components com- I_Destroy Removes a dynamically created task
prising a real-time application. Each I_Lock Allows a task to take exclUSive control
task is an independent program that of the CPU.
shares the processor with the other I_Reschedule Changes the PriOrity of a task.
tasks in the system. Tasks provide a
I_Resume Aclivates a suspended task,
mechamsm that allows a complicated
application \0 be subdivided mto I_Suspend Suspends another task,
several independent, understandable, I_Unlock Releases exclUSive control of the CPU
and manageable units. for other tasks,
Suspends task executIon
Semaphores. Semaphores provide a
low overhead facility for allowing one SEMAPHORE MANAGEMENT
task to signal another. Semaphores can
SerTL.-Clear Clears semaphore queue and
be used for indicating the availability
relmhahzes a semaphore.
of a shared resource, timing pulses or
Sem_Create Creates a semaphore dynamIcally
event notification.
Sem_Destroy Removes a dynamically created
Exchanges and Messages. Exchanges semaphore.
and Messages provide the mechamsm
SerTL.-Slgnal Signals a semaphore, mcrements the
for one task to send data to another. A
counter.
Message is a buffer of data, while an
Exchange serves as a mailbox at which Tests a semaphore for a SIgnal.
tasks can wait for Messages and to Causes a task to walt untIl a semaphore
whICh Messages are sent ~nd held. IS Signaled, decrements the counter.
CLOCK MANAGEMENT
The ZRTS Kernel. The Kernel is the
basIC buildmg block of ZRTS and per- ClLDelayJbsolute Places a task on the clock queue
forms the management functions for waiting for absolute hme.
tasks, semaphores, the real-time clock, ClLDelay_Interval Places a task on the clock queue
memory and interrupts. The Kernel walhng for passage of an mterval of
also provides for task-to-task com- tIme
mumcahons via Exchanges and CILSet Sets the real-time clock.
Messages. All requests for Kernel ClLIlme Reads the clock,
operations are made via system call MEMORY MANAGEMENT
instructions with parameters m
PrOVides status of the memory
registers, according to the standard resource.
Zilog calling conventions.
Alloc Dynamically allocates memory,
Task Management. One of the main
Release Releases allocated memory.
activities of the Kernel is to arbitrate
the competition that results when INTER-TASK COMMUNICATION
several tasks each want to use the pro- ~cqU1re Gets a message from an exchange pool
cessor. Each task has a unique task and assigns a deshnahon or a reply
descriptor that is managed by the exchange to It.
Kernel. The data contamed in the MJsslgn Assigns a new source and destinatIon
descriptor include the task name, to an eXlstmg message.
6-62
Semaphore Management. The Kernel 'l'ULII.
provides semaphore management for CONSTANTS SpeCifies system constants.
synalfronizing interactmg tasks. A
tYPICal use of semaphores is to provide EXCHANGES Dehnes the characterlshcs of applica-
mutual exclusion of a shared resource. lion exchanges.
When a resource IS to be used by only FILES IndICates additional hies to be mcluded
one task at a lime, a semaphore with a m the conhguralion Imk.
counter of I controls the resource.
Every task requiring the resource must HARDWARE Describes the target hardware con-
hguralion-Z8001, Z8002, or Develop-
hrst wait on that semaphore. Since the
counter is I, only one task will acquire ment Module.
the resource. The others will be INITIALIZATION SpeClhes routines that are to execute
queued on the semaphore and prior to begmmng execuhon of the hrst
suspended until the semaphore is task. '
signaled that the resource IS once INTERRUPT ASSOCiates an mterrupt rouhne with an
again available. At that time, the-lirs.t mterrupt vector or trap and system
task on the semaphore queue will be call-handlers. PrOVides the facililies to
made ready to run and can use the specify a NVI mterrupt-handler that
resource. After all tasks have acquired Will be called from the system NVI-
the resource and signaled the comple- handler routme.
tion of their use, the semaphore returns
to its original state with a counter of I. MEMORY Specihes the memory conhguralion
Counters greater than one are useful and Identifies where seclions are to be
when there are a number of similar placed (l.e.,CODE,DATA, ... ).
resources, (i.e., three tape drives, four SECTIONS Allows modules to be placed m a
I/O buffers, etc.). specifIC section, overrldmg the stan-
In ZRTS, a semaphore can count up dard assignment convenlions.
to 32676 signals. The commands pro-
SEMAPHORES Defmes the characteristics of applica-
vided by the Kernel to manage
lion semaphores.
semaphores are listed in Table 1.
SWITCHES Allows flags that control the system
Cloc:k Management. ZRTS operates
generalion operahon to be set.
with a real-time clock that generates
mterrupts at a hardware-dependent TASKS Defines the characterlslics of apphca-
rate. It IS used for timed waits, hon tasks.
timeouts, and round-robm scheduling.
All limes are given in number of ticks. 250-mlcroseconds. Quicker servICe of Messages can be obtained quickly.
The clock may be manipulated by the interrupts IS pOSSible through the use ZRTS prOVides several commands for
set of commands provided by the of user-written routines. inter-task communicalions. These are
Kernel that are listed in Table 1. listed m Table 1.
Intertask Communication. The
Memory Management. Storage for Kernel prOVides the capability for tasks ZRTS Configuration Language (ZCL).
ZRTS data structures IS allocated either to exchange informalion. ThiS com- Smce ZRTS's modular deSign leads to
stalically at system generation lime, or mum calion process occurs when one so many different conhguralions, a
dynamically at run lime. Dynamic task sends a Message to an Exchange Simple facility for generatmg the target
allocalion occurs via a system call that and another task receives the Message. operatmg system IS a crlhcal part of
speClhes the attributes of the structure A Message contams a length indi- the ZRTS package. The ZRTS Con-
to be created and returns a name that cator, a buffer with a variable amount hguralion Language (ZCL) prOVides an
can be used to refer to the structure. of data, and a code that Idenlihes the easy-to-use means for genera ling the
Memory IS allocated m 256-byte Message type. The Exchange IS a target system. Usmg ZCL, the deSigner
mcrements, and can be released using system data structure that consists of a can specify hardware mformalion, soft-
a system call. queue for Messages sent but not yet ware parameters, linkage mformahon,
The storage allocator can also be received, a semaphore on whICh a task and system data structures m hlgh-
called directly to obtam blocks of can walt for a Message, and an level terms.
memory up to 64K bytes long, which oplional "pool" list from which
can be used by the task for any pur-
pose.
Interrupt Management. Interrupt-
handhng routmes are provided for
system calls, non-vectored mterrupts
and a hardware clock. The user must
provide mterrupt routmes for whatever
other vectored mterrupts are mcluded
m the target system.
ZRTS can switch control to a task
waiting for an external event withm
500-mlcroseconds after the occurrence
of the event. This IS based on the worst
case with a 4MHz Z8000. A more tYPI-
cal response lime would be Development Environment
6-63
ZCL unburdens the user of the
necessIty to learn the detaIls of the
ZRTS mternal structures. System data SWITCHES:
structures can be generated SImply by APPLICATION
specIfymg the approprIate parameters.
HARDWARE:
The ZCL syntax IS free-format wIth
comments allowed to make the con- zS002
ORDERING INFORMATION
Description Prerequsites
ZRTS/SOOI ZIlog Real T,me Software for the ZSOOI ZIlog Development System
ZRTS/S002 ZIlog Real T,me Software for the ZS002 MCZll, PDS, ZDS SerIes or Z-LAB SOOO (ReqUIres Software L,cense)
Zilog
10340 Bubb Road, Cupertino. Cahforma 95014 ThiS document IS subject to change Without notice
Telephone (408) 4464666 TWX 910338-762] 00109702 Prmted m USA
6-64
Peripheral controller chip
ties into 8- and 16-bit systems
Based on one-chip-microcomputer architecture, universal peripheral controller
comes with either multiplexed or nonmultiplexed address and data lines,
provides ROM-less and prototyping packages for product development
D The growing power of high-end microprocessors and microprocessor systems and control of distributed I/O
the complexity of peripheral devices attached to them peripheral functions by means of a multiplexed address
has given rise to a need for general-purpose distributed and data bus. The Z80-bus interface provides easy inter-
processors to handle increasingly complicated input/out- facing with 8-bit microprocessors and others that employ
put activities, As such, these devices must themselves nonmultiplexed address and data buses,
have respectable processing and I/o-manipulation abili-
A logical organization
ties while being able to interact efficiently with high-end
microprocessors, Ideally, they would also communicate The UPC is partitioned into two functional blocks: the
with 8-bit midrange microprocessors and be low in cost. logic for interfacing with the host-processors, and the
Just such a processor has been based on the Z8 core microcomputer (Fig, I). In the multiplexed (Z-BUS)
single-chip microcomputer. The Z-UPC universal periph- version, communication between the host and the UPC
eral controller combines the instruction and 110 capabili- takes place over the Z-BUS, which provides an 8-bit
ty of the Z8 with two versions of bus interfacing: the bidirectional address and data port (ADo-AD,) and a set
Z-UPC offers the Z-BUS interface found on the Z8000, of control lines (AS, OS, R/W, CS, WAIT). Also, under
and the Z-UPC/U provides a Z80-compatible interface. UPC program control, an optional daisy-chain interrupt
The Z-BUS interface allows flexible connection to larger structure-using request (INT), acknowledge (INTACK),
INTERFACE
REGISTERS
(PART OF INPUTI
REGISTER FILE) OUTPUT
INTERFACE
REGISTERS
AS
OS BUS
REGISTER liD
TIMING
R/IN AND POINTER
CONTROL
CS
WAIT
liD
(OPTIONAL
CONTROL
INT FUNCTION)
INTACK
HALF
PORT 3
lEI
lEO
1. Microcomputer plus. The Z-UPC universal peripheral controlier bases much of its architecture on the Z8 chip, to which it adds circuits at
left for interfacing with a host processor. Shown is the Z-BUS-compatible version with multiplexed address and data lines.
-- .. - - - ._------
255 STACK POINTER
254 MASTER CPU INTERRUPT CONTROL
FLAGS/REGISTER POINTER
Z'UPC INTERRUPT CONTROLS
PORT CONFIGURATION REGISTERS
TIMERS
(POINTS TO
240 MASTER CPU INTERRUPT VECTOR STARTING
ADDRESS OF
AWORKING
REGISTER
GROUP\
~~~~fA~OLE'
,_. - . - . """l"""""_'_ '~~'--r~"""",!~::--"-,-'
POINTS
TO START
OF HOST SIZED HOST'
PROCESSOR PROCESSOR
INTERFACE ]
BLOCK
REGISTER TRANSFER
BUFFER)
2. File in. Of the UPC's 256byte register file,
~----------------------------~
234 are generalpurpose and can function as ~____~DA~J~A~IN~D~IR~E~CT~I~ON~AN~D~L~I~MI~T~C~OU~N~T____~
accumulators, buffers, pointers, or stack or THREE I/O PORT'REGISTERS
index registers. The other 22 are specific I/O REGISTER POINTER/DATA TRANSFER CONTROL
pointers and registers, as well as status and
control registers for the UPC's I/O facilities.
enable input (lEI), and enable output (lEo) lines-can be register file (shown in Fig. 2). Besides storing data and
implemented. The microcomputer portion is based on control and I/O functions for the processor, the register
the Z8 microcomputer architecture, whose central pro- file serves as buffer storage for communication between
cessing unit executes instructions averaging 2.2 micro- the UPC and the host cpu.
seconds each using a 4-megahertz clock source. The In addition to 234 general-purpose registers, the regis-
cpu's memory comprises 256 bytes of register-file ran- ter file contains 19 control registers for configuring and
dom-access memory (which can be accessed directly by controlling the z-upc's 110 facilities and three parallel
the host processor and the upc), plus 2,048 bytes of 110 ports. The control registers both specify how the
read-only memory for program storage; other features hardware is configured and should function and provide
include three 110 ports for device control, two status information for it as well.
timer/counters, and six vectored interrupts.
In addition to the standard 40-pin version (with 2-K A multipurpose register Iile
bytes of ROM), there are two 64-pin versions of the All of the general-purpose registers can function as
Z-UPC: a ROM-less version and a RAM version, both of accumulators, data buffers, address pointers, and stack
which have the program address, data, and control lines or index registers. All ports and control registers can be
buffered and brought to external pins. The version with accessed by UPC instructions like any other register.
no program ROM on chip is intended as a development Instructions can access the registers directly or indirectly
tool. The RAM version, which has 36 bytes of vestigial with an 8-bit address field. However, a 4-bit addressing
bootstrap ROM on chip, is intended as a controller whose scheme, which makes use of a register pointer, can save
program is downloaded from the host processor. memory and execution time. In this scheme the register
All three of these configurations are available with file is divided into 16 register groups, each containing 16
either the nonmultiplexed bus or the multiplexed Z-BUS contiguous locations. The register pointer determines
interface to meet the needs of 8-, 16-, or even future which group is being accessed, and a 4-bit address field
32-bit systems. specifies the register within the group. This capability is
The UPC processor is organized around a 256-byte especially useful to speed context switching.
Programs running on the UPC may communicate with pletely independently of each other. The UPC can ignore
those running on the master processor in a number of the data transfer request from the master by setting a bit
ways: under interrupt control (either by the UPC or in its master-processor interrupt control register. Any
master); by transfer of byte data through data, status, attempt to transfer data from the master when this bit is
and command registers; and by transfer of blocks of data set causes an error flag, which will cause an interrupt to
to and from the UPC's register file. the UPC (if interrupts are enabled).
Three group. I/O line. by the dozen
The host CPU can directly access the 19 interface The UPC has 24 lines dedicated to input and output
registers through the Z-BUS interface. As illustrated in that are grouped into three 8-bit ports. Since the ports
Fig. 3, the registers are separated from the upc's inter- are mapped into the register file, 110 data can be directly
nal registers and divided into three groups: manipulated by any instruction. Each port has a mode-
Those for interface status and control, which the mas- control register, which allows the port functions to be
ter processor can access to control upc-generated Z-BUS changed during program execution; for example, each
interrupts, to interrupt the UPC, and to control message line of port 1 and port 2 can be individually configured
transfer over the Z-BUS. as input or output under program control. Each port can
Those for data, status, and control, which are mapped have its output lines defined as push-pull or as open-
into 16 registers by the 1/0 register pointer, controlled by drain drivers.
the UPC. That arrangement gives the master processor Port 3 is a multifunction port. It has four input and
direct access to 16 registers and allows transfer of data, four output lines that can be used for 110 or control
status information, or control commands between the functions. The control functions available through this
UPC and master processor. port include interlocked handshake lines for ports 1 and
Those for block access, used by the master to transfer 2, interrupt request inputs, timer input and output, and
blocks of data into or out of a buffer in the UPc's register Z-BUS interrupt control.
file. The UPC has complete control over the placement
Timing and counting
and size of the buffer in its register file.
Each of the three types can be read or written by the To support timing and counting requirements of soft-
master processor. Because the UPC software has com- ware routines, the UPC provides two 14-bit timer/count-
plete control over how these register groups are mapped ers, To and T,. Among the timer/counter functions that
into the register space, the layout of data in the registers are easily implemented by the UPC are; interval delay
is independent of the host processor's software and pro- timer, time-of-day clock, watchdog timer (as for refresh-
tected from it. ing dynamic memory), external event counting, variable
The UPC and the master processor can operate com- pulse-train output, duration measurement for external
I
r---
I ..
SR
REAO OATA
READ CLOCK 74lS299
WRITE DATA 8BIT
SHIFTI
TIMING SHIFT ClK STORAGE
CONTROL REGISTER .POII~1
IT
Z'UPC
UNIVERSAL
r-" PEfIlPHiAAL AS
-, }
.,
w
..
<C
0:
W
fit SERIAL OUTPUT
GOUT
I
!
CONTROLLER
OS
I-
~ HAHD$IIAAE cs -- ..
'"'"C
INDEX TOUT
, PORTa
INTACK - -
~ T'N
"- INT
READ MODE
~ WRITE GATE --
REAOY "
WAIT
RNi
-
TRACK 0
WRITE PROTECT ~RT2
-
- Voo
STEP
DIRECTION - v
DISK CHANGE
--- -CLOCK
4. Diak jockey. The UPC makes a controller for a floppy-disk drive that actually stores the file system on chip. The host has only to specify the
file name and the function to be performed. The 74LS299 shift register converts senal Into parallel data, which enters port 1 on the UPC.
events, and automatic delay after an external event. the stack, and control passes to one of six predetermined
Each timer/counter is divided into a 6-bit prescaler interrupt-handling routines. The routine is pointed to by
and an 8-bit counter and is driven by the internal UPC an address that has been stored in the first 12 bytes of
clock, divided by four. The internal clock for TI may be program memory. All of the interrupts are disabled after
set up for gating or triggering by an external event, or it an interrupt is accepted. Interrupts can be nested by
may be replaced by an external clock input. Each enabling them during the interrupt service routine; they
timer/counter may operate in either a single-pass or a are automatically enabled during the return from the
continuous mode, so that after the last count either routine.
counting stops or the counter reloads and continues The Z-UPC instruction set is compatible with the Z8
counting. The counter and prescaler registers may be microcomputer instruction set (though the uPC's load-
altered individually while the timer/counter is running; external-memory instruction is only available in the 64-
software controls whether the new values are loaded pin RAM version of the Z8). This instruction set, com-
immediately or when the end of count (EOC) is reached. prising 129 instructions of 43 basic types and using six
The two timer/counters may be cascaded using the main addressing modlls, speeds program execution and
timer-input lines on port 3. achieves byte efficiency. The types of data that it allows
to be used include bits, binary-coded decimal digits,
Interrupting the controller bytes, and 16-bit words.
To serve host or I/o-device requests quickly, the UPC
Z-BUS 8upport
prQvides six interrupts from eight different sources: three
from ports, two from timer/counters, and three from the The UPC can support the full Z-BUS interrupt struc-
host-processor interface. All six interrupts may be indi- ture, including daisy-chained priority resolution and vec-
vidually or globally disabled. The interrupts are priori- tored interrupt acknowledge. Using the interface control
tized, with the interrupt-priority control register provid- and status ports, the master processor has the full range
ing 48 different priority schemes for handling concurrent of Z-BUS mechanisms for enabling or disabling Z-UPC
interrupts, What's more, the masking and prioritizing of interrupts, marking interrupts as being under service,
the interrupts may be dynamically modified under pro- clearing interrupts, setting interrupt vectors, and dis-
gram control. abling interrupts from lower-priority devices.
The upc's interrupts are vectored. When an interrupt A program running on the UPC can start the normal
occurs, the program counter and flags are pushed onto Z-BUS interrupt sequence (assuming interrupts are
o HARDWARE
D SOFTWARE
When transported, the Unix operating system was tion of CRT terminals. The terminal data base can be
enhanced in several ways so that the Z8001 implementa- updated by the user when adding new terminals to the
tion might run more reliably. For example, in the stan- system.
dard Unix operating system, nothing prevents two users The editor lets the user display text files one page at a
from simultaneously modifying a file so that one user time and rapidly move the cursor on that page, inserting
can accidentally invalidate the other's changes. The or deleting characters, words, lines, or groups of lines
Zeus operating system qualifies the three standard Unix with a minimum number of keystrokes. Several addition-
file-opening modes (read, write, and read and write) al features are available, such as cut-and-paste and
with three access-control modes specifying what other word-wrap facilities.
users can do with the file.
Rebuilding the system
The Zeus access control modes are shared, read-only,
and exclusive. The shared mode, the standard Unix Another enhancement is the Sysgen program, which
control mode, allows other users access to any file they automatically rebuilds the Zeus system, letting the user
desire. In the read-only mode, other users may access the tailor it to specific requirements. The user can add disk
file only for read operations. In the exclusive mode, other and tape drives or other input/output devices using the
users may not access the file at all; the first user opening Sysgen program as well.
the file has exclusive access to it until the file is closed. Several other utility programs are supplied with Zeus.
Any attempted access to a file that violates these param- Learn, an interactive program, teaches new users how to
eters results in a failure of that open operation. fully exploit Zeus's facilities; Mail lets users send mes-
sages to each other in postal format; Calendar automati-
Other enhancements cally reminds users of events scheduled during the day
A full-screen text editor, called the visual editor, has when they sign on and begin using their terminal; Spell
been implemented in Zeus for cathode-ray-tube termi- is a spelling-error detection program that uses a 25,000
nals. Its data base contains terminal-control information word dictionary; and Man prints selected portions of the
that permits full-screen editing for almost any combina- Zeus reference manual on the user's terminal. Over
6-72
DEC's PDP-11170 should minimize the transportation
HEXADECIMAL effort.
ADDRESS
On the basis of this background information, the
FFFF
design team decided to run the Z800 I microprocessor in
the nonsegmented mode for user processes and for
almost all of the kernel. In a nonsegmented mode,
programs use 16-bit addresses and are limited to a single
64-K-byte segment. This means that both integers and
pointers are considered 16-bit quantities and therefore
integer arithmetic can be performed on them.
t Because the Z8000 family can support separate code
and data address spaces, user and system programs may
DYNAMIC DATA
have as much memory as a PDP-11I70-128-K bytes, of
which 64-K bytes are code and 64-K bytes are data.
Furthermore, the Z800 I 's 24-bit addressing scheme can
handle a total system memory as large as 16 megabytes.
GLOBAL DATA Because the Z-Lab 8000 can handle up to 1.5 megabytes
of memory the need for swapping programs in and out of
0000
main memory is reduced, thereby minimizing response
time when a large number of users are on the system.
2. Subdivisions. Zeus separates the memory space for programs Much of the existing Unix software base takes advan-
and data, the latter being subdivided into areas for the stack, tage of the operating system's dynamic allocation of
dynamically allocated variables, and global variables Hardware memory. This system characteristic has had a major
ensures that the stack and dynamic areas do not overlap impact on the hardware design of Z-Lab.
6-73
SO-S6
BREAK
REGISTER
CODE
~r-t
~DE
MU
-
Z8001
MICRO-
PROCESSOR
CODE/OATA
STATUS
MEMORY
MANAGEMENT
UNIT
-
STACK
::: - STACK
MMU
SELECT LOGIC
-
3. Multiple MMUs. In the Zeus ...
...
As -A 15
operating system, the zaaa 1 DATA
MMU ~
processor runs in its nonseg-
mented mode, and memory
DATA
management units divide the
memory space into separate
code, stack, and data areas
The break register stops the
stack and data areas from
overrunning one another
solution, in which the references to the two dynamic data solved independently by any of the individual groups.
areas are made through two different MMUs. In Fig. 3, a Likewise, the various goals of the Z-Lab system could
simplified block diagram of Z-Lab's memory manage- be attained only with an integrated approach to the
ment architecture shows that there are separate MMUs hardware, software. and mechanical engineering aspects
for the code, as well as for the stack and data address of the project. Of these goals, the first was to design a
spaces. The MMU select logic determines which one Unix-based system with enough flexibility and file-
should be activated and guarantees that only one will be system integrity that users could configure and maintain
active at any given time. it themselves. A second goal was a performance level
The operating system sets the break register, the key that could comfortably support up to 16 users_ The final
element in determining whether the stack or the data one involved packaging the system for the office environ-
MMU will be activated, pointing to the highest address in ment.
the dynamic data area. On every data reference to To best achieve these goals, the project team sought a
memory, address bits 8 through IS from the Z8001 are system design with minimum power consumption and
compared to the value in the break regis teL Data noise levels. Thus, the Z-Lab offers high-performance
addresses greater than or equal to the break value acti- minicomputer power in a quiet and easily portable pack-
vate the stack MMU; data addresses less than the break age that consumes only 325 watts. It has no special
value activate the data MMU. The MMU selection occurs power requirements and no cooling requirements, if
quickly enough for no wait states to be required, even ambient temperature stays below 40'C.
with a 6-megahertz Z8001. Z-Lab system hardware was also designed for expand-
ability. Using a moderate-sized printed-circuit board
Integrating hardware and software
(approximately 9 by II inches) kept the hardware con-
The memory management design discussed above figuration compact while allowing enough board area for
handles Unix software and nonsegmented Z8000 pro- future Z-Lab products_ A highly reliable two-piece con-
grams. In addition, the memory management architec- nector, although slightly more expensive than the con-
ture of the Z-Lab processor board can be modified under ventional one-piece card-edge connector, improved con-
program control to support segmented user and system nection reliability and permitted more connections per
programs. Future software releases can thus take full inch of pc-board edge.
advantage of the 16 megabytes of address space provided
by the segmented Z8001.
Bus with a future
The Z-Lab development project was approached as an A semi synchronous bus, the ZBI, was chosen for its
integrated product-design effort. A broad-based project high level of system performance and input/output inter-
team was selected to facilitate close cooperation among face. All Z8000 peripheral circuits interface with the bus
the hardware, software, and mechanical engineers, and simply, needing buffering only to attain the TTL drive
the memory management architecture thus developed by levels required on the backplane. Z80 peripherals can
the team solved problems that could not have been also be attached to the bus by generating the required
6-74
unit has slots for the processor, cartridge tape controller,
PARALLEL B SERIAL and Winchester disk controller cards as well.
PRINTER PORT PORTS
Two of the Z-Lab's three peripheral controllers are
intelligent, using Z80B 6-MHz microprocessors. This
offers three distinct advantages.
First, device control chores are offioaded from the
CENTRAL
PROCESSING ANO main processor. The operating system thus can commu-
MEMORY nicate with the peripheral controllers using high-level
MANAGEMENT
UNITS commands that let the peripheral controllers work in
parallel with the main processor. For example, Z-Lab
can issue simultaneous reads or writes to more than one
disk drive; the disk controller keeps track of head posi-
tion, sector position, and data transfer.
Secondly, the intelligent peripheral controllers can
perform self-diagnostics on power-up or on command,
thus certifying to the host processor with a high degree
WINCHESTER OISK of certainty that they are functioning correctly before
CONTROLLER
processing begins.
Finally, product maintenance and upgrading is simpli-
fied by using firmware. As information is gathered on
how the operating system interacts with the disk under
different program mixes, the Winchester disk controller
can be easily "tuned" for higher performance by altering
the firmware.
CARTRIDGE TAPE Initial board set
CONTRO LLER
The Z-Lab board set consists of:
A processor board containing eight serial channels
with programmable bit-rate, a parallel printer interface
ERROR'CORRECTING
MEMORY for either Centronics or Data Products-type printers, a
CONTROLLER memory management subsystem that supports either
segmented or non segmented user processes, and read-
only memory containing the bootstrap software and pow-
er-up diagnostics.
256-K-BYTE An ECC memory controller that supports 32-bit error
MEMORY ARRAY correction for up to 16 256-K-byte memory array cards.
This board contains detection and reporting logic for
uncorrectable errors and error-logging logic for correct-
4. Architectural planning. The Z-Lab development system uses the able errors.
proprietary ZBI 32-bit bus, an error-correcting memory controller that One or more 256-K-byte memory array cards using
communicates with the main memory over a separate high-speed high-speed 16-K dynamic RAMS.
bus, and both Winchester disk and cartridge tape controllers An intelligent cartridge tape controller that handles
up to four tape drives for file archiving or for backup of
Z80 timing with simple interface logic. the entire system.
The ZBI is a true 32-bit bus with the address and the An intelligent Winchester disk controller that supports
data multiplexed on the same lines (Fig. 4). The band- up to four 24-megabyte 8-in. Winchester disk drives.
width of the bus (8 megabytes per second) is sufficient An optional serial 110 controller board that supports
for future high-speed 32-bit processors and for peripher- an additional eight serial lines and an additional printer
al controllers as well. port.
The Z-Lab error-correcting memory controller (ECC) Several other subsystems will be offered with Z-Lab in
supports 8-, 16-, and 32-bit data transfers, performing the near future. An expansion chassis will increase the
32-bit error correction with the aid of seven extra syn- number of card slots in the unit from 10 to 20, the
drome random-access memories that hold the correction maximum number a ZBI bus can support, for construct-
bits for every 32 data RAMs. The ECC communicates ing very large systems.
with its memory array cards over a very high-speed Another offering will be a compatible 40-megabyte
dedicated memory bus. Winchester drive (40- and 24-megabyte drives can be
mixed on the system's Winchester controller). Zilog also
Maximizing memory capacity
will offer an intelligent serial controller that can perform
All timing and refresh circuitry on the controller is direct-memory-access transfers to and from main memo-
centralized, maximizing memory capacity in the system. ry, which will help improve system performance by
In addition to a maximum of 1.5 megabytes of ECC reducing the amount of time that must be spent by the
memory in the processor module enclosure, the Z-Lab processor in servicing terminal interrupts. 0
6-75
Reprinted from ELECTRONICS, March 24, 1981, copyrrght 1981 by McGraw-Hili, Inc_, with all rrghts reserved_
Probing the news
Software
6-77
program development. On the other product development programming Idris [Electronics, March 24, 1981,
hand, Unix is probably best known in its Consumer Products division is p. 125). Some of the newer ones are
for its document-preparation and done in C on a PDP-11170 under aiming at the 8-bit market to main-
-management functions, which are Unix and then transported to the tain compatibility with current soft-
often used by nonprogrammers. And target microsystem. ware bases. Two, for Z80-based
with the addition of a good screen- The first computer to which the microsystems using the S-IOO bus,
oriented editor, like Zilog's visual operating system was transferred come from Morrow Designs of Rich-
editor, Unix offers a wide avenue of from the one on which it was devel- mond, Calif., and Cromemco Inc. of
capability for professionals and non- oped was the Interdata 8/32. The Mountain View, Calif., respectively.
programmers alike. Wollongon Group of Palo Alto, Subtasks. Morrow Designs' ver-
New version. One of the latest Calif., now offers Unix for the 8/32, sion, called ).INIX, runs CP/M as one
Unix versions is the Zeus adaptation as well as for the rest of Perkin- task within its multiuser environ-
by Zilog Inc. Cupertino, Calif., for Elmer's 32-bit minicomputers (Per- ment, thereby maintaining compati-
its Z-Lab software development sys- kin-Elmer having bought Interdata). bility with CP/M software while
tem using the Z8000 [Electronics, The same. In the Wollongon offer- gaining the conveniences of a user-
March 24, p. 120]. And to be ing, a supreme attempt has been transparent Unix. The emphasis
released next month to selected made to make this implementation throughout has been on compatibili-
OEMs is the Z8000 version called virtually identical to the original as ty and portability; ).INIX is written
Xenix from Microsoft in Bellevue, it appears to the user, in the interest entirely in Whitesmiths' C, which is
Wash. [Electronics, March 24, of program portability and of pre- not supplied with the package.
p. 34]. Among the first of the OEMs serving a common command lan- Cromemco's version runs the CDOS
is Codata of Sunnyvale, which is guage across Unix systems. operating system as a subtask and
working on a floppy- and hard- Unix is also available from Am- maintains compatibility with that
disk-based microsystem that makes dahl Corp. for its IBM 370 look- already extensive software base,
use of a Multibus-compatible central alike, the 470 mainframe, and even including its new C compiler.
processing unit. Later this year, the for a computer that is specially opti- There is even a version, from
8086 version of Xenix is to be deliv- mized for the C language-the Technical System Consultants Inc.,
ered to Altos Computer Systems of Cl70-from BBN Computer Corp. for Southwest Technical Products
Santa Clara for its single-board [Electronics, Nov. 6, 1980, p. 46]. Corp.'s 6809-based 128-K-byte mi-
8086-based microsystem. These, like the others, are licensed crosystem. Called Uniflex, it is writ-
After that, Microsoft plans to by Western Electric. ten entirely in assembly language
release a 68000 version (as does However, before the licensing pro- and includes most of Unix's features;
Whitesmiths Ltd. of New York in an cedures were changed to accommo- it supports both floppies and a 20-
original implementation), with an date small systems, several software megabyte hard disk. The West
eye to the iAPX-432 and the 16000 developers began work on Unix look- Lafayette, Ind., firm will add a
in an attempt to establish Xenix as alikes. These user-tranbparent, yet 68000 version soon and is looking to
the standard version of Unix for 16- original, implementation projects are Ada, Pascal, and C for future high-
bit microsystems. Not only is Micro- now coming to fruition. level language projects. 0
soft dedicated to marketing Unix, One that has been around for
but it is also dedicated to using it: all more than a year is Whitesmiths'
6-78
Zilog West South East United Kingdom
Sales Sales & Technical Center Sales & Technical Center Sales & Technical Center Zilog (U.K.) Limited
Offices Zilog, Incorporated Zilog, Incorporated Zilog, Incorporated Babbage' House, King Street
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Phone : (408) 446-9848 Phone: (21 4) 243-6550 Burlington, MA 01803 Phone: (628) 361 31
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Phone: (602) 990-1977
Midwest
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Phone: (312) 885-8080
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Phone: (216) 831 -7040
FAX: 216-831 -2957
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