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7. mars 2011 2
March the 8th Switched Capacitor Circuits
Intro to SC-circuits
12.3 Switched Capacitor Amplifiers
12.3.1 Unity
Unity-Gain
Gain Sampler / Buffer
12.3.2 Noninverting amplifier
12.4 Switched
Switched-Capacitor
Capacitor Integrator
Examples, incl. Oversampling
converters.
Report Writing
7. mars 2011 3
Folding
g and interpolation
p
Switched Capacitor
p Circuits
Sensing / sampling the input only at
periodic instants of time,
time processing
the each sample and producing a
valid output at the end of each
period;
i d discrete-time
di t ti or sampled-
l d
data systems.
Simple
p buildingg blocks like samplers,
p
amplifiers and integrators provide
the foundation for more advanced
circuits and topics.
Filters, comparators, (oversampling)
ADCs and DACs.
Well suited for CMOS
implementation, due to good
switches (low Ron, no offset) and
high input impedance amplifiers.
test 5
Properties of SC circuits
P
Popular
l due
d tto accuratet frequency
f response, good d linearity
li it
and dynamic range
Easily analyzed with z-transform
z transform
Typically require aliasing and smoothing filters
Accuracy
A i obtained
is bt i d since
i filt coefficients
filter ffi i t are determined
d t i d
from capacitance ratios, and relative matching is good in
CMOS
The overall frequency response remains a function of the
clock,, and the frequency
q y mayy be set veryy p
precisely
y through
g
the use of a crystal oscillator
SC-techniques mayy be used to realize other signal g
processing blocks like for example gain stages, voltage-
controlled oscillators and modulators
Basic building blocks in SC circuits; Opamps, capacitors, switches, clock
generators
C p1 C p2
(substrate - ac ground)
transmission
gate
v
1 v
2
p-channel
h l v
1 v
2
1 2
R
eq
V1 V2
V1 V2
C
1
T
R = --
---
Q = C 1V1 V2 every clock period
eq C
1
Qx = Cx Vx
Q1 = C1 V 1 V2
The average current is then given by the change in charge during one cycle
C 1 V1 V2
Iavg = ------------------------------
-
T
Where T is the clock period (1/fs)
SC Resistor Equivalent
q (2/2)
1 2
R
eq
V1 V2
V1 V2
C
1
T
R ------
=C
eq
Q = C 1V1 V2 every clock period 1
V1 V 2
I eq = -------------------
Req
The resistor equivalence is valid when fs is much larger than the signal
frequency. In the case of higher signal frequencies, z-domain analysis is
required : T 1
R eq = ----- = ----------
C1 C1 fs
Example of resistor implementation
What is the resistance of a 5 pF capacitance
sampled at a clock frequency of 100 kHz?
Note the large resistance that can be implemented.
Implemented in CMOS
C OS it would take a large area for
f
a plain resistor of the same resistance
1
-------------------------------3--- = 2M
Req = ---------------------12
5 10 100 10
An inverting integrator
v (nT)
c2
1 2
v (t) C
c
cx 2 1
v (t ) v (t )
ci co
v (t) C
c1 1
Vin(s) Vout(s)
Sample:
S l S1 and
d S2 are on, S3 off.
ff For
F a high
hi h gain
i opamp, VB=VVout0
0 and
d
the voltage accross C1 equal to Vin.
Amplify:
p y S3 on,, S1 and S2 are off.A to g
ground. Since VA changes
g from Vin
to 0, Vout changes to Vin0C1/C2.
Continous time implementation vs the SC implementation
The SC implementation samples the input, setting the output to zero and
provides amplification of the input in the next period, while ignoring the input
voltage. The circuit configuration changes from one phase to another, raising
stability concerns.
When Vout have settled, the current through C2 approaches zero, while R2
continously loads the amplifier.
Unity-Gain Sampler/Amplifier ; turning S2 off slightly before S1,
to avoid problems with charge injection
Suppose Vin=0
S 0 andd S1 injects
i j t q1
1 onto
t
P .Cx is the total capacitance from X to
Fig. 12.31 shows slow motion; S2
ground. The total charge at X cannot
injects
j q2
q onto CH, H p
producingg an error
change after S2 turned off (no dc path
q2 / CH , which is quite independent
in or out). The same holds true after CH
(The body effect makes VTH a function
is placed around the opamp. The
of Vin) of the input level since node X is
output voltage is not influenced by
at virtual ground. Only an offset (rather
charge injection due to S1.
than gain error or nonlinearity is
produced) After the feedback circuit has settled, the
q = WLCOX Veff = WLCOX (VGS VTH) = charge on CH equals V0CH, unaffected
WLCOX (VCK VX - VTH) by S3 (S3 introducing no error).
Unity-Gain Sampler/Amplifier and generation of proper clock edges
ensuring that S1 turns off after S2 does
31
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