Beruflich Dokumente
Kultur Dokumente
QUESTION BANK
2.Give the 2 effects occurred due to the dramatic growth rate in the 20th century .
6.Explain Instruction Set Architecture with its 7 dimensions using illustration of MIPS &
80x86.
7.Give basic instruction & floating point instruction formats for MIPS.
9.Discuss the terms Organization & hardware with respect to designing of computer
architecture.
10.What are the functional requirements to be considered in architecture designing?
11.List out other goals apart fro functional requirements that can be considered in
architecture designing.
18. Which metric is used for the devices which care more for battery life?
19. Some microprocessors are designed to have adjustable voltage, so that a 15% reduction
in voltage may result in a 15% reduction in frequency. What would be impact on
dynamic power?
20. Why static power is also important for CMOS when dynamic power is the primary
source of power dissipation.
22. Explain the impact of time, volume & commodification on the cost of a manufactured
component.
23.To understand the cost of current computers , it is must to understand the cost of chips.
Justify this.
25.Find the no. of dies per300mm wafer for a die that is 1.5cm on a side.
27. Find the die yield fir dies that are 1.5 cm on a side & 1.0 cm on a side, assuming a
defect density of 0.4/sq.cm & is 4.
32. Disk subsystems often have redindant power supplies to improve dependability. Using
the components & MTTFs from above, calculate the reliability of a redundatnt power
supply.Assume one power supply is sufficient to run the disk subsystem & that we are
adding one redundant power supply.
36 Define Spec ratio. Show that the ratio of the geometric means is equal to the geometric
mean of the performance ratios, & that the reference computer of SPEC ratio matters not.
37.Explain quantitative principles of computer design.
38.State Amdahls Law & give speedup in terms of performance &execution time.
40 Give the new executin time obtained by enhancing the execution mode & also give the
overall speedup.
41.Suppose that we want to enhance the processor used for Web serving. The new processor
runs 10 times faster on computation in the web serving application than the original
processor. Assuming that the original pocessor is busy with computation 40% of the time &
is waiting for I/O 60% of time , what is the overall speedup gained by incorporating the
enhancement?
44.Define the terms-i) CPI ii)CPU Time iii) Clock Cycle time iv)Instrution Count v) Overall
CPI vi) CPU Clock cycles.
46. Give different pitfalls & fallacies for computer architecture designing.
PIPELINING
1. Explain the concept of Instruction Level Parallelism. What are the challenges we are
facing in order to exploit ILP?
2. What is data dependence? Explain with an example & what are the hazards that can
happen in pipeline system because of the data dependence?
3. What is name dependence? Explain with an example & what are the hazards that can
happen in pipeline system because of the name dependence?
4. Explain the concept of control dependence with an example. With what problem a
pipeline may suffer if a control dependence is there?
5. When we can implement loop unrolling method in order to exploit loop level
parallelism? Give a proper example.
6. With an example tell how loop unrolling with scheduling can minimize the CPI &
hence is an advantage over simple loop unrolling & scheduling technique.
8. What are different dynamic branch prediction schemes? Explain each with an example.
9. Differentiate between 1- bit & 2- bit dynamic branch prediction scheme.
10. What are correlating branch predictors & their advantages over prediction schemes
that uses branch prediction buffer.
13. How dynamic scheduling takes care of different dependencies that is data , name &
control dependencies ?
16. Justify the statement that Hazard detection & execution control are distributed in
dynamic scheduling.
17. With a neat diagram give the basic structure of a MIPS floating point unit using
Tomasulos algorithm & explain the steps instruction goes through in the approach.
18. Explain the data structures associated with reservation station & register file.
19. Explain in detail the steps of Tomasulos algorithm assuming proper data structures.
22. Explain the concept of hardware based speculation technique, with a neat diagram.
23. How control dependences are taken care in hardware based speculation?
27. What would be the baseline performance (in cycles, per loop iteration) of the code
sequence in Figure 2.35, if no new instructions execution could be initiated until the
previous instructions execution had completed? Assume that execution does not stall for
lack of the next instruction, but only 1 inst/cycle can be issued. Assume that branch is
taken & there is 1 cycle branch delay slot.
28. In above code , how many cycles would the loop body requires if the pipeline detected
true data dependences & only stalled on those? Show the code with <stall> inserted
where necessary to accommodate stated latencies.
29. The following C code will compute the sum of the entries in a 100-entr vector A.
double arraySum = 0;
for (int i = 0; i < 100; i++) {
arraySum += A[i];
}
For the above code give equivalent MIPS code & unroll the loop by unrolling factor of 4.
Assume A[i] is in FP register F10, arraysum in FP register F8, base address of A at 0(R1)
and loop count initialized to 100 in register R2.
Consider the latency as load to FP operation 1 clk cycle latency . Find after unrolling
how many cycles it is taking for an iteration & also tell that before unrolling how many
cycles it is consuming?
30. For the following code sequence show the reservation table status & register file status
when first instruction is in write result state.
ADD R2, R4, R0
SUB R3, R6, R2
ADD R5, R3, R2