K. J.

Somaiya College of Engineering, Mumbai-77

(An Autonomous College Affiliated to University of Mumbai)

Batch:B3
Roll No.:1413104,1413115,1413117,1413118,1413119
Experiment / assignment / tutorial No._______

Grade: AA / AB / BB / BC / CC / CD /DD

Signature of the Staff In-charge with date

TITLE: Mini project - design an application using LPC 2148

OUTCOME: Students will be able to design an application using ARM LPC 2148

INTERFACE DIAGRAM:

Department of Electronics and Telecommunication Engineering

Page No AML Sem VI/Jan- April 2017
Theory: There are two PLL modules in the LPC2148 microcontroller. The PLL0 is used to
generate the CCLK clock (system clock) while the PLL1 has to supply the clock for the
USB at the fixed rate of 48 MHz. Structurally these two PLLs are identical with exception of the
PLL interrupt capabilities reserved only for the PLL0. We have used PLL0.

The PLL0 and PLL1 accept an input clock frequency in the range of 10 MHz to 25 MHz only.
The input frequency is multiplied up the range of 10 MHz to 60 MHz for the CCLK using a
Current Controlled Oscillators (CCO). The multiplier can be an integer value from 1 to 32 (in
practice, the multiplier value cannot be higher than 6 on the LPC2141/2/4/6/8 due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is
an additional divider in the loop to keep the CCO within its frequency range while the PLL is
providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16
to produce the output clock. Since the minimum output divider value is 2, it is insured that the
PLL output has a 50% duty cycle. A block diagram of the PLL is shown in the figure. PLL
activation is controlled via the PLLCON register. The PLL multiplier and divider values are
controlled by the PLLCFG register. These two registers are protected in order to prevent
accidental alteration of PLL parameters or deactivation of the PLL.

The PLL0 is turned off and bypassed following a chip reset and when by entering the power
down mode. The PLL is enabled by software only. The program must configure and activate the
PLL, wait for the PLL to lock, then connect to the PLL as a clock source.

Register Description: The PLL is controlled by the registers shown in the table below:
PLL Control Register (PLL0CON-0xE01F C080):

The PLLCON register contains the bits that enable and connect the PLL. Enabling the PLL
allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting the PLL causes the processor and all chip functions to run from the PLL output
clock. Changes to the PLLCON register do not take effect until a correct PLL feed sequence has
been given.

Bit Symbol Description Reset

Value
0 PLLE PLL Enable. When one, and after a valid PLL feed, this bit 0
will activate the PLL and allow it to lock to the requested
frequency.

1 PLLC PLL Connect. When PLLC and PLLE are both set to one, and 0
after a valid PLL feed, connects the PLL as the clock source
for the microcontroller. Otherwise, the oscillator clock is used
directly by the microcontroller.

7:2 - Reserved, user software should not write ones to reserved bits. N/A
The value read from reserved bit is not defined.

The PLL must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generated.
Hardware does not insure that the PLL is locked before it is connected or automatically
disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is
likely that the oscillator clock has become unstable and disconnecting the PLL will not
remedy the situation.
PLL Configuration register (PLL0CFG-0xE01F C084):

The PLLCFG register contains the PLL multiplier and divider values .Changes to the PLLCFG
register do not take effect until a correct PLL feed sequence has been given. Calculations for the
PLL frequency, and multiplier and divider values are found in the PLL frequency calculations.

Bit Symbol Description Reset Value

4:0 MSEL PLL multiplier value. 0
Supplies the value
M in the PLL
frequency
calculations.
6:5 PSEL PLL divider value. 0
Supplies the value P
in the PLL frequency
calculations.
7 - Reserved, user N/A
software should not
write ones to reserved
bits. The value read
from an observed bit
is not defined.
PLL Status Register (PLL0STAT-0xE01F C088):

The read-only PLLSTAT register provides the actual PLL parameters that are in effect at
the time it is read, as well as the PLL status. PLLSTAT may disagree with values found in
PLLCON and PLLCFG because changes to those registers do not take effect until a
proper PLL feed has occurred.

PLL Modes: The combinations of PLLE and PLLC are shown in the table below:
PLL Feed Register (PLL0FEED-0xE01F C08C):

A correct feed sequence must be written to the PLLFEED register in order for changes to
the PLLCON and PLLCFG registers to take effect. The feed sequence is:
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
The two writes must be in the correct sequence, and must be consecutive VPB bus
cycles. The latter requirement implies that interrupts must be disabled for the duration of
the PLL feed operation. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not
become effective.

PLL and Power-down Mode:

Power-down mode automatically turns off and disconnects activated PLL(s). Wakeup from
Power-down mode does not automatically restore the PLL settings, this must be done in
software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL
can be called at the beginning of any interrupt service routine that might be called due to
the wakeup. It is important not to attempt to restart the PLL by simply feeding it when
execution resumes after a wakeup from Power-down mode. This would enable and
connect the PLL at the same time, before PLL lock is established.

If activity on the USB data lines is not selected to wake up the microcontroller from
Power-down mode, both the system and the USB PLL will be automatically be
turned off and disconnected when Power-down mode is invoked, as described above.
However, in case USBWAKE = 1 and USB_need_clock = 1 it is not possible to go into
Power-down mode and any attempt to set the PD bit will fail, leaving the PLLs in the
current state.
PLL Frequency Calculation:

The PLL equations use the following parameters:

The PLL output frequency (when the PLL is both active and connected) is given by:
CCLK = M FOSC or CCLK = FCCO / (2 P)

The CCO frequency can be computed as:

FCCO = CCLK 2 P or FCCO = FOSC M 2 P

The PLL inputs and settings must meet the following:

FOSC is in the range of 10 MHz to 25 MHz.

CCLK is in the range of 10 MHz to Fmax (the maximum allowed frequency for the
microcontroller - determined by the system microcontroller is embedded in).

FCCO is in the range of 156 MHz to 320 MHz.

Procedure For Determining PLL Settings:

If a particular application uses the PLL0, its configuration may be determined as follows:

1. Choose the desired processor operating frequency (CCLK). This may be based on
processor throughput requirements, need to support a specific set of UART baud
rates, etc. Bear in mind that peripheral devices may be running from a lower clock
than the processor.
2. Choose an oscillator frequency (FOSC). CCLK must be the whole (non-fractional)
multiple of FOSC .
3. Calculate the value of M to configure the MSEL bits. M = CCLK / FOSC. M must be in
the range of 1 to 32. The value written to the MSEL bits in PLLCFG is M 1.
4. Find a value for P to configure the PSEL bits, such that FCCO is within its defined
frequency limits. FCCO is calculated using the equation given above. P must have one
of the values 1, 2, 4, or 8. The value written to the PSEL bits in PLLCFG is 00 for
P = 1; 01 for P = 2; 10 for P = 4; 11 for P = 8.
PLL Divider Values:

PLL Multiplier Values:

CALCULATIONS:

Configuring the PLL0

System design asks for FOSC= 12 MHz and requires CCLK = 60 MHz.

Based on these specifications, M = CCLK / Fosc = 60 MHz / 12 MHz = 5. Consequently,

M - 1 = 4 will be written as PLLCFG[4:0]= 00011

Value for P can be derived from P = FCCO / (CCLK x 2), using condition that FCCO must be
in range of 156 MHz to 320 MHz. Assuming the lowest allowed frequency for
FCCO = 156 MHz, P = 156 MHz / (2 x 60 MHz) = 1.3. The highest FCCO frequency criteria
produces P = 2.67. The only solution for P that satisfies both of these requirements and is
listed in table shown above is P = 2. Therefore, PLLCFG[6:5] = 01 will be used.

Therefore, PLLCFG= 0x23.

Results:

Input frequency of 12 MHz is converted to 48 MHz using PLL0.

Conclusion:

Input frequency of 12 MHz was supposed to be converted to 60 MHz as per the calculations
done above. But, since this is observed on the kit, the minimum and maximum values for FCCO
are considered to be 156 MHz and 320 MHz respectively, as per the data sheet.

But, on the kit, these values for FCCO range will change. Hence, a deviation from the expected
output frequency can be seen.