Sie sind auf Seite 1von 2

Research plan for next 5 years

Next five years I am looking forward to focus on research areas that can extend the availability
and usefulness of current technology and its advancement to our society directly. I believe that
this will certainly bring affordability of technology to the mass.

Domain introduction:

MOSFET scaling is the key driving force for high speed and low power Electronics design.
According to the ITRS, scaling of bulk MOSFET below 45 nm is restricted due to various Short
Channel Effects (SCEs) such as parasitic capacitance scaling, increased leakage power
consumption, and reduced gate control over channel region. In literature, various advanced
structures have been analyzed such as single gate UTSOI, FinFET, quadruple-gate MOSFET and
CNT FET to overcome these problems. However, I have proposed and analyzed planar underlap
fully depleted strained SOI (underlap-SSOI) MOSFET in my PhD work. This device is
undertaken for research in order to continue with the Moores law till 10 nm while utilizing the
current fabrication techniques. The non-planar structures require costly/new fabrication
infrastructure and specialized manpower.
In this direction, Samsung developed 28 FDS (28 nm FD-SOI technology node) device
technology for mass production for IoT applications [52]. Recently, semiconductor industrys
first 22 nm FD-SOI technology has been presented by GLOBALFOUNDRIES and company
has projected to extend the feature of 22nm technology to 10 nm technology.

Research Problem:

During my PhD, I have observed that the underlap structure leads to significant improvement in
scaling capability of FD-SOI MOSFET. However, beyond 10 nm, underlap-SSOI needs spacer
dielectric constant more than 22 (HfO2) which will increase the parasitic capacitance and lower
the operating speed. Another issue with underlap-SSOI device for 10 nm technology is that the
body thickness scaling reaches its ultimate limit, which restricts further device scaling.

Research Aim and Objective:


The aggressive scaling (beyond 10 nm) of underlap-SSOI device requires the innovative
performance booster techniques to overcome the physical limits and lower SCEs. The dual-k
spacer may be utilized for lowering two reasons; firstly lowering the parasitic capacitance by
lowering the outer spacer dielectric constant and secondly improving the gate control over
underlap region by increasing the inner spacer dielectric constant. The inner and outer spacer
length in dual-k spacer may also provide additional flexibility to achieve the performance
requirement for different applications. The limitation of body thickness scaling may be addressed
using raised Source/Drain regions.
Besides the development of novel device, I also wish to fabricate the proposed device to
observe the real time characteristics of the device. The National Nanofabrication Center (NNFC)
has advanced fabrication facilities and provided easy access for academicians or researchers. I
always interested to broaden my research field basing on the new development in science and
technology and ready to work in well co-operated and collaborated research groups.

Static Random Access Memory (SRAM):

SRAM design in the Electronics field is of prominent interest. SRAMs dominate the memory
hierarchy in performance but they are often integrated in a lesser capacity due to area limitations
and high cost per bit. The trend of SRAM increasing for different processors based on different
technology nodes. It is also projected that the percentage of embedded SRAM in System on Chip
(SoC) products will increase further from the current 84% to as high as 94% by the year 2017.
Therefore, SRAM downscaling indicates the great opportunity of reducing the cost per function
in microprocessors and SoCs. The practical utility of novel underlap-SSOI device may be
explored for the robust SRAM design. The higher scalability and lower leakage power
consumption in SRAM design may be achieved using innovative underlap-SSOI device.