Electronics Lab Manual

Electronics
Laboratory Manual
Lab Syllabus
Subject Code 15EEL37 IA Marks 20

No. of Lecture Hrs./ Week 03 Exam Hours 03
Total No. of Lecture Hrs. 42 Exam Marks 80
Credits 02
EXPT NO. TITLE
1 Design and Testing of Full wave centre tapped transformer type and
Bridge type rectifier circuits with and without Capacitor filter.
Determination of ripple factor, regulation and efficiency.
2 Static Transistor characteristics for CE, CB and CC modes and

determination of h parameters.
3 Frequency response of single stage BJT and FET RC coupled amplifier and
determination of half power points, bandwidth, input and output
impedances.
4 Design and testing of BJT - RC phase shift oscillator for given frequency of
oscillation.
5 Determination of gain, input and output impedance of BJT Darlington

emitter follower with and without bootstrapping.
6 Simplification, realization of Boolean expressions using logic

gates/Universal gates.
7 Realization of half/Full adder and Half/Full Subtractors using logic gates.

8 Realization of parallel adder/Subtractors using 7483 chip- BCD to Excess-3
code conversion & Vice -Versa.
9 Realization of Binary to Gray code conversion and vice versa.

10 Design and testing Ring counter/Johnson counter.
11 Design and testing of Sequence generator.
12 Realization of 3 bit counters as a sequential circuit and MOD N counter
design using 7476, 7490, 74192, 74193.
Dept. of Electrical and Electronics 2016-2017 Page 1

Electronics
Laboratory Manual
Course objectives
To design and test half wave and full wave rectifier circuits
To design and test different amplifier and oscillator circuits using BJT
To study the simplification of Boolean expressions using logic gates
To realize different Adders and Subtractors circuits
To design and test counters and sequence generators.
Course outcomes
At the end of the course the student will be able to:

Design and test different diode circuits.
Design and test amplifier and oscillator circuits and analyze their performance.
Use universal gates and ICs for code conversion and arithmetic operations.
Conduct of Practical Examination
All laboratory experiments are to be included for practical examination.

Breakup of marks and the instructions printed on the cover page of answer script to be strictly
adhered by the examiners.
Students can pick one experiment from the questions lot prepared by the examiners.
Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be
made zero.
CONTENTS
Expt. No. TITLE Page No.

Electronics
Laboratory Manual
1. Design and Testing of Full wave centre tapped transformer type and
Bridge type rectifier circuits with and without Capacitor filter.
Determination of ripple factor, regulation and efficiency.
2. Static Transistor characteristics for CE, CB and CC modes and

determination of h parameters.
3. Frequency response of single stage BJT and FET RC coupled amplifier

and determination of half power points, bandwidth, input and output
impedances.
4. Design and testing of BJT - RC phase shift oscillator for given frequency
of oscillation.
5. Determination of gain, input and output impedance of BJT Darlington

emitter follower with and without bootstrapping.
6. Simplification, realization of Boolean expressions using logic

gates/Universal gates.
7. Realization of half/Full adder and Half/Full Subtractors using logic gates.
8. Realization of parallel adder/Subtractors using 7483 chip- BCD to

Excess-3 code conversion & Vice -Versa.
9. Realization of Binary to Gray code conversion and vice versa.
10. Design and testing Ring counter/Johnson counter.
11. Design and testing of Sequence generator.
12. Realization of 3 bit counters as a sequential circuit and MOD N

counter design using 7476, 7490, 74192, 74193.
Expt No: 6 Simplification and Realization of Boolean Expression

Electronics
Laboratory Manual
Aim: To Simplify and realize the given Boolean expressions using Logic Gates/Universal Gates.
Components required: IC 7408,IC 7432, IC 7400,IC 7402, IC 7410,7404,Patch chords and trainer kit
Theory :
Boolean Expression consists of variables, which can have one of the two possible values. Either one or
zero. There are two methods to minimize Boolean expression
1. Boolean Algebra
2. Karnaugh map
Boolean algebra: Boolean algebra provides a means by which logic circuitry may be expresses
symbolically, manipulated and reduced .Use of Boolean algebra in logic circuits lead to following
results:
Minimizes the number of logic gates in a circuit

Minimizes the cost of a circuit
A circuit which uses only one type of basic logic gates such as NAND gate becomes possible.
A circuit having parallel, redundant gates with minimum propagation delay can be designed.
De-Morgan suggested two theorems that form an important part of Boolean algebra that is
1. Sum of Product
2. Product of sum
Procedure:
1. Verify all the components and the Patch Chords whether they are in good condition.
2. Fix the IC on the base board.
3. Connections are made as shown in the logic diagram.
4. Verify the truth Table for each expression.

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Laboratory Manual
LOGIC EXPRESSIONS:
Truth Table
Using Basic Gates
A B C Y1 C
1) Y1=(A+BC)(B+A 0 0 0 0 )
0 0 1 0
Simplification: 0 1 0 0
0 1 1 1
C 1 0 0 1
Y1=(A+BC)(B+A ) 1 0 1 0
C 1 1 0 1
= AB+ A +BC 1 1 1 1

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Laboratory Manual
Using NAND Gates
AB + AC + BC
Y1=
=
AC
A B C
Y1
Using Nor Gate :

C
Y1= ( A+BC)(B+ A )
C
= (A+B)(A+C)(B+A)(A+ )
( A C )( A B)( B C )
=
( A C ) ( A B) B C)
=
( (Using only NOR gates)
A B C
Y11
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Laboratory Manual
A
ABC C AB
2) Z= +AB +Y C+ABC
Using Basic Gates:
AB C C
Z= (C+ )+AB(C+ )
AB
= +AB
Truth Table
A B C Y
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Using Nand Gates
Z=
A B
B

Z
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Laboratory Manual
Using only NOR Gates
B A
Z= (A+ )+( +B)
A B
Result : The given Boolean expression is verified using basic and universal gates.

Electronics
Laboratory Manual
VIVA QUESTIONS :
1. What is Number System? Classify
2. Define Base of a number or Radix of a number system.
3. What is logic gate? Classify
4. Why NAND and NOR are called as Universal gates.
5. What is the difference between Binary addition and Boolean addition
6. Define truth table.
7. What is the need for simplification of Boolean expression?
8. What are the methods followed to simplify a given Boolean expression.
9. Which is the best method to perform simplification.
10. Using K-map, to haw many variables maximum can be simplified.
11. Define cell.
12. What is the difference between Prime implicants and essential prime implicants?
13. Difference between Minterm and Maxterm.
14. What is SOP and POS
15. In K-Map what type of coding is used? Why other codes are not used.

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Laboratory Manual
16. What do you mean by ORing of AND terms and ANDing of OR terms
17. Realize the XNOR function using only XOR gates.
18. What do and indicate.
19. How do you convert SOP into POS and vice versa
20. Does NAND gate obey the commutative, associative and distributive laws? Justify.
21. Why NAND & NOR gates are called universal gates?
22. Realize the EX OR gates using minimum number of NAND gates.
23. Give the truth table for EX-NOR and realize using NAND gates?
24. What are the logic low and High levels of TTL ICs and CMOS ICs?
25. Compare TTL logic family with CMOS family?
26. Which logic family is fastest and which has low power dissipation?
27. What are the different methods to obtain minimal expression?
28. What is a Min term and Max term
29. State the difference between SOP and POS.
30. How an and gate is constructed ?.
Expt No: 7 Half Adder/ Full Adder and Half Subtractor/ Full Subtractor
using Logic Gates / Universal Gates
Half Adder and Full Adder
Aim: Realization of Half /Full Adder using Logic Gates
Components required: IC 7400,, IC 7486, IC 7408, 7404, Patch chords and trainer kit

Electronics
Laboratory Manual
Theory:
About Nand And Nor Gates: The NAND and NOR gates is termed a universal gates (or universal
block), because almost any logic function can be made by suitable inter connecting NAND gates or NOR
gates. For ex: different combinations of the NAND GATE or NOR gate can be employed to produce any
one of the basic three functions of AND, OR and INVERT (NOT) gates.
Ex-Or Gate: Ex-or gate means Exclusive OR gate. This gate has a high output only when an odd number
of inputs are high: or in other words, the Ex-or gate produces a Logic1. Whenever either one of the
inputs is one, but not when both are 1. The Ex-or operator is the Sign +, as indicated in the figure.
Half Adder and Full Adder: The simplest binary adder is called a half adder. Half adder has two input
bits and two output bits. One bit is the sun and the other is carry. S and C represent these respectively in
the logic symbol.
A half adder has no provision to add a carry from the lower order bits when binary numbers are
added. When two input bits and a carry are to be added, the number of input bits becomes three and the
input combination increases to eight. For this, a full adder is used. Like half adder, it also has a sum bit
and carry bit. New carry generated is represented by Cn and carry generated from the previous addition is
represented by Cn 1.
The expression for half adder is as follows,

Sum = A B
Carry = AB
The expression for full adder is as follows,

Sum = A B C

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Laboratory Manual

Carry = AB+C(A B)
Procedure:
1. Verify all the components and patch chords whether they are in good condition.
2. Make connections as shown in logic diagram.
3. Give supply to the trainer kit.
4. Provide the input data to the circuit via switches.
5. Verify the truth table sequence and observe the outputs.

B
A Electronics
Laboratory Manual
Half Adder:
a) Half Adder using Basic gates

C=AB
b) Half Adder using NAND Gates

S= A B
B
A B SUM CARRY
(S) (C) C=AB
0 0 0 0
0 1 1 0 Truth Table :
1 0 1 0
1 1 0 1

C A
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Laboratory Manual
FULL ADDER:
a) Full Adder using Basic Gates
b) Full Adder using NAND Gates only
Truth Table:
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Laboratory Manual
K-Map Simplification
1) SUM
AB
00 01 11 10
0 1 1
2) CARRY
AB
00 01 11 10
Result: The half adder and full adder circuits are verified using basic and universal gates.

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Laboratory Manual
Half Subtractor and Full Subtractor
Aim: Realization of Half /Full Subtractor using Logic Gates
Components required: IC 7400,, IC 7486, IC 7408, 7404,IC 7432, Patch chords and trainer kit
Theory:
Half subtractor :
Half subtractor is a combinational circuit that subtracts 2 bits and produces their difference. It also has an
output to specify if a one has been borrowed. Half subtractor can be implemented by using basic gates or
by using only NAND gates.
Full subtractor :
Full subtractor circuit performs subtraction between 2 bits, taking into account that a one may have been
borrowed by a lower significant stage. The circuit has 3 inputs and 2 outputs. The truth table and the logic
expressions are given below in the observation.
The expression for half subtractor is as follows,

Difference = A B
AB
Borrow =
The expression for full subtractor is as follows,

Difference = A B C
A
Borrow = B+C(A B)
Procedure:
1 Verify all the components and patch chords whether they are in good condition.
2 Make connections as shown in logic diagram.
4. Provide the input data to the circuit via switches.

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Laboratory Manual
5. Verify the truth table sequence and observe the outputs.

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Laboratory Manual
C
Half Subtractor using NAND Gates
A
C= B
Truth Table
A B Diff(D) Borrow
(B)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Full Subtractor:
a. Full Subtractor using Basic Gates
A
B

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Laboratory Manual
b. Full Subtractor using NAND Gates only
A
B0= B+C(A B)
Truth Table:
A B C Diff Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
1) Diff
AB
00 01 11 10
0 1 1

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Laboratory Manual
2) Borrow
AB
00 01 11 10
Result: The half and full subtractor are verified using basic and universal gates

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Laboratory Manual
VIVA QUESTIONS :
1. What is a half adder?
2. What is a full adder?
3. What are the applications of adders?
4. What is a half subtractor?
5. What is a full subtractor?
6. What are the applications of subtractors?
7. Obtain the minimal expression for above circuits.
8. Realize a full adder using two half adders
9. Realize a full subtractors using two half subtractors
10. What is the internal structure of 7483 IC?
11. How do you realize a subtractor using full adder?
12. What is a ripple Adder? What are its disadvantages?
13. Define the function of half adder, Full adder, half Subtractor, and full Subtractor.
14. What is the difference between carry and overflow?
15. What is the function of Parallel adder and subtractor?
16. Give the pin configuration of IC 7483.
17. What is the need for complements?

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Laboratory Manual
18. Classify the types of complements.
19. How the twos complement operation is achieved using IC 7483.
20. What is the need for XOR gates in Parallel adder and subtractor?
21. What are the conditions required to perform Parallel addition, 1s complement parallel subtraction,
and 2s complement parallel subtraction.
22. What is the largest decimal number that can be added with a parallel adder consisting of four full
adders?
23. To perform addition of two 6-bit numbers, we need a parallel adder having ---------- full adder
circuits
24. Can addition of two BCD numbers be performed using IC 7483? If yes, what are the changes to be
made in the circuit?
25. While adding two BCD numbers, if the sum is not a BCD number, what is to be done?
Expt No: 8 Realization of parallel adder/Subtractors using 7483 chip- BCD to

Excess-3 code conversion & Vice -Versa.
Aim: To realize a parallel adder/subtractor using 7483 chip
Components required: , IC 7483, IC 7404, Patch chords and trainer kit
THEORY:
The 7483 is a TTL IC with four full adders in it. This means that it can add nibbles. To add bytes, we
need to use two 7483 ICs.
4-bit binary adder A3 A2 A 1 A0 and B3 B2 B1 B0 are inputs and Cout S3 S2 S1 S0 is the output CARRY IN
Pin is grounded.
4-bit add/subtract circuit:

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Laboratory Manual
The circuit is setup and shown in figure. To add the nibbles, C in is to be made 0. To subtract B 3 B2 B1 B0
from A3 A2 A 1 A0 Cin is to be made 1. EX-OR gates function as controlled inverters.
When Cin = 1, B3 B2 B1 B0 is complemented. Now A3 A2 A 1 A0 complemented version of B3 B2 B1 B0

and Cin pin are added together. Cout is ignored. By this, the 2s complement of subtrahend is added with
minuend. If minuend is less than subtrahend, the obtained output will be the 2s complement of
difference.
For example :
10 (Minued) Binary equivalent of 10 1010 +
9 (Subtrahend) 2s complement 9 0111
-1 (result) Result 1 0001
Carry omitted
When Minued < Subtrained :
9 Binary equivalent of 9 1001 +

10 2s complement of 10 0110
-1 2s complement 1 1111
Procedure:
1. Check all the components and IC Packages.
2. Set Up7483 for parallel adder circuit and verify the Truth Table.
3. Set up Parallel adder/Subtractor as shown in logic diagram.

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Laboratory Manual
4. For C-in=0, the circuit works as a parallel adder. For C-in=1 it acts as a parallel subtractor. Verify
the truth tables for both.

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Laboratory Manual
4 Bit Adder/Subtractor Circuit
B3 B2 B1 B0
Ctrl
=0 to add
A3 A2 A1 A0
=1 to subtract
1 3 8 10 16 4 7 11
VCC
13
5
IC 7483 Cin
GND
12
14 15 2 6 9
Cout S3 S2 S1 S0
Truth Table:
Addition:
Decima Binary Eq no 1 Binary Eq no 2 Output Sum

l no
A B A3 A2 A1 A0 B3 B2 B1 B0 Co S3 S2 S1 S0
9 5 1 0 0 1 0 1 0 1 0 1 1 1 0
12 8 1 1 0 0 1 0 0 0 1 0 1 0 0
Subtraction:
Decima Binary Eq no 1 Binary Eq no 2 Output Sum

l no
A B A3 A2 A1 A0 B3 B2 B1 B0 Co S3 S2 S1 S0
8 14 1 0 0 0 1 1 1 0 0 1 0 1 0
8 2 1 0 0 0 0 0 1 0 1 0 1 1 0
Result : The parallel adder and subtractor circuit is realized using 7483 IC
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Laboratory Manual
BCD TO EXCESS-3 CODE CONVERSION AND VICE VERSA
Aim: To perform the following code conversions
a. BCD to Excess-3 code

b. Excess-3 to BCD Code conversions
Components required: IC 7486, 7483, Trainer kit, patch chords.

Theory:
Natural BCD Code: In these code decimal digits 0 to 9 are represented (coded) by their natural binary
equivalents using 4 bits and each decimal digit of a decimal number is represented by four bit code
individually. For ex: (23)10 is represented by 0010 0011using BCD code, rather than (10111) 2. From this it
is observed that it requires more number of bits to code a decimal number using BCD code than using the
straight binary code. However, in spite of this disadvantage it is very convenient and useful code for input
and output digital systems.
This code is also known as 8-4-2-1 code or simply BCD code. 8, 4, 2, and 1 are the weights of the four
bits of the binary codes of each decimal digit similar to straight binary number system. Therefore this is a
weighted code and arithmetic operations can be performed using this code.
Excess-3 Code: Excess-3 code is another form of BCD code, in which each decimal digit is coded into a
4-bit binary code. This code for each decimal digit is obtained by adding decimal 3 to the natural BCD
code of the digit. For example decimal 2 is coded as 0010+0011=0101 in Excess-3 code. It is not a
weighted code. This code is a self complementing code, which means 1s complement of the coded
number yields 9s complement of the number itself. for example Excess-3 code of a decimal 2 is 0101,
its 1s complement is 1010 which is Excess-3 code for decimal 7,which is 9s, complement of 2. the self
complementing property of this code helps considerably in performing subtraction operation in digital
systems.

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Laboratory Manual
Procedure:
4. For different Excess-3 codes inputs, verify the corresponding BCD data outputs according to
the truth table.
5. And also for different BCD data inputs verify the corresponding Excess-3 code outputs
according to the truth table.

Vcc
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Laboratory Manual
Truth Table: Gnd

BCD i/p Excess i/p
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
Logic diagram for BCD to Excess-3 Code Conversion

IC 748C

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Laboratory Manual
Truth table for Excess-3 to BCD Conversion
Excess 3 i/p BCD o/p

B3 B2 B1 B0 E3 E2 E1 E0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
Result: The BCD to Excess-3 conversion and vice versa is realized using IC-7483.

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Laboratory Manual
VIVA QUESTIONS:
1. Explain the need for code conversion.
2. What are the steps involved to convert a binary number into a Gray Code?
3. What are the steps involved to convert a Gray number into a binary Code?
4. Is gray code a weighted code?
5. What is weighted code? Give examples
6. What is Non weighted codes, give example?
7. What are reflected codes give examples?
8. What are self-complementary codes give examples?
9. What is BCD code?
10. Where are BCD codes used?

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Laboratory Manual
Expt No: 9 BINARY TO GRAY CONVERSION AND VICE VERSA
Aim: To perform the following code conversions

1. A four bit Binary data to gray code converter using only NAND gates
2. A four bit Gray data to binary code converter using only NAND gates
3. A four bit Binary data to gray code converter using only EX-OR gates
4. A four bit Gray code to Binary data converter using only EX-OR gates
Components required: IC 7486, 7400, Patch chords, Trainer kit
Theory:
Gray Code: Gray code is an un-weighted code which means that there are no specific weights assigned to
the bit positions. The gray code exhibits only a single bit change from one code number to the next. Gray
code is not an arithmetic code.
Binary Data: The binary number system is simply another way to count. It is less complicated than the
decimal system, because it is composed of only 2 digits. The two binary digits are 1 and 0. The
position of the 1 or 0 in a binary number indicates its weights or value within the number. The weight
of each successively higher position (to the left) in a binary number is an increasing power of two.
Binary to gray conversion:

The conversion between Binary code and Gray code is sometime useful. The following are the steps to
convert a Binary number to a Gray code number

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Laboratory Manual
1. The most significant digit (left most) in the Gray code is the same as the corresponding digit in the
Binary number.
2. Going from left to right, add each adjacent pair of binary digits to get the next gray code digit.
Disregard carries.
Gray to Binary conversion:

To convert from Gray code to Binary a similar method is used but there are some differences. The
following are the steps to convert a Gray code number to the Binary number
1. The most significant digit (left most) in the binary code is the same as the corresponding digit in
the gray code.
2. Add each binary digit generated to the gray digit in the next adjacent position. Disregard carries.
Procedure:
4. For different Binary data inputs, verify the corresponding Gray code outputs according to the truth
table.
5. And also for different Gray code inputs verify the corresponding Binary data outputs according to
the truth table.

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Laboratory Manual
Truth Table:
Binary i/p Gray code o/p
B B2 B1 B0 G3 G2 G1 G0
3
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

G3= B3 B1B0
G2= B2 B3
B1B0 00 01 11 10
B3B2
00 01 11 10
B3B2 00
00
01
01 11
11
10
10

B1B0
G1= B1 B2 G0= B0 B1
00 01 11 10
B1B0 B3B2
00 01 11 10 00
B3B2
00
01
01
11
11
10 10
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Laboratory Manual
Logic diagram for Binary to G
Logic diagram for Binary to Gray Code Conversion using NAND gates
Bo
Go
B1
G1
B2
G2
B3
G3
Logic diagram for Binary to Gray Code Conversion using basic gates
B3 G3
G2
B2
G1
B1
G0
B0

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Laboratory Manual
Gray to binary conversion
Truth Table:
Gray i/p Binary o/p
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0
K-Map
G1G0 G1G0
00 01 11 10 00 01 11 10
G3G2 G3G2
00 00
01 01
11 11
10 10

B3= G3 B2= G2 G3

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Laboratory Manual
G1G0
G1G0
00 01 11 10
G3G2 00 01 11 10
G3G2
00
00
01
01
11
11
10
10

B1= G1 G2 G3 B0= G0 G1 G2 G3
Logic diagram for GRAY to Binary Code Conversion using basic gates
G3 B3
B2
G2
B1
G1
B0
G0

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Laboratory Manual
Logic diagram for GRAY to Binary Code Conversion using NAND gates
Go
Bo
G1
B1
G2
B2
G3
B3
Result: The binary code to gray code and vice versa is realized using basic gates and universal gates.

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Laboratory Manual
VIVA QUESTIONS :
1. What do you mean by code conversion?
2. What are the applications of code conversion?
3. What are code converters?
4. What is the necessity of code conversions?
5. What is gray code?
6. Realize the Boolean expressions for
a) Binary to gray code conversion

b) Gray to binary code conversion

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Laboratory Manual
Expt No: 10 RING COUNTER & JOHNSON COUNTER
Aim: To realize the operation of ring and Johnson counter using 7495.
Components Required: I.C.7495, patch chords, digital trainer.
Theory:
Ring counter
Ring counter is a basic register with direct feedback such that the contents of the registers simply
circulated around the register when the clock is running. Here the last output that is QD in a shift register
is connected back to the serial input. A four bit shift register ring counter is shown in figure.
Johnson counter
A basic ring counter can be modified slightly to produce another type of shift register counter, which will
have somewhat different properties. That type of basic shift register with inverse feed back is called shift
counter or a Johnson counter or a twisted ring counters. In Johnson counter the compliment of the last
outp8t that is QD is connected back to the not gate input and the Not gate output is connected back to the
serial input. The four bit Johnson counter gives a total of eight states. As the clock pulse is applied at pin
no 9 will fill up with one (1) from left to right and then it will fill up with 0.
Procedure :
1) Connections are made as shown in the logic diagram.
2) Apply the data 1000 at A,B,C,D respectively.
3) Keeping the mode M=1, apply one clock pulse.
4) Now the mode M is made 0 and clock pulse are applied one by one and the truth table is verified

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Laboratory Manual
Logic diagram: Ring Counter
VCC QAc QBc QC QD CLK1
14 13 2 11 10 9 8
IC 7495
1 2 3 4 5 6 7
DSS A BS C DS MC Gnd
* MC = mode control = 0
Truth table ClK 1 QA QB QC QD

0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
4 1 0 0 0
5 0 1 0 0
6 0 0 1 0
7 0 0 0 1
8 1 0 0 0

Electronics
Laboratory Manual
Logic diagram: Johnson Counter
14 13 2 11 10 9 8
IC 7404
IC 7495
1 2 3 4 5 6 7
DSS A BS C DS MC Gnd
Truth Table:
Mode Clock QA QB QC QD
0 0 0 0 0 0
0 1 1 0 0 0
0 2 1 1 0 0
0 3 1 1 1 0
0 4 1 1 1 1
0 5 0 1 1 1
0 6 0 0 1 1
0 7 0 0 0 1
0 8 0 0 0 0
0 9 1 0 0 0
Result: The ring and Johnson counter are verified using IC-7495.

Electronics
Laboratory Manual
VIVA QUESTIONS :
1. What is a ring counter?
2. What is a Johnson counter?
3. What is the difference between Flip-Flop & latch?
4. Give examples for synchronous & asynchronous inputs?
5. What are the applications of different Flip-Flops?
6. What is the advantage of Edge triggering over level triggering?
7. What is the relation between propagation delay & clock frequency of flip-flop?
8. What is race around in flip-flop & how to over come it?
9. Convert the J K Flip-Flop into D flip-flop and T flip-flop?
10. List the functions of asynchronous inputs?
11. What is a Flip-flop?
12. What is the difference between a flip-flop & latch?
13. How J-k flip-flop can be converted into T & D types?
14. What is the difference between Synchronous and Asynchronous clock pulse.
15. What are PISO, SIPO, and SISO with respect to shift register
16. Differentiate between serial data & parallel data
17. What is the significance of Mode control bit?

Electronics
Laboratory Manual
Expt No: 11 SEQUENCE GENERATOR
Aim: Design of a sequence Generator using IC 7495
Components Required: Digital trainer kit, IC 7495 & 7486, patch chords.
Theory:
A sequential circuit, which generates a prescribed sequence of bits, in synchronism with a clock, is
referred as sequence generator. For the design of sequence generator we must determine the required
number of the clocks and the logic circuit for the next state decoder. The output of next state decoder is
function of Qa, QB, QC, QD Qn. The next state decoder is the logic circuit, which decodes the output of
the shift register and generates the output to get desired sequence from QA output of the shift register.
Procedure:
1) Make connections as per the logic diagram

Electronics
Laboratory Manual
2) By keeping the mode=1. Load the input through A, B, C, D as 1111 by giving one clock pulse
3) For count mode make mode=0
4) And observe the sequence at QA, QB, QC and QD.
1.Sequence given ; 100010011010111

K-MAP
QA QB QC QD Y
1 1 1 1 0
0 1 1 1 0
0 0 1 1 0
0 0 0 1 1
1 0 0 0 0
0 1 0 0 0
0 0 1 0 1
1 0 0 1X 1 1 0 1
1 1 0 00 1 00 1 Y=QcQD +QD Qc
0 1 1 0 1
0 1 0 1 Y = Qc+ QD
1 0 1 1 0
0 1 0 10 1 10 1
1 0 1 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1
1 1
1

Electronics
Laboratory Manual
Logic diagram:
14 13 2 11 10 9 8
IC 7495
1 2 3 4 5 6 7
A BS C DS MC Gnd
Serial input

Electronics
Laboratory Manual
Sequence : 1101011 sequence length =7
Truth table :
K-Map:
S QA QB QC QD
1 1 1 0 1X X X X
1 1 1 1 0X 1 1 X
0 1 1 1 1X 1 0 1
1 0 1 1 1X X 0 1
0 1 0 1 1
1 0 1 0 1
1 1 0 1 0
S = QA +QC +QD
Logic diagram :
14 13 2 11 10 9 8
IC 7495
1 2 3 4 5 6 7
DS A BS C DS MC Gnd
Result: The given sequence is designed and implemented using IC-7495.

Electronics
Laboratory Manual
VIVA QUESTIONS :
1. What is the necessity for sequence generation?

Electronics
Laboratory Manual
Expt. No. 12 3 BIT SYNCHRONOUS COUNTER
Aim: To design and test a 3 bit synchronous counter using 7476 FOR the given sequence:
1. Mod 5 Synchronous counter
Components Required: IC 7476, 7408, Trainer Kit, patch chords.

Theory:
The ripple counter requires a finite amount of time for each flip flops to change state. The propagation
delay causes case flip flop in the counter to change state at a lower time than the first, resulting in a
serious limitation in the operating frequency. This problem can be solved by using a synchronous of
parallel counter, where every flip flop is triggered in synchronism with the clock, and all o/ps scheduled
to change do so simultaneously.
The structure, waveforms & truth tables of the synchronous counters are given below. the counter
progresses upwards in a natural binary sequence from count 000 to100 , advancing one. Count with every
negative clock transition and gets back to 000 after this cycle. We call this as mod 5 counter.
Procedure:
1. Connections are made as shown in the logic diagram
2. Find the number of FFs required using the equation
i. M 2n ----- this equation determines.
3. Write the count sequence in the tabular form
4. Prepare the excitation table of the FFs and determine the FF i/ps which must be present for the
desired next state from the present state
5. In terms of flip flop outputs prepare K map for each FF i/p and simplify the K-maps expression
in to a minimized form.
6. make connections as shown in the logic diagram
7. verify the truth table sequence and observe the o/ps.

Electronics
Laboratory Manual
Pin diagram :
Gnd
K1 Q1 Q1 Q2
Q2 J2
16 15 14 13 12 11 10 9
IC 7476
1 2 3 4 5 6 7 8
Cp1 Pr 1 Cr1S J1 VCC Cp2 Pr 2 Cr2
Cp = Clock pulse
Pr = Preset
Cr = Clear
Q = uncomplemented o/p
Q = Complemented o/p
J & k = i/ps
J k Flip flop Truth table:
Pr Cr Clk J K Q+ Q+
1 1 1 0 0 Q Q
No change
1 1 2 0 1 0 1 Reset
1 1 3 1 0 1 set
1 1 4 1 1 1/0 0/1 Toggle

Electronics
Laboratory Manual
Excitation Table:
Q+ Q+ j k
0 0 0 Q
0 1 1 1
1 0 X 1
1 1 X 0
Transition Table:
Present State Next State Inputs
QC QB QA QC QB QA JA KA JB KB JC KC
0 0 0 0 0 1 1 X 0 X 0 X
0 0 1 0 1 0 X 1 1 X 0 X
0 1 0 0 1 1 1 X X 0 0 X
0 1 1 1 0 0 X 1 X 1 1 X
1 0 0 0 0 0 0 X 0 X X 1

Electronics
Laboratory Manual
Karnaugh Map to derive the flip flop input function:
QB QA QB QA
00 01 11 10 00 01 11 10
QC QC
0 0 X 1 1 X
JA=QC
1 1 X X X X
KA=1
QB QA QB QA
00 01 11 10 00 01 11 10
QC QC
0 0
JB=QA KB=QA
1 1
QB QA
QBQA
00 01 11 10
00 01 11 10 QC
QC
0 X X X X
0 0 0 1 0
1 1 X X X
1 X X X X
KC=1
JC=QA. QB

QA
Electronics
Laboratory Manual
Mod 5 Synchronous counter
Mod 8 Synchronous counter (0-7)
Transition table
Present State Next State Inputs

QC QB QA QC QB QA JA KA JB KB JC KC
0 0 0 0 0 1 1 X 0 X 0 X
0 0 1 0 1 0 X 1 1 X 0 X
0 1 0 0 1 1 1 X X 0 0 X
0 1 1 1 0 0 X 1 X 1 1 X
1 0 0 0 0 1 1 X 0 X X 0
1 0 1 1 1 0 X 1 1 X X 0
1 1 0 1 1 1 1 X X 0 X 0
1 1 1 0 0 0 X 1 X 1 X 1
KQB QA
-map
00 01 11 10
QB QA
Qc
0
JA=1 00 01 11 10
Dept.
1 of Electrical and Electronics 2016-2017 Page 52
Electronics
Laboratory Manual
Qc X 1 1 X
0
1 X 1 1 X
KA=1
QB QA QB QA
00 01 11 10 00 01 11 10
QC
Qc 1 1 X X
0 0 KB=QA
1 1 1 X X 1
JB=QA
QB QA QB QA
00 01 11 10 00 01 11 10
Qc 1 X X 1 Qc
0 0
KC=QA.QB
1 1 X X X 1
JC=QB.QA

QC
Electronics
Laboratory Manual
Logic diagram:
Mod 8 Synchronous counter
QB
QA
Vcc
Result : The Mod-5, Mod-8 counters are designed, implemented and verified.

Electronics
Laboratory Manual
VIVA QUESTIONS :
1. How to design a Mod-N counter?
2. How addition and subtraction is done in a parallel adder circuits.
3. Explain the design for a Sequence Generator if the sequence given is ...
4. What is the difference between a sequence generator and PRBS?
5. Give the difference between sequential and combinational circuit.
6. What is a shift register?
7. What are the different modes of operation in a shift register?
8. What is the function of mode-control pin?
9. What are synchronous counters?
10. What are the advantages of synchronous counters?
11. What is an excitation table?
12. Write the excitation table for D, T FF
13. Design mod-5 synchronous counter using T F

Electronics Laboratory Manual
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Electronics

Subject Code 15EEL37 IA Marks 20

2 Static Transistor characteristics for CE, CB and CC modes and

5 Determination of gain, input and output impedance of BJT Darlington

6 Simplification, realization of Boolean expressions using logic

7 Realization of half/Full adder and Half/Full Subtractors using logic gates.

9 Realization of Binary to Gray code conversion and vice versa.

Dept. of Electrical and Electronics 2016-2017 Page 1

At the end of the course the student will be able to:

Conduct of Practical Examination

All laboratory experiments are to be included for practical examination.

Dept. of Electrical and Electronics 2016-2017 Page 2

2. Static Transistor characteristics for CE, CB and CC modes and

3. Frequency response of single stage BJT and FET RC coupled amplifier

5. Determination of gain, input and output impedance of BJT Darlington

6. Simplification, realization of Boolean expressions using logic

7. Realization of half/Full adder and Half/Full Subtractors using logic gates.

8. Realization of parallel adder/Subtractors using 7483 chip- BCD to

9. Realization of Binary to Gray code conversion and vice versa.

10. Design and testing Ring counter/Johnson counter.

11. Design and testing of Sequence generator.

12. Realization of 3 bit counters as a sequential circuit and MOD N

Expt No: 6 Simplification and Realization of Boolean Expression

Dept. of Electrical and Electronics 2016-2017 Page 3

Minimizes the number of logic gates in a circuit

Dept. of Electrical and Electronics 2016-2017 Page 4

Dept. of Electrical and Electronics 2016-2017 Page 5

Using NAND Gates

Using Nor Gate :

Using Basic Gates:

Using Nand Gates

Dept. of Electrical and Electronics 2016-2017 Page 7

Using only NOR Gates

Dept. of Electrical and Electronics 2016-2017 Page 8

1. What is Number System? Classify

2. Define Base of a number or Radix of a number system.

3. What is logic gate? Classify

4. Why NAND and NOR are called as Universal gates.

5. What is the difference between Binary addition and Boolean addition

6. Define truth table.

7. What is the need for simplification of Boolean expression?

8. What are the methods followed to simplify a given Boolean expression.

9. Which is the best method to perform simplification.

10. Using K-map, to haw many variables maximum can be simplified.

11. Define cell.

13. Difference between Minterm and Maxterm.

14. What is SOP and POS

Dept. of Electrical and Electronics 2016-2017 Page 9

17. Realize the XNOR function using only XOR gates.

18. What do and indicate.

22. Realize the EX OR gates using minimum number of NAND gates.

25. Compare TTL logic family with CMOS family?

27. What are the different methods to obtain minimal expression?

28. What is a Min term and Max term

29. State the difference between SOP and POS.

30. How an and gate is constructed ?.

Half Adder and Full Adder

Aim: Realization of Half /Full Adder using Logic Gates

Dept. of Electrical and Electronics 2016-2017 Page 10

The expression for half adder is as follows,

The expression for full adder is as follows,

Dept. of Electrical and Electronics 2016-2017 Page 11

Dept. of Electrical and Electronics 2016-2017 Page 12

b) Half Adder using NAND Gates