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ARM 9

PRESENTATION FOR EMIP-432C


FACULTY IN-CHARGE : DR. SEEMA AWASTHI
INTRODUCTION

THE ARM9 FAMILY IS THE MOST POPULAR ARM PROCESSOR


FAMILY EVER.
ARM9 PROCESSORS CONTINUE TO BE SUCCESSFULLY DEPLOYED
ACROSS A WIDE RANGE OF PRODUCTS AND APPLICATIONS.
THE ARM9 FAMILY OFFERS PROVEN, LOW RISK AND EASY TO USE
DESIGNS WHICH REDUCE COSTS AND ENABLE RAPID TIME TO
MARKET
ARM9 FAMILY PROCESSORS DELIVER DETERMINISTIC HIGH
PERFORMANCE AND FLEXIBILITY FOR DEMANDING AND COST-
SENSITIVE EMBEDDED APPLICATIONS.
ARM 9

ARM7 MICROARCHITECTURE IS GETTING OLD AND WILL BE


REPLACED WITH ARM9
ARM9 IS A GROUP OF OLDER 32-BIT RISC ARM PROCESSOR
CORES
CACHES ARE SEPARATE FOR INSTRUCTIONS AND DATA
(HARVARD ARCHITECTURE)
PIPELINE LENGTH IS 5 STAGES INSTEAD OF ARM7 3 STAGES. THIS
ALLOWS FOR FASTER CLOCKING.
VON NUEMANN VS HARVARD

HARVARD ARCHITECTURE HAS SEPARATE DATA AND INSTRUCTION BUSSES,


ALLOWING TRANSFERS TO BE PERFORMED SIMULTANEOUSLY ON BOTH BUSSES.
A VON NEUMANN ARCHITECTURE HAS ONLY ONE BUS WHICH IS USED FOR
BOTH DATA TRANSFERS AND INSTRUCTION FETCHES, AND THEREFORE DATA
TRANSFERS AND INSTRUCTION FETCHES MUST BE SCHEDULED - THEY CAN NOT BE
PERFORMED AT THE SAME TIME.
IT IS POSSIBLE TO HAVE TWO SEPARATE MEMORY SYSTEMS FOR A HARVARD
ARCHITECTURE. AS LONG AS DATA AND INSTRUCTIONS CAN BE FED IN AT THE
SAME TIME, THEN IT DOESN'T MATTER WHETHER IT COMES FROM A CACHE OR
MEMORY.
VON NUEMANN VS HARVARD
IN PRINCETON ARCHITECTURE
THE FOLLOWING CYCLES ARE REQUIRED TO EXECUTE THE ABOVE INSTRUCTION
CYCLE 1 : READ INSTRUCTION(INSTRUCTION FETCH CYCLE)
CYCLE 2 : READ DATA OUT FROM MEMORY AND STORE IN ACCUMULATOR

IN HARVARD ARCHITECTURE
CYCLE 1 : COMPLETE THE PREVIOUS INSTRUCTIONS AND READ THE PRESENT
INSTRUCTION.
CYCLE 2 : EXECUTE , READ DATA MEMORY AND STORE IN ACCUMULATOR. READ
NEXT INSTRUCTION.

ADVANTAGE OF THIS ARCHITECTURE IS THAT EACH INSTRUCTION TAKES ONE


INSTRUCTION CYCLE.
ARCHITECTURE
BASED ON ARMV5TE ARCHITECTURE
EFFICIENT 5-STAGE PIPELINE FOR FASTER THROUGHPUT AND
SYSTEM PERFORMANCE
SUPPORTS BOTH ARM AND THUMB INSTRUCTION SETS
Efficient ARM-Thumb interworking allows optimal mix of performance and
code density

HARVARD ARCHITECTURE - SEPARATE INSTRUCTION & DATA


MEMORY INTERFACES
Increased available memory bandwidth
Simultaneous access to I & D memory
Improved performance

31 X 32-BIT REGISTERS
5 STAGE PIPE-LINING
FETCH
THE PROCESSOR READS THE INSTRUCTION FROM INSTRUCTION MEMORY.

DECODE
THE PROCESSOR READS THE SOURCE OPERANDS FROM THE REGISTER
FILE AND DECODES THE INSTRUCTION TO PRODUCE THE CONTROL SIGNALS.

EXECUTE
THE PROCESSOR PERFORMS A COMPUTATION WITH THE ALU.
MEMORY
THE PROCESSOR READS OR WRITES DATA MEMORY.

WRITE
THE PROCESSOR WRITES THE RESULT TO THE REGISTER FILE, WHEN
APPLICABLE.
FLEXIBLE CACHE DESIGN
HARVARD CACHE ARCHITECTURE
SIZES CAN BE 4 KB TO 128 KB INCREASING IN POWERS OF 2
I & D CACHES CAN HAVE INDEPENDENT SIZES
LINE LENGTH FIXED AT 8 WORDS
FIXED 4 WAY SET ASSOCIATION
ZERO WAIT STATE ACCESSES
CRITICAL WORD FIRST CACHE LINE FILL
NON BLOCKING
ADVANTAGES OF ARM 9

DECREASE HEAT PRODUCTION AND LOWER


OVERHEATING RISK
CLOCK CYCLE IMPROVEMENT
CYCLE COUNT IMPROVEMENT
FASTER LOAD AND STORE
PRODUCT APPLICATIONS
TYPE
Consumer Smartphones, PDA, Set top box, PMP, Electronic toys,
Digital still cameras, Digital video cameras, etc
Networking Wireless LAN, 802.11, Bluetooth, Firewire, SCSI,
2.5G/3G Baseband, etc
Automotive Power train, ABS, Body systems, Navigation,
Infotainment, etc
Embedded USB controllers, Bluetooth controllers, medical
scanners, etc
Storage HDD controllers, solid state drives, etc
PRESENTED BY
IEC2015087 IMM2015007

IEC2015088 IMM2015008

IEC2015089 IBM2015001

IMM2015002 IBM2015002

IMM2015006

PREPARED BY
IEC2015086 IMM2015001
QUESTIONS ARE WELCOMED