ERA Appnote

Early Rail Analysis
Product Version: Innovus 16.1 or Higher, Voltus 16.1 or Higher

May, 2017
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Early Rail Analysis
Contents
Purpose ....................................................................................................................... 4
Audience...................................................................................................................... 4
Terms .......................................................................................................................... 4
Overview ...................................................................................................................... 4
Introduction to ERA...................................................................................................... 5
ERA Flow and TCL Options ......................................................................................... 6
ERA Flow ................................................................................................................. 6
ERA Flow TCL Options ............................................................................................ 8
ERA Power Specification ............................................................................................. 9
ERA Rail Options ....................................................................................................... 13
Summary of ERA Features ........................................................................................ 18
TIPS........................................................................................................................... 18
Support ...................................................................................................................... 19
Feedback ................................................................................................................... 19

Early Rail Analysis
Purpose
Early stage analysis of power grid is helpful in resolving grid integrity issues early in the
flow. It also improves the robustness of the power grid before the sign-off stage. Voltus
offers the Early Rail Analysis (ERA) feature with the same use model as Signoff Rail
Analysis. Static ERA can also be run with the Innovus base license.
Audience
This document is intended for Innovus/Voltus users who want to improve their grid
integrity at the early design stage or analyze power-grid structures for grid robustness.
Terms
ERA Early Rail Analysis
RLRP Resistance of Least Resistive Path
RC Resistor Current
TC Tap Current
Overview
ERA can analyze power-grid integrity early in the floorplan stage, after placement, as
well as post routing. It uses the available blocks, macros, standard cells and routing to
help improve the accuracy of ERA. The ERA flow lets you specify various power
constraints interactively during the power planning stage and performs rail analysis to
estimate whether the design meets these constraints. It uses the Voltus extractor and
rail analysis engines.

Early Rail Analysis
Introduction to ERA
More than ever, power integrity is vital in the successful creation of system-on-chip
(SoC) designs. Excessive rail voltage drop (IR drop) and ground bounce can create
timing problems. Also, excessive current can cause electromigration and related
thermal effects, leading to chip failures.
Solid power-network planning and implementation helps prevent these problems and a
good rail-signoff analysis flow ensures no power-related issues are left in the design. To
avoid timing problems and device failure, designers need to analyze an SoC's entire
power network to ensure that it provides adequate power integrity.
Undoubtedly, the best suggestion for both power-integrity planning and analysis is to
start as early as possible. Rough statistical toggle-rate estimates supply a useful
starting point to develop and evaluate the power grid. Being a bit pessimistic at the early
stages helps reveal power-grid weaknesses that might create problems later in the flow.
It is important to verify that the PG net routing, which usually goes in as part of
floorplanning process, is adequate, and will not need to be changed late in the flow.
Also, placement and routing engines consider the routing resources that are left over
after PG routing to be available for signal routing. Late changes to PG routing can
cause complications, especially with multi-pattern routing in lower technologies,
because the available legal routing outcomes are more constrained and more intensive
to achieve.
Early flow rail analysis limits sign-off stage surprises. The earliest point in the physical
design stage where reasonably accurate rail analysis can be performed is when coarse
placement and global routing have been performed. Rail analysis can be performed at
later points in the physical design flow. The final sign-off rail analysis is performed after
the final placement and routing.

Early Rail Analysis
ERA Flow and TCL Options

ERA Flow
ERA flow involves the following steps:
Grid completion
Ability to perform rail analysis early in the physical design flow is the capacity to process
PG routing data that is incomplete. ERA engine checks for the follow pins routing and
create virtual follow pins and virtual vias if they are missing.
Power estimation and user-defined distribution
ERA provides flexibility to specify power for various modules. This feature helps assign
power constraints to the fully unplaced, partially placed and fully placed designs. This
power can then be used for rail analysis.

Early Rail Analysis
Static and EM analysis
Static rail analysis is based on the average power consumption caused by the switching
probability for each instance in the design. This helps in computing IR drops and
current densities to verify if the power-grid routing has low enough resistance to deliver
the required current for a reliable chip operation and identify places with insufficient
power/ground mesh or missing connection causing electromigration failure.
The goal here is to ensure the quality of routing that makes up the power grid. The
computation of current drawn by a cell can be performed using the older style nonlinear
delay model (NLDM) or the newer current source waveforms (CCS power) liberty
models. For cells with larger footprints like memories and macros, the consumed
current may be distributed evenly as the first approximation.
Dynamic analysis
Dynamic rail analysis is a time-dependent (transient) circuit analysis in which each

current source is a time-dependent waveform. It enables the measurement of transient
spikes or droop at points of interest in the grid. This helps to analyze whether
decoupling capacitance between the power and ground networks is sufficient to keep
these deviations within the limit.

Early Rail Analysis
ERA Flow TCL Options

The following example shows the TCL command options to set up an ERA flow. Prior to
running ERA, the design must have power stripes for a net to be analyzed. If vias are
not dropped among stripes, ERA grid completion can create virtual connections.
Instances need not be placed but need to be logically connected to the PG net under
consideration. Design must be loaded for virtual follow pin routing. If the design has no
instances, a single current region can be automatically created with all the current
attached to it.
Step 1: Read the inputs namely lefs, Verilog and DEF.
read_lib -lef design/full.lef

read_verilog design/test.v.gz
set_top_module test
read_def design/full.def
Step 2: Specify power. In the ERA flow, power constraints can be specified interactively
during the power planning stage and quickly perform rail analysis to estimate whether
the design meets constraints. The following command should be specified before
analyze_rail:
set_power_data -format area -power 1 -bias_voltage 1
For placed designs, power data can be generated using the report_power
command. In this case, libraries must also be loaded. Power specification methods for
the different stages of the design are explained in the next section.
Step 3: Specify the rail analysis mode options and voltage source locations, and
execute rail analysis. Rail analysis mode options for the ERA flow are described in the
subsequent sections.
set_rail_analysis_mode \
-method era_static \
-accuracy xd \
-extraction_tech_file design/tech.tch \
-era_current_region_file design/current_region
set_pg_nets -net VDD -voltage 1.1 -threshold 1.067
set_power_pads -net VDD -format xy -file pads/vdd.pp
analyze_rail -type net -results_directory early_vdd VDD

Early Rail Analysis
ERA Power Specification

This section describes power specification methods used for designs at different stages
in the flow.
Fully Unplaced Design
If you want to prototype the power grid for a fully unplaced design, you can specify
power based on the region and layer. This is called region-based power specification.
The specified power is distributed evenly on the specified layer in the given region.
Specifying the lowermost routable layer in the current region helps analyze IR drop
across all layers used in the power grid. This method can be used in conjunction with
other methods. Current regions are specified using the following option:
-era_current_region_file <filename>
Example:
set_rail_analysis_mode -method era_static -accuracy xd \

-extraction_tech_file design/tech.tch \
-era_current_region_file design/current_region
The current region file includes the list of regions and the amount of current to be
distributed within them for the power grid. This file format differs for static and dynamic
analysis. Default units in the file are in mA.
Format:
label <name> net <name> area <x1 y1 x2 y2> layer <layer name>
<current|pwl > intrinsic_cap <value> loading_cap <value>
Static example:
label cr1 net VDD area 100 200 140 280 layer M1 current 10
Dynamic example:
label cr1 net VDD area 100 200 140 280 layer M1 pwl (0ns 0mA
1ns 2mA 1.9ns 5mA 2ns 10mA 2.9ns 5mA 3ns) intrinsic_cap 10
loading_cap 60

Early Rail Analysis
Partially Placed Design
For partially placed designs, you can specify the total power consumption for the design
and optionally specify the estimated or known power consumption for cells or macros. In
addition, the region-based power specification can be used to specify the distribution of
total power.
The following two methods can be used:
1. User-defined cell power file and user-defined current region
Here, the user-defined cell power file is instance_power_file.txt in the

set_power_data command. The set_power_data command is used to specify the
static and dynamic power or current files for IR drop and EM analysis.
set_power_data -format ascii -bias_voltage 1 -power 1.5

power/instance_power_file.txt
set_rail_analysis_mode -method era_static -accuracy xd -

extraction_tech_file design/tech.tch -era_current_region_file
design/current_region
The user-defined current region specification is described in the previous section

(Fully Unplaced Design).
2. Tool-generated current region and tool-generated power file for placed

instances
The following commands show how to enable the current region and power file
generation by the tool:
set_power_data -format area -power 1.5 -bias_voltage 1
set_rail_analysis_mode \
-extraction_tech_file tech.tch \
-accuracy xd -ignore_shorts true \
-method era_static \
-era_current_distribution all \
-era_current_distribution_layer Metal1 \
-era_current_distribution_unplaced_area diearea
Note: When -era_current_distribution is set to all, the software will generate

both instance power file (for placed instances) and current region file (for unplaced
instances). This can be found in rail/era_work/incremental_output. These rail
options for ERA are explained in the next section.
Early Rail Analysis
Fully Placed /Routed Design
When the design is fully placed, power can be calculated using the report_power
command. The power is computed using the synthesized netlist.
set_power_analysis_mode method static

write_static_currents true
set_default_switching_activity global_activity 0.2
report_power
set_power_data format current scale 1
power/static_VDD.ptiavg
set_rail_analysis_mode power_grid_library tech.pgv
accuracy hd method era_static
To summarize, set_power_data is the command used to specify power data. Here is

a brief description of the options available in this command:
[-bias_voltage value]: Specifies the value of the bias voltage. This

parameter must be set if -format is set to ascii or area.
{-format {current | ascii | area | ascii_current}: The power

data format can be either current, ascii, area or ascii_current.
o When using the current format option, specify the current file (*ptiavg)
generated during the power analysis within Voltus.
set_power_data format current static_VDD.ptiavg
o When using the ascii format option, specify the ascii power file. The ascii
power file has three columns namely instance/cell name, power in W, and
power pin name.
<instance/cell name> <power in Watts> <power pin

name>
Inst1 0.003 vdd
Inst2 0.005 vdd1
Inst3 0.006 vdd3
set_power_data format ascii bias_voltage 1.08

instance_power.txt

Early Rail Analysis
When using the area format, specify the total power of the chip in watts.
The power is distributed based on the cell area.
set_power_data format area bias_voltage 1.08 power

10
When using the ascii_current format option, specify an ASCII instance current file for
static analysis. The format is a three-column input file.

Early Rail Analysis
ERA Rail Options

This section briefly describes the different rail analysis mode settings that can be used
for the ERA flow.
-accuracy xd
The xd or acceleration definition accuracy mode is used for the early

implementation stage IR analysis.
-era_check_wires_for_generated_current_regions {true | false}
This specifies to generate the unplaced current regions only in areas where the
actual net wires are present. The default value is false. The current regions are
generated from the power domain information present in the design.
era_current_distribution_factor_for_placed value
When you use -era_current_distribution and set to distribute current for

placed blocks/macros, the ratio of power allocated to each placed instance is
calculated based on its total area. Using this parameter, you can control the
current distribution factors for placed blocks/macros, hence the power allocated
for area-based power calculation. For example, if you specify 0.5, the tool will
assume all placed blocks/macros to be 50% of its actual size and distribute
current accordingly. The default value is 1.
-era_current_region_file filename
This specifies a file that includes a list of regions and the amount of current to be
distributed within them for the power grid. Default units in the file are mA. You
can also specify rectilinear current regions in the file.
Format:
label name net netName area x1 y1 x2 y2 layer layername
<current value |pwl (t1 i1 t2 i2 )> intrinsic_cap value
loading_cap value
Unit: current mA, cap pf, time ns, coordinate um
Static example:
label test1 net VDD area 100 200 400 500 layer M1 current
10

Early Rail Analysis
Dynamic example:
label test1 net VDD area 100 200 400 500 layer M1 pwl (0ns
0mA 1ns 0mA 1.9ns 0mA 2ns 10mA) intrinsic_cap 10
loading_cap 60
era_current_distribution_layer layer_name
This specifies the layer name to distribute unplaced current in the early rail
analysis mode.
era_current_distribution {unplaced | placed | all | none}
This parameter controls the behavior of ERA current distribution. The

set_power_data area-based power or current_region_file need to be
specified for the ERA current distribution to work. Placed instanced without the
uti or asci-based power can also be considered for ERA current distribution.
Unplaced: Enable current distribution only for unplaced instances.
If the set_power_data area-based power is specified, the following will be

required:
-era_current_distribution_layer
Placed: Enable current distribution for placed instances without any power
specified.
All: Both unplaced and placed instances without power specified will have ERA
current.
None: Disable the ERA current distribution.
-era_current_distribution_nets { net1 net2 ...}
This specifies to distribute current for unplaced instances by the total die area on
the specified nets only. The default behavior is to distribute current for all nets.
This parameter will be required when the following is used:
-era_current_distribution_unplaced_area diearea
This parameter is not applicable for single net analysis.
-era_current_distribution_unplaced_area {instance | diearea}

Early Rail Analysis
This specifies to distribute current for unplaced instances by the total die area or
actual instance area. The default value is instance. When the die area is
specified, the entire unplaced die area is considered for the computation of
current distribution. The die area considered excludes the user-specified current
regions, placed instances, and placement blockages.
-era_insert_virtual_followpins { standard | extended | none }
This specifies to generate virtual followpins. The extended followpins will create
followpins that extend from one stripe to another. The standard followpins may
extend to the previous stripe but does not reach the next stripe.
Default: none
-era_insert_virtual_via_on_layers value
This lets you control on which layers virtual via can be inserted in early rail
analysis. Using this parameter, virtual via can only be inserted between each pair
of layer names provided in the design. Alternatively, you can provide wildcard, *,
as the second layer name and virtual via will be allowed to be inserted from the
first layer to any layers in the design.
For example, -era_insert_virtual_via_on_layers { {M1 *} } will
allow virtual via to be inserted from M1 to any layers in the design.
This parameter does not have a default value, but ERA will insert virtual via for all
layers if the -era_skip_virtual_via parameters are not provided.
-era_lef_layermap filename
If a technology library or an extraction techfile is not provided, ERA can

automatically create a technology library. This parameter specifies the layer map
file to generate the technology library. If a layer map file is not provided, it will be
automatically inferred by the tool.
-era_power_gate_file filename
If a power gate PGV is not provided, this parameter specifies the name of the
power gate (power switch) file that will be used to perform power gate steady-
state analysis.
File format:
CELL <CELLNAME> SUPPLY <SUPPLY_PIN> SWITCHED
<SWITCHNET_PIN> RON <VALUE> IDSAT <VALUE> ILEAK <VALUE>

Early Rail Analysis
CELL HDRSID SUPPLY TVDD SWITCHED VDD RON 500 IDSAT 1 ILEAK
0.001
-era_skip_virtual_via_by_type {whatif | def | all | none}
This specifies to skip a given via type. By default, ERA generates all virtual via
layer types.
The what-if vias are virtual vias that have connectivity to user-defined what if
shapes.
The def vias are virtual vias between two metal shapes defined in DEF.
all will skip all virtual via generation.
none will insert both what-if and DEF vias. It will insert vias on all layers, unless
the layers are controlled by other parameters.
Default: all
-era_skip_virtual_via_on_layers {{ layer1 layer2 } {

layer3 layer4 } ... }
This skips via insertion between stripes and non-stripes on the specified LEF
layer pairs.
-era_techlib_generation {true | false}
This specifies to skip technology PGV generation in the early rail analysis mode.
This parameter skips technology PGV generation even if the following parameter
is specified:
-extraction_tech_file
The default value is true.
-extraction_tech_filefilename
This specifies the extraction technology file to be used for the top-level power-
grid extraction. If you do not specify this parameter, the software will use the
extraction technology file stored inside the power-grid view library.
-method { era_static | era_dynamic}

Early Rail Analysis
This specifies whether static or dynamic rail analysis, or static or dynamic early
rail analysis will be performed.

Early Rail Analysis
Summary of ERA Features

Interactive current/power specification use-model to enable static and dynamic rail
analysis at the floorplanning stage
Power and rail analysis during the placement stage using the ERA-driven virtual
follow pin routing and virtual via for grid completion
Automatic current region generation accounting for unplaced instance in the
design, and automatic area-based distribution of power among placed instances
in the design
Support of the user-specified explicit power value at macro, cell and instance level
in an ASCII file format, hence, enabling flexible power distribution
PGV library is optional. If not provided, it is generated on the fly using the
specified technology file.
Static Power and Rail Analysis without PGV can also be run using the Innovus
license.
Power and rail analysis on a placed and routed database
Early power-switch analysis to refine power-switch placement
Support for the unplaced flow during static and dynamic analysis
TIPS
ERA with analyze_rail requires a mandatory qrcTechFile or a technology Power
Grid View generated with it, to be able to run the flow.
This means set_rail_analysis_mode must include either:
-extraction_tech_file ./qrcTechFile or,
-power_grid_library {./tech.cl}.
If the grid is okay, the missing vias that need to be fixed can be found with
the verifyPowerVia or verify_power_via command.
While specifying power, ideally consider all cells even if they are not toggling. Spare
Cells may become real cells after ECOs. So, it is correct to consider them during
ERA.
If you still want to exclude some cells/macros, you can define the power value for
these cells/macro as zero and include it in the run using the following command:
analyze_early_rail -macro_power_file <macroPowerFile>

Early Rail Analysis
While specifying power for macros using the ascii or macro power file, all connected
rails get equal currents. In reality, if a design has two rails, for example VDD and
VDD2, it is expected that most current will flow through VDD and very little will flow
through VDD2. There is a way to control how ERA will divide current/power between
the rails (using the -pg_nets option of the set_power command).
Example:
set_power -pg_net vdd -type instance Top/A/clkin_neg_L1_I1

.005
set_power -pg_net vdd2 -type instance Top/A/clkin_neg_L1_I1
.002
Normally, the power specified using set_power without the -pg_net switch will be
divided equally to all the rails to which the instance/cell is connected. This is also true
of the macro power file.
The set_power_data -format ascii accepts a three-column instance power file,

with the third column being the rail to which you want the power assigned. The format
of the input file is as follows:
top/inst1 0.001 vdd

top/inst1 0.001 vdd1
top/inst1 0.003 vdd3
Here, vdd, vdd1, and vdd3 are power pin names of the instances.
Support
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knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.
Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com.


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Early Rail Analysis

Product Version: Innovus 16.1 or Higher, Voltus 16.1 or Higher

Learn more at Cadence Online Support - https://support.cadence.com

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RLRP Resistance of Least Resistive Path

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Learn more at Cadence Online Support - https://support.cadence.com

ERA Flow and TCL Options

Power estimation and user-defined distribution

Learn more at Cadence Online Support - https://support.cadence.com

Static and EM analysis

Dynamic rail analysis is a time-dependent (transient) circuit analysis in which each

Learn more at Cadence Online Support - https://support.cadence.com

ERA Flow TCL Options

Step 1: Read the inputs namely lefs, Verilog and DEF.

read_lib -lef design/full.lef

set_power_data -format area -power 1 -bias_voltage 1

set_pg_nets -net VDD -voltage 1.1 -threshold 1.067

set_power_pads -net VDD -format xy -file pads/vdd.pp

analyze_rail -type net -results_directory early_vdd VDD

ERA Power Specification

Fully Unplaced Design

set_rail_analysis_mode -method era_static -accuracy xd \

Learn more at Cadence Online Support - https://support.cadence.com

Partially Placed Design

The following two methods can be used:

1. User-defined cell power file and user-defined current region

Here, the user-defined cell power file is instance_power_file.txt in the

set_power_data -format ascii -bias_voltage 1 -power 1.5

set_rail_analysis_mode -method era_static -accuracy xd -

The user-defined current region specification is described in the previous section

2. Tool-generated current region and tool-generated power file for placed

set_power_data -format area -power 1.5 -bias_voltage 1

Note: When -era_current_distribution is set to all, the software will generate

Fully Placed /Routed Design

set_power_analysis_mode method static

To summarize, set_power_data is the command used to specify power data. Here is

[-bias_voltage value]: Specifies the value of the bias voltage. This

{-format {current | ascii | area | ascii_current}: The power

set_power_data format current static_VDD.ptiavg

<instance/cell name> <power in Watts> <power pin

set_power_data format ascii bias_voltage 1.08

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The power is distributed based on the cell area.

set_power_data format area bias_voltage 1.08 power

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ERA Rail Options

The xd or acceleration definition accuracy mode is used for the early

-era_check_wires_for_generated_current_regions {true | false}

When you use -era_current_distribution and set to distribute current for

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era_current_distribution {unplaced | placed | all | none}

This parameter controls the behavior of ERA current distribution. The

If the set_power_data area-based power is specified, the following will be

None: Disable the ERA current distribution.

-era_current_distribution_nets { net1 net2 ...}

This parameter is not applicable for single net analysis.

-era_current_distribution_unplaced_area {instance | diearea}

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-era_insert_virtual_followpins { standard | extended | none }

If a technology library or an extraction techfile is not provided, ERA can

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-era_skip_virtual_via_by_type {whatif | def | all | none}

-era_skip_virtual_via_on_layers {{ layer1 layer2 } {