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Version 2.

3, 19 Nov 2012

CoolSET®-F3R

ICE3BR0665J

Off-Line SMPS Current Mode
Controller with integrated 650V
CoolMOS® and Startup cell
(frequency jitter Mode) in DIP-8

Power Management & Supply

N e v e r s t o p t h i n k i n g .

CoolSET®-F3R
ICE3BR0665J
Revision History: 2012-11-19 Datasheet
Previous Version: 2.2
Page Subjects (major changes since last revision)
27 revised outline dimension for PG-DIP-8 package

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www.infineon.com

CoolMOS®, CoolSET® are trademarks of Infineon Technologies AG.

Edition 2012-11-19
Published by
Infineon Technologies AG,
81726 Munich, Germany,
© 2012 Infineon Technologies AG.
All Rights Reserved.

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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.

Information
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Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

CoolSET®-F3R
ICE3BR0665J

Off-Line SMPS Current Mode Controller with
integrated 650V CoolMOS® and Startup cell
(frequency jitter Mode) in DIP-8
Product Highlights
• Active Burst Mode to reach the lowest Standby Power
Requirements < 50mW
• Auto Restart protection for overload, overtemperature, overvoltage PG-DIP-8
• External auto-restart enable function
• Built-in soft start and blanking window
• Extendable blanking Window for high load jumps
• Built-in frequency jitter and soft driving for low EMI
• Green Mould Compound
• Pb-free lead plating; RoHS compliant
Features Description
• 650V avalanche rugged CoolMOS® with built-in The CoolSET®-F3R jitter series (ICE3BRxx65J) is the
Startup Cell latest version of CoolSET®-F3. It targets for the Off-Line
• Active Burst Mode for lowest Standby Power battery adapters and low cost SMPS for lower power
• Fast load jump response in Active Burst Mode range such as application for DVD R/W, DVD Combi, Blue
• 65kHz internally fixed switching frequency ray DVD player, set top box, etc. Besides inherited the
• Auto Restart Protection Mode for Overload, Open outstanding performance of the CoolSET®-F3 in the
Loop, VCC Undervoltage, Overtemperature & BiCMOS technology, active burst mode, auto-restart
Overvoltage protection, propagation delay compensation, etc.,
• Built-in Soft Start CoolSET®-F3R series has some new features such as
• Built-in blanking window with extendable blanking built-in soft start time, built-in blanking window, built-in
time for short duration high current frequency jitter, soft gate driving, etc. In case a longer
• External auto-restart enable pin blanking time is needed for high load application, a simple
• Max Duty Cycle 75% addition of capacitor to BA pin can serve the purpose.
• Overall tolerance of Current Limiting < ±5% Furthermore, an external auto-restart enable feature can
• Internal PWM Leading Edge Blanking provide extra protection when there is a need of
• BiCMOS technology provide wide VCC range immediate stop of power switching.
• Built-in Frequency jitter and soft driving for low EMI

Typical Application
+

Snubber Converter
CBulk DC Output
85 ... 270 VAC
-

CVCC
VCC Drain
Startup Cell
Power Management

PWM Controller
Current Mode
CS
Precise Low Tolerance Peak CoolMOS®
Current Limitation
RSense

FB
Active Burst Mode
GND Control
Unit BA
Auto Restart Mode
CoolSET®-F3R ™

(Jitter Mode)

Type Package Marking VDS FOSC RDSon1) 230VAC ±15%2) 85-265 VAC2)
ICE3BR0665J PG-DIP-8 ICE3BR0665J 650V 65kHz 0.65 74W 49W
1)
typ @ Tj=25°C
2)
Calculated maximum input power rating at Ta=50°C, Ti=125°C and without copper area as heat sink. Refer to input power curve for other Ta.

Version 2.3 3 19 Nov 2012

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.8 3. . . . . . .20 4. . . . . . . . . . . . . . . . . . . .3. .21 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 PWM Section . . . . .16 3.13 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7. . . . . . . . . . . . . . . . . . . . . . . . CoolSET®-F3R ICE3BR0665J Table of Contents Page 1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . .2 Active Burst Mode . . . . . . . .3. . . . . . . . . . . . . . .8 3. . . . . . . . .13 3. . . . . . . . . . .3 Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3. . . . .21 4. . . .3. . . . . . .3 Gate Driver . . .7 Control Unit . . . . . . . . . .19 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Basic and Extendable Blanking Mode . . . . . . . . . . . . . . .21 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Startup Phase . . . . . . .2 Auto Restart without extended blanking time . . . . .6 1. . .20 4. . . . .2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4. . . . . . . .4 Soft Start time .6 Current Limiting . . . . . . . . . . .1 Pin Configuration with PG-DIP-8 .2 Power Management . . . . . . . . . . . . . . . . . . . . . . . .7. . . . . . .7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. .2 PWM-Comparator . . . . . . . . . . . . .18 4 Electrical Characteristics . . . . . . . . . . . . . .16 3. . . . . . . . . . . . . . . . . . . .3. . . . . .20 4. . . . . . . . . . . . . . . . . . .7 CoolMOS® Section . . . .7. . . .3. . . . . . . . . . . . . . . .5 Control Unit . . . . . . . . . . .11 3.8 3. . . . . . . . . . . .1 PWM-OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Current Limiting . . . . . . . . .2 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . .15 3. . . . . . . . . . .7. .3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.7. . . . . . . . . .5. . . . . . . . . . . . .6 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4. . . . .2 Internal Voltage Reference . . . . . . . . .12 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Oscillator . . . . . . .1 Introduction . . . . .2. . . . . . . . .15 3.17 3. . . . . . . . . . . . . . . . . . . . . . . . . . .5 PWM Section . . . . .1 Auto Restart mode with extended blanking time . .6 2 Representative Blockdiagram . . . . . . . . . . . . . . .15 3. . . .3. . . . . . . . .10 3. . . . . . .5.24 Version 2. . . . . . . . . . .3.23 5 Typical CoolMOS® Performance Characteristic . . . . . . . . . . . . . . . . .6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Leading Edge Blanking . . . . . . . . . . . .7 3 Functional Description .3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Propagation Delay Compensation . . . . . . . . . .10 3. .15 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3. .12 3. . . . . . . .2 PWM-Latch FF1 . . . . . . . . .14 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7. . . . . . . . . . . . . . . . .6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Absolute Maximum Ratings . . . . . . .3. . . . . . .14 3. . . .3 Protection Modes . . . . . . . . .7. .3 4 19 Nov 2012 . . . . . .1 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. . . . . . . . . . .2 Pin Functionality . . . . . . . . . . . .19 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . CoolSET®-F3R ICE3BR0665J 6 Input Power Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 5 19 Nov 2012 . .27 8 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 9 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . .26 7 Outline Dimension . . . . .29 Version 2. . . . . . . . . . . . . . . . . . . . . . . . .

33V. range is between 10. 4 Drain 650V1) CoolMOS® Drain 5 Drain 650V1) CoolMOS® Drain FB (Feedback) 6 n. Figure 1 Pin Configuration PG-DIP-8 (top view) Note: Pin 4 and 5 are shorted Version 2. Not connected The information about the regulation is provided by the FB Pin to the internal Protection Unit and to the internal 7 VCC Controller Supply Voltage PWM-Comparator to control the duty cycle. The operating CS 3 6 n. Furthermore the current information is provided for the PWM- Comparator to realize the Current Mode. FB 2 7 VCC VCC (Power Supply) VCC pin is the positive supply of the IC. the Driver output is immediately switched off. GND (Ground) Drain 4 5 Drain GND pin is the ground of the controller.1 Pin Configuration with PG-DIP-8 1.c. 1) at Tj=110°C CS (Current Sense) The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the integrated CoolMOS® If voltage in CS pin reaches the Package PG-DIP-8 internal threshold of the Current Limit Comparator. BA 1 8 GND Drain (Drain of integrated CoolMOS®) Drain pin is the connection to the Drain of the integrated CoolMOS®. The FB- 8 GND Controller GrouND Signal is the only control signal in case of light load at the Active Burst Mode. The extendable blanking time 1 BA extended Blanking & Auto-restart function is to extend the built-in 20 ms blanking time by 2 FB FeedBack adding an external capacitor at BA pin to ground.3 6 19 Nov 2012 .c. It is triggered by pulling down the BA pin to less than 0.2 Pin Functionality BA (extended Blanking & Auto-restart) The BA pin combines the functions of extendable Pin Symbol Function blanking time for over load protection and the external auto-restart enable. The external auto-restart enable function is an external 3 CS Current Sense/ access to stop the gate switching and force the IC enter 650V1) CoolMOS® Source auto-restart mode. CoolSET®-F3R ICE3BR0665J Pin Configuration and Functionality 1 Pin Configuration and Functionality 1.5V and 25V.

0V Power Management CoolMOS® 3. 2 Figure 2 Version 2.3 220ns RSense C6a PWM OP & 3. #1 : CBK is used to extend the Blanking Time #2 : TAE is used to enable the external Auto-restart feature 19 Nov 2012 CoolSET®-F3R Representative Blockdiagram ICE3BR0665J . 270 VAC VOUT - CVCC VCC Drain 5..5V TAE VCC Oscillator Section & C1 G1 Duty Cycle Representative Blockdiagram 20.9V 1 ms VCC counter C2 120us Blanking Time Soft Start Soft-Start Clock 25.25kΩ Startup Cell Internal Bias Voltage 5.5V G10 C12 & 0.72 PWM #2 10.34V Current Limiting C6b G11 Current Mode 3.3 + Converter CBulk Snubber DC Output 85 .6V GND Signal Power-Down #1 CBK Undervoltage Lockout T1 Reset 18V 0.35V Time 2pF G6 Blanking 1pF D1 x3.5V Comparator Thermal Shutdown Soft Freq..05V Control Unit ICE3BR0665J / CoolSET®-F3R ( Jitter Mode ) ™ # : optional external components.5V max 0.0V Reference IBK T2 Auto-restart Enable BA T3 0.0V Comparator & C8 4.67V FB Mode C10 Edge 1.33V C7 G7 Driver C9 Block 1 S R Q & S1 G8 1 G9 7 C3 G2 4. jitter Tj >130°C & Gate Start FF1 0.0V PWM 5.0V Spike Auto RFB C4 20ms G5 Blanking Restart Blanking 30us Mode Propagation-Delay Compensation Representative Blockdiagram 25kΩ Time Active Burst Vcsth Leading 10kΩ CS C5 20ms Blanking & 0.

the lowest Standby Power at light load and no load Furthermore. It can further save external component Power-Down Reset Voltage Reference counts. Once the malfunction is removed. the switching pulse at gate frequency jitter. Power losses are Power Management therefore reduced. After entering the burst mode. over temperature. through the optocoupler.1 Introduction the SMPS over time. this F3R series implements the conditions. that is used for the normal PWM control. The Vout is 3. the basic mode and the extendable mode. there is still a frequency jitter mode to the switching clock such that full control of the power conversion to the output the EMI noise will be effectively reduced. it can increase the 10.0V function.2 Power Management on well controlled in this mode. This increases the efficiency under light load conditions drastically. Thus there is no need for the over-sizing of the The intelligent Active Burst Mode can effectively obtain SMPS.g. an external auto-restart enable pin is provided. CoolSET®-F3R jitter series (ICE3BRxx65J) is the latest normal operation is automatically retained after the version of the CoolSET®-F3 for the lower power next Start Up Phase.3 8 19 Nov 2012 . The min/max values which can be found in section 4 Auto Restart Mode reduces the average power Electrical Characteristics have to be considered. modulated gate driving. Drain VCC The usually external connected RC-filter in the feedback line after the optocoupler is integrated in the Startup Cell IC to reduce the external part count. propagation delay compensation. For calculating the worst cases the system. Furthermore a high voltage Startup Cell is integrated into the IC which is switched off once the Undervoltage Lockout on-threshold of 18V is exceeded. the proven outstanding influence of the change in the input voltage on the features in CoolSET®-F3 are still remained such as the maximum power limitation can be avoided together active burst mode. CoolMOS™ Cell is part of the integrated CoolMOS®. Internal Bias Undervoltage Lockout 18V Adopting the BiCMOS technology. over load. conversion to a minimum level under unsafe operating conditions. With this concept no further external components are necessary to adjust the blanking window. The response on load jumps is optimized and the voltage ripple on Vout is minimized. In order to further increase the flexibility of the The internal precise peak current control reduces the protection feature. the IC provides Auto Restart protection. It provides the flexibility to increase the will stop and the IC enters the auto-restart mode after blanking window by simply addition of a capacitor in BA the pre-defined spike blanking time. Moreover. with the integrated Propagation Delay Compensation. built-in features for soft start. on the input voltage. The external startup resistor is no longer necessary as this Startup Cell is connected to the Drain. The features are added. The CoolSET®-F3R has a built-in 20ms soft start 5. e. blanking window and When the pin is triggered. the transformer and the output diode. The particular enhanced features are the flexible. This is necessary for a prolonged fault condition which could otherwise lead to a destruction of 3. auto-restart protection for Vcc Therefore the maximum power is nearly independent overvoltage. During this blanking time window the overload detection is disabled. pin. which is required for wide range etc. This Startup Depl. CoolSET®-F3R ICE3BR0665J Functional Description 3 Functional Description All values which are used in the functional description In order to increase the robustness and safety of the are typical values. open loop. The Auto Restart blanking time for the basic mode is set at 20ms while Mode the extendable mode will increase the blanking time by Soft Start block Active Burst adding an external capacitor at the BA pin in addition to Mode the basic mode blanking time. To make the protection more application.5V design flexibility as the Vcc voltage range is increased to 25V. an external auto-restart enable costs for the transformer and the secondary diode. Figure 3 Power Management Version 2. There are 2 modes of blanking time for high load jumps. SMPS.

By means of Current Mode regulation. Thus it is ensured that at every startup cycle the soft start starts at zero. CoolSET®-F3R ICE3BR0665J Functional Description The Undervoltage Lockout monitors the external Current Mode means the duty cycle is controlled by the supply voltage VVCC. resistor RSense inserted in the source of the integrated CoolMOS®. which is built by Driver the switch T2. the voltage source V1 and a resistor R1 (see Figure 6). a hysteresis start up voltage is implemented. which controls the duty cycle.3 Improved Current Mode variations. the bias circuit is switched off and the soft start counter is reset. The duty cycle is then x3. t Once the malfunction condition is removed. When the oscillator triggers the Gate Driver.67V T2 is opened so that the voltage ramp can start. Soft-Start Comparator The external RSense allows an individual adjustment of the maximum source current of the integrated CoolMOS®. To avoid uncontrolled ringing at switch-on. the internal Bias is FB signal the on-time Ton of the driver is finished by switched off most of the time but the Voltage Reference resetting the PWM-Latch (see Figure 5). 0.3 CS controlled by the slope of the Voltage Ramp. Then the Startup Cell is switched off by the Undervoltage Lockout and therefore no power FB losses present due to the connection of the Startup Cell to the Drain voltage. PWM-Latch To improve the Current Mode during light load FB conditions the amplified current ramp of the PWM-OP C8 R Q is superimposed on a voltage ramp. ton The internal bias circuit is switched off if Auto Restart Mode is entered. the secondary output voltage is insensitive to the line 3. The maximum current consumption Driver t before the controller is activated is about 150μA. When the SMPS is plugged to the slope of the primary current.67V The switch-off of the controller can only take place when VVCC falls below 10. In case the amplified current sense signal exceeds the When Active Burst Mode is entered. The current waveform slope will change with the line variation. Version 2.9mA by the Startup Cell. 0. the Gate Driver is switched-off Current Mode until it reaches approximately 156ns delay time (see Figure 7).5V after normal operation was entered. When VVCC falls below the off-threshold VCCoff=10. this block will then turn back on. The recovery from Auto Restart Figure 5 Pulse Width Modulation Mode does not require re-cycling the AC line. The current consumption is then reduced to 150μA. When the VVCC Amplified Current Signal exceeds the on-threshold VCCon=18V the bias circuit are switched on. to charge the external capacitor CVCC which is connected to the VCC pin. By means of the time delay circuit which is triggered by Improved the inverted VOSC signal.5V.3 9 19 Nov 2012 . This VCC charge current is controlled to 0. This is done by comparing main line the internal Startup Cell is biased and starts the FB signal with the amplified current sense signal. Every time the oscillator shuts down for S Q maximum duty cycle limitation the switch T2 is closed by VOSC. In that case the PWM OP Voltage Ramp is a well defined signal for the comparison with the FB-signal. In case of light load the amplified current ramp is too small to ensure a stable regulation. is kept alive in order to reduce the current consumption The primary current is sensed by the external series below 450μA. It allows the duty cycle to be reduced continuously till 0% by decreasing VFB below that Figure 4 Current Mode threshold.

3 FB Improved Gate Driver t Current Mode 156ns time delay Figure 8 PWM Controlling t Figure 7 Light Load Conditions Version 2.67V X3. CoolSET®-F3R ICE3BR0665J Functional Description 3.67V signal of the integrated CoolMOS® with the feedback 10kΩ signal VFB (see Figure 8).3. Duty Cycle PWM Comparator 0.3 by PWM OP. The output of C8 the PWM-OP is connected to the voltage source V1. PWM-Latch The voltage ramp with the superimposed amplified Oscillator current signal is fed into the positive inputs of the PWM- Comparator C8 and the Soft-Start-Comparator (see VOSC Figure 6).1 PWM-OP The input of the PWM-OP is applied over the internal Soft-Start Comparator leading edge blanking to the external sense resistor PWM Comparator RSense connected to pin CS. time delay circuit (156ns) Gate Driver 3. VFB is created by an external X3.2 PWM-Comparator The PWM-Comparator compares the sensed current 0. Voltage Ramp 5V Figure 6 Improved Current Mode RFB Soft-Start Comparator VOSC FB PWM-Latch C8 max.3 10 19 Nov 2012 . When the V1 PWM OP amplified current signal of the integrated CoolMOS® C1 exceeds the signal VFB the PWM-Comparator switches off the Gate Driver.3 optocoupler or external transistor in combination with the internal pull-up resistor RFB and provides the load T2 R1 information of the feedback circuitry. RSense converts the source current into a sense voltage.3. The sense voltage is FB amplified with a gain of 3.67V Voltage Ramp t Optocoupler PWM OP CS 0.

The Soft Start will be finished in 20ms (tSoft-Start) after the IC is switched on. At the end of the Soft Start period. Soft Start counter would send a signal to the current sink control in every 600us such that the current sink decrease gradually and the duty ratio of the gate drive increases gradually. VSoftS tSoft-Start VSOFTS32 V SoftS V SoftS2 t V SoftS1 Gate Driver t Figure 10 Soft Start Phase Figure 12 Gate drive signal under Soft-Start Phase Version 2.3 11 19 Nov 2012 .6 7 V Counter x 3 . an current sink and a counter. The function is realized by an internal Soft Start S o ft S ta rt c o u n te r resistor. S o ftS Soft Start finish S o ft S ta rt 5V S o ft S ta rt R SoftS S o ft-S ta rt SoftS C o m p a ra to r G a te D riv e r C7 & G7 Soft Start 32I 8I 4I 2I I 0 . the IC starts the Soft Start mode (see Figure 10).3 CS PW M OP Figure 9 Soft Start In the Startup Phase. wisely (32 steps) with the increase of the counts. the IC provides a Soft Start Figure 11 Soft Start Circuit period to control the primary current by means of a duty After the IC is switched on. the current sink is switched off. the VSFOFTS voltage is cycle limitation. The Soft Start function is a built-in controlled such that the voltage is increased step- function and it is controlled by an internal counter. CoolSET®-F3R ICE3BR0665J Functional Description 3. And the amplitude of the current sink is controlled by the counter (see Figure 11). The .4 Startup Phase When the VVCC exceeds the on-threshold voltage.

with frequency jittering of ±4% (which is ±2.5 PWM Section from zero to maximum gradually (see Figure 12). it is reset by the PWM comparator. jittering period of 4ms. In order to integrated CoolMOS®.5.0V Block FF1 S Gate Driver Soft Start 1 Comparator R & G8 Q PWM G9 VOUT t Comparator Current VOUT Limiting tStart-Up CoolMOS® Gate t Figure 14 PWM Section Block Figure 13 Start Up Phase 3. 3. Once the Soft Start period is over and when the IC goes into normal operating mode. the Soft Start comparator or the Current -Limit comparator.75 PWM Section each restart attempt during Auto Restart. Soft-Start is also activated at 0. the clamp circuit and the output achieve a very accurate switching frequency. Oscillator VSoftS Duty Cycle tSoft-Start max VSOFTS32 Clock Frequency Jitter VFB t Soft Start 4. the overshoot and it helps to prevent saturation of the charging and discharging current of the implemented transformer during Start-Up. In addition to Start-Up.5.1 Oscillator The Start-Up time tStart-Up before the converter output The oscillator generates a fixed frequency of 65KHz voltage VOUT is settled. By means of Soft-Start there is an effective A capacitor. Version 2. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of Dmax=0. After the PWM-Latch is set.2 PWM-Latch FF1 The output of the oscillator block provides continuous pulse to the PWM-Latch which turns on/off the integrated CoolMOS®. When it is in reset mode. must be shorter than the Soft. Then the switching frequency is varied in range of 65KHz ± 2.6KHz) at a Start Phase tSoft-Start (see Figure 13). the switching frequency of the clock is varied by the control signal from the Soft Start block.75. the output of the driver is shut down immediately.3 12 19 Nov 2012 . a current source and current sink which minimization of current and voltage stresses on the determine the frequency are integrated.6KHz at period of 4ms. oscillator capacitor are internally trimmed. the duty cycle is increasing 3. CoolSET®-F3R ICE3BR0665J Functional Description Within the soft start period.

Version 2. when VCC is below the undervoltage Blanking is integrated in the current sense path for the lockout threshold VVCCoff. is set to low in order to disable power transfer to the secondary side. That is a slope control of Mode D1 the rising edge at the output of the driver (see Figure 16). The source current of the integrated CoolMOS® is sensed ca.3 13 19 Nov 2012 . When it is activated.5. t = 130ns via an external sense resistor RSense.6 Current Limiting PWM Latch VCC FF1 Current Limiting PWM-Latch 1 Propagation-Delay Gate Compensation CoolMOS® Vcsth C10 Leading Edge Blanking PWM-OP 220ns Gate Driver & G10 C12 Figure 15 Gate Driver 0. t A Propagation Delay Compensation is added to support the immediate shut down of the integrated Figure 16 Gate Rising Slope CoolMOS® with very short propagation delay. CS (internal) Figure 17 Current Limiting Block VGate There is a cycle by cycle peak current limiting operation realized by the Current-Limit comparator C10. C12 and the PWM-OP. the comparator C10 immediately turns off the gate drive by resetting the PWM Latch FF1. The output of comparator C12 is activated by the Gate G10 if Active Burst Mode is entered. If the voltage 5V VSense exceeds the internal threshold voltage Vcsth. This voltage level determines the maximum power level in Active Burst Mode.3 Gate Driver 3. the current limiting is reduced to 0. Thus the influence of the AC input voltage on the maximum Thus the leading switch on spike is minimized. CoolSET®-F3R ICE3BR0665J Functional Description 3. In order to prevent the current limit from distortions caused by leading edge spikes.34V. By means of RSense the source current is transformed to a sense voltage VSense which is fed into the CS pin. output power can be reduced to minimal. The switch on speed is 1pF slowed down before it reaches the integrated Active Burst 10k CoolMOS® turn on threshold.34V The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. the output of the Gate Driver comparators C10. a Leading Edge During power up. Furthermore the driver circuit is designed to eliminate cross conduction of the output stage.

Propagation Figure 21 Dynamic Voltage Threshold Vcsth Delay Compensation is integrated to reduce the overshoot due to dI/dt of the rising primary current. V OSC max. Ipeak = 0.9 0 0.3 14 19 Nov 2012 .1 leading edge spike is generated due to the primary. An overshoot of the peak current Ipeak is 21). In case of a steeper slope the switch off of the induced to the delay. or dVSense/dt = 0. Duty Cycle Signal2 Signal1 ISense tPropagation Delay Ipeak2 IOvershoot2 Ipeak1 off time ILimit V Sense Propagation Delay t IOvershoot1 V csth t Figure 19 Current Limiting The overshoot of Signal2 is larger than of Signal1 due Signal1 Signal2 to the steeper rising waveform.15 Whenever the integrated CoolMOS® is switched on. In order to avoid a 0. and a propagation delay time of tPropagation Delay =180ns leads Vcsth to an Ipeak overshoot of 14.8 2 V premature termination of the switching pulse.6.5A with RSense = 2. The current sense threshold is set to a static voltage level Vcsth=1V VSense without Propagation Delay Compensation. dt of the peak current (see Figure 19). there is always The Propagation Delay Compensation is realized by propagation delay to switch off the integrated means of a dynamic threshold voltage Vcsth (see Figure CoolMOS®.3 t 1.2 Figure 18 Leading Edge Blanking VSense 1.05 side capacitances and reverse recovery time of the 1 secondary-side rectifier. A current ramp of dI/dt = 0.4A/µs.2 Propagation Delay Compensation Figure 20 Overcurrent Shutdown In case of over-current detection. a 1. Current Limiting is then very accurate.2 1.95 drive to switch off unintentionally.25 1. dt 3. CoolSET®-F3R ICE3BR0665J Functional Description 3.4 0. This change in the t slope depends on the AC input voltage. this spike dVSense μs is blanked out with a time constant of tLEB = 220ns.6 0.4%. the overshoot is only around 2% (see Figure 20).1 Leading Edge Blanking For example. Thus the propagation delay time between exceeding the current sense threshold Vcsth and the switching off of the integrated CoolMOS® is compensated over temperature within a wide range.2 0. Version 2. with compensation without compensation V 1. With the propagation tLEB = 220ns delay compensation. 1. This spike can cause the gate 0.6 1.8 1 1.6.4 1. which depends on the ratio of dI/ driver is earlier to compensate the delay.8V/µs.

the internal blanking time constant current. the maximum CBK extendable Blanking Time is achieved by adding capacitor is restricted to less than 0. basic mode and 3. the Auto Restart Mode is activated. The basic mode is just an internal set 20ms blanking time while the extendable Figure 23 Active Burst Mode mode has an extra blanking time by connecting an external capacitor to the BA pin in addition to the pre- set 20ms blanking time.35V Time Mode C6a Control Unit 3.0V through the internal IBK During normal operation. counter is reset to 0. For the Auto Restart Mode. Then the 0.0V 20ms G5 Auto C4 C4 Blanking Restart Time Mode Active FB Burst C5 & Mode FB & 20ms Active 1. The IC enters Active Burst Mode under low load conditions. Furthermore those buffer time for the extendable blanking mode. By means of this Blanking The Active Burst Mode has basic blanking mode only Time. The Control Unit contains the functions for Active Burst For example. the IC is BA 5. While the 20ms blanking time is passed.1 Entering Active Burst Mode S1 is opened by G2. For the extendable mode. it can be a very fast response to the quick # CBK IBK change at the FB signal. The Active Burst Mode and the Auto Restart Mode both have 20ms internal Blanking time = 20ms + CBK x (4. the IC avoids entering into these two modes while the Auto Restart Mode has both the basic and the accidentally.7.22uF.0 .0V controlled by the FB signal. With the Active Burst Mode.2. external capacitor at BA pin. overload detection is very useful for the application that works in low current but requires a short duration of 3.9) / IBK = 72ms Blanking Time. the switch 3. it starts to count.2 Active Burst Mode high current occasionally. Once the FB signal falls below 1.05V Control Unit the extendable mode. IBK = 13uA Mode and Auto Restart Mode. a further In order to make the startup properly.9V clamped voltage at The FB signal is kept monitoring by the comparator C5.9V 1 S1 G2 Internal Bias Current C3 Spike 20 ms Blanking Limiting 4. 0.0V 4.0.7 Control Unit After the 30us spike blanking time. CoolSET®-F3R ICE3BR0665J Functional Description 3.7.1 Basic and Extendable Blanking Mode increases significantly at light load conditions while still maintaining a low ripple on VOUT and a fast response on load jumps. is reached if an external capacitor CBK is added to BA pin. the The Active Burst Mode is located in the Control Unit.3 15 19 Nov 2012 .35V. The Start up Cell is kept OFF in order to minimize the power loss. the efficiency 3.0V Blanking Time & 30us G10 & 4.35V G6 C5 Blanking G6 Burst 1. BA pin is charged to 4. During Active Burst Mode. Since the IC is always active. G5 is enabled by comparator C3.5V & Figure 22 Basic and Extendable Blanking Mode C6b G11 There are 2 kinds of Blanking mode.65uF. gate G5 is blocked even though the 20ms blanking time Figure 23 shows the related components. if CBK = 0. When the counter reach 20ms Version 2.7.

This is observed by the comparator C4. which is due to the inactive PWM section.34V.34V VOUT is still kept unchanged.5V The FB voltage will increase immediately if there is a high load jump.3 16 19 Nov 2012 . the FB voltage is changing like a saw tooth between 3.0V current consumption of the IC to approx. 34% during Active Burst Mode.05V and 3. 3. Active Burst Active Burst After entering Active Burst Mode. The minimum VCC level during Active Burst Mode depends on the load condition and the 20ms Blanking Time application. 3. 450uA VOUT t t Figure 24 Signals in Active Burst Mode Version 2. the FB voltage rises as VOUT starts to decrease.35V.2.7.03V during Active Burst current limit is reduced to 0. the FB signal will drop to 3. The maximum current can then be resumed to stabilize the VOUT.5V (see figure 24). If the voltage level is larger than 3.3 Leaving Active Burst Mode 10. CoolSET®-F3R ICE3BR0665J Functional Description and FB signal is still below 1.05V.8mA the Active Burst Mode control which in turn blocks the comparator C12 by the gate G10. The comparator C6a monitors VCS t the FB signal. The gate VVCC t G11 is active again as the burst flag is set after entering Active Burst Mode. At that time the comparator C4 resets 3. it needs a certain load jump to rise the FB signal to exceed 4. the Internal Bias circuit resumes and starts to provide switching pulse. the internal circuit will be activated.5V 3. If the load at 0.2. This time window prevents a sudden entering into the Active Burst Mode due to VFB Entering Leaving large load jumps.5V such 1. IVCC t Since the current limit is app.7.5V. In Current limit level Active Burst Mode the gate G10 is released and the 1. At this level the C6b deactivates the internal circuit again by switching off the internal Bias.2 Working in Active Burst Mode After entering the Active Burst Mode.0V. 450uA. The lowest VCC level is reached at no load condition.05V It needs the application to enforce the VCC voltage above the Undervoltage Lockout level of 10.35V that the Startup Cell will not be switched on accidentally. a burst flag is set and Mode Mode the internal bias is switched off in order to reduce the 4. In Active Burst Mode. which can reduce the Mode conduction loss and the audible noise. the system enters the Active Burst Mode. 3. Or otherwise the power loss will increase Blanking Timer t drastically.

normal operation is resumed. Then will be off. it will reach 4. When there the startup cell current to Vcc turn on threshold. If CBK is 0.7. the IC will go to elapsed. there is a blanking window generated which prevents the system to enter Auto Restart Mode due to large load jumps.22uF and IBK is 13uA. the IC 4.3. However.1 Auto Restart mode with extended The IC provides Auto Restart Mode as the protection blanking time feature. CBK. Vcc Undervoltage. 5. Since there is no more switching. In case of Overload or Open Loop. the Vcc the internal blanking counter starts to count. If the fault condition persists. Over Control Unit temperature.9V to 4. Overload FB Time Mode and open loop protection are the one can have extended blanking time while Vcc Overvoltage. CoolSET®-F3R ICE3BR0665J Functional Description 3. the extendable blanking time is around 52ms and the total blanking time is 72ms. The IC is no external capacitor CBK connected. After the Start Up Phase. when an extra blanking time is auto restart mode again. The following table shows the relationship between possible system failures and the BA corresponding protection modes. A constant current source of IBK will start to charge the capacitor CBK from 0. the switch S1 is released. the fault condition is activated after the extra spike blanking time of 30us is checked. otherwise.0V immediately. reaches 20ms. If. When both the input signals at enter the startup phase (soft start) with switching AND gate G5 is positive. it can be achieved by adding an external removed. In combining the FB and blanking time. & some of the protections can have extended blanking 20ms G5 Auto time to delay the protection and some needs to fast 4. the Auto Restart Mode will be cycles.0V Blanking C4 Restart react and will go straight to the protection. Then the the start up cell will turn on and the Vcc is charged by clamped voltage 0. the VBA will is on and the startup cell will turn off.0V which will be observed by comparator C4.3 17 19 Nov 2012 . Auto Restart mode can prevent the SMPS from destructive states.9V to 4. When it voltage will drop.3 Protection Modes 3. Version 2. the FB exceeds After the system enters the Auto-restart mode.9V Overload Auto Restart Mode 1 S1 Open Loop Auto Restart Mode G2 VCC Undervoltage Auto Restart Mode Short Optocoupler Auto Restart Mode C3 Spike Auto restart enable Auto Restart Mode 4.0V # CBK IBK VCC Overvoltage Auto Restart Mode Overtemperature Auto Restart Mode 0. capacitor.0V are the extendable blanking time.9V at VBA can increase. At this stage.0V Blanking 30us Before entering the Auto Restart protection mode. The charging time from 0. When it hits the Vcc turn off threshold.7. the fault is needed. short opto-coupler and external auto restart enable will go to protection Figure 25 Auto Restart Mode right away.0V after the switch S1 is released.

To ensure this auto-restart function will not be Auto Restart mis-triggered during start up. In case the pre-defined auto-restart features are not sufficient.33V.0V C4 Voltage FB Thermal Shutdown Reference Tj >140°C Control Unit Figure 26 Auto Restart mode There are 2 modes of VCC overvoltage protection. When the function is enabled. there is a customer defined external Auto- restart Enable feature.2 Auto Restart without extended blanking a trigger signal to the base of the externally added time transistor. one is during soft start and the other is at all conditions. It can simply add Version 2. TAE at the BA pin. the Auto Restart Mode is entered. And this leads to Auto Enable Stop Signal C9 8us gate Restart Mode. The Thermal Shutdown block monitors the junction temperature of the IC. The 2nd one is VVCC >25. CoolSET®-F3R ICE3BR0665J Functional Description 3. After detecting a junction temperature higher than 130°C. the gate drive switching will be stopped and then the IC will enter auto-restart mode if the signal persists.5V Vcc OVP protection is inactivated during burst mode. The first one is VVCC voltage is > 20.5V reference and bias.3.7.5V implemented to blank the unstable signal. 120us C2 Blanking VCC Time VCC Spike & Blanking C1 20.5V and last for 120us and the IC enters Auto Restart Mode. This function can be triggered by pulling down the BA pin to < 0. The fault conditions are to detect the abnormal operating during start up such as open loop during light load start up.5V and FB is > 4. The logic can eliminate the possible of entering Auto Restart mode if there is a small voltage overshoots of VVCC during normal operating. 1ms VCC undervoltage is the Vcc voltage drop below Vcc UVLO counter turn off threshold. 0. Then the IC will turn off and the start Auto-restart BA up cell will turn on automatically. a 1ms delay time is Mode Reset VVCC < 10.3 18 19 Nov 2012 .5V 30us G1 softs_period 4. The VCC voltage is observed by comparator C1 and C4.3V Blanking Auto Restart Time drive mode Short Optocoupler also leads to VCC undervoltage as there is no self supply after activating the internal TAE 25. etc. This 25.0V and during soft_start period and the IC enters Auto Restart Mode.

Ta=25°C unless otherwise specified. Switching drain current. 15. which when being exceeded may lead to destruction of the integrated circuit.3 19 19 Nov 2012 . pulse width tp limited ID_Puls . Tj=150°C1) VCC Supply Voltage VVCC -0.1 Absolute Maximum Ratings Note: Absolute maximum ratings are defined as ratings.6mm (0.5kΩ series resistor) Version 2.063in.75 A by Tj=150°C Avalanche energy. 4. pulse width tp Is . CoolSET®-F3R ICE3BR0665J Electrical Characteristics 4 Electrical Characteristics Note: All voltages are measured with respect to ground (Pin 5). Drain Pin) VESD .5 V Junction Temperature Tj -40 150 °C Controller & CoolMOS® Storage Temperature TS -55 150 °C Thermal Resistance RthJA . For the same reason make sure. 90 K/W Junction -Ambient Soldering temperature. 260 °C 1.95 A limited by Tj=150°C Pulse drain current.3 5. repetitive tAR limited by IAR .3 5. max.5 A max.3 27 V FB Voltage VFB -0. 9. 2 kV Human body model2) 1) Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f 2) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5 V CS Voltage VCS -0.3 5.47 mJ max. 2. Parameter Symbol Limit Values Unit Remarks min. repetitive tAR limited by EAR . The voltage levels are valid if other ratings are not violated. 0. that any capacitor that will be connected to pin 4 (VCC) is discharged before assembling the application circuit. Tj=150°C1) Avalanche current.5 V BA Voltage VBA -0. wavesoldering Tsold .) from only allowed at leads case for 10s ESD Capability (incl.

Parameter Symbol Limit Values Unit Remarks min. V Version 2.2 50 μA VDrain = 450V Start Up Cell and CoolMOS® at Tj=100°C Supply Current with IVCCsup1 .3.5 2.1 Supply Section Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from – 25 °C to 125 °C. μA IFB = 0A Auto Restart Mode with Inactive Gate Supply Current in Active Burst IVCCburst1 . 450 950 μA VFB = 2. 3. 250 . 150 250 μA VVCC =17V VCC Charge Current IVCCcharge1 . 450 950 μA VVCC = 11. 7. typ.60 mA VVCC = 1V IVCCcharge3 .5V. Start Up Current IVCCstart .0 18. 0. .5V VCC Turn-On Threshold VVCCon 17. Parameter Symbol Limit Values Unit Test Condition min.8 4. If not otherwise stated.0 V VCC Turn-Off Threshold VVCCoff 9.55 0. 0.5 mA Inactive Gate Supply Current with Active Gate IVCCsup2 .5V Mode with Inactive Gate IVCCburst2 .3 Characteristics 4.0 mA VVCC = 0V IVCCcharge2 0. which are related to 25°C. max.2 V VCC Turn-On/Off Hysteresis VVCChys .3 20 19 Nov 2012 . mA VVCC =17V Leakage Current of IStartLeak .VFB = 2.2 mA IFB = 0A Supply Current in IVCCrestart . max. VCC Supply Voltage VVCC VVCCoff 25 V Max value limited due to Vcc OVP Junction Temperature of TjCon -25 130 °C Max value limited due to thermal Controller shut down of controller Junction Temperature of TjCoolMOS -25 150 °C CoolMOS® 4. 5.5 . 1. Typical values represent the median values. a supply voltage of VCC = 18 V is assumed.9 1.0 19.5 11. CoolSET®-F3R ICE3BR0665J Electrical Characteristics 4.2 Operating Range Note: Within the operating range the IC operates as described in the functional description.7 .8 10.

0 73.3 PWM Section Parameter Symbol Limit Values Unit Test Condition min. ms Version 2. Soft Start time tSS .3 3. typ. typ.6 . V VFB Operating Range Max level VFBmax .3V PWM-OP Gain AV 3. 4. 0.2 kHz Tj = 25°C Frequency Jittering Range fjitter . 4. Duty Cycle Dmin 0 .3.4 22 kΩ 1) The parameter is not subjected to production test . ±2.5 Voltage Ramp Offset VOffset-Ramp . max.1 3. typ.00 5.2 Internal Voltage Reference Parameter Symbol Limit Values Unit Test Condition min. .0 . Duty Cycle Dmax 0.5 kHz fOSC2 59.10 V measured at pin FB IFB = 0 4.3. CoolSET®-F3R ICE3BR0665J Electrical Characteristics 4.5 .3 V CS=1V.75 0.3 21 19 Nov 2012 .70 0.0 70. . VFB < 0.4 Soft Start time Parameter Symbol Limit Values Unit Test Condition min. ms Tj = 25°C Max. max.0 .80 Min.verified by design/characterization 4. 0.8 65. 20. limited by Comparator C41) FB Pull-Up Resistor RFB 9 15. V VFB Operating Range Min Level VFBmin . max.67 . Trimmed Reference Voltage VREF 4.5 65. Fixed Oscillator Frequency fOSC1 56.90 5.3. kHz Tj = 25°C Frequency Jittering period Tjitter .

μs Restart Protection 1) The parameter is not subjected to production test .85 4.5 21. Version 2. 30 .93 3.25 1.00 4.0 25.9 μA Charge starts after the built-in 20ms blanking time elapsed Thermal Shutdown1) TjSD 130 140 150 °C Controller Built-in Blanking Time for tBK .45 V Comparator C5 Active Burst Mode Level for VFBC6a 3.4 V >30μs Charging current at BA pin IBK 10 13.5 26.95 V VFB = 4V Normal Operating Mode Blanking time voltage limit for VBKC3 3. Clamped VBA voltage during VBAclmp 0.25 0. ms without external Overload Protection or enter capacitor at BA pin Active Burst Mode Inhibit Time for Auto-Restart tIHAE .5 Control Unit Parameter Symbol Limit Values Unit Test Condition min.3.5 20.9 0.15 V Comparator C3 Over Load & Open Loop Detection VFBC4 3. 20 .5 V Comparator C2 Auto-restart Enable level at BA pin VAE 0. ms Count when VCC>18V enable function during start up Spike Blanking Time before Auto.85 4.verified by design/characterization.5 V VFB = 5V Comparator C1 Overvoltage Detection Limit for VVCCOVP2 25.05 3.85 0. CoolSET®-F3R ICE3BR0665J Electrical Characteristics 4. The thermal shutdown temperature refers to the junction temperature of the controller.33 0.0 16.00 4.0 .50 3. tSpike .65 V After Active Burst Comparator C6a Mode is entered Active Burst Mode Level for VFBC6b 2.35 1.16 V After Active Burst Comparator C6b Mode is entered Overvoltage Detection Limit for VVCCOVP1 19.3 22 19 Nov 2012 . Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP.15 V Limit for Comparator C4 Active Burst Mode Level for VFBC5 1.35 3. typ. max. 1.

2 .verified by design/characterization 2) Measured in a Typical Flyback Converter Application Version 2.7 CoolMOS® Section Parameter Symbol Limit Values Unit Test Condition min. ns Fall Time tfall .6 Current Limiting Parameter Symbol Limit Values Unit Test Condition min. 302) . ns CS Input Bias Current ICSbias -1. Peak Current Limitation Vcsth 0.5A Effective output capacitance. typ. 220 .3 23 19 Nov 2012 . typ. 26 .6V/μs (incl.3.3.10 V dVsense / dt = 0. ns 1) The parameter is not subjected to production test . max.58 Ω Tj=125°C1) at ID = 2. pF VDS = 0V to 480V1) related Rise Time trise .03 1. 0.38 V Active Burst Mode Leading Edge Blanking tLEB . Propagation Delay) (see Figure 20) Peak Current Limitation during VCS2 0.34 0. energy Co(er) .65 0. .96 1. V Tj = 110°C Refer to Figure 30 for other V(BR)DSS in different Tj Drain Source On-Resistance RDSon .29 0. 1. 302) .37 1. max. μA VCS =0V 4. Drain Source Breakdown Voltage V(BR)DSS 650 .5 -0. CoolSET®-F3R ICE3BR0665J Electrical Characteristics 4.75 Ω Tj = 25°C .

Tc : TO220 Figure 28 SOA temperature derating coefficient curve Version 2.C] Ta : DIP.01 tp = 0.001 tp = 1000ms DC 0.01ms tp = 0.C 100 10 1 ID [A] 0.0001 1 10 100 1000 V DS [V] Figure 27 Safe Operating area (SOA) curve for ICE3BR0665J SOA temperature derating coefficient curve ( package dissipation ) for F3 & F2 CoolSET 120 100 SOA temperature derating coefficient [%] 80 60 40 20 0 0 20 40 60 80 100 120 140 Ambient/Case temperature Ta/Tc [deg. TC = 25deg. CoolSET®-F3R ICE3BR0665J Typical CoolMOS® Performance Characteristic 5 Typical CoolMOS® Performance Characteristic Safe Operating Area for ICE3A(B)R0665J ID = f ( VDS ) parameter : D = 0.3 24 19 Nov 2012 .1 0.1ms tp = 1ms tp = 10ms tp = 100ms 0.

CoolSET®-F3R ICE3BR0665J Typical CoolMOS® Performance Characteristic Allowable Power Dissipation for F3 CoolSET in DIP-8 package 1. Ptot=f(Ta) 700 660 V BR(DSS) [V] 620 580 540 -60 -20 20 60 100 140 180 T j [°C] Figure 30 Drain-source breakdown voltage.2 0.C] Figure 29 Power dissipation.0 0 20 40 60 80 100 120 140 Ambient temperature.4 1.4 0.8 0.3 25 19 Nov 2012 .6 1.2 Allowable Power Dissipation.0 0. VBR(DSS)=f(Tj) Version 2.6 0. Ptot [W] 1. Ta [deg.

60 54 Input power (85~265Vac) [W] 48 42 36 PI-001-ICE3BR0665J_85Vac 30 24 18 12 6 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Ambient Temperature [°C] Figure 31 Input power curve Vin=85~265Vac. a wide range input voltage (Figure 31). Pin=f(Ta) 100 90 80 Input power (230Vac) [W] 70 PI-002-ICE3BR0665J_230Vac 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Ambient Temperature [°C] Figure 32 Input power curve Vin=230Vac+/-15%.The device saturation current (ID_Puls @ Tj=125°C) is also considered.3 26 19 Nov 2012 . operating temperature is 50°C. The input power already includes the power loss at input common mode choke. Pin=f(Ta) Version 2. estimated efficiency is 85%. bridge rectifier and the CoolMOS. For example. CoolSET®-F3R ICE3BR0665J Input Power Curve 6 Input Power Curve Two input power curves giving the typical input power versus ambient temperature are showed below. Vin=85Vac~265Vac (Figure 31) and Vin=230Vac+/-15% (Figure 32). then the estimated output power is 42W (49W * 85%). To estimate the output power of the device. it is simply multiplying the input power at a particular operating ambient temperature with the estimated efficiency for the application. The calculation is based on no copper area as heatsink for the device. The curves are derived based on a typical discontinuous mode flyback model which considers either 50% maximum duty ratio or 100V maximum secondary to primary reflected voltage (higher priority).

CoolSET®-F3R ICE3BR0665J Outline Dimension 7 Outline Dimension PG-DIP-8 (Plastic Dual In-Line Outline) Figure 33 PG-DIP-8 (Pb-free lead plating Plastic Dual-in-Line Outline) Version 2.3 27 19 Nov 2012 .

CoolSET®-F3R ICE3BR0665J Marking 8 Marking Marking Figure 34 Marking for ICE3BR0665J Version 2.3 28 19 Nov 2012 .

b. GND pin of IC11.0mm b. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2. DC ground of the CoolSET® device. L1: Gap separation is around 1. 600V traces (drain voltage of CoolSET® IC11) to nearby trace: > 2. C11: “Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11 separately in one point. DC ground of the primary auxiliary winding in power transformer. C14. arcing would incur. the signal grounds from C13. R12 c.5mm 3. a. Add spark gap Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated charge during surge test through the sharp point of the saw-tooth plate. DC ground of the current sense resistor. The primary DC grounds include the followings. Spark Gap 3 and Spark Gap 4. C4 2. a. d. C14 and C15 should be placed as close to the controller ground and the controller pin as possible so as to reduce the switching noise coupled into the controller. DC ground from the bridging Y-capacitor. Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 35): 1. TR1. High voltage traces clearance: High voltage traces should keep enough spacing to the nearby traces. input common mode choke. and ground of C16 and Z11. Otherwise. C15 and collector of IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground. DC ground from bridge rectifier.3 29 19 Nov 2012 .5mm (no safety concern) Version 2. BR1 e. C13. CoolSET®-F3R ICE3BR0665J Schematic for recommended PCB layout 9 Schematic for recommended PCB layout TR1 BR1 R11 C12 Spark Gap 3 D21 FUSE1 C11 X-CAP Vo L bulk cap L1 D11 Spark Gap 1 C1 C21 GND Spark Gap 2 D11 Spark Gap 4 Z11 GND N IC11 C2 C3 R12 C16 R21 CS DRAIN R13 Y-CAP Y-CAP C4 D13 R14 Y-CAP F3 BA CoolSET VCC R23 R22 GND FB NC C22 C13 C15 * C14 C23 R24 IC12 IC21 R25 F3 CoolSET schematic for recommended PCB layout Figure 35 Schematic for recommended PCB layout General guideline for PCB layout design using F3/F3R CoolSET® (refer to Figure 35): 1. It can reduce the switching noise going into the sensitive pins of the CoolSET® device effectively. a. “Star Ground “at bulk capacitor ground. Filter capacitor close to the controller ground: Filter capacitors.

The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the sensitive components such as the primary controller.3 30 19 Nov 2012 . the gap separation is around 3mm 2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input 3. The diode can be a fast speed diode such as IN4148. Version 2. Add negative pulse clamping diode. IC11. Live / Neutral to GROUND: These 2 Spark Gaps can be used when the lightning surge requirement is >6KV. D11 to the Current sense resistor. Spark Gap 1 and Spark Gap 2. 230Vac input voltage application. the gap separation is around 5. CoolSET®-F3R ICE3BR0665J Schematic for recommended PCB layout b. R12: The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET® and reduce the abnormal behavior of the CoolSET®.5mm 115Vac input voltage application.

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