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IRF520N
HEXFET Power MOSFET
l Advanced Process Technology
D
l Dynamic dv/dt Rating VDSS = 100V
l 175C Operating Temperature
l Fast Switching
RDS(on) = 0.20
l Fully Avalanche Rated G
Description ID = 9.7A
Fifth Generation HEXFETs from International Rectifier S
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use
in a wide variety of applications.
Thermal Resistance
Parameter Typ. Max. Units
RJC Junction-to-Case 3.1
RCS Case-to-Sink, Flat, Greased Surface 0.50 C/W
RJA Junction-to-Ambient 62
5/13/98
IRF520N
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 100 V VGS = 0V, ID = 250A
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient 0.11 V/C Reference to 25C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance 0.20 VGS = 10V, ID = 5.7A
VGS(th) Gate Threshold Voltage 2.0 4.0 V VDS = V GS, ID = 250A
gfs Forward Transconductance 2.7 S VDS = 50V, ID = 5.7A
25 VDS = 100V, VGS = 0V
IDSS Drain-to-Source Leakage Current A
250 VDS = 80V, VGS = 0V, TJ = 150C
Gate-to-Source Forward Leakage 100 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage -100 VGS = -20V
Qg Total Gate Charge 25 ID = 5.7A
Qgs Gate-to-Source Charge 4.8 nC VDS = 80V
Qgd Gate-to-Drain ("Miller") Charge 11 VGS = 10V, See Fig. 6 and 13
td(on) Turn-On Delay Time 4.5 VDD = 50V
tr Rise Time 23 ID = 5.7A
ns
td(off) Turn-Off Delay Time 32 RG = 22
tf Fall Time 23 RD = 8.6, See Fig. 10
Between lead, D
LD Internal Drain Inductance 4.5
6mm (0.25in.)
nH G
from package
LS Internal Source Inductance 7.5
and center of die contact S
38
(Body Diode) p-n junction diode. S
Notes:
Repetitive rating; pulse width limited by ISD 5.7A, di/dt 240A/s, VDD V(BR)DSS,
max. junction temperature. ( See fig. 11 ) TJ 175C
VDD = 25V, starting TJ = 25C, L = 4.7mH Pulse width 300s; duty cycle 2%.
RG = 25, IAS = 5.7A. (See Figure 12)
IRF520N
I , D rain-to-Source Current (A )
I , D rain-to-Source Current (A )
6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
BOTTOM 4.5V BOTTOM 4.5V
10 10
4 .5V
D
D
4.5 V
20 s P U LS E W ID TH 2 0 s P U L S E W ID TH
TC = 2 5C T C = 17 5C
1 A 1 A
0.1 1 10 100 0.1 1 10 100
V D S , D rain-to-S ourc e V oltage (V ) V DS , D rain-to-S ource V oltage (V )
100 3.0
I D = 9.5 A
R D S (on) , D ra in-to -S o urc e O n R e s is ta nc e
I D , D ra in -to-S ourc e C urrent (A)
2.5
2.0
TJ = 25 C
(N o rm alize d)
TJ = 17 5 C
10 1.5
1.0
0.5
V DS= 50V
2 0 s P U LS E W ID TH V G S = 1 0V
1 0.0 A
A
4 5 6 7 8 9 10 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
600 20
V GS = 0V , f = 1MHz I D = 5.7 A
C is s = C g s + C g d , C d s S H O R TE D V D S = 80 V
400
12
300 C oss
8
200
C rss
4
100
FO R TE S T C IR C U IT
S E E FIG U R E 1 3
0 A 0 A
1 10 100 0 5 10 15 20 25
V D S , D rain-to -S ource V oltage (V ) Q G , T otal G ate C harge (nC )
100 100
O P E R A TIO N IN TH IS A R E A LIM ITE D
B Y R D S (o n)
I SD , Reverse D rain C urrent (A)
10s
I D , Drain C urrent (A )
10
TJ = 17 5C 100 s
10
TJ = 2 5C
1m s
1
10m s
T C = 25 C
T J = 17 5C
V G S = 0V S ing le P u lse
1 A 0.1 A
0.4 0.6 0.8 1.0 1.2 1.4 1 10 100 1000
V S D , S ourc e-to-D rain V oltage (V ) V D S , D rain-to-S ource V oltage (V )
10V
Pulse Width 1 s
6.0
Duty Factor 0.1 %
0.0
25 50 75 100 125 150 175 10%
TC , Case Temperature ( C) VGS
td(on) tr t d(off) tf
10
Thermal Response (Z thJC )
D = 0.50
1
0.20
0.10
0.05
0.02 SINGLE PULSE P DM
0.01 (THERMAL RESPONSE)
0.1
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
L
VDS 200
ID
10 V IAS
120
tp
0.01
V(BR)DSS
40
tp
VDD
V D D = 25 V
0 A
25 50 75 100 125 150 175
VDS S tarting T J , J unc tion T em perature (C )
Current Regulator
Same Type as D.U.T.
50K
QG 12V .2F
.3F
10 V +
QGS QGD V
D.U.T. - DS
VGS
VG
3mA
Charge IG ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit
IRF520N
+
- +
-
RG dv/dt controlled by RG +
Driver same type as D.U.T. VDD
-
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VGS=10V *
Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD
Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent
Ripple 5% ISD
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http://www.irf.com/ Data and specifications subject to change without notice. 5/98
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/