MOSModels Gatech PDF

MOS Models (5/23/00) Page 1
1.8 - MOSFET MODELS

INTRODUCTION
Objective
The objective of this presentation is:
1.) Understand how the MOS transistor works
2.) Understand and apply the simple large signal model
3.) Understand and apply the small-signal model
Outline
MOS Structure and Operation
Large Signal Model
Small-Signal Model
Capacitance
Short Channel Large Signal Model
Subthreshold Large Signal Model
Summary
ECE 4430 - Analog Integrated Circuits and Systems Phillip E. Allen 2000
MOS STRUCTURE AND OPERATION

Metal-Oxide-Semiconductor Structure
Bulk/Substrate
p+
,,,
Source
,,,
n+
Gate
Polysilicon
Drain
n+
Thin Oxide
(10-100nm
100-1000)
p- substrate
Heavily Lightly Intrinsic Lightly Heavily Metal

Doped p Doped p Doping Doped n Doped n Fig1.8-1
Terminals:
Bulk - Used to make an ohmic contact to the substrate
Gate - The gate voltage is applied in such a manner as to invert the doping of the material directly
beneath the gate to form a channel between the source and drain.
Source - Source of the carriers flowing in the channel
Drain - Collects the carriers flowing in the channel
Formation of the Channel for an Enhancement MOS Transistor
,,,
Subthreshold (VG<VT)
VB = 0 VS = 0 VG < VT VD = 0
Polysilicon
p+ n+ n+
,,,
p- substrate
Threshold (VG=VT)
VB = 0 VS = 0 VG =VT VD = 0
Polysilicon
p+ n+ n+
,,,
p- substrate Inverted Region
Strong Threshold (VG>VT)
,,,
VB = 0 VS = 0 VG >VT VD = 0
Polysilicon
p+ n+ n+
Fig1.8-2
The MOSFET Threshold Voltage

When the gate voltage reaches a value called the threshold voltage (VT), the substrate beneath the gate
becomes inverted (it changes from p-type to n-type).
Qb QSS
V T = MS + -2 F -
Cox + Cox
where
MS = F(substrate) - F(gate)
F = Equilibrium electrostatic potential (Femi potential)
kT
F(PMOS) = - q ln(NA/ni) = -Vt ln(NA/ni)
kT
F(NMOS) = q ln(ND/ni) = Vt ln(ND/ni)
Qb 2qNAsi(|-2F+vSB|)
QSS = undesired positive charge present in the interface between the oxide and the bulk silicon
Rewriting the threshold voltage expression gives,
Q b0 QSS Q b - Q b0
V T = MS -2 F - C - C - Cox = V T0 + |-2 F + v S B | - |-2 F |
ox ox
where
Q b0 Q SS 2qsiNA
V T0 = MS - 2 F - =
Cox - Cox and Cox
Signs for the Quantities in the Threshold Voltage Expression
Parameter N-Channel P-Channel

Substrate p-type n-type
MS
Metal
n+ Si Gate
p+ Si Gate + +
F +
Qb0,Qb +
Qss + +
VSB +
+
Example 1 - Calculation of the Threshold Voltage

Find the threshold voltage and body factor for an n-channel transistor with an n+ silicon gate if tox =
200 , NA = 3 1016 cm -3, gate doping, ND = 4 1019 cm -3, and if the positively-charged ions at the
oxide-silicon interface per area is 10 10 cm-2.
Solution
From above, F(substrate) is given as
3 10 16
F(substrate) = 0.0259 ln = 0.377 V
1.45 1 0
1 0
The equilibrium electrostatic potential for the n+ polysilicon gate is found from as
4 10 1 9
F(gate) = 0.0259 ln = 0.563 V
1.45 10 1 0
Therefore, the potential MS is found to be

F(substrate) F(gate) = 0.940 V.
The oxide capacitance is given as
3.9 8.854 10 -14
C ox = ox /tox = = 1.727 10-7 F/cm2
200 10 - 8
The fixed charge in the depletion region, Qb0, is given as

Qb0 = [2 1.6 10-19 11.7 8.854 10-14 2 0.377 3 1016]1/2 = 8.66 10-8 C/cm2.
Example 1 - Continued
Dividing Qb0 by Cox gives 0.501 V. Finally, Qss/Cox is given as
Qss 10 10 1.60 10 -19
= = 9.3 10-3 V
Cox 1.727 10 -7
Substituting these values for VT0 gives
V T0 = - 0.940 + 0.754 + 0.501 - 9.3 x 10-3 = 0.306 V

The body factor is found as
1/2
2 1.6 10 -19 11.7 8.854 10 -14 3 10 1 6
= = 0.577 V1/2
1.727 10 -7
SIMPLE LARGE SIGNAL MOSFET MODEL

Large Signal Model Derivation
Derivation-
+
1.) Let the charge per unit area in the channel inversion vGS +
- v
iD - DS
layer be
n+ n+
Q I(y) = -C ox[vGS - v(y) - VT] (coulombs/cm2) v(y)
Source dy Drain
p- y
2.) Define sheet conductivity of the inversion layer per 0 y y+dy L
square as
cm2 coulombs amps 1
S = oQ I(y) vs cm2 = volt = /sq.

3.) Ohm's Law for current in a sheet is
iD dv -iD -iDdy
JS =
W = - E
S y = - S dy dv = SW dy = oQ I(y)W iD dy = -W oQ I(y)dv
4.) Integrating along the channel for 0 to L gives

L vD S vD S

iD dy = -
W oQ I(y)dv =
W o C ox [v GS -v(y)-V T ] dv
0 0 0
5.) Evaluating the limits gives
WoCox v 2 (y) v D S W oC o x v DS 2
iD = (v GS -V T )v(y) - iD = (v -V )v - 2
L 2 0 L GS T DS
Saturation Voltage - V D S(sat)

Interpretation of the large signal model:
iD
vDS = vGS - VT
Active Region Saturation Region
Increasing
values of vGS
vDS
The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of the inverted
parabolas.
diD oCoxW

dvDS = [(vGS -V T ) - vDS ] = 0 v D S (sat) = v G S - V T
L
Useful definitions:
oCoxW KW
= L =
L
Complete Large Signal Model

Regions of Operation of the MOS Transistor:
1.) Cutoff Region:
iD = 0, v GS - V T < 0 (Ignores subthreshold currents)
2.) Active Region
oCoxW
iD = 2L [ 2(v G S - V T ) - v D S] v DS , 0 < v DS < v GS - V T
3.) Saturation Region

oCoxW
iD = v - VT) 2 , 0 < v GS - V T < v D S
2L ( G S
Output Characteristics of the MOSFET:
iD /ID0
vDS = vGS - VT
vGS-VT = 1.0
1.0
Active VGS0 - VT
Saturation Region
Region vGS-VT = 0.867
0.75 VGS0 - VT
Channel modulation effects vGS-VT = 0.707
0.5 VGS0 - VT
vGS-VT = 0.5
VGS0 - VT
0.25 vGS-VT = 0
Cutoff Region VGS0 - VT
0 vDS
0 0.5 1.0 1.5 2.0 2.5 VGS0 - VT
Influence of VD S on the Output Characteristics

Channel modulation effect:
As the value of vDS increases, it causes the effective L to decrease which causes the current to increase.
Illustration:
,,,
VG > VT VD > VDS(sat)
,,,,,,,
B S
Depletion
Polysilicon
,,,,,,,
Region
p+ n+ n+
Leff
p- substrate Xd
Fig1.8-3
Note that Leff = L - Xd

Therefore the model in saturation becomes,
KW diD KW dL eff iD dX d
dvDS = - 2Leff2 (v GS - V T ) dvDS = Leff dvDS iD
iD = 2L (v GS -V T ) 2 2
eff
Therefore, a good approximation to the influence of vDS on iD is
diD KW
iD iD(vDS=0) + dv vDS = iD (vDS=0)(1 + vDS) = 2L (v GS -V T )2(1+ v DS )
DS
Influence of the Bulk Voltage on the Large Signal MOSFET Model

Illustration of the influence of the bulk:
V SB0 = 0V: VSB0 =0V Gate Drain
- + VGS>VT VDS>0
Bulk Source Poly
p+ n+ n+
p- Substrate/Bulk
V SB1>0V: VSB1 Gate Drain

- + VGS>VT VDS>0
Bulk Source Poly
p+ n+ n+
p- Substrate/Bulk
V SB2 > V SB1 : VSB2 Gate Drain

- + VGS>VT VDS>0
Bulk Source Poly
p+ n+ n+
p- Substrate/Bulk
Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued
Bulk-Source (vBS) influence on the transconductance characteristics-
iD
Decreasing values
of bulk-source voltage
VBS = 0
vDS vGS - VT
vGS
VT0 VT1 VT2 VT3
In general, the simple model incorporates the bulk effect into VT by the following empirically developed
equation-
V T (v BS ) = V T0 + 2| f | + |v BS | - 2| f |
MOSFET Schematic Symbols

Enhancement:
VBS 0V VBS=0V Simple
D D D
NMOS G B G G
S S S
D D D
PMOS G B G G
S S S Fig1.8-4
Summary of the Simple Large Signal MOSFET Model

N-channel reference convention: D
iD +
G B vDS
+ +
vGS vBS
- --
Non-saturation- S
WoCox vDS2
iD = (v - V T )v D S - 2 (1 + vDS )
L GS
Saturation-
WoCox v DS (sat) 2 W oC ox
(1 + v DS ) =
2L (v GS - V T ) (1 + v DS )
iD = (v GS - V T )v DS (sat) - 2
L 2
where:
o = zero field mobility (cm2/voltsec)
Cox = gate oxide capacitance per unit area (F/cm2)
= channel-length modulation parameter (volts-1)
V T = V T0 + 2| f | + |v B S | - 2| f|
VT0 = zero bias threshold voltage
= bulk threshold parameter (volts-0.5)
2|f| = strong inversion surface potential (volts)
For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert current.
MOSFET
Constants for Silicon:
Constant Symbol Constant Description Value Units

VG Silicon bandgap (27C) 1.205 V
k Boltzmanns constant 1.381x10-23 J/K
ni Intrinsic carrier concentration (27C) 1.45x1010 cm-3
0 Permittivity of free space 8.854x10-14 f/cm
si Permittivity of silicon 11.7 0 F/cm
ox Permittivity of SiO2 3.9 0 F/cm
Model Parameters for a Typical CMOS Bulk Process (0.8m CMOS n-well):
Parameter Parameter Typical Parameter Value

Symbol Description N-Channel P-Channel Units
VT0 Threshold Voltage 0.7 0.15 0.7 0.15 V
(VBS = 0)
K' Transconductance 110.0 10% 50.0 10% A/V2
Parameter (in
saturation)
Bulk threshold 0.4 0.57 (V)1/2
parameter
Channel length 0.04 (L=1 m) 0.05 (L = 1 m) (V)-1
modulation 0.01 (L=2 m) 0.01 (L = 2 m)
parameter
2|F| Surface potential at 0.7 0.8 V
strong inversion
MOSFET SMALL SIGNAL MODEL

Small-Signal Model
Complete schematic model:
D D
id
G B
+ + +D
G B G B vgs vbs rds vds
gmvgs gmbsvbs
- - -
S S
S S Fig. 4.2-4
where
diD
| = (V -V ) = diD
| iD
gm dv 2 ID gds dv = iD
DS Q 1 + v D S
GS T
GS Q
D iD vGS i D vT gm
gmbs = v Q = v v = -
and
BS GS BS Q vTvBSQ 2 2| F | - V B S = gm
=
Simplified schematic model:

id
D D G
+ +D
G G vgs rds vds
gmvgs
- -
S S S S Fig. 4.2-2
Extremely important assumption:

g m 10g m b s 100g ds
Illustration of the Small-Signal Model Application

DC resistor:
i
v V
DC resistance = i = AC Resistance
Q I
Useful for biasing - creating current from voltage and DC Resistance
ID
vice versa
v
VT VDS Fig. 4-2-2B
Small-Signal Load (AC resistance):
D D
id
G B
+ + +D
G B G B vgs vbs rds vds
gmvgs gmbsvbs
- - -
S S
S S Fig. 4.2-4
vds 1 1
AC resistance = i = g + g g
d m ds m
Example 2 - Small-Signal Load Resistance

Find the small signal resistance of the MOS diode VDD = 5V
shown using the parameters of Table 3.2-1.
Assume that the W/L ratio is 10m/1m.
Solution rac
If we are going to include the bulk effect, we must first find the dc value
of the bulk-source voltage. Unfortunately, we do not know the threshold
voltage because the bulk-source voltage is unknown. The best approach is to 100A
ignore the bulk-source voltage, find the gate-source voltage and then iterate if
Fig. 4.2-5
necessary.
2I 2100
VGS = + V = + 0.7 = 1.126V
T0 11010
Thus let us guess at a gate-source voltage of 1.3V (to account for the bulk effect) and calculate the resulting
gate-source voltage.
V T = V T0 + 2| F | - (-3.7) - 2|F| = 0.7 + 0.4 0.7+3.7 - 0.4 0.7 = 1.20V VGS = 1.63V
Now refine our guess at VGS as 1.6V and repeat the above to get VT = 1.175V which gives VGS = 1.60V.
Therefore, V BS = -3.4V.
Example 2 - Continued
id rac
The small signal model for this example is shown. G,D,B
+
The ac input resistance is found by,
rds vds = vgs vac
iac = gdsvac - gmvgs - gmbsvbs gmvgs gmbsvbs
-
= gdsvac + gmvs + gmbsvs = vac(gm+gmbs+gds) S iac Fig. 4.2-6
vac 1
rac = i = g +g +g
ac m mbs ds
Now we must find the parameters which are,
gm = 2ID = 211010100 S = 469S, gds = 0.04V-1100A = 4S,
469S0.4
and gmbs = = 0.0987469S = 46.33S
2 0.7+3.4
Finally,
106
rac = 469 + 46.33 + 4 = 1926
If we had used the previous approximations of gm 10gmbs 100gds, then we could have simply let
1 1
rac g = 469 = 2132
m
Probably the most important result of this approximation is that we would not have to find VBS which took
a lot of effort for little return.
Small-Signal Model for the Active Region
iD | KWV DS KW
gm =
v GS Q = (1+ V DS ) VD S
L L
iD KW V D S
gmbs = v Q| =
BS 2L 2 F - V B S
iD KW ID KW
gds = v Q| = L ( V GS - V T - V DS )(1+ V DS ) + 1+V L (V GS - V T - V DS )
DS DS
MOSFET CAPACITANCES
Types of Capacitance
Physical Picture:
SiO2
Gate
Source Drain
C1 C2 C3
FOX FOX
C4
CBS CBD
Bulk
Fig1.8-5
MOSFET Capacitances consist of:

Depletion capacitance
Charge storage or parallel plate capacitance
MOSFET Depletion Capacitors

Polysilicon gate
Model:
H G
CJAS CJSWPS
MJSW, v BS FCPB
C BS = + D C
MJ
v B S v B S
1 - 1 - Source Drain
PB PB
F
and E
A B
SiO2
Bulk
CJAS V B S Fig1.8-6
C BS =
1+MJ 1 - (1+MJ)FC + MJ
PB Drain bottom = ABCD
( 1- F C)
Drain sidewall = ABFE + BCGF + DCGH + ADHE
CBS
CJSWPS V B S
+
1+MJSW 1 - (1+MJSW)FC + MJSW ,
PB
( 1 - F C)
vBS FCPB
vBS> FCPB vBS FCPB
PB
where vBS
FCPB Fig1.8-6B
AS = area of the source
PS = perimeter of the source
CJSW = zero bias, bulk source sidewall capacitance
MJSW = bulk-source sidewall grading coefficient
For the bulk-drain depletion capacitance replace "S" by "D" in the above.
Charge Storage (Parallel Plate) MOSFET Capacitances - C1 , C2 , C3 and C4
Mask L Oxide encroachment
Actual
L (Leff) Mask Actual
LD W W (Weff)
Gate
Source-gate overlap Drain-gate overlap

capacitance CGS (C1) capacitance CGD (C3)
Gate
FOX FOX
Source Drain
Gate-Channel Channel-Bulk
Bulk
Capacitance (C2) Capacitance (C4)
Fig1.8-7
Overlap capacitances:
C1 = C3 = LDWeffCox = CGSO or CGDO (LD 0.015 m for LDD structures)
Channel capacitances:
C2 = gate-to-channel = CoxW eff(L-2LD) = CoxW effLeff
C4 = voltage dependent channel-bulk/substrate capacitance
Charge Storage (Parallel Plate) MOSFET Capacitances - C5

View looking down the channel from source to drain
Overlap Overlap
Gate
FOX C5 Source/Drain C5 FOX
Bulk
Fig1.8-8
C5 = CGBO
Capacitance values and coefficients based on an oxide thickness of 140 or Cox=24.7 104 F/m2:
Type P-Channel N-Channel Units

CGSO 220 1012 220 1012 F/m
CGDO 220 1012 220 1012 F/m
CGBO 700 1012 700 1012 F/m
CJ 560 106 770 106 F/m2
CJSW 350 1012 380 1012 F/m
MJ 0.5 0.5
MJSW 0.35 0.38
Expressions for CGD, CG S and CG B
,,,
Cutoff Region: Cutoff
VB = 0 VS = 0 VG < VT VD > 0
CGB = C2 + 2 C 5 = Cox(Weff)(Leff) + 2CGBO(Leff) CGS CGD
Polysilicon
CGS = C1 Cox(LD)Weff) = CGSO(Weff)
p+ n+ n+
CGD = C3 Cox(LD)Weff) = CGDO(Weff) CGB
,,,
p- substrate
Saturation Region: Saturated

VB = 0 VS = 0 VG >VT VD >VG -VT
CGB = 2C5 = CGBO(Leff) CGS CGD
Polysilicon
CGS = C1 +(2/3)C2 = Cox(LD+0.67Leff)(Weff)
p+ n+ n+
,,,
= CGSO(Weff) + 0.67Cox(Weff)(Leff)
CGD = C3 Cox(LD)Weff) = CGDO(Weff)
Active
,,,
VB = 0 VS = 0 VG >VT VD <VG -VT
Active Region: CGS CGD
Polysilicon
CGB = 2 C 5 = 2CGBO(Leff)
p+ n+ n+
CGS = C1 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGSO + 0.5CoxLeff)Weff
Fig1.8-9
CGD = C3 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGDO + 0.5CoxLeff)Weff
Illustration of CGD, CG S and CG B

Capacitance
C4 Large
C2 + 2C5
CGS
C1+ 0.67C2
CGS, CGD
C1+ 0.5C2
vDS = constant
CGS, CGD CGD vBS = 0
C1, C3 C4 Small
2C5 CGB
0 vGS
Off Saturation Non-
Saturation
VT vDS +VT
Fig1.8-10
Comments on the variation of CBG in the cutoff region:

1
CBG = 1 1 + 2C5
+ C
C2 4
For vGS 0, C GB C 2 + 2C 5
(C4 is large because of the thin inversion layer in weak inversion where VGS is slightly less than VT))
For 0<vGS V T, C GB 2C 5
(C4 is small because of the thicker inversion layer in strong inversion)
Small-Signal Frequency Dependent Model

Cgd id
G D
+ +
Cgs
vgs rds vds
gmvgs gmbsvbs
- -
Cgb S - S Cbd
vbs Cbs
+
B Fig1.8-15
The depletion capacitors are found by evaluating the large signal capacitors at the DC operating point.
The charge storage capacitors are constant for a specific region of operation.
Gainbandwidth of the MOSFET:
Assume VSB = 0 and the MOSFET is in saturation,
1 gm 1 gm
f T = 2 C + C 2 C
gs gd gs
Recalling that
2 W
Cgs 3 C ox WL and gm = oCox (V GS -V T )
L
gives
3 o
fT = 4 2 (V GS -V T )
L
Summary of the MOSFET Large Signal Model
D
rD
CGD CBD
vBD
+ -
iD iBD
G rG vBS rB
+ -
B
iBS
where,
CGS CBS rG, rS, rB, and rD are ohmic and contact resistances
vBD vBS
iBD = Is exp - 1 and iBS = Is exp V - 1
CGB Vt t
rS
SHORT-CHANNEL MOSFET MODEL

Velocity Saturation
The most important short-channel effect in MOSFETs is the velocity saturation of carriers in the
channel. A plot of electron drift velocity versus electric field is shown below.
Electron Drift Velocity (m/s)

105
5x104
2x104
104
5x103
105 106 107
Electric Field (V/m) Fig1.8-11
An expression for the electron drift velocity as a function of the electric field is,
nE
v d 1 + E/E
c
where
vd = electron drift velocity (m/s)
n = low-field mobility ( 0.07m2/Vs)
Ec = critical electrical field at which velocity saturation occurs
Short-Channel Model Derivation

As before,
iD WQ I(y) nE E
JD = JS = W = Q I(y)vd(y) iD = W QI(y)vd(y) = iD 1 + E = WQ I(y)nE
1 + E/E c C
Replacing E by dv/dy gives,
1 d v dv
iD 1 + E dy= WQ I(y)n
C dy
Integrating along the channel gives,
L vD S
1 d v
iD 1 +
Ec dydy = WQ I(y) ndv
0 0
The result of this integration is,

nCox W K W
iD = [2(v - V )v - v 2] = [2(vGS - V T )vDS - vDS 2]
1 D S
v L GS T DS DS 2[1 + (v -V
GS T )] L
2 1 + E L
c
where = 1/LEc with dimensions of V-1.
The saturation voltage has not changed so substituting for vDS by vGS-VT gives,
K W
iD = 2[1 + (v -V )] L [ vGS - V T ]2
GS T
Note that the transistor will enter the saturation region for vDS < vGS - VT in the presence of velocity
saturation.
The Influence of Velocity Saturation on the Transconductance Characteristics

The following plot was made for K = 110A/V2 and W/L = 1:
1000
=0
= 0.2
800
= 0.4
iD/W (A/m)
600
= 0.6
400
= 0.8
= 1.0
200
0
0.5 1 1.5 2 2.5 3
vGS (V) Fig1.8-12
Note as the velocity saturation effect becomes stronger, that the drain current-gate voltage relationship
becomes linear.
Circuit Model for Velocity Saturation

D
A simple circuit model to include the influence of velocity saturation is the
following: iD
G
+ +
vGS' -
vGS RSX
We know that Fig1.8-13 - S
KW
iD = 2L (v GS -V T )2 and v GS = v GS + iD RSX or v GS = v GS - iD R XS
Substituting vGS into the current relationship gives,

KW
iD = 2L (v GS - iD R SX -V T )2
Solving for iD results in,
K W
iD = (v GS - V T )2
W L
21 + K
L R SX (v GS -V T )
Comparing with the previous result, we see that
W L 1
= K L R SX R SX =
KW
= E KW
c
Therefore for K = 110A/V2, W = 1m and Ec = 1.5x106V/m, we get RXS = 6.06k.
Output Characteristics of Short-Channel MOSFETs

IBM, 1998, tox = 3.5nm
800
PFET NFET VGS=1.8V
700 Leff = Leff =
0.08m
Drain Current (A/m)

0.11m
600
VGS=1.4V
500
400 VGS=-1.8V
VGS=1.0V
300 VGS=-1.4V
200
VGS=-1.0V
100 VGS=0.6V
VGS=-0.6V
0
-1.8 -1.2 -0.6 0.0 0.6 1.2 1.8
Drain Voltage (V) Fig1.8-14
Su, L., et.al., A High Performance Sub-0.25m CMOS Technology with Multiple Thresholds and Copper Interconnects, 1998 Symposium on VLSI
Technology Digest of Technical Papers, pp. 18-19.
SUBTHRESHOLD MOSFET MODEL
zz

,,
y y
Weak inversion operation occurs when the applied gate voltage is below V T and pertains to when the
,,,
surface of the substrate beneath the gate is weakly inverted.
VGS
n+ n-channel n+
Diffusion Current
p-substrate/well
Regions of operation according to the surface potential, S.

S < F : Substrate not inverted
F < S < 2 F : Channel is weakly inverted (diffusion current)
2F < S : Strong inversion (drift current)
Drift current versus diffusion current in a MOSFET:
log iD
Diffusion Current
Drift Current
10-6
10-12 VGS
0 VT
Large-Signal Model for Subthreshold

Model:
W
iD = K x L evGS/nVt(1 - e-vDS/Vt)(1 + vDS)
where
Kx is dependent on process parameters and the bulk-source voltage
n 1.5 - 3
and
iD
kT VGS=VT
Vt = q 1A
If vDS > 0, then

W
iD = K x L evGS/nVt (1 + vDS)
VGS<VT
Small-signal model:
0 vDS
0 1V
iD qID Fig1.8-18
gm = v Q| = nkT
GS
iD ID
gds = v Q|
DS VA
SUBSTRATE CURRENT FLOW IN MOSFETS

Impact Ionization
Impact Ionization:
Occurs because high electric fields cause an impact which generates a hole-electron pair. The electrons
flow out the drain and the holes flow into the substrate causing a substrate current flow.
,,,
Illustration:
VG > VT
,,,,,,,,
B S VD > VDS(sat)
Polysilicon
Depletion
,,,,,,,,
Region
p+ n+ A
Free n+
,,,,,,,,
Fixed electron
Atom
p- substrate Free
hole
Fig1.8-16
Model of Substrate Current Flow

Substrate current:
iDB = K1(vDS - vDS(sat))iDe-[K2/(vDS-vDS(sat))]
where
K1 and K2 are process-dependent parameters (typical values are K1 = 5V-1 and K2 = 30V)
Schematic model:
D
iDB
G
B
S Fig1.8-17
Small-signal model:
iDB IDB
gdb = v = K 2 V
DB DS - V DS (sat)
This conductance will have a negative influence on high-output resistance current sinks/sources.
SUMMARY
Simple Large-Signal Model
Non-saturation-
WoCox vDS2
iD = (v - V T )v D S - 2 (1 + vDS )
L GS
Saturation-
W oC ox
2L (v GS - V T ) (1 + v DS )
iD = 2
Small-Signal Model
diD
| diD
| iD gm
gm dv = (V GS -V T ) = 2 ID g ds dv = iD g mbs =
GS Q DS Q 1 + v D S 2 2| F | - V B S
Capacitances
Capacitance
C4 Large
C2 + 2C5
CGS
C1+ 0.67C2
CGS, CGD
C1+ 0.5C2
vDS = constant
CGS, CGD CGD vBS = 0
C1, C3 C4 Small
2C5 CGB
0 vGS
Off Saturation Non-
Saturation
VT vDS +VT
Fig1.8-10

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MOS Models (5/23/00) Page 1

1.8 - MOSFET MODELS

MOS STRUCTURE AND OPERATION

Heavily Lightly Intrinsic Lightly Heavily Metal

Formation of the Channel for an Enhancement MOS Transistor

Strong Threshold (VG>VT)

p- substrate Inverted Region

The MOSFET Threshold Voltage

Signs for the Quantities in the Threshold Voltage Expression

Parameter N-Channel P-Channel

Example 1 - Calculation of the Threshold Voltage

Therefore, the potential MS is found to be

The fixed charge in the depletion region, Qb0, is given as

Substituting these values for VT0 gives

V T0 = - 0.940 + 0.754 + 0.501 - 9.3 x 10-3 = 0.306 V

SIMPLE LARGE SIGNAL MOSFET MODEL

4.) Integrating along the channel for 0 to L gives

Saturation Voltage - V D S(sat)

Active Region Saturation Region

Complete Large Signal Model

3.) Saturation Region

Influence of VD S on the Output Characteristics

Note that Leff = L - Xd

Influence of the Bulk Voltage on the Large Signal MOSFET Model

V SB1>0V: VSB1 Gate Drain

V SB2 > V SB1 : VSB2 Gate Drain

MOSFET Schematic Symbols

Summary of the Simple Large Signal MOSFET Model

Constant Symbol Constant Description Value Units

Parameter Parameter Typical Parameter Value

MOSFET SMALL SIGNAL MODEL

Simplified schematic model:

Extremely important assumption:

Illustration of the Small-Signal Model Application

Example 2 - Small-Signal Load Resistance

Small-Signal Model for the Active Region

MOSFET Capacitances consist of:

MOSFET Depletion Capacitors

Charge Storage (Parallel Plate) MOSFET Capacitances - C1 , C2 , C3 and C4

Mask L Oxide encroachment

Source-gate overlap Drain-gate overlap

Charge Storage (Parallel Plate) MOSFET Capacitances - C5

Type P-Channel N-Channel Units

Expressions for CGD, CG S and CG B

Saturation Region: Saturated

Illustration of CGD, CG S and CG B

Comments on the variation of CBG in the cutoff region:

Small-Signal Frequency Dependent Model

Summary of the MOSFET Large Signal Model

SHORT-CHANNEL MOSFET MODEL

Electron Drift Velocity (m/s)

Short-Channel Model Derivation

The result of this integration is,

The Influence of Velocity Saturation on the Transconductance Characteristics

Circuit Model for Velocity Saturation

We know that Fig1.8-13 - S

Substituting vGS into the current relationship gives,

Output Characteristics of Short-Channel MOSFETs

Drain Current (A/m)

SUBTHRESHOLD MOSFET MODEL

Regions of operation according to the surface potential, S.

Large-Signal Model for Subthreshold

If vDS > 0, then