8085 Microprocessor

Microprocessor
Microprocessor is defined as a silicon chip embedded with a Central Processing Unit or CPU. It is also
referred to as a computer's logic chip, micro chip, and processor.
Advantages of Microprocessors is that these are general purpose electronic processing devices which can be
programmed to execute a number of tasks. These are used in personal computers as well as a number of other
embedded products.
There are no disadvantages as such but when compared tofixed logic devices or certain ASICs (application
specific intergrated circuits), there is a need to program Microprocessors and write software/firmware when
used in embedded applications.

Function
The function of a Microprocessor is to conduct arithmetic and logic operations.

Speed
One advantage of a Microprocessor is its speed, which is measured in hertz. For instance, a Microprocessor
with 3 gigahertz, shortly GHz, is capable of performing 3 billion tasks per second.

Data Movement
Another advantage of a Microprocessor is that it can quickly move data between the various memory
locations.

Complex Mathematics
Microprocessors are used to perform complicated mathematical operations, like operating on the floating
point numbers.

Disadvantages
Some of the disadvantages with the Microprocessor are that it might get over-heated, and the limitation it
imposes on the size of data.

Applications of Microprocessors
Microprocessors are a mass storage device. They are the advanced form of computers. They arealso called as
microcomputers. The impact of microprocessor in different lures of fields is significant. The availability of
low cost, low power and small weight, computing capability makes it useful in different applications. Now a
days, a microprocessor based systems are used in instructions, automatic testing product, speed control of
motors, traffic light control , light control of furnaces etc. Some of the important areas are mentioned below:

Instrumentation:
it is very useful in the field of instrumentation. Frequency counters, function generators, frequency
synthesizers, spectrum analyses and many other instruments are available, when microprocessors are used as
controller. It is also used in medical instrumentation.

Control:
Microprocessor based controllers are available in home appliances, such as microwave oven, washing
machine etc., microprocessors are being used in controlling various parameters like speed, pressure,
temperature etc. These are used with the help of suitable transduction.

Communication:
Microprocessors are being used in a wide range of communication equipments. In telephone industry, these
are used in digital telephone sets. Telephone exchanges and modem etc. The use of microprocessor in

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8085 Microprocessor

television, satellite communication have made teleconferencing possible. Railway reservation and air
reservation system also uses this technology. LAN and WAN for communication of vertical information
through computer network.

Office Automation and Publication:

Microprocessor based micro computer with software packages has changed the office environment.
Microprocessors based systems are being used for word processing, spread sheet operations, storage etc. The
microprocessor has revolutionize the publication technology.

Consumer:
The use of microprocessor in toys, entertainment equipment and home applications is making them more
entertaining and full of features. The use of microprocessors is more widespread and popular.Now the
Microprocessors are used in :

1. Calculators
2. Accounting system
3. Games machine
4. Complex Industrial Controllers
5. Traffic light Control
6. Data acquisition systems
7. Multi user, multi- function environments
8. Military applications
9. Communication systems

Evolution of Microprocessor:

Microprocessors were categorized into five generations: first, second, third, fourth, and fifth generations.
Their characteristics are described below:

First-generation: The microprocessors that were introduced in 1971 to 1972 were referred to as the first
generation systems. First-generation microprocessors processed their instructions seriallythey fetched the
instruction, decoded it, then executed it. When an instruction was completed, the microprocessor updated the
instruction pointer and fetched the next instruction, performing this sequential drill for each instruction in
turn.

Second generation: By the late 1970s, enough transistors were available on the IC to usher in the second
generation of microprocessor sophistication: 16-bit arithmetic and pipelined instruction processing.
Motorolas MC68000 microprocessor, introduced in 1979, is an example. Another example is Intels 8080.
This generation is defined by overlapped fetch, decode, and execute steps (Computer 1996). As the first
instruction is processed in the execution unit, the second instruction is decoded and the third instruction is
fetched.
The distinction between the first and second generation devices was primarily the use of newer
semiconductor technology to fabricate the chips. This new technology resulted in a five-fold increase in
instruction, execution, speed, and higher chip densities.

Third generation: The third generation, introduced in 1978, was represented by Intels 8086 and the Zilog
Z8000, which were 16-bit processors with minicomputer-like performance. The third generation came about
as IC transistor counts approached 250,000.

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8085 Microprocessor

Motorolas MC68020, for example, incorporated an on-chip cache for the first time and the depth of the
pipeline increased to five or more stages. This generation of microprocessors was different from the previous
ones in that all major workstation manufacturers began developing their own RISC-based microprocessor
architectures (Computer, 1996).

Fourth generation: As the workstation companies converted from commercial microprocessors to in-house
designs, microprocessors entered their fourth generation with designs surpassing a million transistors.
Leading-edge microprocessors such as Intels 80960CA and Motorolas 88100 could issue and retire more
than one instruction per clock cycle.

Fifth generation: Microprocessors in their fifth generation, employed decoupled super scalar processing,
and their design soon surpassed 10 million transistors. In this generation, PCs are a low-margin, high-
volume-business dominated by a single microprocessor.

Classification of Microprocessor:

The microprocessor is identified with the word size of data. For E.g. The ALU can perform a 4- bit data
operation at a time these microprocessor is called as 4-bit microprocessor.

4-Bit Processors
INTEL 404 4040

8-Bit Processors
8008 8080 8085 MOTOROLA 6800 (M6800)

16-Bit Processors
8086 8088 Zilog Z800 80186 80286

32-Bit Processors
Intel 80386 80387 80486 PENTIUM PENTIUM PRO

Architechture of 8085

This is the functional block diagram of the 8085 Microprocessor.

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Acumulator
It is a 8-bit register which is used to perform airthmetical and logical operation. It stores the output of any
operation. It also works as registers for i/o accesses.
Temporary Register
It is a 8-bit register which is used to hold the data on which the acumulator is computing operation. It is also
called as operand register because it provides operands to ALU.
Registers
These are general purposes registers. Microprocessor consists 6 general purpose registers of 8-bit each
named as B,C,D,E,H and L. Generally theses registers are not used for storing the data permanently. It
carries the 8-bits data. These are used only during the execution of the instructions.
These registers can also be used to carry the 16 bits data by making the pair of 2 registers. The valid register
pairs available are BC,DE HL. We can not use other pairs except BC,DEand HL. These registers are
programmed by user.
ALU
ALU performs the airthmetic operations and logical operation.
Flag Registers
It consists of 5 flip flop which changes its status according to the result stored in an accumulator. It is also
known as status registers. It is connected to the ALU.

There are five flip-flops in the flag register are as follows:

1. Sign(S)
2. zero(z)
3. Auxiliary carry(AC)
4. Parity(P)
5. Carry(C)
The bit position of the flip flop in flag register is:

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D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
All of the three flip flop set and reset according to the stored result in the accumulator.
1.Sign-
If D7 of the result is 1 then sign flag is set otherwise reset. As we know that a number on the D7 always
desides the sign of the number. if D7 is 1: the number is negative. if D7 is 0: the number is positive.
2.Zeros(Z)-
If the result stored in an accumulator is zero then this flip flop is set otherwise it is reset.
3.Auxiliary carry(AC)-
If any carry goes from D3 to D4 in the output then it is set otherwise it is reset.
4.Parity(P)-
If the no of 1's is even in the output stored in the accumulator then it is set otherwise it is reset for the odd.
5.Carry(C)-
If the result stored in an accumulator generates a carry in its final output then it is set otherwise it is reset.
Instruction registers(IR)
It is a 8-bit register. When an instruction is fetched from memory then it is stored in this register.
Instruction Decoder(ID)
Instruction decoder identifies the instructions. It takes the informations from instruction register and decodes
the instruction to be performed.
Program Counter(PC)
It is a 16 bit register used as memory pointer. It stores the memory address of the next instruction to be
executed. So we can say that this register is used to sequencing the program. Generally the memory have 16
bit addresses so that it has 16 bit memory. The program counter is set to 0000H.
Stack Pointer(SP)
It is also a 16 bit register used as memory pointer. It points to the memory location called stack. Generally
stack is a reserved portion of memory where information can be stores or taken back together.
Timing and Control Unit
It provides timing and control signal to the microprocessor to perform the various operation.It has three
control signal. It controls all external and internal circuits. It operates with reference to clock signal.It
synchronizes all the data transfers.

There are three control signal:

1. ALE-Airthmetic Latch Enable, It provides control signal to synchronize the components of
microprocessor.
2. RD- This is active low used for reading operation.
3. WR-This is active low used for writing operation.
There are three status signal used in microprocessor S0, S1 and IO/M. It changes its status according the
provided input to these pins.
Serial Input Output Control-
There are two pins in this unit. This unit is used for serial data communication.
Interrupt Unit
There are 6 interrupt pins in this unit. Generally an external hardware is connected to these pins. These pins
provide interrupt signal sent by external hardware to microprocessor and microprocessor sends
acknowledgement for receiving the interrupt signal. Generally INTA is used for acknowledgement.
Register Section
Many registers has been used in microprocessor. PIPO shift register It consists of PIPO(Parallel Input
Parallel Output) register.

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Pin Diagram and Pin description of 8085

8085 is a 40 pin IC, The signals from the pins can be grouped as follows

1. Power supply and clock signals

2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports

1. Power supply and Clock frequency signals:

Vcc: + 5 volt power supply

Vss: Ground
X1, X2 : Crystal or R/C network or LC network connections to set the frequency of internal clock generator.
The frequency is internally divided by two. Since the basic operating timing frequency is 3 MHz, a 6 MHz
crystal is connected externally. CLK (output)-Clock Output is used as the system clock for peripheral and
devices interfaced with the microprocessor.

2. Address Bus:

A8 - A15: (output; 3-state)

It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address.

3. Data bus:

AD0 - AD7 (input/output; 3-state)

These multiplexed set of lines used to carry the lower order 8 bit address as well as data bus.
During the opcode fetch operation, in the first clock cycle, the lines deliver the lower order address
A0 - A7.
In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.
The CPU may read or write out data through these lines.

4. Control and Status signals:

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ALE (output) - Address Latch Enable.

It is an output signal used to give information of AD0-AD7 contents.
It is a positive going pulse generated when a new operation is started by uP.
When pulse goes high it indicates that AD0-AD7 are address.
When it is low it indicates that the contents are data.
RD (output 3-state, active low)
Read memory or IO device.
This indicates that the selected memory location or I/O device is to be read and that the data bus is
ready for accepting data from the memory or I/O device
WR (output 3-state, active low)

device.
IO/M (output) - Select memory or an IO device.
This status signal indicates that the read / write operation relates to whether the memory or I/O
device.
It goes high to indicate an I/O operation.
It goes low for memory operations.
5. Status Signals:
S1: S2:
It is used to know the type of current operation of the microprocessor.
IO/M S1 S0 OPERATION
0 1 1 Opcode fetch
0 1 0 Memory read
0 0 1 Memory write
1 1 0 I/O read
1 0 1 I/O write
1 1 0 Interrupt acknowledge
Z 0 1 Halt
Z x x Hold
Z x x Reset

6. Interrupts and Externally initiated operations:

They are the signals initiated by an external device to request the microprocessor to do a particular task or
work.
There are five hardware interrupts called, TRAP, RST 7.5, RST 6.5, RST 5.5, INTA
On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active low INTA
(Interrupt Acknowledge) signal.
Reset In (input, active low)
This signal is used to reset the microprocessor.
The program counter inside the microprocessor is set to zero.
The buses are tri-stated. Reset Out (Output)
It indicates CPU is being reset.
Used to reset all the connected devices when the microprocessor is reset.

7. Direct Memory Access (DMA): Tri state devices:

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When 2 or more devices are connected to a common bus, to prevent the devices from interfering with
each other, the tristate gates are used to disconnect all devices except the one that is communicating at
a given instant.
The CPU controls the data transfer operation between memory and I/O device. Direct Memory
Access operation is used for large volume data transfer between memory and an I/O device directly.
The CPU is disabled by tri-stating its buses and the transfer is effected directly by external control
circuits.
HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the
microprocessor acknowledges the request by sending out HLDA signal and leaves out the control of
the buses. After the HLDA signal the DMA controller starts the direct transfer of data.
READY (input)
Memory and I/O devices will have slower response compared to microprocessors.
Before completing the present job such a slow peripheral may not be able to handle further data or
control signal from CPU.
The processor sets the READY signal after completing the present job to access the data.
The microprocessor enters into WAIT state while the READY pin is disabled.

8. Single Bit Serial I/O ports:

SID (input) Serial input data line

SOD (output) Serial output data line
These signals are used for serial communication.

Addressing Modes in 8085

1. Immediate Addressing Mode

2. Register Addressing Mode
3. Direct Addressing Mode
4. Indirect Addressing Mode
5. Implied/implicit Addressing Mode

Immediate Addressing Mode:

An immediate is transferred directly to the register.

Eg: -
MVI A, 30H (30H is copied into the register A)
MVI B,40H(40H is copied into the register B).

Register Addressing Mode

Data is copied from one register to another register.

Eg: -
MOV B, A (the content of A is copied into the register B)
MOV A, C (the content of C is copied into the register A).

Direct Addressing Mode

Data is directly copied from the given address to the register.

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8085 Microprocessor

Eg: -
LDA 3000H (The content at the location 3000H is copied to the register A).

Indirect Addressing Mode

The data is transferred from the address pointed by the data in a register to other register.
Eg: - MOV A, M (data is transferred from the memory location pointed by the regiser to the accumulator).

Implied Addressing Mode

This mode doesn't require any operand. The data is specified by opcode itself.
Eg: -
RAL
CMP

Bus Structure in 8085

There are three buses in Microprocessor:
1. Address Bus
2. Data Bus
3. Control Bus

Address Bus
Genearlly, Microprocessor has 16 bit address bus. The bus over which the CPU sends out the address of the
memory location is known as Address bus. The address bus carries the address of memory location to be
written or to be read from.
The address bus is unidirectional. It means bits flowing occurs only in one direction, only from
microprocessor to peripheral devices. We can find that how much memory location it can using the formula
2^N. where N is the number of bits used for address lines.

Data Bus
8085 Microprocessor has 8 bit data bus. So it can be used to carry the 8 bit data starting from
00000000H(00H) to 11111111H(FFH). Here 'H' tells the Hexadecimal Number. It is bidirectional. These
lines are used for data flowing in both direction means data can be transferred or can be received through
these lines. The data bus also connects the I/O ports and CPU. The largest number that can appear on the data
bus is 11111111.
It has 8 parallel lines of data bus. So it can access upto 2^8 = 256 data bus lines.

Control Bus

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The control bus is used for sending control signals to the memory and I/O devices. The CPU sends control
signal on the control bus to enable the outputs of addressed memory devices or I/O port devices.
Some of the control bus signals are as follows:
1. Memory read
2. Memory write
3. I/O read
4. I/O write

Interrupts In 8085

what is Interrupt?
Interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution of processor
and get itself serviced. Generally, a particular task is assigned to that interrupt signal. In the microprocessor
based system the interrupts are used for data transfer between the peripheral devices and the microprocessor.

Interrupt Service Routine(ISR)

A small program or a routine that when executed services the corresponding interrupting source is called as
an ISR.

Maskable/Non-Maskable Interrupt
An interrupt that can be disabled by writing some instruction is known as Maskable Interrupt otherwise it is
called Non-Maskable Interrupt.

There are 6 pins available in 8085 for interrupt:

1. TRAP
2. RST 7.5
3. RST6.5
4. RST5.5
5. INTR
6. INTA

Execution of Interrupts
When there is an interrupt requests to the Microprocessor then after accepting the interrupts Microprocessor
send the INTA (active low) signal to the peripheral. The vectored address of particular interrupt is stored in
program counter. The processor executes an interrupt service routine (ISR) addressed in program counter.

There are two types of interrupts used in 8085 Microprocessor:

1. Hardware Interrupts
2. Software Interrupts

Software Interrupts
A software interrupts is a particular instructions that can be inserted into the desired location in the rpogram.
There are eight Software interrupts in 8085 Microprocessor. From RST0 to RST7.
1. RST0
2. RST1
3. RST2
4. RST3
5. RST4
6. RST5
7. RST6
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8085 Microprocessor

8. RST7

They allow the microprocessor to transfer program control from the main program to the subroutine
program. After completing the subroutine program, the program control returns back to the main program.
We can calculate the vector address of these interrupts using the formula given below:
Vector Address = Interrupt Number * 8

For Example:
RST2: vector address=2*8 = 16
RST1: vector address=1*8 = 08
RST3: vector address=3*8 = 24
Vector address table for the software interrupts:
Interrupt Vector Address
RST0 0000H
RST1 0008H
RST2 0010H
RST3 0018H
RST4 0020H
RST5 0028H
RST6 0030H
RST7 0038H
Hardware Interrupt
As i have already discussed that there are 6 interrupt pins in the microprocessor used as Hardware Interrrupts
given below:
1. TRAP
2. RST7.5
3. RST6.5
4. RST5.5
5. INTR

Note:

INTA is not an interrupt. INTA is used by the Microprocessor for sending the acknowledgement. TRAP has
highest priority and RST7.5 has second highest priority and so on.
The Vector address of these interrupts are given below:

Interrupt Vector Address

RST7.5 003CH
RST6.5 0034H
RST5.5 002CH
TRAP 0024H

TRAP
It is non maskable edge and level triggered interrupt. TRAP has the highest priority and vectores interrupt.
Edge and level triggered means that the TRAP must go high and remain high until it is acknowledged. In
case of sudden power failure, it executes a ISR and send the data from main memory to backup memory.

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As we know that TRAP can not be masked but it can be delayed using HOLD signal. This interrupt transfers
the microprocessor's control to location 0024H.
TRAP interrupts can only be masked by reseting the microprocessor. There is no other way to mask it.

RST7.5
It has the second highest priority. It is maskable and edge level triggered interrupt. The vector address of this
interrupt is 003CH. Edge sensitive means input goes high and no need to maintain high state until it is
recognized.
It can also be reset or masked by reseting microprocessor. It can also be resetted by DI instruction.

RST6.5 and RST5.5

These are level triggered and maskable interrupts. When RST6.5 pin is at logic 1, INTE flip-flop is set. RST
6.5 has third highest priority and RST 5.5 has fourth highest priority.
It can be masked by giving DI and SIM instructions or by reseting microprocessor.

INTR
It is level triggered and maskable interrupt. The following sequence of events occurs when INTR signal goes
high:

1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends active low interrupt
acknowledge signal, if the interrupt is enabled.
3. On receiving the instruction, the 8085 save the address of next instruction on stack and execute
received instruction.
It has the lowest priority. It can be disabled by reseting the microprocessor or by DI and SIM instruction.

Instruction Set 8085

1. Control
2. Logical
3. Branching
4. Arithmetic
5. Data Transfer

Control Instructions

Explanation of
Opcode Operand Description
Instruction
No operation is performed. The instruction is fetched and decoded. However
NOP none No operation
no operation is executed. Example: NOP
The CPU finishes executing the current instruction and halts any further
Halt and enter
HLT none execution. An interrupt or reset is necessary to exit from the halt state.
wait state
Example: HLT
Disable The interrupt enable flip-flop is reset and all the interrupts except the TRAP
DI none interrupts are disabled. No flags are affected. Example: DI
The interrupt enable flip-flop is set and all interrupts are enabled. No flags are
affected. After a system reset or the acknowledgement of an interrupt, the
EI none Enable interrupts
interrupt enable flipflop is reset, thus disabling the interrupts. This instruction
is necessary to reenable the interrupts (except TRAP). Example: EI

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This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5,
Read interrupt
RIM none 5.5 and read serial data input bit. The instruction loads eight bits in the
mas
accumulator with the following interpretations. Example: RIM
This is a multipurpose instruction and used to implement the 8085 interrupts
Set interrupt
SIM none 7.5, 6.5, 5.5, and serial data output. The instruction interprets the accumulator
mask
contents as follows. Example: SIM

LOGICAL INSTRUCTIONS

Explanation of
Opcode Operand Description
Instruction
The contents of the operand (register or memory) are M compared with the
contents of the accumulator. Both contents are preserved . The result of the
comparison is shown by setting the flags of the PSW as follows:
R Compare register or
CMP memory with if (A) < (reg/mem): carry flag is set
M accumulator if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset

Example: CMP B or CMP M

The second byte (8-bit data) is compared with the contents of the
accumulator. The values being compared remain unchanged. The result of
the comparison is shown by setting the flags of the PSW as follows:
Compare immediate
CPI 8-bit data with accumulator
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
Example: CPI 89H
The contents of the accumulator are logically ANDed with M the contents
R Logical AND of the operand (register or memory), and the result is placed in the
ANA register or memory accumulator. If the operand is a memory location, its address is specified
M with accumulator by the contents of HL registers. S, Z, P are modified to reflect the result of
the operation. CY is reset. AC is set. Example: ANA B or ANA M
The contents of the accumulator are logically ANDed with the
Logical AND
8-bit 8-bit data (operand) and the result is placed in the
ANI immediate with
data accumulator. S, Z, P are modified to reflect the result of the
accumulator
operation. CY is reset. AC is set. Example: ANI 86H
The contents of the accumulator are Exclusive ORed with M the contents
R Exclusive OR of the operand (register or memory), and the result is placed in the
XRA register or memory accumulator. If the operand is a memory location, its address is specified
M with accumulator by the contents of HL registers. S, Z, P are modified to reflect the result of
the operation. CY and AC are reset. Example: XRA B or XRA M
The contents of the accumulator are Exclusive ORed with the 8-bit data
Exclusive OR
8-bit (operand) and the result is placed in the accumulator. S, Z, P are modified
XRI immediate with
data to reflect the result of the operation. CY and AC are reset.
accumulator
Example: XRI 86H
R Logical OR register The contents of the accumulator are logically ORed with M the contents of
ORA or memory with the operand (register or memory), and the result is placed in the
M accumulator accumulator. If the operand is a memory location, its address is specified

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by the contents of HL registers. S, Z, P are modified to reflect the result of

the operation. CY and AC are reset. Example: ORA B or ORA M
The contents of the accumulator are logically ORed with the 8-bit data
Logical OR
8-bit (operand) and the result is placed in the accumulator. S, Z, P are modified
ORI immediate with
data to reflect the result of the operation. CY and AC are reset.
accumulator
Example: ORI 86H
Each binary bit of the accumulator is rotated left by one position. Bit D7 is
Rotate accumulator
RLC none placed in the position of D0 as well as in the Carry flag. CY is modified
left
according to bit D7. S, Z, P, AC are not affected. Example: RLC
Each binary bit of the accumulator is rotated right by one position. Bit D0
Rotate accumulator
RRC none is placed in the position of D7 as well as in the Carry flag. CY is modified
right
according to bit D0. S, Z, P, AC are not affected. Example: RRC
Each binary bit of the accumulator is rotated left by one position through
Rotate accumulator the Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is
RAL none left through carry placed in the least significant position D0. CY is modified according to bit
D7. S, Z, P, AC are not affected. Example: RAL
Each binary bit of the accumulator is rotated right by one position through
Rotate accumulator the Carry flag. Bit D0 is placed in the Carry flag, and the Carry flag is
RAR none right through carry placed in the most significant position D7. CY is modified according to bit
D0. S, Z, P, AC are not affected. Example: RAR
Complement The contents of the accumulator are complemented. No flags are affected.
CMA none accumulator Example: CMA
The Carry flag is complemented. No other flags are affected.
CMC none Complement carry
Example: CMC
STC none Set Carry Set Carry Example: STC

BRANCHING INSTRUCTIONS

Explanation of
Opcode Operand Description
Instruction
The program sequence is transferred to the
16-bit Jump memory location specified by the 16-bit
JMP
address unconditionally address given in the operand.
Example: JMP 2034H or JMP XYZ
Flag
Opcode Description
Status
JC Jump on Carry CY = 1
JNC Jump on no Carry CY = 0 The program sequence is transferred to the
JP Jump on positive S = 0 memory location specified by the 16-bit
16-bit Jump address given in the operand based on the
JM Jump on minus S=1 address conditionally specified flag of the PSW as described below.
JZ Jump on zero Z= 1
JNZ Jump on no zero Z= 0 Example: JZ 2034H or JZ XYZ
Jump on parity
JPE P=1
even
JPO Jump on parity P = 0

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odd

Flag
Opcode Description
Status
CC Call on Carry CY = 1
The program sequence is transferred to the
CNC Call on no Carry CY = 0 memory location specified by the 16-bit
CP Call on positive S=0 address given in the operand. Before the
16-bit Unconditional transfer, the address of the next instruction
CM Call on minus S=1 subroutine call after CALL (the contents of the program
address
CZ Call on zero Z= 1 counter) is pushed onto the stack.
CNZ Call on no zero Z= 0
Example: CALL 2034H or CALL XYZ
Call on parity
CPE P=1
even
CPO Call on parity odd P = 0
The program sequence is transferred from the
Return from subroutine to the calling program. The two
RET none subroutine bytes from the top of the stack are copied into
unconditionally the program counter,and program execution
begins at the new address. Example: RET
Flag
Opcode Description
Status
RC Return on Carry CY = 1
Return on no
RNC CY = 0 The program sequence is transferred from the
Carry
subroutine to the calling program based on
RP Return on positive S = 0 Return from the specified flag of the PSW as described
RM Return on minus S=1 none subroutine below. The two bytes from the top of the
RZ Return on zero Z= 1 conditionally stack are copied into the program counter,
and program execution begins at the new
RNZ Return on no zero Z = 0 address. Example: RZ
Return on parity
RPE P=1
even
Return on parity
RPO P=0
odd
The contents of registers H and L are copied
Load program into the program counter. The contents of H
PCHL none counter with HL are placed as the high-order byte and the
contents contents of L as the low-order byte. Example:
PCHL
The RST instruction is equivalent to a 1-byte
call instruction to one of eight memory
locations depending upon the number. The
RST instructions are generally used in conjunction
0-7 Restart with interrupts and inserted using external
hardware. However these can be used as
software instructions in a program to transfer
program execution to one of the eight
locations. The addresses are:

Prof. K. Adisesha 15
8085 Microprocessor

Restart
Instruction
Address
RST 0 0000H
RST1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H

The 8085 has four additional interrupts and

these interrupts generate RST instructions
internally and thus do not require any external
hardware. These instructions and their Restart
addresses are:
Restart
Interrupt
Address
TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

Arithmetic Instructions

Explanation of
Opcode Operand Description
Instruction
The contents of the operand (register or memory) are added to the
R Add register or contents of the accumulator and the result is stored in the accumulator. If
ADD memory, to the operand is a memory location, its location is specified by the
M accumulator contents of the HL registers. All flags are modified to reflect the result
of the addition. Example: ADD B or ADD M
The contents of the operand (register or memory) and M the Carry flag
R Add register to are added to the contents of the accumulator and the result is stored in
ADC accumulator with the accumulator. If the operand is a memory location, its location is
M carry specified by the contents of the HL registers. All flags are modified to
reflect the result of the addition. Example: ADC B or ADC M
The 8-bit data (operand) is added to the contents of the accumulator and
Add immediate to
ADI 8-bit data the result is stored in the accumulator. All flags are modified to reflect
accumulator
the result of the addition. Example: ADI 45H
The 8-bit data (operand) and the Carry flag are added to the contents of
Add immediate to the accumulator and the result is stored in the accumulator. All flags are
ACI 8-bit data accumulator with modified to reflect the result of the addition.
carry
Example: ACI 45H
Reg. pair, Load register pair The instruction loads 16-bit data in the register pair designated in the
LXI
16-bit data immediate operand. Example: LXI H, 2034H or LXI H, XYZ

Prof. K. Adisesha 16
8085 Microprocessor

The 16-bit contents of the specified register pair are added to the
contents of the HL register and the sum is stored in the HL register. The
Add register pair to
DAD Reg. pair contents of the source register pair are not altered. If the result is larger
H and L registers
than 16 bits, the CY flag is set. No other flags are affected. Example:
DAD H
The contents of the operand (register or memory ) are subtracted from
R Subtract register or the contents of the accumulator, and the result is stored in the
SUB memory from accumulator. If the operand is a memory location, its location is
M accumulator specified by the contents of the HL registers. All flags are modified to
reflect the result of the subtraction. Example: SUB B or SUB M
The contents of the operand (register or memory ) and M the Borrow
flag are subtracted from the contents of the accumulator and the result is
R Subtract source and
placed in the accumulator. If the operand is a memory location, its
SBB borrow from
location is specified by the contents of the HL registers. All flags are
M accumulator
modified to reflect the result of the subtraction. Example: SBB B or
SBB M
The 8-bit data (operand) is subtracted from the contents of the
Subtract immediate
SUI 8-bit data accumulator and the result is stored in the accumulator. All flags are
from accumulator
modified to reflect the result of the subtraction. Example: SUI 45H
Subtract immediate The contents of register H are exchanged with the contents of register D,
SBI 8-bit data from accumulator and the contents of register L are exchanged with the contents of register
with borrow E. Example: XCHG
The contents of the designated register or memory) are incremented by 1
R
Increment register and the result is stored in the same place. If the operand is a memory
INR or memory by 1 location, its location is specified by the contents of the HL registers.
M Example: INR B or INR M
Increment register The contents of the designated register pair are incremented by 1 and the
INX R pair by 1 result is stored in the same place. Example: INX H
The contents of the designated register or memory are M decremented
R
Decrement register by 1 and the result is stored in the same place. If the operand is a
DCR or memory by 1 memory location, its location is specified by the contents of the HL
M registers. Example: DCR B or DCR M
Decrement register The contents of the designated register pair are decremented by 1 and
DCX R pair by 1 the result is stored in the same place. Example: DCX H
The contents of the accumulator are changed from a binary value to two
4-bit binary coded decimal (BCD) digits. This is the only instruction that
uses the auxiliary flag to perform the binary to BCD conversion, and the
conversion procedure is described below. S, Z, AC, P, CY flags are
altered to reflect the results of the operation.
Decimal adjust
DAA none accumulator If the value of the low-order 4-bits in the accumulator is greater than 9
or if AC flag is set, the instruction adds 6 to the low-order four bits.

If the value of the high-order 4-bits in the accumulator is greater than 9

or if the Carry flag is set, the instruction adds 6 to the high-order four
bits. Example: DAA

Data Transfer Instructions

Prof. K. Adisesha 17
8085 Microprocessor

Explanation of
Opcode Operand Description
Instruction
Rd, Rs This instruction copies the contents of the source register into the
destination register; the contents of the source register are not altered.
Copy from source(Rs)
MOV M, Rs If one of the operands is a memory location, its location is specified by
to destination(Rd)
the contents of the HL registers. Example:
Rd, M MOV B, C or MOV B, M
Rd, data The 8-bit data is stored in the destination register or memory. If the
MVI Move immediate 8-bit operand is a memory location, its location is specified by the contents
M, data of the HL registers. Example: MVI B, 57H or MVI M, 57H
The contents of a memory location, specified by a 16-bit address in the
16-bit
LDA Load accumulator operand, are copied to the accumulator. The contents of the source are
address not altered. Example: LDA 2034H
The contents of the designated register pair point to a memory location.
B/D Reg. Load accumulator This instruction copies the contents of that memory location into the
LDAX
pair indirect accumulator. The contents of either the register pair or the memory
location are not altered. Example: LDAX B
Reg. pair, Load register pair The instruction loads 16-bit data in the register pair designated in the
LXI
16-bit data immediate operand. Example: LXI H, 2034H or LXI H, XYZ
The instruction copies the contents of the memory location pointed out
16-bit Load H and L by the 16-bit address into register L and copies the contents of the next
LHLD
address registers direct memory location into register H. The contents of source memory
locations are not altered. Example: LHLD 2040H
The contents of the accumulator are copied into the memory location
16-bit specified by the operand. This is a 3-byte instruction, the second byte
STA 16-bit address
address specifies the low-order address and the third byte specifies the high-
order address. Example: STA 4350H
The contents of the accumulator are copied into the memory location
Store accumulator
STAX Reg. pair specified by the contents of the operand (register pair). The contents of
indirect
the accumulator are not altered. Example: STAX B
The contents of register L are stored into the memory location specified
by the 16-bit address in the operand and the contents of H register are
16-bit Store H and L stored into the next memory location by incrementing the operand. The
SHLD registers direct contents of registers HL are not altered. This is a 3-byte instruction, the
address
second byte specifies the low-order address and the third byte specifies
the high-order address. Example: SHLD 2470H
The contents of register H are exchanged with the contents of register
Exchange H and L
XCHG none D, and the contents of register L are exchanged with the contents of
with D and E
register E. Example: XCHG
The instruction loads the contents of the H and L registers into
Copy H and L the stack pointer register, the contents of the H register provide the
SPHL none registers to the stack high-order address and the contents of the L register provide the low-
pointer order address. The contents of the H
and L registers are not altered. Example: SPHL
The contents of the L register are exchanged with the stack location
pointed out by the contents of the stack pointer register. The contents
Exchange H and L
XTHL none of the H register are exchanged with the next stack location (SP+1);
with top of stack
however, the contents of the stack pointer register are not altered.
Example: XTHL

Prof. K. Adisesha 18
8085 Microprocessor

The contents of the register pair designated in the operand are copied
onto the stack in the following sequence. The stack pointer register is
Push register pair decremented and the contents of the highorder register (B, D, H, A) are
PUSH Reg. pair onto stack copied into that location. The stack pointer register is decremented
again and the contents of the low-order register (C, E, L, flags) are
copied to that location. Example: PUSH B or PUSH A
The contents of the memory location pointed out by the stack pointer
register are copied to the low-order register (C, E, L, status flags) of the
Pop off stack to operand. The stack pointer is incremented by 1 and the contents of that
POP Reg. pair register pair memory location are copied to the high-order register (B, D, H, A) of
the operand. The stack pointer register is again incremented by 1.
Example: POP H or POP A
Output data from
8-bit port The contents of the accumulator are copied into the I/O port specified
OUT accumulator to a port
address by the operand. Example: OUT F8H
with 8-bit address
Input data to
8-bit port accumulator from a The contents of the input port designated in the operand are read and
IN port with 8-bit loaded into the accumulator. Example: IN 8CH
address
address

Introduction of 8237

Direct Memory Access (DMA) is a method of allowing data to be moved from one location to
another in a computer without intervention from the central processor (CPU).
It is also a fast way of transferring data within (and sometimes between) computer.
The DMA I/O technique provides direct access to the memory while the microprocessor is
temporarily disabled.
The DMA controller temporarily borrows the address bus, data bus and control bus from the
microprocessor and transfers the data directly from the external devices to a series of memory
locations (and vice versa).

Basic DMA Operation:

Two control signals are used to request and acknowledge a direct memory access (DMA) transfer in
the microprocessor-based system.
1. The HOLD signal as an input(to the processor) is used to request a DMA action.
2. The HLDA signal as an output that acknowledges the DMA action.
When the processor recognizes the hold, it stops its execution and enters hold cycles.
HOLD input has higher priority than INTR or NMI.
The only microprocessor pin that has a higher priority than a HOLD is the RESET pin.
HLDA becomes active to indicate that the processor has placed its buses at high-impedance state.

Basic DMA Definitions

Direct memory accesses normally occur between an I/O device and memory without the use of the
microprocessor.
1. A DMA read transfers data from the memory
to the I/O device.
2. A DMA write transfers data from an I/O device
to memory.
Prof. K. Adisesha 19
8085 Microprocessor

The system contains separate memory and I/O control signals.

Hence the Memory & the I/O are controlled simultaneously
The DMA controller provides memory with its address, and the controller signal selects the I/O
device during the transfer.
Data transfer speed is determined by speed of the memory device or a DMA controller.
In many cases, the DMA controller slows the speed of the system when transfers occur.
The serial PCI (Peripheral Component Interface) Express bus transfers data at rates exceeding DMA
transfers.
This in modern systems has made DMA is less important.

CPU having the control over the bus When DMA operates

The 8237 DMA Controller

The 8237 supplies memory & I/O with control signals and memory address information during the
DMA transfer.
It is actually a special-purpose microprocessor whose job is high-speed data transfer between memory
and I/O
8237 is not a discrete component in modern microprocessor-based systems.
It appears within many system controller chip sets
8237 is a four-channel device compatible with 8086/8088, adequate for small systems.
Expandable to any number of DMA channel inputs
8237 is capable of DMA transfers at rates up to 1.6MB per second.
Each channel is capable of addressing a full 64K-byte section of memory.

Block Diagram of 8237

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8085 Microprocessor

8237 Internal Registers

CAR
The current address register holds a 16-bit memory address used for the DMA transfer.
each channel has its own current address
register for this purpose.
When a byte of data is transferred during a DMA operation, CAR is either incremented
or decremented. depending on how it is programmed

CWCR
The current word count register programs a channel for the number of bytes to transferred during a
DMA action.

CR
The command register programs the operation of the 8237 DMA controller.
The register uses bit position 0 to select the memory-to-memory DMA transfer mode.
1. Memory-to-memory DMA transfers use DMA channel
2. DMA channel 0 to hold the source address
3. DMA channel 1 holds the destination address

Prof. K. Adisesha 21
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BA and BWC
The base address (BA) and base word count (BWC) registers are used when auto-initialization is
selected for a channel.
In auto-initialization mode, these registers are used to reload the CAR and CWCR after the DMA
action is completed.

MR
The mode register programs the mode of operation for a channel.
Each channel has its own mode register as selected by bit positions 1 and 0.
1. Remaining bits of the mode register select operation, auto-initialization, increment/decrement,
and mode for the channel

BR
The bus request register is used to request a DMA transfer via software.
1. very useful in memory-to-memory transfers, where an external signal is not available to begin
the DMA transfer

MRSR
The mask register set/reset sets or clears the channel mask.
1. if the mask is set, the channel is disabled
2. the RESET signal sets all channel masks to disable them

Prof. K. Adisesha 22
8085 Microprocessor

MSR

The mask register clears or sets all of the masks with one command instead of individual channels, as
with the MRSR.

SR

The status register shows status of each DMA channel. The TC bits indicate if the channel has
reached its terminal count (transferred all its bytes).
When the terminal count is reached, the DMA transfer is terminated for most modes
of operation.
The request bits indicate whether the DREQ input for a given channel is active.

8237 Software Commands

Prof. K. Adisesha 23
8085 Microprocessor

Master clear
Acts exactly the same as the RESET signal to the 8237. As with the RESET signal, this command
disables all channels

Clear mask register

Enables all four DMA channels.

Clear the first/last flip-flop

Clears the first/last (F/L) flip-flop within 8237. The F/L flip-flop selects which byte (low or high
order) is read/written in the current address and current count registers. if F/L = 0, the low-order byte
is selected if F/L = 1, the high-order byte is selected Any read or write to the address or count register
automatically toggles the F/L flip-flop.

Pin Diagram and Pin description of 8237

VCC

POWER: a5V supply.

VSS

GROUND: Ground.

CLK Input

CLOCK INPUT:Clock Input controls the internal operations of the 8237A and its rate of data transfers. The
input may be driven at up to 5 MHz for the 8237A-5.

CS Input

CHIP SELECT:Chip Select is an active low input used to select the 8237A as an I/O device during the Idle
cycle. This allows CPU communication on the data bus.

Prof. K. Adisesha 24
8085 Microprocessor

RESET Input

RESET: Reset is an active high input which clears the Command, Status, Request and Temporary registers. It
also clears the first/ last flip/flop and sets the Mask register. Following a Reset the device is in the Idle cycle.

READY Input

READY: Ready is an input used to extend the memory read and write pulses from the 8237A to
accommodate slow memories or I/O peripheral devices. Ready must not make transitions during its specified
setup/hold time.

HLDA Input

HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has
relinquished control of the system busses.

DREQ0 DREQ3 Input

DMA REQUEST: The DMA Request lines are individual asynchronous channel request inputs used by
peripheral circuits to obtain DMA service. In fixed Priority, DREQ0 has the highest priority and DREQ3 has
the lowest priority. A request is generated by activating the DREQ line of a channel. DACK will
acknowledge the recognition of DREQ signal. Polarity of DREQ is programmable. Reset initializes these
lines to active high. DREQ must be maintained until the corresponding DACK goes active.

DB0 DB7

DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus. The
outputs are enabled in the Program condition during the I/O Read to output the contents of an Address
register, a Status register, the Temporary register or a Word Count register to the CPU. The outputs are
disabled and the inputs are read during an I/O Write cycle when the CPU is programming the 8237A control
registers. During DMA cycles the most significant 8 bits of the address are output onto the data bus to be
strobed into an external latch by ADSTB. In memory-to-memory operations, data from the memory comes
into the 8237A on the data bus during the read-from-memory transfer. In the write-to-memory transfer, the
data bus outputs place the data into the new memory location.

IOR Input/Output

I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input control
signal used by the CPU to read the control registers. In the Active cycle, it is an output control signal used by
the 8237A to access data from a peripheral during a DMA Write transfer.

IOW Input/Output

I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input control
signal used by the CPU to load information into the 8237A. In the Active cycle, it is an output control signal
used by the 8237A to load data to the peripheral during a DMA Read transfer.

EOP Input/Output

Prof. K. Adisesha 25
8085 Microprocessor

END OF PROCESS: End of Process is an active low bidirectional signal. Information concerning the
completion of DMA services is available at the bidirectional EOP pin. The 8237A allows an external signal
to terminate an active DMA service. This is accomplished by pulling the EOP input low with an external
EOP signal. The 8237A also generates a pulse when the terminal count (TC) for any channel is reached. This
generates an EOP signal which is output through the EOP line. The reception of EOP, either internal or
external, will cause the 8237A to terminate the service, reset the request, and, if Autoinitialize is enabled, to
write the base registers to the current registers of that channel. The mask bit and TC bit in the status word
will be set for the currently active channel by EOP unless the channel is programmed for Autoinitialize. In
that case, the mask bit remains unchanged. During memory-to-memory transfers, EOP will be output when
the TC for channel 1 occurs. EOP should be tied high with a pull-up resistor if it is not used to prevent
erroneous end of process inputs.

A0 A3 Input/Output

ADDRESS: The four least significant address lines are bidirectional three-state signals. In the Idle cycle they
are inputs and are used by the CPU to address the register to be loaded or read. In the Active cycle they are
outputs and provide the lower 4 bits of the output address.

A4 A7 Output

ADDRESS: The four most significant address lines are three-state outputs and provide 4 bits of address.
These lines are enabled only during the DMA service.

HRQ Output

HOLD REQUEST: This is the Hold Request to the CPU and is used to request control of the system bus. If
the corresponding mask bit is clear, the presence of any valid DREQ causes 8237A to issue the HRQ.

DACK0 DACK3 Output

DMA ACKNOWLEDGE: DMA Acknowledge is used to notify the individual peripherals when one has
been granted a DMA cycle. The sense of these lines is programmable. Reset initializes them to active low.

AEN Output

ADDRESS ENABLE:Address Enable enables the 8-bit latch containing the upper 8 address bits onto the
system address bus. AEN can also be used to disable other system bus drivers during DMA transfers. AEN is
active HIGH.

ADSTB Output

ADDRESS STROBE: The active high, Address Strobe is used to strobe the upper address byte into an
external latch.

MEMR Output

MEMORY READ: The Memory Read signal is an active low three-state output used to access data from the
selected memory location during a DMA Read or a memory-to-memory transfer.

MEMW Output

Prof. K. Adisesha 26
8085 Microprocessor

MEMORY WRITE: The Memory Write is an active low three-state output used to write data to the selected
memory location during a DMA Write or a memory-to-memory transfer.

PIN5 Input

PIN5: This pin should always be at a logic HIGH level. An internal pull-up resistor will establish a logic high
when the pin is left floating. It is recommended however, that PIN5 be connected to VCC

Prof. K. Adisesha 27
8085 Microprocessor

8085 Microprocessor AL Programs

Store 8-bit data in memory

1. Program 1:
2. MVI A, 52H : "Store 32H in the accumulator"
3. STA 4000H : "Copy accumulator contents at address 4000H"
4. HLT : "Terminate program execution"

1. Program 2:
2. LXI H : "Load HL with 4000H"
3. MVI M : "Store 32H in memory location pointed by HL register pair (4000H)"
4. HLT : "Terminate program execution"

Note: The result of both programs will be the same. In program 1 direct addressing instruction is used,
whereas in program 2 indirect addressing instruction is used.

Exchange the contents of memory locations

Statement: Exchange the contents of memory locations 2000H and 4000H.

1. Program 1:
2. LDA 2000H : "Get the contents of memory location 2000H into accumulator"
3. MOV B, A : "Save the contents into B register"
4. LDA 4000H : "Get the contents of memory location 4000Hinto accumulator"
5. STA 2000H : "Store the contents of accumulator at address 2000H"
6. MOV A, B : "Get the saved contents back into A register"
7. STA 4000H : "Store the contents of accumulator at address 4000H"

1. Program 2:
2. LXI H 2000H : "Initialize HL register pair as a pointer to memory location 2000H."
3. LXI D 4000H : "Initialize DE register pair as a pointer to memory location 4000H."
4. MOV B, M : "Get the contents of memory location 2000H into B register."
5. LDAX D : "Get the contents of memory location 4000H into A register."
6. MOV M, A : "Store the contents of A register into memory location 2000H."
7. MOV A, B : "Copy the contents of B register into accumulator."
8. STAX D : "Store the contents of A register into memory location 4000H."
9. HLT : "Terminate program execution."

Note: In Program 1, direct addressing instructions are used, whereas in Program 2, indirect addressing
instructions are used.

Add two 8-bit numbers

Statement: Add the contents of memory locations 4000H and 4001H and place the result in memory location
4002H.

1. Sample problem
2. (4000H) = 14H

Prof. K. Adisesha 28
8085 Microprocessor

3. (4001H) = 89H
4. Result = 14H + 89H = 9DH
5. Source program
6. LXI H 4000H : "HL points 4000H"
7. MOV A, M : "Get first operand"
8. INX H : "HL points 4001H"
9. ADD M : "Add second operand"
10. INX H : "HL points 4002H"
11. MOV M, A : "Store result at 4002H"
12. HLT : "Terminate program execution"

Subtract two 8-bit numbers

Statement: Subtract the contents of memory location 4001H from the memory location 2000H and place the
result in memory location 4002H.

1. Program : Subtract two 8-bit numbers

2. Sample problem:
3. (4000H) = 51H
4. (4001H) = 19H
5. Result = 51H 19H = 38H

Source program:

LXI H, 4000H : "HL points 4000H"

MOV A, M : "Get first operand"
INX H : "HL points 4001H"
SUB M : "Subtract second operand"
INX H : "HL points 4002H"
MOV M, A : "Store result at 4002H"
HLT : "Terminate program execution"

Add two 16-bit numbers

Statement: Add the 16-bit number in memory locations 4000H and 4001H to the 16-bit number in memory
locations 4002H and 4003H. The most significant eight bits of the two numbers to be added are in memory
locations 4001H and 4003H. Store the result in memory locations 4004H and 4005H with the most
significant byte in memory location 4005H.
Sample problem:
(4000H) = 15H
(4001H) = 1CH
(4002H) = B7H
(4003H) = 5AH
Result = 1C15 + 5AB7H = 76CCH
(4004H) = CCH
(4005H) = 76H

Source Program 1:
LHLD 4000H : "Get first I6-bit number in HL"
XCHG : "Save first I6-bit number in DE"
Prof. K. Adisesha 29
8085 Microprocessor

LHLD 4002H : "Get second I6-bit number in HL"

MOV A, E : "Get lower byte of the first number"
ADD L : "Add lower byte of the second number"
MOV L, A : "Store result in L register"
MOV A, D : "Get higher byte of the first number"
ADC H : "Add higher byte of the second number with CARRY"
MOV H, A : "Store result in H register"
SHLD 4004H : "Store I6-bit result in memory locations 4004H and 4005H"
HLT : "Terminate program execution"

Source program 2:
LHLD 4000H : Get first I6-bit number
XCHG : Save first I6-bit number in DE
LHLD 4002H : Get second I6-bit number in HL
DAD D : Add DE and HL
SHLD 4004H : Store I6-bit result in memory locations 4004H and 4005H.
HLT : Terminate program execution

NOTE: In program 1, eight bit addition instructions are used (ADD and ADC) and addition is performed in
two steps. First lower byte addition using ADD instruction and then higher byte addition using ADC
instruction.In program 2, 16-bit addition instruction (DAD) is used.

Add contents of two memory locations

Statement: Add the contents of memory locations 40001H and 4001H and place the result in the memory
locations 4002Hand 4003H.
Sample problem:
(4000H) = 7FH
(400lH) = 89H
Result = 7FH + 89H = lO8H
(4002H) = 08H
(4003H) = 0lH

Source program:
LXI H, 4000H : "HL Points 4000H"
MOV A, M : "Get first operand"
INX H : "HL Points 4001H"
ADD M : "Add second operand"
INX H : "HL Points 4002H"
MOV M, A : "Store the lower byte of result at 4002H"
MVIA, 00 : "Initialize higher byte result with 00H"
ADC A : "Add carry in the high byte result"
INX H : "HL Points 4003H"
MOV M, A : "Store the higher byte of result at 4003H"
HLT : "Terminate program execution"

Subtract two 16-bit numbers

Prof. K. Adisesha 30
8085 Microprocessor

Statement: Subtract the 16-bit number in memory locations 4002H and 4003H from the 16-bit number in
memory locations 4000H and 4001H. The most significant eight bits of the two numbers are in memory
locations 4001H and 4003H. Store the result in memory locations 4004H and 4005H with the most
significant byte in memory location 4005H.
Sample problem:
(4000H) = 19H
(400IH) = 6AH
(4004H) = I5H (4003H) = 5CH
Result = 6A19H 5C15H = OE04H
(4004H) = 04H
(4005H) = OEH
Source program:
LHLD 4000H : "Get first 16-bit number in HL"
XCHG : "Save first 16-bit number in DE"
LHLD 4002H : "Get second 16-bit number in HL"
MOV A, E : "Get lower byte of the first number"
SUB L : "Subtract lower byte of the second number"
MOV L, A : "Store the result in L register"
MOV A, D : "Get higher byte of the first number"
SBB H : "Subtract higher byte of second number with borrow"
MOV H, A : "Store l6-bit result in memory locations 4004H and 4005H"
SHLD 4004H : "Store l6-bit result in memory locations 4004H and 4005H"
HLT : "Terminate program execution"

Finding ones complement of a number

Statement: Find the ls complement of the number stored at memory location 4400H and store the
complemented number at memory location 4300H.
Sample problem:
(4400H) = 55H
Result = (4300B) = AAB
Source program:
LDA 4400B : "Get the number"
CMA : "Complement number"
STA 4300H : "Store the result"
HLT : "Terminate program execution"

Finding Twos complement of a number

Statement: Find the 2s complement of the number stored at memory location 4200H and store the
complemented number at memory location 4300H
Sample problem:
(4200H) = 55H
Result = (4300H) = AAH + 1 = ABH
Source program:
LDA 4200H : "Get the number"
CMA : "Complement the number"
ADI, 01 H : "Add one in the number"
STA 4300H : "Store the result"
HLT : "Terminate program execution"
Prof. K. Adisesha 31
8085 Microprocessor

Pack the unpacked BCD numbers

Statement: Pack the two unpacked BCD numbers stored in memory locations 4200H and 4201H and store
result in memory location 4300H. Assume the least significant digit is stored at 4200H.
Sample problem:
(4200H) = 04
(4201H) = 09
Result = (4300H) = 94
Source program:
LDA 4201H : "Get the Most significant BCD digit"
RLC
RLC
RLC
RLC : "Adjust the position of the second digit (09 is changed to 90)"
ANI FOH : "Make least significant BCD digit zero"
MOV C, A : "store the partial result"
LDA 4200H : "Get the lower BCD digit"
ADD C : "Add lower BCD digit"
STA 4300H : "Store the result"
HLT : "Terminate program execution"

Unpack a BCD number

Statement: Two digit BCD number is stored in memory location 4200H. Unpack the BCD number and store
the two digits in memory locations 4300H and 4301H such that memory location 4300H will have lower
BCD digit.
Sample problem:
(4200H) = 58
Result = (4300H) = 08 and
(4301H) = 05
Source program:
LDA 4200H : "Get the packed BCD number"
ANI FOH : "Mask lower nibble"
RRC
RRC
RRC
RRC : "Adjust higher BCD digit as a lower digit"
STA 4301H : "Store the partial result"
LDA 4200H : "Get the original BCD number"
ANI OFH : "Mask higher nibble"
STA 4201H : "Store the result"
HLT : "Terminate program execution"

Execution format of instructions

Statement: Read the program given below and state the contents of all registers after the execution of each
instruction in sequence.
Main program:
4000H LXI SP, 27FFH
4003H LXI H, 2000H
Prof. K. Adisesha 32
8085 Microprocessor

4006H LXI B, 1020H

4009H CALL SUB
400CH HLT
Subroutine program:
4100H SUB: PUSH B
4101H PUSH H
4102H LXI B, 4080H
4105H LXI H, 4090H
4108H SHLD 2200H
4109H DAD B
410CH POP H

1. 410DH POP B
2. 410EH RET

Right shift, bit of data( 8 bit and 16 bit)

Statement: Write a program to shift an eight bit data four bits right. Assume data is in register C.
Sample problem:
(4200H) = 58
Result = (4300H) = 08 and
(4301H) = 05

Source program 1:
MOV A, C
RAR
RAR
RAR
RAR
MOV C, A
HLT
Statement: Write a program to shift a 16 bit data, 1 bit right. Assume that data is in BC register pair.
Source program 2
MOV A, B
RAR
MOV B, A
MOV A, C
RAR
MOV C, A
HLT

Left Shifting of a 16-bit data

Statement: Program to shift a 16-bit data 1 bit left. Assume data is in the HL register
HL = 1025 = 0001 0000 0010 0101

HL = 0001 0000 0010 0101

+ HL = 0001 0000 0010 0101
----------------------------
Result = 0010 0000 0100 1010
Prof. K. Adisesha 33
8085 Microprocessor

Alter the contents of flag register in 8085

Statement: Write a set of instructions to alter the contents of flag register in 8085.
PUSH PSW : "Save flags on stack"
POP H : "Retrieve flags in L"
MOV A, L : "Flags in accumulator"
CMA : "Complement accumulator"
MOV L, A : "Accumulator in L"
PUSH H : "Save on stack"
POP PSW : "Back to flag register"
HLT : "Terminate program execution"

Count number of ones in a number

Statement: Write a program to count number of ls in the contents of D register and store the count in the B
register.
Sample problem
(2200H) = 04
(2201H) = 34H
(2202H) = A9H
(2203H) = 78H
(2204H) = 56H
Result = (2202H) = A9H
MVI B, 00H
MVI C, 08H
MOV A, D
BACK: RAR
JNC SKIP
INR B
SKIP: DCR C
JNZ BACK
HLT

Arrange in ascending order

Statement: Write a program to sort given 10 numbers from memory location 2200H in the ascending order.
MVI B, 09 :"Initialize counter"
START :"LXI H, 2200H: Initialize memory pointer"
MVI C, 09H :"Initialize counter 2"
BACK: MOV A, M :"Get the number"
INX H :"Increment memory pointer"
CMP M :"Compare number with next number"
JC SKIP :"If less, dont interchange"
JZ SKIP :"If equal, dont interchange"
MOV D, M
MOV M, A
DCX H
MOV M, D
INX H :"Interchange two numbers"
SKIP:DCR C :"Decrement counter 2"
Prof. K. Adisesha 34
8085 Microprocessor

JNZ BACK :"If not zero, repeat"

DCR B :"Decrement counter 1"
JNZ START
HLT :"Terminate program execution"

Calculate the sum of series of even numbers

Statement: Calculate the sum of series of even numbers from the list of numbers. The length of the list is in
memory location 2200H and the series itself begins from memory location 2201H. Assume the sum to be 8
bit number so you can ignore carries and store the sum at memory location 2210H.
Sample problem
2200H= 4H
2201H= 20H
2202H= l5H
2203H= l3H
2204H= 22H
Result 22l0H= 20 + 22 = 42H
= 42H
LDA 2200H
MOV C, A :"Initialize counter"
MVI B, 00H :"sum = 0"
LXI H, 2201H :"Initialize pointer"
BACK: MOV A, M :"Get the number"
ANI 0lH :"Mask Bit l to Bit7"
JNZ SKIP :"Dont add if number is ODD"
MOV A, B :"Get the sum"
ADD M :"SUM = SUM + data"
MOV B, A :"Store result in B register"
SKIP: INX H :"increment pointer"
DCR C :"Decrement counter"
JNZ BACK :"if counter 0 repeat"
STA 2210H :"store sum"
HLT :"Terminate program execution"

Calculate the sum of series of odd numbers

Statement: Calculate the sum of series of odd numbers from the list of numbers. The length of the list is in
memory location 2200H and the series itself begins from memory location 2201H. Assume the sum to be 16-
bit. Store the sum at memory locations 2300H and 2301H.
Sample problem
2200H = 4H
2201H= 9AH
2202H= 52H
2203H= 89H
2204H= 3FH
Result = 89H + 3FH = C8H
2300H= H Lower byte
2301H = H Higher byte
Source program :
LDA 2200H
Prof. K. Adisesha 35
8085 Microprocessor

MOV C, A :"Initialize counter"

LXI H, 2201H :"Initialize pointer"
MVI E, 00 :"Sum low = 0"
MOV D, E :"Sum high = 0"
BACK: MOV A, M :"Get the number"
ANI 0lH :"Mask Bit 1 to Bit7"
JZ SKIP :"Dont add if number is even"
MOV A, E :"Get the lower byte of sum"
ADD M :"Sum = sum + data"
MOV E, A :"Store result in E register"
JNC SKIP
INR D :"Add carry to MSB of SUM"
SKIP: INX H :"Increment pointer"

Find the square of given number

Statement: Find the square of the given numbers from memory location 6100H and store the result from
memory location 7000H.
Sample problem
2200H = 4H
2201H= 9AH
2202H= 52H
2203H= 89H
2204H= 3FH
Result = 89H + 3FH = C8H
2300H= H Lower byte
2301H = H Higher byte
LXI H, 6200H :"Initialize lookup table pointer"
LXI D, 6100H :"Initialize source memory pointer"
LXI B, 7000H :"Initialize destination memory pointer"
BACK: LDAX D :"Get the number"
MOV L, A :"A point to the square"
MOV A, M :"Get the square"
STAX B :"Store the result at destination memory location"
INX D :"Increment source memory pointer"
INX B :"Increment destination memory pointer"
MOV A, C
CPI 05H :"Check for last number"
JNZ BACK :"If not repeat"
HLT :"Terminate program execution"

Search a byte in a given number

Statement: Search the given byte in the list of 50 numbers stored in the consecutive memory locations and
store the address of memory location in the memory locations 2200H and 2201H. Assume byte is in the C
register and starting address of the list is 2000H. If byte is not found store 00 at 2200H and 2201H.
LX I H, 2000H :"Initialize memory pointer 52H"
MVI B, 52H :"Initialize counter"
BACK: MOV A, M :"Get the number"
CMP C :"Compare with the given byte"
Prof. K. Adisesha 36
8085 Microprocessor

JZ LAST :"Go last if match occurs"

INX H :"Increment memory pointer"
DCR B :"Decrement counter"
JNZ B :"If not zero, repeat"
LXI H, 0000H
SHLD 2200H
JMP END :"Store 00 at 2200H and 2201H"
LAST: SHLD 2200H :"Store memory address"
END: HLT :"Stop"

Add two decimal numbers of 6 digit each

Statement: Two decimal numbers six digits each, are stored in BCD package form. Each number occupies a
sequence of byte in the memory. The starting address of first number is 6000H Write an assembly language
program that adds these two numbers and stores the sum in the same format starting from memory location
6200H.
LXI H, 6000H :"Initialize pointer l to first number"
LXI D, 6l00H :"Initialize pointer2 to second number"
LXI B, 6200H :"Initialize pointer3 to result"
STC
CMC :"Carry = 0"
BACK: LDAX D :"Get the digit"
ADD M :"Add two digits"
DAA :"Adjust for decimal"
STAX.B :"Store the result"
INX H :"Increment pointer 1"
INX D :"Increment pointer2"
INX B :"Increment result pointer"
MOV A, L
CPI 06H :"Check for last digit"
JNZ BACK :"If not last digit repeat"
HLT :"Terminate program execution"

Separate even numbers from given numbers

Statement: Write an assembly language program to separate even numbers from the given list of 50 numbers
and store them in the another list starting from 2300H. Assume starting address of 50 number list is 2200H.
LXI H, 2200H :"Initialize memory pointer l"
LXI D, 2300H :"Initialize memory pointer2"
MVI C, 32H :"Initialize counter"
BACK:MOV A, M :"Get the number"
ANI 0lH :"Check for even number"
JNZ SKIP :"If ODD, dont store"
MOV A, M :"Get the number"
STAX D :"Store the number in result list"
INX D :"Increment pointer 2"
SKIP: INX H :"Increment pointer l"
DCR C :"Decrement counter"
JNZ BACK :"If not zero, repeat"
Prof. K. Adisesha 37
8085 Microprocessor

HLT :"Stop

Transfer contents to overlapping memory blocks

Statement: Write assembly language program with proper comments for the following:
A block of data consisting of 256 bytes is stored in memory starting at 3000H. This block is to be shifted
(relocated) in memory from 3050H onwards. Do not shift the block or part of the block anywhere else in the
memory.
Two blocks (3000 30FF and 3050 314F) are overlapping. Therefore it is necessary to transfer last byte
first and first byte last.
MVI C, FFH :"Initialize counter"
LX I H, 30FFH :"Initialize source memory pointer 3l4FH"
LXI D, 314FH :"Initialize destination memory pointer"
BACK: MOV A, M :"Get byte from source memory block"
STAX D :"Store byte in the destination memory block"
DCX H :"Decrement source memory pointer"
DCX :"Decrement destination memory pointer"
DCR C :"Decrement counter"
JNZ BACK :"If counter 0 repeat"
HLT :"Stop execution"

Prof. K. Adisesha 38