Achieving Determinism in

SystemVerilog 3.1 Scheduling

Semantics
Phil Moorby, Arturo Salz, Peter Flake
Surrendra Dudani, Tom Fitzpatrick
Synopsys, Inc.

DVCon 2003
 Motivation
Enable SystemVerilog 3.1 charter
Increase the verification capabilities of Verilog
One language for design, testbench and assertions

Reduce the need to use PLI to get verification

environment to work
Predictable semantics across all tools
Simulation
Synthesis
Formal verification

No performance degradation
Backwards compatible with Verilog IEEE 1364-2001
Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (2)
 Can IEEE 1364-2001 do the job?

Problems
Verilog zero-delay simulation races
Lack of predictability
Lack of consistency across design and verification tools
Different semantics between event-driven and cycle-accurate

Proposed solution
Extend the scheduling semantics of the Verilog 2K1 standard
Apply partial ordering of design, testbench and assertion-
based code using 3 new event scheduling regions

Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (3)

 Proposed new scheduling algorithm
Why?
Simulation races between design, testbench and assertion-
based event executions are hard to avoid
Users resort to the PLI for synchronizing and de-racing the
interactions
Synchronize at beginning of time slot to sample data
Synchronize at beginning of time slot react and drive new
stimulus

Proposed solution uses three new event regions

Preponed
Observe
Reactive

Allows non-zero delay models to work with cycle-

accurate models
Enables significant performance improvements
Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (4)
 Verilog standard flow of event regions
within a time slot
PLI
from previous
pre-active
time slot pre-NBA

active

post-NBA
inactive
iterative
regions

NBA

Read-only
to next
time slot

Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (5)

 2-stage shift register

drive here
sample here
FF1 b FF2 c
a

clk
clock trigger

Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (6)

 sample here drive here
FF1 b FF2 c
a

clock trigger
clk

dffGate FF1(b, a, clk);

dffGate FF2(c, b, clk);

Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (7)

 sample here drive here
FF1 b FF2 c
a

clock trigger
clk

active

dffUdp FF1(b, a, clk); clk

dffUdp FF2(c, b, clk);
inactive

b c

read-only

Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (8)

 sample here drive here
FF1 b FF2 c
a

clock trigger
clk

active
dffUdp FF1(b, a, clk);
clk
dffUdp FF2(c, b, gclk2);
and G1(gclk2, clk, w1);
inactive

gclk2 b

read-only

Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (9)

 sample here drive here
FF1 b FF2 c
a

clock trigger
clk

always @(posedge clk) begin active

c = b; // FF2
b = a; // FF1
end inactive

always @(posedge clk)

b = a; // FF1 read-only
always @(posedge clk)
c = b; // FF2

Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (10)

 sample here drive here
FF1 b FF2 c
a

clock trigger
clk

assign #0
#1 c = cTemp; active
always @(posedge clk) cTemp = b;
assign #0
#1 b = bTemp;
always @(posedge clk) bTemp = a; inactive

read-only

Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (11)

 sample here drive here
FF1 b FF2 c
a

clock trigger
clk
active

always @(posedge clk) c <= b; inactive

always @(posedge gclk2) b <=
clk) b <= a; a;
and G1(gclk2, clk, w1);
NBA

read-only

Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (12)

 Continuous invariant assertions
on non-overlapping clocks
non-overlapping clocks active
clk2 = clk; clk2
clk1
inactive

clk2 clk1 <= clk;

what order? NBA

clk1
assert ((clk1 && clk2) == 0);
observe
must read
and evaluate
here

read-only

Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (13)

 010 010 drive here
FF1 b FF2 c sample here
a
preponed

clock trigger sample

clk here
active
assign #0 gclk = clk;
always @(posedge gclk) b = a; // FF1
inactive
always @(posedge clk) c = b; // FF2
evaluate
sequence @(posedge clk) sa = (!a ; a ; !a); here NBA
sequence @(posedge clk) sc = (!c ; c ; !c);

property p = (sa => [2] sc); // clocked assertion observe

reactive
assert (p) pass_statement; react
else; fail_statement; here

postponed

Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (14)

 Conclusions preponed

SystemVerilog 3.1 charter brings together design, active

testbench, and assertion-based code into one

language
inactive

Need for consistent semantics and results across

design and verification tools, from simulation to NBA
formal verification

observe
A new event scheduling algorithm has been proposed
that enables design and verification code to
consistently work together without the need to resort reactive
to PLI synchronization

postponed

Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics, DVCon 2003 (15)