ADVANCED ESD PROTECTION

June 8, 2010
Prof. Albert Wang
Dept. of Electrical Engineering
University of California

417 EBU2, Riverside, CA 92521 Email: aw@ee.ucr.edu

Tel: (951) 827-2555 http://www.ee.ucr.edu/~aw
Fax: (951) 827-2425 Lab: http://lics.ee.ucr.edu

Copyright2009byAlbertWang,AllRightsReserved
 Outlines

YOU ARE ENJOYING EDS-MEMBER BENEFITS!

Basics on ESD Protection

Mixed-Mode ESD Simulation-Design Method

On Chip ESD Protection Design Examples

On-Chip

Summary
y

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 1

 WHY JOIN?

Technical events like this MQ!

Global-Networking at home!

Stay in
St i touch
t h with
ith state-of-the-art
t t f th t globally,
l b ll
Discounts for IEEE conferences and journals, etc.
Chapter & local activities,
activities
Awards & Recognitions, (Early Career Award, etc.)
PhD/MS Student Fellowship Awards,

All for $12/$6 EDS Membership Fee!

How to join? Ask Prof. J. Burghartz!

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 2
 A Multi
Multi-Billion-$
Billion $ Problem!
ESD = Electrostatic Discharge
Phenomena: huge I/V-pulses
IC damages!

A multi-billion-$ problem
ESD failures 30%-50% IC failures
A killing factor to time-to-market
Informal ESD Failure Statistics
Assembly
.. Good
on-chip ESD protection required! tri ca. 14%
Elec 4%Ion 3
%
Fab Unknown
26% 15%

ESD/EOS
Ref: L. Brown, et al, Electronic Packaging & Production, April 1990.
37%
R Merril
R. Merril, et al
al, EOS/ESD
EOS/ESD, 1993
1993.

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 3

 Old Devil
D il Re-Appears
R A

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 4

 ESD Protection Mechanisms
VDD

ND
ND
PD
Simple turn-on I-V,

PD
SD
Snapback I-V. IN
OUT
Protect EVERY I/O pad on chip!

DS

PS
NS
PS
NS
2nd Breakdown
I I
(Vt2, It2)
VSS
(ESD protection region)
Low-R dischargeg
(ESD protection region)
Low-R discharge

Turn on Holding
(Vt1, It1, t1) (Vh, Ih) Triggering
T i i
(Vt1, It1, t1)

ESD-critical parameters are the KEY to ESD circuit design protection!

V V

Ref.: A. Wang, On-Chip ESD Protection for Integrated Circuits, Kluwer, ISBN: 0-7923-7647-1, 2002.
Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 5
 ESD Protection: Simple or Complex?!
VDD VDD

VSS

R2
Q1 ND VSS
IDz I/O PD
DZ
VSS

Q2 Rext

NS
VSS PS VSS
Ref: J. Chen, et al, IEEE IEDM Digest, 1995, pp. 337-340; Ker, et al, US Patent 5,572,394, 1996.
Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 6
Moores
Moore s Law ~ ESD Protection in CMOS

7
Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 7
 ESD Challenges for sub
sub-90nm
90nm CMOS
Reverse trend
R d ffor <90nm
90 CMOS?

Narrower ESD design window? ESD Design Window
10% 10~
I 20%
Failure
(Vt2, It2)

VSafe

BV
VDDmax
Discharging

VDD
(RON)

Holding
(Vh, Ih) Triggering
(Vt1, It1, t1)

IDD
V

Ref.: L. Lin & A. Wang, et al, Proc. EOS/ESD Symp, pp.28-37, 2009.
Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 8
 E
Emerging
i Challenges
Ch ll in
i ESD Design
D i

Design prediction by simulation

D i optimization
Design ti i ti by
b simulation
i l ti

3D ESD protection device modeling

Whole-chip ESD design theory and methodology

CAD algorithm & tools for ESD synthesis and verification

ESD protection circuitry for RF/AMS ICs

RF-ESD co-design
g method

ESD protection for nano technologies

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 9

 Mixed Mode ESD Simulation-Design
Mixed-Mode Simulation Design

2D/3D Mixed-Mode ESD Simulation-Design Methodology:

Electro-thermal-process-device-circuit-layout coupling
Static-transient ESD simulation

ESD design optimization,

optimization no trial
trial-and-error!
and error!
no over/under-design!
Forward ESD design, not backward analysis!
Compact ESD protection designs
Minimize ESD-induced parasitic effects
Explore
E l novell ESD structures
t t

Ref:
e A. Wang,
a g, e
et a
al,, IEEE Trans
a s Elec.
ec Devs.,
e s , v52,
5 , n7,, p
p1304,
30 , 2005.
005
H. Feng, et al, IEEE JSSC, v38, n6, p995, 2003.
H. Xie, MS Thesis, IIT, 2004.
Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 10
 Mixed Mode ESD Design: Example 1
Mixed-Mode
Chip-level
Chi l l ESD circuit
i i design
d i
No-assumptions

Cs

VHBM Rd Core
Ls ESD
ESD source
CC circuit IC
Circuit Chip
(e.g., HBM model) Ct

ESD sub-circuit
to be simulated

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 11

 Example-1: ggNMOS ~ gcNMOS ESD
4
1.4

1.2
3
C u rre n t (A m p )

2 0.8

I( A )
0.6
1
04
0.4

0.2
0
0.E+00 2.E-07 4.E-07 6.E-07 8.E-07 1.E-06 1.E-06 0
Time (Second) 0 5 10 15 20
20 V(v)

15 B S Hot Spot D
G
V (V )

10

0
1.E-12 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05
t(s)

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 12

 Example-1: ggNMOS ~ gcNMOS ESD
1.5 4
3.5
3
1 2.5
Id (A )

V g (V )
1.5
0.5
1
05
0.5
0
0
1.E-14
-0.5 20 1.E-12 1.E-10 1.E-08 1.E-06
0 5 10 15
Vd(V)
( ) log(t) (s)

20 2500

2000
15
To reduce triggering Vt1 by design
1500

T m a x (K )
V d (V )

10
1000

5
500

0 0
1.E-12 1.E-10 1.E-08 1.E-06 1.E-04 1.E-02 1.E-12 1.E-10 1.E-08 1.E-06
log(t) (s) log(t) (s)

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 13

 Example 2: ESD + RF
1300

tmaxM1
tmaxM2
1100
tmaxESD

900

Tmax (K)
RF output buffer block,
700
Differential buffer with open collector
collector,
5kV SCR ESD protection 500

300
0.E+00 2.E-07 4.E-07 6.E-07 8.E-07 1.E-06 1.E-06
Time (s)
Out1
Out2
3.0
In1 I-M1

I-ESD
In2
Currrent (A)

2.0
ES

ES
SCR

SCR
SD-

SD-

bias
1.0

0.0
Ref: H. Feng, et al, IEEE JSSC, V38, N6, p995, 2003.0.E+00 2.E-07 4.E-07 6.E-07 8.E-07 1.E-06
Time (s)
Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 14
 RF ESD Protection Design

Whats Unique for RF ESD protection?!

RF IC is extremely sensitive to ESD-induced parasitics
Need accurate RF ESD characterization
Low-parasitic compact RF ESD protection design
Whole-chip ESD protection circuit design concept

New & Critical: ESD-Circuit Interactions

ESD
ESD-to-Circuit
to Circuit Influences
Circuit-to-ESD Influences
RF+ESD co-design
g

Ref: A. Wang, et al, invited, IEEE Proc. CICC, 2002, pp411-418.

A. Wang, et al, invited, Proc. IEEE RFIC 2008.

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 15

 ESD Parasitics: CESD

Circuit performance may be affected by ESD circuitry:

ESD-induced parasitic CESD (up to ~pF) & RESD,
CESD RESD delay signal integrity, clock corruption,
CESD loading
l di effect,
ff t Z-matching,
Z t hi power efficiency,
ffi i BW,
BW
CESD, RESD ~ frequency, biasing, temperature,

Unique Challenge:
Accurate CESD estimation,
Including CESD in RF IC design,
Reduce CESD over fRF

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 16

 ESD Parasitics: Noises
Substrate noise coupling effect due to CESD:
Incident noises at I/O coupled into substrate,
Substrate noises I/O signal path

ESD self-generated noises:

I/O
Thermal noises,
Flicker noises, CESD
Shot noises, etc.

Unique Challenge:
ESD noises into RF ICs.

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 17

 Mixed-Signal ESD Protection

No global ESD solutions!

No one Vt1 f
fits the whole chip!
p
Multi-VDD/VSS locally-optimized Vt1 for different I/Os,
Need a safety margin for Vt1:
Vt1 of 5V fits VDD=3.3V blocks,
Vt1 of 23V good for VDD=15V blocks.

Challenge 4: multi-Vt1 ESD design in RF/AMS ICs

whole-chip ESD design optimization,
on-chip local ESD design optimization

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 18

Example-3: ESD-Protected RF IC Design

ESD affects
ff RF IC substantially:
b i ll
5GHz LNA for dual-band WLAN transceiver
CE-CB cascode topology
High/low gain switching
Unique double shutdown function
0.18m SiGe BiCMOS
2KV ESD protection

GSG RF
GSG RFIN

FOUT
ESD
ESD

Ref.: G. Chen, et al, Proc. IEEE EMC, 2005.

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 19
 Example 3: LNA Noise ~ ESD
Example-3:
LNA
S21(dB) S11(dB) NF(dB)
circuits
w/o ESD 18.11 -8.3 2.99
NF
with ESD 15.08 -7.2 3.19
5
Degradation 16.73% 17.25% 6.8%
4.5

3.5

3
LNA w/ ESD
FLNA 1
NF (dB)

2.5 LNA w/o ESD

NF: ESD device FTotal FESD
2
GESD
15
1.5

0.5
NFESD 0.1 dB
0
4.5 5 5.5 6 6.5 7
Frequency (GHz)

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 20

 Example-4: RF ESD Characterization

Most commonly ESD protection structures

ggMOS
SCR
dSCR
Diode string: Dx1, Dx2, Dx3, Dx4, Dx5, Dxn

Designed and fabricated in 0.35m BiCMOS

2kV/5kV ESD protection

Design optimization by mixed-mode

mixed mode ESD simulation

Simulation matches measurement very well

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 21

 Example 4: 2kV CESD by SIM & Test
Example-4:
1

Simulation
0.8 SCR
ggNMOS
Dx1
0.6 Dx2
CESD (pF)

dSCR

0.4 0.8 SCR

ggNMOS
0.2 Dx1
0.6 Dx2
Dx3
0 Dx4
F)

Dx5
ESD(p

0 2 4 6 8 10
0.4 f (GHz) dSCR
C

0.2 M
Measurement
t

0
0 2 4 6 8 10
f (GHz)
Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 22
 Example-4: 2kV CESD by Test
01
0.1 SCR
Dx1
Dx2
0 08
0.08 Dx3
Dx4
Dx5
0 06
0.06
CESD (pF))

dSCR

0 04
0.04

0 02
0.02

0
0 2 4 f (GHz) 6 8 10
Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 23
 Example-4:
p 2kV CESD ~ Size
2kV Layout Size Comparison

2500

2000
Layout Size (um2)

1500

1000

500
2kV CESD Comparison at 2
2.4GHz
4GHz
0
Dx1 Dx2 Dx3 Dx4
0.45 Dx5 ggNMOS SCR dSCR
ESD Structures
0.4
0.35
0.3
CEESD (pF)

0.25
02
0.2
0.15

0.1
0.05
0
Dx1 Dx2 Dx3 Dx4 Dx5 ggNMOS SCR dSCR
ESD Structures
Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 24
FoM for Overall ESD Design Evaluation
Each parameter has different/conflicting meaning,
Optimization by overall ESD design performance,
Need a new FoM parameter: F-factor
F factor
kV
F
Size( m 2 ) C ESD ( pF ) NF ( dB ) 2kV F-Factor Comparison (Measured)

200

150
ctor
F-fac

100

50

0
Dx1 Dx2 Dx3 Dx4 Dx5 ggNMOS SCR dSCR
ESD Structures
Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 25
 Novell ESD
E Protection Design Helps
l
VDD VDD

VDD
ND/PD
ND/PD
PD ND PD
ND
DS/SD
SD DS
IN NS/PS
DS
OUT
PS NS NS/PS
PS
NS

VSS
VSS VSS

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 26

 Example-6: All-Mode SCR ESD Protection
A C C A
(ND) K K (PD)
0 4 3 0
P+ N- P+ 2 1 P+ N- P+
Q6 Q5
PW Rw P-well PW Rw P-well
3 2

Q41 N-Epi Q41

N-Epi
4 3

A
0

K A K A K
(PS) 1 2 (NS)
1 0 0 2
P+ N- P+ P+ N- P+
Q2 Q3
PW Rw P-well Rw
PW P-well

N-Epi Q1 Q1
N-Epi
Ref: A. Wang, et al, IEEE Electron Device Letters, Vol. 22, No. 10, pp.493-495, Oct. 2001.
A. Wang, US Patent # 6,635,931 B1, 2003.
Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 27
 Example 7: Low-Parasitic
Example-7: Low Parasitic Poly-Si
Poly Si SCR ESD
Cathode Anode

Polysilicon S

N+ P+ N+ P+
N5 P4 I3 N2 P1
Not to Scale)

R2
Q1
(N

Q2 R1
Field Oxide

P-Substrate

Xie, et al, A New Low-Parasitic Polysilicon SCR ESD Protection Structure for RF ICs, IEEE Electron Device
Letters, Vol. 26, No.2, pp.121-123, February 2005

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 28

 E
Example-7:
l E
Excellent
ll Prediction
d
3

0.35m
0 35m SiGe BiCMOS
BiCMOS.
3.2kV HBM ESD protection level 2.5 Simulation
using a small 750m2 poly-Si SCR
TLP Testing
a high F-factor of 42 2
the lowest reported CESD of ~92.3fF.
92.3fF.

A)
I (Anode) (A
Ajustable Vt1.
1.5

4 1

3.5
0.5
3
A)
I (Anode) (A

25
2.5 0
2 0 5 10 15 20 25
Poly Diode V (Anode) (V)
1.5 Poly SCR_1
1 Poly SCR_2
SCR 2
Poly SCR_3
0.5 Poly SCR_4

0
0 5 10 15 20 25 30 35 40
V (Anode) (V)

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 29

 Summary

ESD failure is a killing factor to ICs,

O hi ESD protection
On-chip t ti required
i d for
f ICs,
IC
RF/AMS ESD design is very challenging,
ESD design prediction by mixed-mode simulation

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 30

 REFERENCES
L. Lin, A. Wang, et al, Whole-Chip ESD Protection Design Verification by CAD, Proc. EOS/ESD Symp, pp.28-37, 2009
X. Guan, et al, ESD-RFIC Co-Design Methodology, Invited, Proc. IEEE RFIC, pp467-470, 2008.
A. Wang, et al, A Review on RF ESD Protection Design, IEEE Trans. Electron Devices, V2, N7, p.1304, July 2005.
H. Xie, et al, A New Low-Parasitic Polysilicon SCR ESD Protection Structure for RF ICs, IEEE Electron Device Letters,
V26 N2
V26, N2, p.121,
p 121 February 2005
2005.
R. Zhan, et al, ESDInspector: A New Layout-level ESD Protection Circuitry Design Verification Tool Using A Smart-
Parametric Checking Mechanism, IEEE Trans on CAD of Integrated Circuits and Systems, V23, N10, p.1421, Oct. 2004.
G. Chen, et al, Characterizing Diodes For RF ESD Protection, IEEE Electron Device Letters, V25, N5, p.323, May 2004.
A. Wang, On-Chip ESD Protection For Integrated Circuits, Kluwer Academic Publishers, Boston, ISBN: 0-7923-7647-1,
2002.
2002
A. Wang, et al, ESD Protection Design for RF Integrated Circuits: New Challenges, Invited, IEEE CICC, p.411, 2002.
A. Wang, A Study of Parasitic Effects of ESD Protection on RF ICs, IEEE Trans. Microwave Theory & Tech., V50, N1,
p.393, Jan. 2002.
H. Feng, et al, A Mixed-Mode ESD Protection Circuit Simulation-Design Methodology , IEEE J. Solid-State Circuits, V38,
No. 6, p.995, June 2003.
R. Zhan, et al ESDExtractor: A New Technology-Independent CAD Tool For Arbitrary ESD Protection Device Extraction,
IEEE Trans on CAD of Integrated Circuits and Systems, V22, N10, p.1362, October 2003.
A. Wang, et al, " An on-Chip ESD Protection Circuit with Low Trigger-Voltage in BiCMOS Technology", IEEE J. Solid-State
Circuits, V36, N1, p.40, January 2001.
A. Wang,g, et al,, "On a Dual-Direction on-Chip
p Electrostatic Discharge
g Protection Structure,, IEEE Trans. Elec. Devices,,
V48, N5, p.978, May 2001.
R. Zhan, ESDcat: a New CAD Package for Full-Chip ESD Protection Design Verification, PhD Dissertation, IIT, 2005.
X. Xie, 3D Mixed-Mode Simulation-Design Methodology and Electro-Thermal Modeling for ESD Protection Circuits, MS
Thesis, IIT, 2004.
G. Chen, Design g and Characterization of ESD Protection for RFICs, MS Thesis, IIT, 2003.
H. Feng, A Mixed-Mode Simulation-Design Methodology For On-Chip ESD Protection Design, MS Thesis, IIT, 2001.
K. Gong, ESD Protection in Copper Interconnect and ESD-to-Circuit Performance Influences, MS Thesis, IIT, 2001.

Prof. Albert Wang/UCR - IEEE-DL, Stuttgart, Germany, 06/08/2010 31