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Document preface:
This document has been created for both beginners and advanced
programmers. There may be some information that you may well
consider 'unnecessary' (such as the introduction to planar image
storage), but please think of people who would really like to
program the PC-Engine, but dont have a clue on how some basic
techniques (like planar) work.
This document is in very early state and may well contain
a lot of information not being correct. For any wrong in-
formation in this document you may discover, please write
me a mail at eschleus@luva.lb.bawue.de so I can fix it and
release a new version.
The latest version of this document can always be obtained
at my homepage located at:
www.classicgaming.com/aec/
or just write me an email and ask me to send you the latest
revision.
Any help on improving this document is highly appreciated!
I think its the most complete one out there at this time.
Yours,
Manuel
eschleus@luva.lb.bawue.de
www.classicgaming.com/aec/
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----- T O P I C S -------------
--------------------------------------------------------
+-------------------------------------------+
| 1. Purpose of the VDC / General info |
| |
| 2. The VRAM structure / encoding VRAM data|
| |
| 3. Accessing the VDC from the CPU |
| |
| 4. The VDC registers in detail |
| |
| 5. The Sprites in the VRAM |
| |
| 6. The Sprite attribute table (SATB) |
| |
| 7. The Video Color Encoder |
| |
+-------------------------------------------+
--------------------------------------------------------
----- 1. Purpose of the VDC / General info -------------
--------------------------------------------------------
The VDC (Video Display Processor), also known as the HuC6270,
is the main graphics processing unit in the PC-Engine. Despite
the CPU of the PC-Engine is only 8-bit, the VDC is a full 16-bit
processor with very powerful capabilities. Its accessible from
the main system via 3 special opcodes that write/read data from/
into the Video Display. The VDC is connected to another chip known
as the HuC6260 VCE (Video Color Encoder), which supplies the color
palette data for the Video System.
The VDC in the PC-Engine has two modes of operation:
1. Background character processing
2. Sprite processing
The 64 kB VRAM that the VDC is connected to does NOT contain one big
bitmap with all the display information stored pixel by pixel like
on a Amiga or PC, the Graphics are stored tile-based. In case you do
not know what tile-based graphics are, be sure to read section 2
very carefully.
--------------------------------------------------------
----- 2. The VRAM structure / encoding VRAM data -------
--------------------------------------------------------
The VRAM of the PC-Engine is 64 kBytes in size. No chip other
than the VDC can access it. It contains all the important data
needed for the display generation.
The way graphical data is organized in the VRAM is called 'tile
based'. This means there is NOT a huge bitmap containing a color
index for every pixel, but only a list of pointers to small,
rectangular areas in the VRAM that will, aligned to each other,
make up the display. Explanation follows.
Think of it like this:
We have a 512*256 pixel 256 color screen. On a PC, for instance,
we would have to have the following VRAM structure:
+---------------------------------------+
| <--512 pixels across --> |
| |
| | 256
| | pixels
| | down
| |
| |
| |
| |
| |
+---------------------------------------+
The color depth is 8 bit ^= 256 colors
This would result in 512 * 256 * 8
= 1.048.576 bit
= 130 kbytes (roughly)
So, if the PC-Engine would do it the same way, it would not be
able to have such high resolutions due to the lack of VRAM.
Thats why data is stored in the VRAM as follows:
The screen background area is made up out of 8*8 pixels large
blocks, called the 'tiles', each tile having a color palette of
16 colors. There are 16 different palettes to choose from for
each tile, resulting in 256 different colors for the background
generation (the other 256 colors are reserved for sprite usage
which will be described later).
In the background, colour 0 of all palettes are equal. Colour 0 of
palette 0 determines colour 0 of all the background palettes. Even
though these colour CAN be set independently, the screen will not
reflect these settings.
-----Now, how are those tiles aligned to each other?
Starting at the very beginning of the VRAM ($0) there is the so-
called BAT (Block Attribute Table), which is a list of pointers
to tiles stored in the Video RAM. The amount of pointers varies
depending on how big the actual screen is. (As I told you, you
have 8*8 pixel tiles, so if the screen is larger, theres more
tiles). For our test screen (512*256), we would need:
512 / 8 = 64 tiles per line
256 / 8 = 32 tiles vertical
64 * 32 = 2048 tiles
That means, we would be in need of a BAT 2048 words in lenght.
-----WHY WORDS? How does a BAT pointer to the VRAM look like?
A Pointer to a tile in the VRAM must contain palette information
as well as the actual VRAM address where to find the tile. This
ONE WORD LONG index pointer looks like this:
PPPPAAAAAAAAAAAA
| |
| |
| +------- 12 lower bits: Index of the tile
|
+--------------- 4 upper bits: Palette number (0-15)
If you multiply the tile index by 32 (LSL #5 ;-), you will get
the actual VRAM pointer address.
The pointers in the BAT are ordered from the left to the right
and top to down.
----->Small example:<-----
Here is the first few words of data in the VRAM of HATRIS, just having
the intro screen up. If you look closely, note how VRAM was saved using
the same tiles over and over again in the BAT:
--------------------------------------------------------
----- 3. Accessing the VDC from the CPU ----------------
--------------------------------------------------------
---HOW CAN I TRANSFER DATA INTO THE VRAM?
Well, there are three memory locations involved that can be read/
written by the CPU to supply the VDC with data / read data from
the VDC (all in the I/O Memory Segment $FF):
Full address Access Purpose
$1FE000 R/W VDC Register select
$1FE002 R/W Low Data register
$1FE003 R/W High Data register
The first of the three locations here is the so-called REGISTER
SELECT. The VDC has 19 Registers (several of them being totally
unknown, btw) to access. To tell the VDC to which register you
want to write the value contained in $1FE002 (and $1FE003), simply
write the number of the register to write to into the low 5 bits
of $1FE000. As the VDC is a 16 bit processor (ALL VDC registers
are one word wide) in most cases you will need to supply both
of the data values.
Detailed description of the VDC ports by Videoman (slightly changed):
Address | Access | Description
(Mapped | mode |
to $FF) | |
--------------+--------+---------------------------------------------------
$0000 | R | 6270 Status register
| |
| | Different bits flag different conditions.
| | Not all are known.
| | (Note: can use special ST0 opcode to store
| | an immediate value.)
| | b 7 = 0
| | b 6 = 'BSY' flag
| | I believe this is '1' when a DMA transfer
| | is happening
| | b 5 = 'VD' flag
| | I believe this is a '1' when Vertical Sync
| | happens, otherwise a '0' (uncertain)
| | b 4 = 'DV' flag (unknown)
| | b 3 = 'DS' flag (unknown)
| | b 2 = 'RR' flag
| | Set during a Scanline interrupt (see RCR
| | register)otherwise '0'
| | b 1 = 'OR' flag (unknown)
| | b 0 = 'CR' flag (unknown)
| |
$0000 | W | 6270 Address register
| |
| | b 7-5 = ignored
| | b 4-0 = 6270 register number to access using
| | the 6270 data registers
| | ($0002 and $0003). Please see 6270
| | register list (SECTION 4) for details.
| |
$0002 | R/W | 6270 data LSB
| |
| | Note: can use special ST1 opcode to store
| | an immediate value.)
| |
$0003 | R/W | 6270 data MSB
| |
| | Note: can use special ST2 opcode to store
| | an immediate value.)
--------------+--------+---------------------------------------------------
----->One short example on this one:<------
To read the contents of Register 2 (VRAM-Read-Register) simply use the
following line of code:
ST0 #2
...and then the two data values will sort of 'mirror' the value in
this VDC register.
--------------------------------------------------------
----- 4. The VDC registers -----------------------------
--------------------------------------------------------
This huge and very complete list has been taken from Videomans
hardwaremap document, Jens' PCE documentation, and some information
to it was added by me.
--------------------------------------------------------
----- 5. The Sprites in the VRAM -----------------------
--------------------------------------------------------
Well, I will not try to explain what Sprites are here. Basically,
all of the PC-Engines' sprites are 16*16 to 32*64 pixels in size,
and have a sprite palette of 16 colors.
There are 16 separate sprite palettes available. (remember, there
was 16*16 colors for the background processing, those colors are
INDEPENDENT from the sprite palettes).
In the Sprites colours, colour 0 is transparent in all palettes,
although it does peek it's head in a peculiar place; beyond the display
width of the BG.
Explanation:
The background display area (in it's most often used setting) is 256x216.
The display width of a television may be adjusted to squash the screen
vertically, or horizontally. Even normal TVs show a little more that 256
TG-16 dots wide, leaving a black border on the sides. This border colour is
actually controlled by sprite colour 0. The programmer can actually set the
screen width more narrow or vertically shorter, showing more of this area.
It's only use that I've ever implemented was in measuring the CPU load of
the TG-16 during development.
--HOW ARE SPRITES STORED IN THE VRAM?
For the sprite characters the principe is the same as for the background
tiles, but in place of using bytes (8 pixels) they use words (16 pixels).
Note that the words still use the same encoding as all word data within the
PC-Engine, this means that the first byte of the word is the lower byte.
Sprite data is stored like in the following drawing:
Byte Data
offset
+-------------------+
0 | plane 1 of line 1 |
+-------------------+
2 | plane 1 of line 2 |
+-------------------+
. .
: :
30 | plane 1 of line 16|
+-------------------|
32 | plane 2 of line 1 |
+-------------------+
34 | plane 2 of line 2 |
+-------------------+
36 | plane 2 of line 3 |
+-------------------+
. .
: :
46 | plane 2 of line 16|
+-------------------+
48 | plane 3 of line 1 |
......and so on.
Not only you can display sprites, you can do some sort of funny stuff
with them, like mirroring, for instance. All this is controlled in the
so-called SPRITE ATTRIBUTE TABLE.
--------------------------------------------------------
----- 6. The Sprite attribute table (SATB) -------------
--------------------------------------------------------
The sprites' positions and attributes are defined in the so-
called SPRITE ATTRIBUTE TABLE (SATB). The SATB can be contained any-
where in the VRAM ($0000-$7FFF).
--HOW DOES THE VDC KNOW WHERE THE SATB IS TO BE FOUND?
The VDC has a special register containing nothing but the start
address of the SATB in the VRAM. This is register 19 (SEE SECTION 4)
The actual sprite attributes are stored at the address mentioned
above. For aech sprite, there is a 4 word long attribute section,
which looks as follows:
Word | Access | Description
offset | mode |
--------------------------------------------------------------------------
0 R/W Y position
b 15-10 (unused)
b 9-0 y position (relative to
virtual-screen origin)
1 R/W X position
b 15-19 (unused?)
b 9-0 x position (relative to
virtual-screen origin)
2 R/W Pattern address
b 15-11 (unused?)
b 10-0 sprite data VRAM address shifted
right 5 bits(Shift left 6 bits to
get real VRAM address)
3 R/W Sprite attributes
b 15 y-invert flag (upside-down)
b 14 unused
b 13-12 'CGY'
00 = sprite is 1 'cell' (16 pixels) high
01 = sprite is 2 cells high (32 pixels)
10 = invalid
11 = sprite is 4 cells high (64 pixels)
b 11 x-invert flag (left-right invert)
b 10-9 unused
b 8 'CGX'
0 = sprite is 1 'cell' wide (16 pixels)
1 = sprite is 2 cells wide (32 pixels)
b 7 'SPBG'; is sprite in foreground (in front
of CG) or background (behind CG)
b 6-4 unused
b 3-0 sprite colour (i.e. which of 16 sprite
palettes to use)
--------------------------------------------------------
----- 5. The HuC6260 Video Color Encoder (VCE) ---------
--------------------------------------------------------