Specification and Simulation of Digital Systems

Final Project Report

Building a custom MIPS-like

processor

Vittorio Giovara
149374

16/06/2008 http://gle-mips.googlecode.com
Contents

1 Introduction 3
1.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Expansions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Architectural Behaviour 5
2.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.1 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.2 Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.3 Instruction Decode . . . . . . . . . . . . . . . . . . . . . . 6
2.2.4 Execution Stage . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.5 Memory Stage . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.6 Write-Back . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Modular View 7
3.1 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.1 Input and Outputs . . . . . . . . . . . . . . . . . . . . . . 7
3.1.2 Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.3 Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.1 Input and Outputs . . . . . . . . . . . . . . . . . . . . . . 8
3.2.2 Components . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.3 Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Instruction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.1 Input and Outputs . . . . . . . . . . . . . . . . . . . . . . 9
3.3.2 Components . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.3 Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Execution Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.1 Input and Outputs . . . . . . . . . . . . . . . . . . . . . . 10
3.4.2 Components . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.3 Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5.1 Input and Outputs . . . . . . . . . . . . . . . . . . . . . . 11
3.5.2 Components . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5.3 Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6 Memory Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6.1 Input and Outputs . . . . . . . . . . . . . . . . . . . . . . 12

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 3.6.2 Components . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6.3 Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Write-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7.1 Input and Outputs . . . . . . . . . . . . . . . . . . . . . . 13
3.7.2 Components . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7.3 Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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Chapter 1

Introduction

The aim of this report is to provide complete and detailed documentation about
the design and implementation of a MIPS-like processor in VHDL language.

1.1 Specifications
The custom processor must produce a result in 5 clock cycles, using a non
pipelined architecture. A complete instruction set has been built, with working
• Arithmetic operations
• Logical operations
• Shift operations
• Memory operations
• Branch operations
In order to load the encoded instructions, a special ROM file is used and is
accessed using the Program Counter as index.

1.2 Expansions
In addition to the requested functionality, several optional features have been
included:
Division and Modulo: working code for division or modulo operations;
Greater/Less than or Equal: complete evaluation case module;
Rotate: arithmetical or logical, right or left rotation module;
MOV instruction: for rapidly storing values in the register file;
Inverse logical fuctions: for NAND, NOR and XNOR computation;
RAM file: a functional volatile memory with read and write support;
64 bit support: integer and memory size expansion.

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1.2.1 Notes
The RAM file and the 64 bits support have only limited implementation due to
VHDL intrinsic boundaries.
Synthesis for a complete RAM module take excessive computational effort
and for this reason its size has been limited to 26 words; however this parameter
can be increased, since all the modules are built using generics.
The 64 bits support is available only at synthesis time, selecting the correct
generics flags; the main advantage for using this extension is to be able to
manipulate and compute operations with 32 bits integer numbers (instead of
16) and have the result on 64 bits. However enabling this feature will cause
more warnings during synthesis as the base architecture was thought in 32 bits;
furthermore the ROM file can be only accessed in 32 bits fashion, because the
available integer conversion functions only support 32 bits numbers.
Warning: Xilinx behaves weirdly when simulatining a module with two dif-
ferent configurations; for this reason the configuration sections have been com-
mented out and in order to test the 64 bits extension using the provided ROM
file, it is necessary to manually change the architecture used by ROM. This bug
is not present in other simulation/synthesis tool like Modelsim or Synopsis.

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Chapter 2

Architectural Behaviour

This chapter provides a general overview on the structure of the processor.

2.1 Structure
The processor is organized in 5 separated blocks, corresponding to the five RISC
stages; each stage corresponds to a single module written in VHDL; each module
includes all the smaller devices needed for correct functionality

• Instruction Fetch

• Instruction Decode

• Execution Stage

• Memory Stage

• Write-Back

The control logic is implemented by a Control Unit that enables only one
stage at each clock cycle, activating control signals according to the istruction
in execution. Even though the last stage doesn’t actually need a clock cycle, it
has been preferred to force an additional clock period in order to fully adhere
to the project speficiations.

2.2 Modules
2.2.1 Control Unit
This module implements two finite state machine, one for enabling the stages
in sequence, the other for setting up the correct path for data to enter or exit
in the Exectution and Memory Stage.

2.2.2 Instruction Fetch

In this module the Program Counter is loaded and read, and it is used to extract
the new instruction from the ROM.

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2.2.3 Instruction Decode
In this phase there is the Register File in which the registers are written and
read, provinding data to the execution stage.

2.2.4 Execution Stage

This stage processes data and executes the operation commanded by the exter-
nal control unit through the Arithmetic Logic Unit.

2.2.5 Memory Stage

In this stage there is a simple RAM implementation that is capable of storing
data as long as the processor is powered. Data can be loaded and stored in 32,
16 or 8 bits words.

2.2.6 Write-Back
This is a multiplexer that selects the source to be written in the Register File.

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Chapter 3

Modular View

In this chapter the main modules are presented, listing all the signals, compo-
nents and processes involved.

3.1 Control Unit

3.1.1 Input and Outputs

Signal Name Type Signal description

clk IN Clock synchronization signal
rst IN Reset control signal
opcode IN Operation code from the Instruction Register
func IN Function code from the Instruction Register
alu mux OUT Operation selection for the ALU
info OUT Control signal for selecting signed/unsigned numbers,
positive/negative operations or left/right shift in many modules
types OUT Control signal for selecting addition/subtraction operation or
logical/arithmetical shifts in various modules
extra OUT Control signal for shift/rotate selection and logical operations
left mux OUT Selects the first operand for the ALU
right mux OUT Selects the second operand for the ALU
cond pilot OUT Branch evaluation parameter
mem cnt OUT Word size for the RAM module
mem wr OUT Write enable for the RAM module
npc mux OUT Selection signal for the mux 1
(handles the Jump and Link operations)
w en OUT Register File Write enable
wb mux OUT Selection signal for the Write Back stage
en if OUT Enable signal for the Istruction Fetch stage
en id OUT Enable signal for the Istruction Decode stage
en ex OUT Enable signal for the Execution stage
en mm OUT Enable signal for the Memory stage

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3.1.2 Processes

Process Name Process description

ENBL Commutates the enable signal for the next stage at every clock cycle
DECODE Enables and activates many control signals depending on the operation code

3.1.3 Behaviour
In the ENBL process there is a finite state machine which, at every clock cycle,
sets one single enable signal for the next phase in this order: IF, ID, EX, MM
plus one pseudo enable (that is, when they are all 0) for the WB that has not
enable inputs.
In the other process, DECODE all the control signals (listed above) are
actived accordingly to the operation that must be executed. Since not every
operation always activates every control signal (with the exception of left mux,
right mux and alu mux ) at the beginning of the process, a default value is
assigned.

3.2 Instruction Fetch

3.2.1 Input and Outputs
Signal Name Type Signal description
clk IN Clock synchronization signal
rst IN Reset control signal
enb IN Register enable
en start IN Program Counter enable
PC in IN Input for the Program Counter
opcode OUT Operation code from the Instruction Register
rs OUT Register address from the Instruction Register
rt OUT Register address from the Instruction Register
rd OUT Register address from the Instruction Register
Imm OUT Immediate number
shamt OUT Shift amount from the Instruction Register
func OUT Function to be exectued when
NPC out OUT Predicted new Program Counter

3.2.2 Components

Component Name Component description

PC The Program Counter register
Adder4 Simple +4 adder, for the New Program Counter generation
NPC The New Program Counter register
MEM ROM array in which instructions are hardwired
IR The Istruction Register, in which the current instruction is stored
and separated towards others modules

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3.2.3 Behaviour
First of all a new istruction is extracted from the instruction memory (MEM ),
a read-only array of blocks of 8 bits, using the program counter value as vector
index; then this value is stored inside a special register (IR) which splits the
various part of an instruction (opcode, registers etc).
Finally the content of the program counter (PC ) is increased of 4 through
Adder4 and stored in NPC.

3.3 Instruction Decode

3.3.1 Input and Outputs
Signal Name Type Signal description
clk IN Clock synchronization signal
rst IN Reset control signal
enb IN Register enable
opcode in IN Operation code from the Instruction Register
rs IN Register address for the first operand
rt IN Register address for the first operand
rd IN Register address for the destination
Imm in IN Immediate number
mem in IN Data to be saved in the Register File
w en IN Enable Write on the Register File
A out OUT First register output
B out OUT Second register output
Imm out OUT Immediate register output

3.3.2 Components
Component Name Component description
REG FILE The Register File
SIGN Sign extension for the Immediate number
A The register for the first operand
B The register for the second operand
Imm The register for the extended immediate number

3.3.3 Behaviour
The two source registers are extracted from the Register File according to the
addresses r s and r t, and stored in a register (respectively A out and B out).
As for the destination register, there’s a condition on opcode in:

• in case of a register to register fuction, it is mapped to r d ;

• in case of a register to immediate function, it is mapped to r t;

• in case of a Jump and Link or Jump and Link Register it is forced to

11111, that is the last register of the array.

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 As for the immediate number, it must be first extended to complete the
register size; so in SIGN the Most Significant Bit of Imm in is repeated to
cover the whole size of Imm out, the register in which this value is stored.

3.4 Execution Stage

3.4.1 Input and Outputs

Signal Name Type Signal description

clk IN Clock synchronization signal
rst IN Reset control signal
enb IN Register enable
NewPC IN Corresponds to Program Counter + 4
A reg IN Register of the first operand
B reg IN Register of the second operand
Imm reg IN Register of the immediate number
shamt in IN Shift amount value
operation IN Operation to be executed
info in IN Control signal for signed/unsigned, positive/negative, left/right
types in IN Control signal for addition/subtraction, logical/arithmetical
extra in IN Control signal for shift/rotate and logical operations
mux l pilot IN Selection for the left mux
mux r pilot IN Selection for the right mux
cmp pilot IN Selction of the type of comparison
ALU out OUT Result of the operation
branch OUT Control signal to determine whether a branch is taken or not
status OUT Status signal for overflow cases

3.4.2 Components

Component Name Component description

MUX L Multiplexer between the New Program Counter and the first operand
MUX R Multiplexer between the second operand and the immediate
ALU Arithmetic Logic Unit core
CHK The condition evaluator for branch taking
ALU reg The register holding the ALU result

3.4.3 Behaviour
The Control Unit chooses the inputs that are going to be processed by the ALU
with the two multiplexers MUX L (NPC or register A) and MUX R (register B
or immediate). The ALU performs the operation selected with the omonimous
signal (always commanded by the Contro Unit) and stores the result in the
ALU out register.
In the meantime the CHK controls the branch output. It can be forced to
produce always 0 (000, no branch taken) and always 1 (111 always jump); the
intemediate value correspond to the desired comparison operation (=, 6=, >, <,

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≥, ≤) between 0 and the input operand, and they determine whether a branch
is taken or not.

3.5 Arithmetic Logic Unit

3.5.1 Input and Outputs

Signal Name Type Signal description

left IN First operand (from register A or from the New Program Counter)
right IN Second operand (from register B or from the Immediate)
alu mux IN Output selection
sh amt IN Shift amount
info IN Control signal for signed/unsigned, positive/negative, left/right
types IN Control signal for addition/subtraction, logical/arithmetical
extra IN Control signal for shift/rotate and logical operations
output OUT Final result of operation
status OUT Status flag (overflow for adder and divider)

3.5.2 Components

Component Name Component description

ADDER Computes addition or subtraction implementing a Ripple Carry Adder
MULT Performs multiplication using synthetizer primitives
LOGICS Implements different logical operations
SHIFTER Realizes a parallel shifter/rotate in arithmetical and logical mode
DIVISOR Calculates division and modulo operations

3.5.3 Behaviour
This is the central operating unit which provides the actual output of the oper-
ation, located inside the execution stage.
The input operands from left and right are connected to all the modules
above and each one of them provides a result; only the selected result is sent to
output, using a behavioral muxer controlled by alu mux. The various modules
options (like for signed and unsigned numbers) are carefully activated with the
signals info, types and extra.

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3.6 Memory Stage
3.6.1 Input and Outputs
Signal Name Type Signal description
clk IN Clock synchronization signal
rst IN Reset control signal
enb IN Register and memory enable
cond IN Control signal for mux 0
sel IN Control signal for mux 1
mem wr IN Enable Write on the RAM
mem cnt IN Word size selection
B in IN Data to be saved in memory
ALU in IN Address for the memory array
NewPC IN Corresponds to Program Counter + 4
mux out OUT Output from mux 1
result OUT Output from the memory array
NPC final OUT Correct Next Program Counter

3.6.2 Components

Component Name Component description

MUX 0 Multiplexer between the New Program Counter and the
output of the ALU towards the New Program Counter register
MUX 1 Multiplexer between the output of the ALU and
the New Program Counter towards the Write Back
(handles Jump and Link operations)
SPLIT in Select the word size for the input of the memory array
SPLIT out Select the word size for the ouput of the memory array
MEM The RAM implementation
PCreg The register holding the final Program Counter

3.6.3 Behaviour
According to condition evaluation of the Execution Stage, the correct Program
Counter is selected via MUX 0 (either PC+4 or the value computed by the
ALU) and stored in PCreg.
In case of Jump and Link or Jump and Link Register operations, the ouput
value must be the New Program Counter while in the Instruction Decode the
correct destination register has already been selected. To do so, MUX 1 selects
the NPC, instead of the ALU ouput, and sends it Write Back stage.
The input and output of the memory is first filtered with SPLIT in and
SPLIT out to obtain just the desired word size (the control signal mem cnt is
directly sent from the Control Unit). Then the least significant bits (only due
to design limitation) of the ALU output is used to access the RAM (which is
simply an array of registers) and the result in sent directly to the Write Back.

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3.7 Write-Back
3.7.1 Input and Outputs
Signal Name Type Signal description
LOAD in IN Clock synchronization signal
ALU in IN Reset control signal
sel IN Register enable
output OUT Control signal for mux 0

3.7.2 Components
Component Name Component description
MUX Multiplexer between the output of the memory and
of the ALU towards the Register File

3.7.3 Behaviour
This module selects the final data to be stored in the Register File; depending
on the operation, it selects either the memory output, or the result of the ALU.

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