1882 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO.

9, SEPTEMBER 2009

The Impact of On-Chip Interconnections on

CMOS RF Integrated Circuits
Munir M. El-Desouki, Student Member, IEEE, Samar M. Abdelsayed, Member, IEEE, M. Jamal Deen, Fellow, IEEE,
Natalia K. Nikolova, Senior Member, IEEE, and Yaser M. Haddara, Member, IEEE

AbstractAchieving power- and area-efficient fully integrated

transceivers is one of the major challenges faced when designing
high-frequency electronic circuits suitable for biomedical applica-
tions or wireless sensor networks. The power losses associated with
the parasitics of on-chip inductors, transistors, and interconnec-
tions have posed design challenges in the full integration of power-
efficient CMOS radio-frequency integrated circuits (RF ICs). In
addition, the parasitics of on-chip passive components that are
integrated on lossy silicon substrates have made CMOS-based
integrated circuits inferior to their compound-semiconductor
counterparts. The parasitic effects of on-chip interconnections
play a key role in RF circuit performance, particularly as the
frequency of operation increases. Neglecting these effects leads
to the significant degradation in circuit performance or even
failure of operation in some cases. Furthermore, unlike transis-
tors, miniaturization of interconnections does not improve their
performance. This paper demonstrates the impact of metal layer Fig. 1. Conceptual diagram of an on-chip interconnect shown in 3-D with the
resistivity and layout parasitics on an RF power amplifier (PA) and equivalent circuit representation.
a low-noise amplifier (LNA). A nonlinear fully integrated 2.4-GHz
class-E PA, with a class-F driver stage, and a 5-GHz LNA are dis- extent from on-chip parasitic effects. Examples are parasitics
cussed. The circuits were fabricated in a standard 0.18-m CMOS due to RF pads, electrostatic discharge protection diodes, and
technology. The layouts of the presented CMOS amplifiers were
designed by carefully modeling the interconnection wires during vias, and most importantly, parasitics due to metal interconnec-
the simulations and optimizing their widths for minimum parasitic tions. If these parasitics were not carefully taken into account
effects and hence optimum measured circuit performance. Due in the design stage, then the circuit measurement results will
to the careful layout design and interconnection optimization, the vary significantly with respect to their simulated performance.
implemented amplifier circuits showed a good match between the In such cases, it will be very difficult to design efficient high-
measured and simulated performance characteristics.
frequency fully integrated transceiver blocks that can operate
Index TermsAmplifier, class-E, class-F, CMOS radio- from very low supply voltages, for applications such as ad hoc
frequency integrated circuits (RF ICs), interconnections, low- wireless sensor networks and biomedical implantable electronic
noise amplifier (LNA), low-power, parasitic-aware design, power
amplifier (PA), radio frequency (RF). systems [1], [2].
Since the miniaturization of interconnections with CMOS
I. INTRODUCTION downscaling does not enhance their performance, parasitics
due to interconnections are significantly worse in gigascale

F OR FULLY integrated system-on-chip solutions, having

compact models to accurately predict the performance
of active and passive components is crucial to the successful
implementation of the design. Further, when operating at
frequencies in the gigahertz range, CMOS radio-frequency
integrated-circuit (RF IC) implementations suffer to a great
Manuscript received December 8, 2008; revised May 20, 2009. First pub-
lished July 28, 2009; current version published August 21, 2009. This work was
supported in part by the Natural Sciences and Engineering Research Council of
Canada and in part by the King Abdul-Aziz City for Science and Technology
of Saudi Arabia. The review of this paper was arranged by Editor S. Saha.
M. M. El-Desouki is with the Department of Electrical and Computer
Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada, and also
with the Computer and Electronics Institute, King Abdul-Aziz City for Science
and Technology, Riyadh, Saudi Arabia.
S. M. Abdelsayed, M. J. Deen, N. K. Nikolova, and Y. M. Haddara are with
the Department of Electrical and Computer Engineering, McMaster University,
Hamilton, ON L8S 4K1, Canada (e-mail: jamal@mcmaster.ca).
Digital Object Identifier 10.1109/TED.2009.2026194
0018-9383/$26.00 2009 IEEE
integration (GSI), where it is predicted that the performance
governing factor in GSI will be limited to the performance
of on-chip interconnections [3], [4]. For example, the intrinsic
switching delay of a 1-m CMOS technology transistor is about
20 ps, compared to 2.5 ps in a 35-nm CMOS technology [4]. On
the other hand, the latency of a 1-mm-long interconnection in a
1-m CMOS technology is 1 ps, compared to 250 ps in a 35-nm
CMOS technology [4].
Interconnection models in the simplest form should include a
resistor, a capacitor, and an inductor [5][7], as shown in Fig. 1.
Such models have been verified using a number of RF circuit
designs [8][13]. This paper demonstrates the impact of metal
layer resistivity and layout parasitics on RF power amplifier
(PA) and low-noise amplifier (LNA) circuits. A nonlinear fully
integrated 2.4-GHz class-E PA, with a class-F driver stage, and
a 5-GHz LNA were used to verify the parasitic-aware design
procedure used in this paper.
EL-DESOUKI et al.: IMPACT OF ON-CHIP INTERCONNECTIONS ON CMOS RF INTEGRATED CIRCUITS
Fig. 2. Parasitic-aware RF IC design flowchart.
The layouts of the presented CMOS PAs were designed
by modeling the interconnection wires in simulation and then
optimizing their widths for minimum parasitic effects and
hence optimum measured circuit performance. The intercon-
nection modeling and layout design considerations resulted
in improvements from 8% to 35% in the drain efficiency of
the class-E PA. The design was further improved by using a
standard CMOS process with a 2-m-thick top-metal layer,
which was double the thickness of the first design. This thicker
metal resulted in an increase in inductor quality factor and,
hence, an increase in drain efficiency from 35% to 55%. Due to
the careful layout design and interconnection optimization, the
implemented circuits had a good match between the measured
and simulated performance characteristics.
This paper is organized as follows: Section II contains a
description of the interconnection modeling and circuit simu-
lation procedure. In Section III, the PA layouts and layout de-
sign considerations following the parasitic-aware circuit design
approach are presented and discussed. The LNA design and
measurement results that were used to verify the parasitic-aware
design approach are also presented in this section. Finally, the
conclusions are stated in Section IV.
II. INTERCONNECTION MODEL AND DESIGN PROCEDURE
On-chip interconnections add parasitics to the RF circuit,
which can have various effects, and depending on the RF
circuit being designed, these effects need to be traded off.
The tradeoff between the parasitic capacitance, inductance, and
resistance of interconnections can be optimized by modeling
every interconnection with a lumped element circuit model,
which is generally not available from the foundries.
A. Interconnection Model
Fig. 2 shows a flowchart of the RF design procedure that was
used in this paper [12][17]. After obtaining a schematic of the
circuit design that achieves the desired design specifications, a
1883
floor plan of the chip layout must be designed based on active
and passive device sizing and positioning. Once the devices are
placed on the layout, the length of the interconnections can be
found, and the metal layers can be chosen. The interconnection
models are then added to the circuit schematic in the simulator,
and the effects of the layout parasitics can then be carefully
accounted for. Generally, minimizing the resistive losses is the
major concern in PA designs. However, in the case of tuned
amplifiers, such as class-E and class-F, the parasitic inductances
and capacitances can significantly affect the tuning if not taken
into account during the simulations. Once the parasitic compo-
nents are taken into account, the circuit component values can
be fine tuned, and the performance can be enhanced. Finally, a
layout-versus-schematic step is necessary to ensure that there
are no errors in the layout.
The work in this paper focuses on using a simple three-
element T-section equivalent circuit model of the interconnec-
tion. Fig. 3(a) shows a screen capture of the InterConnect
application interface that was designed to calculate the in-
terconnection equivalent circuit component values. The figure
also shows the equivalent circuit model used to represent the
interconnections. The InterConnect program takes layout in-
formation regarding the interconnections width (w), length
(l), and metal layer used, and produces the value of the ca-
pacitance, resistance, and inductance of the interconnection
parasitics based on the following equations, where Lmetal is in
nanohenries [7]:
Rmetal = R l/w (1)
Cmetal = C w l (2)
Lmetal = 2l [ln (2l/(w + t)) 0. 50049 + (w + t)/3l] (3)
where Rmetal , Cmetal , and Lmetal are the interconnection
equivalent resistance, capacitance, and inductance, respectively.
For the selected metal layer, t, R , and C are the interconnec-
tions thickness, sheet resistance, and capacitance of a single
metal square, respectively, which are usually provided in the
foundry documentation supplied to the designers.
1884
Fig. 3. (a) Screen capture of the InterConnect application interface showing
the three-component equivalent circuit model used. (b) Equivalent circuit used
in [14] to model and meander-line resistor. (c) Cross-sectional example of the
upper four metal layers of a six-metal-layer CMOS process showing the vias.
Using the equivalent circuit shown in Fig. 3(a) is sufficient
for applications at frequencies below 10 GHz, after which, the
lumped element model must be refined [18]. At higher frequen-
cies, i.e., above 10 GHz, the resistance of the metal intercon-
nections begins to rise due to skin and proximity effects, which
require the use of frequency-dependent elements to model the
interconnections resistance and inductance [19]. In addition,
since every interconnection is characterized separately, issues
such as interconnection overlap capacitance, crosstalk, and
antenna effects are not accounted for. However, these effects
can be avoided by careful placement of the components during
the layout. The substrate resistance, which is neglected in this
model, can be justified by careful layout and ensuring that
there are abundant substrate ground contacts near all the circuit
components.
A more advanced model, such as the one shown in Fig. 3(b)
[20], [21], can be used for frequencies above 10 GHz, which
takes into account the substrate resistance (Repi ). This model
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 9, SEPTEMBER 2009
was initially designed as an equivalent circuit of meander-line
resistors [20], [21]; however, it can be simplified to represent
a simple interconnection metal. In this case, Cmf will be the
mutual capacitance between the modeled interconnection and
any other interconnection within close proximity, specifically
overlapping ones from another metal layer. For very high fre-
quencies, i.e., up to 100 GHz, parallel-plate waveguide models,
such as the model described in [22] and [23], can be used.
The models described in [22] and [23] can also be used for
the case of thin-film interconnects. In this case, even at low
frequencies, when the height of the interconnection is less
than or comparable to the skin depth, the simplified model
in Fig. 3(a) may not be very accurate, and a parallel-plate
waveguide model [22], [23] will be more appropriate.
Vias are also a concern in RF design. Fig. 3(c) shows a cross
section through the top four metal layers in a six-layer metal
CMOS process. The main parasitic effect of vias is the via
resistance, which is due to confining the current flow in narrow
metals. This parasitic effect can be minimized by implementing
a large number of vias in parallel.
B. Simulation Setup
The PA circuit that was designed to operate at 2.4 GHz for
low-voltage biomedical applications consisted of two stages:
a class-E output stage and a class-F driver stage. Fig. 4(a)
shows the schematic of the designed two-stage PA with all the
components fully integrated. Class-E PAs have an ideal drain
efficiency of 100% when the active device acts as a switch with
zero ON-resistance [24]. For optimum class-E operation, the
following three criteria must be met [24], [25]:
1) the voltage across the switch in the OFF-mode should not
rise until after the transistor is OFF;
2) the voltage across the switch should go back to zero
immediately before turn-ON;
3) the slope of the switch voltage should be zero at turn-on
to achieve soft switching.
Many design equations exist to aid in achieving optimum
operation by accurately tuning the output network [25], [26].
The theory of the class-F driver stage PA is based on peaking
the odd harmonics and attenuating the even ones to obtain a
square-shaped waveform. This results in less overlap between
the voltage and current signals, which leads to less power
dissipation in the active device. In theory, class-F can achieve
very high efficiencies; however, the networks used for harmonic
peaking must be accurately tuned.
Class-F has proven to be a good driver for class-E PAs, since
class-E is more efficient when driven with a square wave [27],
[28]. The detailed operation of the circuit shown in Fig. 4(a)
is described in [16] and [17]. From the brief explanation given
of how this PA topology operates, it can be realized that the
successful operation of this circuit depends greatly on the how
well the components are tuned. This, in addition to the effect of
resistive losses on the PAs drain efficiency, makes this circuit
extremely sensitive to layout parasitics.
By following the parasitic-aware design procedure explained
in Section II-A, the schematic representation shown in Fig. 4(b)
can be obtained, where there is an interconnection model repre-
senting every on-chip interconnection wire. It is noted that this
EL-DESOUKI et al.: IMPACT OF ON-CHIP INTERCONNECTIONS ON CMOS RF INTEGRATED CIRCUITS
Fig. 4. (a) Schematic of the fully integrated CMOS 2.4-GHz PA. (b) Sim-
ulation setup showing all the interconnect models added to the schematic.
(c) Output drain efficiency of the PA as a function of frequency at the biasing
conditions shown in Fig. 4(b).
circuit was designed to operate from a very low supply voltage
for biomedical or short-range applications [16], [17]. The losses
from the RF cables and bias-T connectors were also modeled
and included into the schematic simulations.
Fig. 4(c) shows the output drain efficiency of the PA as
a function of frequency. This figure, showing the simulation
results with and without layout parasitic modeling, is compared
to the measurement results of the first layout that was designed.
This design is described in the following section. Due to the
poor parasitic unaware layout of this design, there was a drop
of 26% in drain efficiency. When comparing the parasitic-aware
1885
Fig. 5. Photomicrograph of (a) the first fabricated PA design and (b) the
improved design. These designs include an output filter, which is why there
is an additional inductor when compared to (c), which is the PA fabricated with
a thick top-metal option [16].
simulations to the measurement results, a very close match can
be seen, which shows that, had a parasitic-aware layout tech-
nique been used, the drop in efficiency could have been avoided.
III. LAYOUTS AND DESIGN CONSIDERATIONS FOR
MINIMUM PARASITIC EFFECTS
The PA circuit described in the previous section has been
fabricated and tested in three different layouts, where the first
two were fabricated in a standard 0.18-m six-layer metal
CMOS technology with a 1-m-thick top-metal layer. The
photomicrographs of the fabricated designs are shown in Fig. 5,
where the first two designs [Fig. 5(a) and (b)] occupy an area
of 1.1 mm2 [16], [17], whereas the third layout [Fig. 5(c)]
occupies an area of 0.7 mm2 . In the improved layouts, all major
interconnections and inductors were laid out using the top metal
layer to minimize both parasitic capacitive and resistive effects.
All the dc paths in the circuit, or paths carrying high-power
signals, needed to have a very low resistance to minimize the
power losses or drop in efficiency.
The increase in width of the interconnections from the first
to the improved design can be seen in Fig. 5(a) and (b). The dc
supply connections of the output stage were very critical since
they carried the largest currents. The three topmost metal layers
were connected in parallel to provide ground and dc supply
connections with minimum resistive losses. To minimize the
parasitic capacitance of the RF input and output pads, only the
top metal layer was used. However, since this is a tuned am-
plifier, using very wide metals was not the ultimate solution for
all interconnections. For example, the interconnections between
the harmonic tuning networks of the class-F driver stage or the
output LC-tank filter of the class-E stage had to be carefully de-
signed to take into account the capacitive and inductive effects
to make sure that the tanks were still tuned after the layout.
1886 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 9, SEPTEMBER 2009

Fig. 6. Measurement setup used to test the PA designs.

The third PA design was fabricated in a six-layer-metal

0.18-m CMOS technology with a 2-m-thick AlCu top-metal
layer, which is double the thickness of the first two designs. No
other modifications have been done to the circuit or component
values, except for removing the output filter stage, which will Fig. 7. Comparison between the measured (a) output power and (b) drain
efficiency of the three layouts shown in Fig. 5 at a supply voltage of 0.8 V.
not affect the comparison to the other two circuits since the
output before the filter is being compared.
The chips were probed on-wafer using a groundsignal
ground configuration for the RF signals and a single pad for
dc connections. An Agilent-4422B signal generator was used
to provide the RF input, and an Agilent-E4440A spectrum
analyzer was used to measure the output power delivered to
a 50- output load. An HP-4145B semiconductor parameter
analyzer was used to provide the biasing and to measure the dc
power. Fig. 6 shows the measurement setup used.
Fig. 7(a) and (b) shows a comparison between the measured
characteristics of the three layouts shown in Fig. 5 at a sup-
ply voltage of 0.8 V and an input power of 1.7 dBm as
a function of the operating frequency. Improving the layout
using the InterConnect program resulted in an 8-dB increase
in output power, which corresponded to a 26% increase in
drain efficiency. The tuning of peak output power and efficiency
was also improved to be exactly at 2.4 GHz. Increasing the
thickness of the top-metal layer, while not modifying any of
the circuit component values, resulted in an increase of 2.5 dB
in output power, which corresponded to an increase of 20% in
drain efficiency due to having interconnections with almost half
the resistivity and inductors with double the quality factor, but
without increasing the parasitic capacitance.
The results from the layout improvements that are shown
in Fig. 7 could not have been realized without having accu-
rate simulations. Fig. 8(a) shows a comparison between the
measured and simulated output power and drain efficiency as
a function of the operating frequency and at a supply voltage
of 0.8 V and an input power of 1.7 dBm. The simula- Fig. 8. Comparison between the simulated and measured (a) output power and
drain efficiency () as a function of the operating frequency and (b) power gain
tions were done using Cadence Spectre RF by characterizing at an operating frequency of 2.4 GHz as a function of the input power. Both (a)
and including all the layout parasitics following the method and (b) are at a supply voltage of 0.8 V.
EL-DESOUKI et al.: IMPACT OF ON-CHIP INTERCONNECTIONS ON CMOS RF INTEGRATED CIRCUITS
Fig. 9. Circuit schematic of the 5-GHz LNA (a) without the interconnect
models and (b) with the interconnect models [17].
previously described. A comparison between the measured and
simulated power gain as a function of the input power, for a
supply voltage of 0.8 V and an operating frequency of 2.4 GHz,
is shown in Fig. 8(b). As the input drive approaches the point
at which the amplifier delivers its maximum output power and
where it is most efficient, the gain increases as a result of having
a proper switching operation. A further increase in the input
power results in a decrease in the output power when the input
exceeds the compression point.
To demonstrate the utility of our interconnection parasitic-
aware layout, we verified the design procedure with a 5-GHz
LNA in 0.18-m CMOS technology [17]. The schematic of the
LNA without and with the interconnection wires is shown in
Fig. 9. The pad capacitances and the via resistances are not
shown to avoid cluttering the figure. The LNA is a basic single-
stage topology utilizing the common technique of inductive
1887
Fig. 10. Photomicrograph of the 5-GHz LNA showing the variability of the
interconnection widths [23].
source degeneration (Ls ) to provide input matching to the 50-
source resistance. A cascode transistor has been added to isolate
the input and output signals, hence facilitating the design of
their matching networks (Lg , Cg and Lo , Co ). The inductor Li
and the capacitor Ci are used to provide the necessary interstage
matching between the input transistor and the cascode transis-
tor. Biasing is provided to the gate of M1 through an on-chip
biasing circuit, which is not shown in the figure.
The top layer metal (metal 6) was used to construct all the
interconnections. A photomicrograph of the fabricated circuit
is shown in Fig. 10, which shows the variability in the wire
widths resulting from the interconnection design approach dis-
cussed previously [17]. As shown in Fig. 9(b) and from the
photomicroph, the source degeneration inductor (0.2 nH) and
the interstage matching capacitor (30 fF) have been omitted in
the actual layout. For a 22-finger NMOS device with 2.5-m
channel width biased close to threshold, a source degeneration
inductor of 0.2-nH value is needed to realize a 50- impedance
at the input. This is a very small value for an actual on-chip
spiral inductor. The layout parasitics have been utilized instead,
and we have relied on the parasitic inductances and resistances
at the input of M1 to provide the required matching. As can be
seen in the chip photomicrograph, the interconnection between
the source of M1 and ground [interconnection number 10 in
Fig. 9(b)] was designed to be long to introduce the needed
inductance for source degeneration. The parasitic series resis-
tance of the inductor Lg and the parasitic series resistance of
the gate of transistor M1 further contribute to the real part of the
input impedance. Additionally, the capacitor Ci with a value of
30 fF has been realized using a wide metal wire rather than an
actual on-chip capacitor. Connections 4 and 5 were designed to
be wide to provide the necessary interstage matching (Ci ).
It was observed that connections 1 and 2 at the input are sen-
sitive to high parasitic resistance. The connections at the gate
of M1 and the output nodes are all sensitive to both resistances
and capacitances and were hence optimized to give the minimal
parasitic effect. The supply and ground connections were found
to be extremely sensitive to high parasitic resistance. There-
fore, they were designed using the widest possible dimension
(35 m).
1888
Fig. 11. Comparison between the measured and simulated gains (S21 ).
On-wafer S-parameter measurements were performed using
an Agilent-8722ES vector network analyzer, an HP-4145B
semiconductor parameter analyzer, and a probe station. Fig. 11
shows the measured performance characteristics together with
the simulation results of the designed LNA. The performance
of the circuit was evaluated in terms of its gain (S21 ). The peak
gain shifted and dropped slightly due to a shift in the input and
output return losses. This is suspected to be due to the very
low values of the output matching capacitor Co and the source
degeneration inductor LS . However, as can be seen from the
figure, a good match was obtained between measurement and
simulation results due to the careful consideration of the layout
effects in the simulations.
The comparison of the measured gain and the gain predicted
by the ideal simulation leads to the following observation:
the measured gain peak experienced a frequency downshift of
0.2 GHz and a decrease of 4 dB in magnitude. Following the
interconnection modeling approach, both effectsmagnitude
change and frequency shiftwere predicted and minimized,
and a good match between the measurements and the simula-
tions was finally achieved.
IV. CONCLUSION
Layout parasitics, particularly those due to metal intercon-
nections, can significantly degrade the performance of CMOS
RF ICs, particularly at gigahertz frequencies. This paper pro-
poses a simple but effective layout design procedure to carefully
account for and reduce those parasitics. When used early in the
design stage, this procedure helps in reducing the RF design
cycle significantly and in achieving a good match between
measurements and simulations. The proposed approach has
been explained and verified using a 2.4-GHz PA and a 5-GHz
LNA. The layout parasitics were accounted for during simula-
tions using the InterConnect program, which resulted in a very
good match between measurement and simulation results.
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Munir M. El-Desouki (S03) was born in Toronto,
Canada, in 1980. He received the B.Sc. degree
in electrical engineering in 2002 from King Fahd
University of Petroleum and Minerals (KFUPM),
Dhahran, Saudi Arabia, and the M.A.Sc. degree in
electrical engineering and the M.Eng. degree in en-
gineering entrepreneurship and innovation in 2006
and 2007, respectively, from McMaster University,
Hamilton, ON, Canada, where he is currently work-
ing toward the Ph.D. degree in electrical engineering.
During the summer of 2001, he was a Field
Engineer with General Electric Medical Systems. Since 2002, he has been
with the Computer and Electronics Institute, King Abdul-Aziz City for Science
and Technology (KACST), Riyadh, Saudi Arabia, where he is currently an
Electronics Researcher attending McMaster University with a scholarship from
KACST to complete his graduate studies. In April 2006, he was awarded the
Ontario Graduate Scholarship award, and in March 2006, he was awarded
the Natural Science and Engineering Research Council of Canada three-year
doctorate award. He was also awarded one patent on a project completed
during his B.Sc. degree at KFUPM. His current research interests include high-
sensitivity and ultrahigh-speed CMOS imagers and camera-on-a-chip design
for biomedical applications. His previous research interests include high-
efficiency circuits and building blocks for low-power microwave transceivers,
mixed-signal IC design, biotelemetry, and wireless sensor networks.
Mr. El-Desouki was a member of the Saudi Engineering Committee from
1998 to 1999 and the Saudi Osteoporosis Club from 1999 to 2001. He has also
been a member of the Canadian Blood Services since 2005.
Samar M. Abdelsayed (S03M06) received the
B.Sc. degree in electronics and communications
engineering from Cairo University, Cairo, Egypt,
in 2003 and the M.A.Sc. degree in electrical engi-
neering from McMaster University, Hamilton, ON,
Canada, in 2006.
During her Masters studies, she was a Teach-
ing Assistant with the Department of Electrical and
Computer Engineering, McMaster University, and
has held a research assistantship position in both
the Microelectronics Research Group and the Com-
putational Electromagnetic Research Group. She is currently with Research
In Motion Ltd., Waterloo, ON, working with the Research and Development
Team. She was a recipient of the Postgraduate Scholarship from the National
Sciences and Engineering Research Council of Canada during 20052006 on
the Masters level and during 20062007 on the Doctoral level. She is the
author of one journal and two conference proceeding publications. Her research
interests include the design, implementation, and testing of highly efficient low-
power RF blocks for low-power applications.
1889
M. Jamal Deen (F02) was born in Georgetown,
Guyana, South America. He received the Ph.D. de-
gree in electrical engineering and applied physics
from Case Western Reserve University, Cleveland,
OH, in 1985. His Ph.D. dissertation was on the
design and modeling of a new CARS spectrometer
for dynamic temperature measurements and combus-
tion optimization in rocket and jet engines, and was
sponsored by NASA, Cleveland.
He is currently a Professor of electrical and
computer engineering with McMaster University,
Hamilton, ON, Canada, and holds of the Senior Canada Research Chair in infor-
mation technology. His research interests are microelectronics/ nanoelectronics,
optoelectronics, nanotechnology, and their emerging applications.
Dr. Deen was a Fulbright Scholar (under the Latin American scholarship
program) from 1980 to 1982, an American Vacuum Society Scholar from 1983
to 1984, and a Natural Science and Engineering Research Council of Canada
Senior Industrial Fellow in 1993. He was awarded the 2002 Thomas D. Callinan
Award from the Electrochemical Society, the Distinguished Researcher Award,
Province of Ontario, in July 2001, a Humboldt Research Award in 2006, an IBM
Faculty award in 2006, and the Eadie Medal from the Royal Society of Canada
in 2008, and has won seven best paper awards. He is a Distinguished Lecturer
of the IEEE Electron Devices Society. His research record includes about
400 peer-reviewed articles (83 are invited), 14 invited book chapters, and
7 awarded patents. He is currently an Editor of the IEEE TRANSACTIONS
ON E LECTRON D EVICES , Executive Editor of Fluctuations and Noise Letters,
and a member of the Editorial Board of The Journal of Nanoscience and
Nanotechnology, the Microelectronics Journal, and the International Journal
of High Speed Electronics and Systems. He has been elected a Fellow of
The Royal Society of Canada (FRSC)The Academies of Arts, Humanities
and Sciences of Canada, a Fellow of the Canadian Academy of Engineering
(FCAE), a Foreign Fellow of the Indian National Academy of Engineering
(FINAE-Foreign), a Fellow of The American Physical Society (FAPS), a Fellow
of The Electrochemical Society (FECS), a Fellow of The American Association
for the Advancement of Science (FAAAS), a Fellow of The Engineering
Institute of Canada (FEIC), and an Honorary Member of the World Innovation
Foundationthe foundations highest honor.
Natalia K. Nikolova (S93M97SM05) received
the Dipl. Eng. degree from the Technical Univer-
sity of Varna, Varna, Bulgaria, in 1989 and the
Ph.D. degree from the University of Electro-
Communications, Tokyo, Japan, in 1997.
From 1998 to 1999, she held a Postdoctoral
Fellowship with the Natural Sciences and Engineer-
ing Research Council of Canada (NSERC), during
which time she was initially with the Microwave and
Electromagnetics Laboratory, DalTech, Dalhousie
University, Halifax, Canada, and, later, for a year,
with the Simulation Optimization Systems Research Laboratory, McMaster
University, Hamilton, ON, Canada. In July 1999, she joined the Department
of Electrical and Computer Engineering, McMaster University, where she is
currently a Professor. Her research interests include theoretical and computa-
tional electromagnetism, inverse scattering, and microwave imaging, as well
as methods for the computer-aided analysis and design of high-frequency
structures and antennas.
Dr. Nikolova was the recipient of a University Faculty Award of NSERC
from 2000 to 2005. Since 2008, she has been a Canada Research Chair in high-
frequency electromagnetics. She is a member of the Applied Computational
Electromagnetics Society and the International Union of Radio Science.
1890 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 9, SEPTEMBER 2009

Yaser M. Haddara (S85M97) received the

B.Eng. degree in electrical engineering from the
Memorial University of Newfoundland, St. Johns,
NB, Canada, in 1991 and the M.S. and Ph.D. degrees
from Stanford University, Stanford, CA, in 1993 and
1997, respectively.
He was a Postdoctoral Research Associate with
the University of Florida, Gainesville, and a Senior
Engineer in the device group with Cypress Semicon-
ductor. Since 2002, he has been with McMaster Uni-
versity, Hamilton, ON, Canada, where he is currently
an Associate Professor in electrical and computer engineering. His research
interests are in front-end silicon and silicongermanium process modeling,
technology CAD, polymer semiconductor devices and processing, and RF
circuit design. His teaching interests are in microelectronics, device physics,
process modeling, and probability and statistics.