Carrier Phase Shifted SPWM for CMV reduction In
a three-level inverter using Open-end winding
induction motor drive
Narendra Kumar G and S. Srinivas, Member, IEEE
Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai, India
Email: eeI5s036@ee.iitm.ac.in
Abstract-Dual two-level inverter can synthesize three-level
output voltage. Carrier phase-shifted sinusoidal pulse width
modulation (SPWM) is proposed in this paper by exploiting the
idea of using both phase shifted modulating signals and also
phase shifted carrier signals for the dual two-level inverter. The
proposed pulse width modulation (PWM) method is aimed at
reducing the common mode voltage (CMV) generated by the dual
two-level inverter. The implementation of the proposed PWM is
simple as it involves a simple comparison of modulating and
carrier signal. A significant reduction in the peak to peak value
ofthe CMV is achieved which is as high as 66.66 % with the use of
the proposed PWM compared to existing SPWM. The proposed
carrier based PWM is first simulated using MATLAB/Simulink
and experimentally validated using a laboratory prototype of a
dual two-level inverter feeding a 3- open-end winding induction
motor drive.
Index Terms - Dual-inverter, Open-end winding induction
motor, Phase shifting carriers, Common mode voltage, Pulse
width modulation .
I. INTRODUCTION
Pulse width modulated voltage source inverters are widely
utilized in variable speed motor drive applications for speed
and torque control. Their popularity grew owing to their simple
and energy efficient control with good output voltage quality.
In low and medium power drives, higher switching frequencies
are attempted to further improve the output voltage quality.
This however, increases the switching power losses in the
inverters and is also known to contribute to increased CMV
generation from the inverters leading to high motor shaft
voltage, premature bearing damages and other conducted elec-
tromagnetic interference issues [1] . Many PWMs are reported
in the literature for the conventional three-phase two-level
inverters that suggest use of passive filters [2] at the motor load
end to mitigate CMV related problems. Such methods though
effective, have the drawback that they demand added hardware.
Alternative approaches are also available in the literature that
includes the use of reduced CMV PWM techniques [3] for
the two-level inverters. Recently, a new carrier based PWM
was reported for the two-level inverter that uses phase shifted
carrier signals for the implementation of sinusoidal PWM
(SPWM) aimed at reducing the CMV in the inverter drive
[4].
In addition to the improvisations in the PWM switching
strategies, use of multilevel inverters such as neutral-poi nt-
978-1-5090-2597-8/16/$31.00 2016 IEEE
clamped inverter, capacitor-clamped inverter, series and cas-
caded H-bridge inverters etc. are also being researched to
further improve the output voltage quality of the inverter drives
[5] . In addition, methods to reduce CMV are also reported for
multilevel inverters in [6].
The power circuit involving a dual two-level inverter using
open-end winding induction motor drive was reported in [7]
which falls under the series connected H-bridge configuration
that increased researchers attention in the recent times. This
primarily is due to the fact that it does not suffer from any
neutral point fluctuation, capacitor initialization and balancing
problems etc. that are known to be the key disadvantages of
the other equivalent power circuit configurations listed above
[8] . Many PWM switching techniques are reported for this
dual-inverter power circuit using both the space vector as
well as scalar based approaches. While it is reported that the
two inverters can be controlled with tight coupling between
them [8]- [9], it is also shown that they can be controlled
independently following different PWM control strategies as
in [10]. In the recent times, it is reported that zero-sequence
voltage and CMV in this dual-inverter power circuit are
noticeably different [10]. It also reports many space vector
based PWM methods in order to reduce CMV. Further, use
of passive filters for reduced CMV is also reported for this
dual-inverter topology in [11].
This paper presents a simple, scalar based SPWM approach-
for the dual inverter topology by exploiting the idea of phase
shifted carriers and modulating signals for reducing the CMV
in the drive. The proposed reduced CMV PWM switching
scheme is simple to implement and its effectiveness to reduce
CMV in the dual-inverter topology are critically analyzed, sim-
ulated and experimentally validated on a laboratory prototype
II. DUAL-INVERTER CONFIGURATION DRIVING OPEN-END
WINDING INDUCTION MOTOR (OEWIM)
Open-end winding induction motor is obtained by removing
the star point of it's three-phase stator windings to facilitate
the dual-inverter topology to be fed from both its ends. The
open-end winding induction motor is shown in Fig.l and it is
connected to two two-level, 3- voltage source inverters from
both its ends. There exists 8 switching combinations for each
individual inverter (Fig 1). Thus, a total of 64 combinations
exist for the dual-inverter [8]. Each inverter leg in Fig. 1 can
707
 ,--- ---------- ----- ------- --- -----
Open end winding

Induction machine

Vdd2
Sal a I ~b' I ~c, I /~-'" I I I a'Sa2
bl ~~~~------~ b'
CI - C'
Vdd2
--- '"
~,,-
. "

o ,--------------------------------- 0'

Fig. 1: Dual two-level Inverter feeding open end winding induction motor

independently attain a voltage of +Vdc/2 or that depends

upon whether the top switching device is turned on or the
modulating signal and a high frequency carrier signal for the
generation of gating pulses to the inverter switching devices.

bottom switching device. Thus, the dual inverter can generate This typically comprises of a sinusoidal modulating signal and
three voltage levels viz. Vdc, and - Vdc that can be obtained a triangular carrier signal in SPWM method. In general, for
as the difference between the pole voltages (of same phase) an m-level inverter, if SPWM were to be used, it typically
of the two two-level inverters. The CMV generated by the involves (m - 1) level shifted carrier signals and a sinusoidal
dual-inverter can be mathematically given in terms of the two modulating signal for the generation of gating pulses of each
two-level inverter pole voltages as in [11] as : phase of such m-level inverter [12] .
Dual two-level inverter was first proposed for obtaining
V V aa + Vba + V ca + va' a' + Vb' a' + V c' a' three-level inversion in [7]. Later, the choice of splitting the
C MV = 6 (1)
desired space vector into two equal halves to be synthesized
where V aa ' Vba , V ca are the three phase pole voltages of by the individual two-level inverters using SVPWM, SPWM
inverter-l and for inverter-2.
va' a' , Vb' a' , Vc ' a' and other hybrid PWM methods was reported in [8]- [10].
The carrier-based approach using two independent reference-
The CMV generated by the dual two-level inveter for a modulating signals of equal and opposite magnitudes and
given switching combination is explained for easy understand- using one single carrier signal was recently reported in [13].
ing. For instance, for a switching combination 15' of the dual However, there is no mention of CMV problem in [13].
inverter, inverter-l attains the state 1 ( + - - )whereas inverter- Keeping this in mind, this PWM is taken as reference in
2 the state 5' (- - +). Here, a '+' means the top switching paper and is brietly presented here. The carrier based SPWM
device is turned on whereas a ' - ' means, it is turned off. As a implementation principle for the dual inverter using two 180 a
result, CMV can be calculated for this switching combination phase shifted sinusoidal modulating signals and one carrier
using (1) as: signal for the generation of gating pulses is depicted in Fig. 2.
Comparison of modulating signal' m a l ' and carrier signal' c'
Va a =
Vd c
+2 ' Vba = 0, V ca = (Fig. 2) determines the gating pulse generation for a-phase leg
of inverter-l and the modulating signal ' m a 2' and the carrier
Vdc
V , ,
a a
= 0, Vb' ,
a
= 0, V , ,
ca
= +- 2 signal' c' (Fig. 2) determines the gating signal generation for
same phase leg of inverter-2. In a similar manner, the other
Vdc
VC M V =+ 6 modulating signals can be used to control the other phases
of the dual two-level inverter using SPWM control scheme.
Considering all the 64 switching combinations present for the
The gating signal generating to the top switching devices
dual two-level inverter, CMV generated for each switching
of the two, three-phase inverters (Fig. 1) and the resulting
combination is obtained using (1) and are tabulated in Table-
V C MV (p _u) (normalized to Vdc) using Table-I is also presented
I. In Table-I, 1, 2 .. ,7, 8 are switching states of Inverter-l and
1' , 2' .. , 7' , 8' are switching states of Inverter-2.

in Fig. 2. It can be found from Fig. 2 that VC M V attains a peak
value of +Vdc/2 at some time and at the other extreme.
III. SINUSOIDAL PULS E WIDTH MODULATION (SPWM)
USING SINGLE CARRIER FOR THE DUAL TWO-LEVEL IV. PROPOSED SPWM USING PHASE SHIFTED CARRIERS
INVERTER FOR THE TWO LEVEL DUAL-INVERTER
It is well known that scalar PWM approach or carrier The principle of the carrier phase shifted PWM for the two-
based PWM implementation involves a simple comparison of level inverter was reported in [3] and its improvised version

708 20161 Region 10 Conference (TNCON) - Proceedings of the International Conference

 TABLE I: CMV contribution from the Dual two-level Inverter in Fig. I

States 1'(+- -) 2'(++-) 3'(-+-) 4'(-++) 5'(- -+) 6'(+-+) 7'(+++) 8'(- --)

Vdc Vdc Vdc Vdc Vdc V dc Vdc Vdc

1(+ --) +- +- +- +- +- +- +- + 12
6 4 6 4 6 4 3
Vdc Vdc Vdc Vdc Vdc V dc 5 Vdc V dc
2(++-) +- +- +- +- +- +- + -- +-
4 3 4 3 4 3 6 6
Vdc Vdc Vdc V dc Vdc V dc V dc V dc
3(-+-) +- +- +- +- +- +- +- +-
6 4 6 4 6 4 3 12
Vdc Vdc V dc V dc Vdc V dc 5 Vdc V dc
4( -++) +- +- +- +- +- +- + -- +-
4 3 4 3 4 3 6 6
V dc V dc V dc V dc V dc V dc V dc V dc
5(- -+) +- +- +- +- +- +- +- +-
6 4 6 4 6 4 3 12
Vdc Vdc V dc V dc Vdc V dc 5 Vdc V dc
6(+-+) +- +- +- +- +- +- + -- +-
4 3 4 3 4 3 6 6
Vdc 5Vdc V dc 5Vdc Vdc 5 Vdc V dc V dc
7(+++) +- + -- +- + -- +- + -- +- +-
3 12 3 12 3 12 2 4
V dc Vdc V dc V dc V dc V dc V dc
8(- - - ) +- +- +- +- +- +- +- 0
12 6 12 6 12 6 4

m",
:::i,Eo
mbl//
nmnnmm
_~
0~
7/
1

'" . " , ,
~ m
, ~.mmmumB~
'~
,

'"

,',
...
::t
m~,; 0I,,~
, '~~
~>xu.f , /J,..f~
1, 7),
,
'"
~
m el/
#
m bV .~ ,
m a2 m el!
m a2

Sal sal

Sbl Sbl" I

Sel
Sel~ i
sa2
Sa2" I

Sb2
Sb2" I I
sc2
U

~J .. 1 1. 'i l
Sel I ::
:

;J
3
:::.
~
f:;l li(),,,,,
i.:
Ii I?, ~ ~j~ -. ""11...,,,. ... """.
o '"
Fig. 2: Principle of the SPWM using single carrier, gating Fig. 3: Principle of the SPWM using proposed phase shifted
pulse pattern and VCM V for dual two-level inverter carrier, gating pulse pattern and VC MV for dual two-level
inverter

in [4]. The principle used is similar to the space vector based

PWMs reported for two-level inverter in [3] wherein the PWM avoiding the use of null-states of the three-phase inverter which
successfully reduces the peak of the CMV by appropriately are known to the cause of high CMV in the two-level inverter.

20161 Region 10 Conference (TNCON) - Proceedings of the International Conference 709

 20:

0,032 0,064 0,096 0,144

20:

0,032 0,064 0,096 0,144

20t"IIIUUIII" I I II !I!~!I I I I!I """I111"""""UII" I I I ! !~ ! !I I I """""'' ' ,'' ' ' ",I'I I II!~!~
-200
0,032 0,064 0,096 0,144
(a) (b)

Fig. 4: (a) Simulation results (b) experimentally obtained results of vao(top), va'o,(middle) and vaa,(bottom) for m i=0.75

litk Sto

"~~~~I~~
200
~ . . . ~
1O~IIIIIII~IIIIIIIIIIIW!UIIII~IIIII!IIIIIIBIIIIII:"~III1IIIIIIIB~llllllIIm!llIlIl~IIIIIIIIII~\IIIIIIIIIIIIWIIIIIIIIIIII!lfl1li'11I1I1I1IIIIIIMII:'IIIIIIIIIHIIIII ~f

fO-:-Oms fMkl,-, - -1- f - ...-::ZO-funll

0.032 0.064 0.096 0.144 '-0-0-" ro--:-OrtlS IOkoolnts - 010.0 v JI5:33:52

(a) (b)

Fig. 5: (a) Simulation results (b) experimentally obtained results of Van (top) and vCMv (bottom) for m i=0.75

200

100

0.032 0.064 0.096 0.144

(a) (b)

Fig. 6: (a) Simulation results (b) experimentally obtained results of VCMV for m i=0.75 using the PWM reported in [13]

This paper proposes a new PWM method by adopting the of the dual two-level inverter (Fig. 1).Here m a 2, mb2 and
phase-shifted carrier signals reported in [4] and also the use me2 are 1800 phase shifted versions of mal, mbl and mel,
of SPWM principle presented in the preceding sub-section. respectively.
The principle of the proposed carrier-phase shifted SPWM for
the dual two-level inverter is depicted in Fig. 3. The proposed
scheme consists of three carriers CI(t) , C2 (t) and C3(t), phase CI (t) sin (wet)
shifted by 2 7r /3 radians with respect to each other and have 27r
a frequency of We and are given by (2).
C2(t) sin (wet - :3)
In Fig. 3, comparison of m al, m a 2 and CI determines the 27r
gating signals for the switching devices of a-phase of the dual-
C3 (t) sin(wet + :3) (2)

inverter (Fig. I). Similarly, mbl , mb2 and C2 determines the The gating signals to the top switching devices and the
gating signals for the b-phase and finally mel , m e 2 and C3 resulting VCMV is also shown in Fig. 3 and it can be seen
determines the gating signals for the c-phase switching devices that with the proposed carrier phase shifted PWM for dual

710 20161 Region 10 Conference (TNCON) - Proceedings of the International Conference


140 .. - _ _
. _-- -... / with Ihe PWM reported in [13J
120
"',
.,
..
100
Q "'~
, ~~
~ Cj'O
80
t?
"',
60
with the proposed PWM
40
--
20L
I ____- L_ _ _ _- L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _L __ _ _ _L __ _
~ ~ ~ ~
o 0. 1 0.2 0.3 0.4 0.5 0.6 0.7
Fig. 7: % THD in phase voltage using the proposed carrier
phase shifted SPWM and single carrier SPWM for different
m i
two-level inverter, V C MV attains a peak value of +Vdc/3 and
+ Vdcl6 at the other times.
V. RESULTS AND DISCUSSIONS
To test the performance of the proposed carrier phase-
shifted SPWM for the dual two-level inverter feeding a
1.1 kW, 415 V , 2.5 A, 50 H z, 3-<jJ , open end-winding induc-
tion machine, constant V / f control is employed in the linear
modulation region of the motor drive, for its speed control. The
proposed PWM is first simulated using MATLAB/Simulink.
The gating signals are generated using a digital platfonn
based on TMS320F240 processor. The DC bus voltage 'Vdc'
of the dual two-level inverter is chosen equal to 400 V and
a maximum switching frequency of 1.15 kHz is chosen at
m i=l. Here, m i is the ratio of peak of the modulating signal
of the dual inverter to the peak of the carrier signal. Also, the
number of carrier signals in one modulating signal is always
chosen equal to 23, irrespective of the value of m i.
Firstly, simulation results of the a-phase pole voltage of
the two two-level inverters i.e., Vao and v a' 0' are obtained
along with the resulting a-phase dual-inverter output voltage
for m i =0 .75 and are shown in Fig. 4a. The experimentally
obtained results of the same are shown in FigAb. Due to the
use of two isolated DC power supplies for the dual-inverter,
the zero-sequence voltage gets dropped between 0 and 0 ' (Fig.
1) and the motor a-phase voltage is obtained as shown in
Fig. 5a along with the CMV generated by the dual-inverter
scheme. The experimental results of the same are shown in
Fig.5b for a quick comparison. It can be seen from Figs.
5a-5b that the motor phase voltage and CMV profile match
with each other. From the bottom traces of Figs. 5a-5b, it can
be clearly seen that the CMV varies between voltage levels
+ 133.33 V and + 66.66 V i.e. + V dc/3 and + V dc/ 6 while
using the carrier phase shifted SPWM proposed in this paper.
In order to critically compare the CMV results obtained using
the carrier phase-shifted SPWM proposed in this paper with
the SPWM reported in [13], both simulated and experimental
20161E Region 10 Conference (TENCON) - Proceedings of the International Conference
Existing PWM scheme
,.
200
~
'"
'0'
'" :;::'"
~
<oj .~
"'~
.s"'-
""
<oj
ce
~
0.8 0.9
m., 0.2 0.4 0. 6 0.8 1.0 m;
Fig. 8:Peak to peak values of VCM V with the proposed carrier
phase shifted and single carrier SPWM for different m i
CMV wavefonns for same m i of 0.75 are obtained and shown
in Fig.6. It can be seen from Fig. 6 that CMV varies between
voltage levels + 200V and OV i.e.,+Vdc/2 and O. From
Figs.5b and 6b it can be clearly observed that the peak to peak
value of the CMV levels is drastically reduced from 200 V to
66.66 V, which is a significant 66.66 % reduction. To study
the performance of the proposed PWM and compare the same
with the single carrier SPWM, the total harmonic distortion
(% THD) in the output voltage of the dual two-level inverter
and VCM V are obtained and presented in Fig. 7 and Fig. 8
respectively. The THD in phase voltage is calculated using
(3) and the same are shown in Fig. 7 for quick comparision.
It may be appreciated that with the proposed PWM, not only
that VC MV reduces at any m i value (Fig. 8), the THD in output
voltage is also improved (Fig. 7). Thus, the usefulness of the
carrier phase-shifted SPWM proposed in this paper is clearly
demonstrated.
(%) THD ylV22 + Vl + Vi + ... * 100 (3)
VI
where VI , V2 , V3 , V4 are the RMS values of the funda-
mental, second, third, fourth harmonics, etc. respectively in
the phase voltage considerd.
VI. CONCLUSION
Carrier phase shifted SPWM for a dual two-level inverter
is proposed in this paper by exploring the combination of
both phase shifted modulating signals and also phase shifted
carrier signals. The gating signal generation using the proposed
PWM involves a simple comparison of modulating and carrier
signal making it fairly simple to implement. The use of the
PWM proposed in this paper manages to reduce the CMV
generated from the dual two-level inverter. The peak to peak
value of CMV is reduced successfully by as much as 66.66 %.
On account of the significant reduction in the peak value of
CMV, together with the rate of change of CMV itself, the
bearing current issues that otherwise may flow in the open-
end winding induction motor drive may be less severe when
711
using the carrier phase shifted SPWM proposed in this paper.
The effectiveness of the proposed PWM is demonstrated using
simulations and are verified experimentally.
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712 20161 Region 10 Conference (TNCON) - Proceedings of the International Conference