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Analog to Digital
Converters (A/D)
Successive Approximation Type Analog to Digital
Converter
A successive approximation A/D converter consists of a comparator, a successive approximation register
(SAR), output latches, and a D/A converter. The circuit diagram is shown below.

Successive Approximation Type Analog to Digital Converter

The main part of the circuit is the 8-bit SAR, whose output is given to an 8-bit D/A converter. The analog output
Va of the D/A converter is then compared to an analog signal V in by the comparator. The output of the
comparator is a serial data input to the SAR. Till the digital output (8 bits) of the SAR is equivalent to the analog
input Vin, the SAR adjusts itself. The 8-bit latch at the end of conversation holds onto the resultant digital data
output.

Working
At the start of a conversion cycle, the SAR is reset by making the start signal (S) high. The MSB of the SAR
(Q7) is set as soon as the first transition from LOW to HIGH is introduced. The output is given to the D/A
converter which produces an analog equivalent of the MSB and is compared with the analog input V in.
If comparator output is LOW, D/A output will be greater than V in and the MSB will be cleared by the SAR.
If comparator output is HIGH, D/A output will be less than V in and the MSB will be set to the next position (Q7 to
Q6) by the SAR.
According to the comparator output, the SAR will either keep or reset the Q6 bit. This process goes on until all
the bits are tried. After Q0 is tried, the SAR makes the conversion complete (CC) signal HIGH to show that the
parallel output lines contain valid data. The CC signal in turn enables the latch, and digital data appear at the
output of the latch. As the SAR determines each bit, digital data is also available serially. As shown in the
figure above, the CC signal is connected to the start conversion input in order to convert the cycle continuously.

The biggest advantage of such a circuit is its high speed. It may be more complex than an A/D converter, but it
offers better resolution.

http://www.eleccircuit.com/analog-to-digital-converter-circuit-using-simple-parts/
18/02/2017

Usually an analog to digital converter circuit or A/D that need to use the high accurate devices
and and high difficult. But this circuit, The error of all devices does not affect the accuracy of the
circuit. We just use the reference voltage only.

How it works

The CA3130 op-amp IC1 is assembled as the comparator circuit. Thus if voltage at the inverting
input less than the analog signal at the non-inverting input. The output will be 1 and when FF1
get pulse from the clock pulse generator. Which include of N1 and N2.
Fig. 1: Schematic diagram of Analog To Digital Converter Circuit Using Simple Parts
While input D of FF1 is still 1 by result of IC1, so cause the output Q is also 1. The CMOS
switch S1 will close circuit, at the same time S2 open circuit. Thus, the capacitor-C2 is charged
by the reference voltage (Uref), that by through S1 and R2.

When the C2s voltage same voltage at the non inverting input, cause the IC1s output will be
0. But C2 still continue charging until the next circle clock into the circuit, then cause the output
Q of FF1 is 0, S1 open circuit and S2 close circuit.
This time C2 will discharge through R2,R5 and S2 until voltage at C1 reduce lower than the
analog input. And when output of IC1 is 1 again that next cycle, output Q of FF1 will be 1
again and the same operational continually.

Since the capacitor C2 is charged and discharged in exponential form. Thus the signal input is
long times C2 will get the charging, and C2 will discharge in short times range.

This result cause output of IC1 has square waveform that duty cycle is proportion with analog
input. However, the circuit is working properly, only the first input, C1 is charged up, the voltage
across it is zero.

When switch to Start is pressed, Signal change will start,begin with set value to FF2 cause IC5
and IC6 that is counter circuit, start up both Ics acts as the pulse counter. IC6 will count all
pulse, but IC5 will count while output Q of FF1 is 1 only.

When output Q12 of IC6 is 1 FF2 will be reset and changing will be end. The number of cycle
at IC5 count will be proportional to the duty cycle from output Q of FF1. Which is related to the
analog input..

If reference voltage is 2.048 fitted, IC5 will the 1000 fitted, same the input is 1V. By value a
linear change of 1%. Because this circuit IC1 is used Ob Amps (Numbers LF357). Therefore, it
requires a symmetrical dual supply well. For the frequency of the clock signal in this circuit can
be changed. By changing the value of C3 (lowest 390 pF at 50 Hz).

Adjustment and Usage

For tuning the circuit to short circuit input to ground, then adjust P1 until the counting from IC5 is
0. And the testing all by take the reference voltage into the analog input, at output of IC5 will
must be 1 all pins (can count as 2047)

How to builds
First of all, you need to buy all parts then make the PCB
Fig. 2: The actual-size of Single-sided Copper PCB layout

Next assemble all parts on PCB as components layout.

Fig. 3: The components layout of this projects.

Parts you will need

IC1___CA3130___Op Amp, BiMOS, MOSFET Inputs, CMOS Outputs, 15MHz
IC2___CD4013___CMOS DUAL D-TYPE FLIP-FLOP
IC3___CD4066___Quad Analog Switch/Multiplexer/Demultiplexer
IC4___CD4023___Buffered Triple 3-Input NAND/NOR Gate
IC2_________CD4040___12 Stage Binary Ripple Counter DIP-16
C1,C2_____0.47uF 50V___Ceramic capacitor
C3________0.0022 50V___Ceramic capacitor
C4________1uF 35V_____Tantalum capacitor
C5_________100pF 50V____Ceramic capacitor
C6_________0.001uF 50V____Ceramic capacitor
ETC