UNIVERSIDADE DE PERNAMBUCO

Escola Politcnica de Pernambuco

Eletrnica Digital

Autores:

- GRUPO 3 -

Eduardo Miranda Silva

Andre Felipe Dantas de Matos
Nelson de Aquino Albuquerque Neto
Carlos Eduardo Arajo Diniz Filho

PROJETO DE DETECTOR DE MAGNITUDE RELATIVA COM

SADA PARA DISPLAYS LCD DE 7 SEGMENTOS

Recife, PE
2017
 UNIVERSIDADE DE PERNAMBUCO
Escola Politcnica de Pernambuco
Eletrnica Digital

Autores:

- GRUPO 3 -

Eduardo Miranda Silva

Andre Felipe Dantas de Matos
Nelson de Aquino Albuquerque Neto
Carlos Eduardo Arajo Diniz Filho

PROJETO DE DETECTOR DE MAGNITUDE RELATIVA COM

SADA PARA DISPLAYS LCD DE 7 SEGMENTOS

Projeto para composio da nota

do 1 EE de Eletrnica Digital
2017.1

Orientador: Prof. Reginaldo Pereira Leal

Recife, PE
2017
 RESUMO

Este trabalho documenta a soluo da questo 4.25 do livro Sistema

Digitais: Princpios e Aplicaes (11 Edio, Tocci, Widmer & Moss). A
abordagem foi feita pelos integrantes do grupo III, atendendo s exigncias de
projeto pedidas pelo professor orientador, usando os conhecimentos de
circuitos lgicos absorvidos nas aulas. Primeiramente, o problema foi
analisado, para depois serem elaboradas as solues completas, com tabelas-
verdade, mapas K, equaes lgicas e circuitos. A equipe tambm simplificou
o circuito e as equaes, quando isso era possvel, e depois simulou o circuito
no software NI MULTISIM. Aps a simulao, o circuito foi montado em
protoboard e testado. Ao final do trabalho, foram verificados os resultados
prticos com os tericos, a fim de determinar se todas as exigncias foram
suficientemente atendidas
Palavras-chave: Detector de Magnitude Relativa. Circuitos Lgicos. Display 7
segmentos. Eletrnica Digital.
 SUMRIO

1. INTRODUO ........... 4
2. METODOLOGIA ..... 5
3. RELATRIO TERICO ....
3.1. Tabela-verdade ...................................................................
3.2. Mapa K ..............................................................................
3.3. Equaes Lgicas ..............................................................
3.4. Circuito Lgico ...................................................................
3.5. Circuito Eltrico .................................................................
4. SIMULAO NO MULTISIM ......
5. RELATRIO PRTICO .................................................................
5.1. Montagem ...........................................................................
5.2. Testes .................................................................................
6. VERIFICAO DE RESULTADOS ................................................
7. CONCLUSO ................................................................................
8. RELAO DE MATERIAIS E ORAMENTO.................................
9. APNDICES ..................................................................................
10. REFERNCIAS .............................................................................
 1. INTRODUO

Um circuito integrado um dispositivo microeletrnico que consiste de

muitos transistores e outros componentes interligados capazes de
desempenhar muitas funes. Suas dimenses so extremamente reduzidas,
sendo os seus componentes formados em pastilhas de material semicondutor.
A importncia da integrao est no baixo custo e alto desempenho,
alm do tamanho reduzido dos circuitos aliado alta confiabilidade e
estabilidade de funcionamento. Uma vez que os componentes so formados
ao invs de montados, a resistncia mecnica destes permitiu montagens cada
vez mais robustas a choques e impactos mecnicos, permitindo a concepo
de portabilidade dos dispositivos eletrnicos.
Com o uso desses minsculos CIs, a Eletrnica Digital nos permite criar
uma infinidade de sistemas, capazes de realizar operaes que vo de imitar o
som da chuva, at transmitir ligaes de uma estao espacial a uma base na
Terra. Atravs de diagramas, equaes e mapas possvel representar as
operaes algbricas booleanas presentes em qualquer sistema. Hoje em dia,
a eletrnica digital est presente em praticamente todas as tecnologias, e
continua em evoluo.

Objetivos

O objetivo desse projeto montar um circuito capaz de comparar e

indicar em Displays LCD, se dois nmeros binrios de 3-bits x2x1x0 e y2y1y0 so
iguais entre si, maiores ou menores que o outro. A questo correspondente a
4-25, como segue:
As exigncias de projeto so:
Se X = Y, o display deve mostrar G e os outros displays devem ser
apagados;
Se X > Y, o display deve mostrar A e os outros displays devem ser
apagados;
Se X < Y, o display deve mostrar E e os outros displays devem ser
apagados;
O circuito do Detector de Magnitude Relativa deve ser completamente
digital;
Usar Displays de 7 segmentos.
Especificamente para o GRUPO III:

Utilizar na montagem somente portas NAND e circuitos integrados ALS.

2. METODOLOGIA

A primeira fase do projeto consistiu em montar a tabela-verdade. Para

isso, tabelou-se todas as possibilidades de combinao dos sinais binrios de
3 bits de entrada, e a cada linha somente uma das trs sadas seria nvel
ALTO(Mapeamos os mintermos). Em seguida, para a montagem dos Mapas
K, utilizou-se ajuda computacional devido ao tamanho do mapa, o que facilitou
o processo pois para cada sada do problema, so necessrios 64 quadrculos,
o que seria muito trabalhoso e sujeito a falhas, se feito mo.
Aps a criao dos Mapas K, o mesmo programa forneceu a equao de
sada no modo SOP(Soma de Produtos). Foi necessrio simplificar e
reescrever a equao para melhorar a montagem.

3. RELATRIO TERICO

3.1. Tabela-verdade

A tabela-verdade do problema composta de 6 variveis e 3 sadas, e

segue as seguintes premissas:

Se X = Y M ALTO; N BAIXO; P BAIXO

Se X > Y M BAIXO; N ALTO; P BAIXO
 Se X < Y M BAIXO; N BAIXO; P ALTO
Linha X2 X1 X0 Y2 Y1 Y0 M N P
s
0 0 0 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 0 1
2 0 0 0 0 1 0 0 0 1
3 0 0 0 0 1 1 0 0 1
4 0 0 0 1 0 0 0 0 1
5 0 0 0 1 0 1 0 0 1
6 0 0 0 1 1 0 0 0 1
7 0 0 0 1 1 1 0 0 1
8 0 0 1 0 0 0 0 1 0
9 0 0 1 0 0 1 1 0 0
10 0 0 1 0 1 0 0 0 1
11 0 0 1 0 1 1 0 0 1
12 0 0 1 1 0 0 0 0 1
13 0 0 1 1 0 1 0 0 1
14 0 0 1 1 1 0 0 0 1
15 0 0 1 1 1 1 0 0 1
16 0 1 0 0 0 0 0 1 0
17 0 1 0 0 0 1 0 1 0
18 0 1 0 0 1 0 1 0 0
19 0 1 0 0 1 1 0 0 1
20 0 1 0 1 0 0 0 0 1
21 0 1 0 1 0 1 0 0 1
22 0 1 0 1 1 0 0 0 1
23 0 1 0 1 1 1 0 0 1
24 0 1 1 0 0 0 0 1 0
25 0 1 1 0 0 1 0 1 0
26 0 1 1 0 1 0 0 1 0
27 0 1 1 0 1 1 1 0 0
28 0 1 1 1 0 0 0 0 1
29 0 1 1 1 0 1 0 0 1
30 0 1 1 1 1 0 0 0 1
31 0 1 1 1 1 1 0 0 1
32 1 0 0 0 0 0 0 1 0
33 1 0 0 0 0 1 0 1 0
34 1 0 0 0 1 0 0 1 0
35 1 0 0 0 1 1 0 1 0
36 1 0 0 1 0 0 1 0 0
37 1 0 0 1 0 1 0 0 1
38 1 0 0 1 1 0 0 0 1
39 1 0 0 1 1 1 0 0 1
40 1 0 1 0 0 0 0 1 0
41 1 0 1 0 0 1 0 1 0
42 1 0 1 0 1 0 0 1 0
43 1 0 1 0 1 1 0 1 0
44 1 0 1 1 0 0 0 1 0
45 1 0 1 1 0 1 1 0 0
46 1 0 1 1 1 0 0 0 1
47 1 0 1 1 1 1 0 0 1
48 1 1 0 0 0 0 0 1 0
49 1 1 0 0 0 1 0 1 0
50 1 1 0 0 1 0 0 1 0
51 1 1 0 0 1 1 0 1 0
52 1 1 0 1 0 0 0 1 0
3.2. Mapa K e equaes lgicas
Para a simplificao das equaes da tabela verdade, foi utilizado o
mtodo do Mapa de Karnaugh.
Para x = y
= (!A*B*!C*!D*E*!F)+(!A*B*C*!D*E*F)+(!A*!B*!C*!D*!E*!F)+(!A*!B*C*!D*!E*F)
+(A*!B*!C*D*!E*!F)+(A*!B*C*D*!E*F)+(A*B*!C*D*E*!F)+(A*B*C*D*E*F)

Para x > y
= (A*C*!E*!F)+(A*B*C*!F)+(B*!D*!E)+(B*C*!D*!F)+(A*!D)+(C*!D*!E*!F)+(A*B*!
E)

Para x < y
 = (!A*D)+(!A*!B*!C*F)+(!A*!B*E)+(!A*!C*E*F)+(!B*!C*D*F)+(!B*D*E)+(!
C*D*E*F)

3.3. Equaes Lgicas

PRIMEIRA TENTATIVA:
 Aps levantar as equaes de sada pelos mapas, notou-se que
escolhendo duas sadas a restante poderia ser obtida apelas pela utilizao de
lgica NOR onde as entradas so as duas funes levantadas anteriormente.
Com esse racioccio, possvel enxugar o circuito. Foi necessrio converter
uma porta lgica NOR para portas NAND para fazer esse arranjo.

Outro passo importante foi utilizar teorema de De Morgan para adequar

as sadas utilizao de portas NAND. As esquaes finais sero mostradas a
seguir. Outro passo a se notar que foram selecionadas as sadas N e P para
serem montadas e a sada M foi escolhida para ser a sada da lgica NOR
onde N e P so as entradas. Isso se deve ao fato de que a sada M era de
difcil simplificao e necessitava de mais termos para ser escrita.
As sadas so:

( )
N=( x2 . y 2) .( x2 . x1 . y 1 . x 0 . y 0 ). ( x 2 . x 0 . y 1 . y 0 ) . ( y2 ( x 0 . y 0 ( x1 . x0 )( x 1 . y1 ) ))

Que vai para o display A.

x0 . y 0

y ()
1

x1 ( )

y 2 (). ( x2 . x0 . y 1 . y 0) . ( y 2 . x 1 . y 1) .( x0 . y 0 . y 2 ( x 1 . y 1))
x2


P=

Que vai para o display E.

Com essas funes montamos o seguinte circuito:

 Porm essa montagem alm de grande e complexa, apresentou falha na
montagem em protoboard apesar de ter funcionado corretamente no simulador
Multisim.
Optou-se por repensar o circuito e conversar com o orientador prof.
Reginaldo Pereira para sanar possveis erros de projeto e montagem.

SEGUNDA TENTATIVA:

Porm, aps a montagem do circuito no simulador e ter conversado com

o professor orientador, notou-se que havia uma soluo mais simples para o
problema do projeto. A soluo baeava-se em comparar bit a bit os dois sinais
de entrada(x e y) atravs de uma lgica XOR(Ou exclusivo) e invertendo o
sinal de sada. Essa configurao permite detectar sinais de magnitudes
iguais, dando o sada M(Dispay G).

Escreve-se a sada G como:

G=(x 2 y 2 . x 1 y 1 . x 0 y 0)

Feita essa observao, percebemos tambm que poderamos usar essa

lgica para comparar sequencialmente cada bit das sinais x e y de entrada, do
mais significativo para o menos significativo, utilizando uma lgica and onde as
entradas so o sinal advindo da comparao via lgica XOR dos dois dgitos
de mesma magnitude do sinal de entrada(exemplo: x 2 e y 2 ) e o dgito que se

quer analisar( x 2 ou y 2 ). Utilizou-se a anlise do caso Y>X e para a sada

restante, utilizou-se do artifcio com lgica NOR comentado no incio dessa
seo.
3.4/3.5 Circuitos Lgico e Eltrico
(Circuito Lgico com displays).
(Circuito Eltrico dos Displays.)
 Os displays escolhidos foram de 7 segmentos com Ctodo Comum. Foi
observado a utilizao de resistores limitadores de tenso de 220 ohms nas
entradas. Os leds foram utilizados para facilitar a compreenso da simulao.

4. SIMULAO NO MULTISIM

A simulao foi feita no NI Multisim e no Proteus. Utilizamos um gerador

de sinal DC de 5V como nvel alto e chaves SPDT para fazer a seleo dos
sinais de Entrada. O esquema da simulao foi apresentado na sesso
anterior(circuito lgico). A simulao corre sem problemas.

5. RELATRIO PRTICO
5.1. Montagem

Para iniciar a montagem avaliamos a quantidade de CIs e demais

componentes empregados para soluo do problema: Necessitamos de 11
Cis, 6 botes SPDT, 3 displays e 21 resistores de 220 ohms. Decidiu-se por
utilizar 3 protoboards, 2 protoboards de 850 furos e 1 de 1700 furos a fim de
espaar melhor os componentes. Por segurana, foram comprados alguns
componentes com sobras, visando precaver possveis problemas com
queima de componentes(CIs).
Iniciou-se com a montagem da protoboard que comporta os displays e a
que comporta os botes, que so as 2 protoboards menores. Os botes
tiveram suas entradas ligadas entre si, a entrada NF recebeu o sinal do ground
a NA recebe o sinal ALTO(6V), as sadas so no pino central.
Em seguida, foram feitas as conexes dos CIs na protoboard maior,
respeitando o esquema de ligao apresentado. As sadas dos CIs foram
ligadas no arranjo de resistncias que alimentam os displays. Os displays tem
Ctodos Comum que so ligados ao ground..
Tivemos problemas tambm com a tecnologia dos CIs, no foi
encontrado no mercado os CIs do tipo especificado(ALS), usamos as
tecnologias disponveis a fim de conseguir concretizar a montagem.
5.2. Testes

Foram necessrios vrios testes de continuidade por conta de eventuais

mal contatos na protoboard. Antes de ligar o circuito, todas as entradas foram
checadas. Os displays tambm foram testados, respeitando o limite de de
corrente de cada segmento. O circuito montado por etapas, cada sada tem
sua montagem, isso facilitou a execuo de testes.
Na dvida do funcionamento dos CIs, por se tratar apenas de portas
NAND, curto circuitamos as entradas, aplicamos um sinal de entrada e
checamos se a sada estava invertida(Funo inversora com portas NAND).

6. VERIFICAO DE RESULTADOS

Os resultados so verificados acionando-se todas as combinaes de

entradas e comparando com os valores esperados de sada e Caracteres
mostrados nos displays. O circuito apresentou sada correspondente a
esperada para todas as entradas exceto para 2 combinaes de bits.
Esgotamos as possibilidades de erros de ligao, refazendo e checando todas
as ligaes e chegamos a suspeita de curto em alguma das trilhas da
protoboard. No pudemos verificar mais a fundo a protoboard por falta de
tempo hbil para concluso do projeto.

7. CONCLUSO

Esse projeto foi proveitoso para elucidar questes sobre o

funcionamento de CIs, leitura de datasheets, obteno e simplificao de
equaes lgicas, funcionamento de displays de 7 segmentos.
Vrios desafios foram encontrados durante a montagem, aprendizado
possvel apenas pela prtica. No final das contas, o projeto do circuito se
mostrou um desafio intermedirio frente a dificuldade e desafio da
montagem real do circuito.
A restrio do uso de portas tornou o projeto muito mais dispendioso e
complexo devido ao nmero de Cis. Porm, o fato de trabalhar apenas com
 portas NAND possibilitou o uso de criatividade para manipular as equaes
de sada utilizando o Teorema de De Morgan e algebra de Boole.
Tivemos sorte de j ter alguns componentes do projeto, isso facilitou a
questo financeira e logstica.
8. RELAO DE COMPONENTES E ORAMENTO

TIPO DE MARCA MODELO QUANTIDADE

COMPONENTE
Protoboard 1700 HIKARI MP-2420 1
furos
Protoboard 850 HIKARI BB830 1
furos
CI FAIRCHILD 74LS00 9
CI TI 74LS20 1
CI TI 74LS10 1
Resitor 220 ohms - 0,4W 22
Boto SPDT - - 6
Displays 7 seg - - 3
CC

COMPONENTE PREO QUANTIDADE TOTAL

Protoboard 2420 110,00 1 110,00
furos
Protoboard 830 25,00 2 50,00
furos
74LS00 3,50 9 31,50
74LS20 4,50 1 4,50
74LS10 3,00 1 3,00
Resitor 220 ohms 0,10 22 2,20
Boto SPDT 1,00 6 6,00
Displays 7 seg 1,20 3 3,60
CC

TOTAL DO PROJETO: 210,80

 9. APNDICES

SN5400, SN54LS00, SN54S00

SN7400, SN74LS00, SN74S00

SDLS025C DECEMBER 1983 REVISED NOVEMBER 2016

SNx400, SNx4LS00, and SNx4S00 Quadruple 2-Input Positive-NAND

Gates
1 Features
Package Options Include:
Plastic Small-Outline (D, NS, PS)
Shrink Small-Outline (DB)
Ceramic Flat (W)
Ceramic Chip Carriers (FK)
Standard Plastic (N)
Ceramic (J)
Also Available as Dual 2-Input Positive-NAND Gate in Small-Outline (PS) Package
Inputs Are TTL Compliant; VIH = 2 V and VIL = 0.8 V
Inputs Can Accept 3.3-V or 2.5-V Logic Inputs
SN5400, SN54LS00, and SN54S00 are Characterized For Operation Over the Full Military
Temperature Range of 55C to 125C

2 Applications
AV Receivers
Portable Audio Docks
Blu-Ray Players

3 Description
The SNx4xx00 devices contain four independent, 2-input NAND gates. The devices perform the
Boolean function Y = A B or Y = A + B in positive logic.
 (1)
Device Information
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LS00DB SSOP (14) 6.20 mm 5.30 mm
SN7400D,
SN74LS00D, SOIC (14) 8.65 mm 3.91 mm
SN74S00D
SN74LS00NSR PDIP (14) 19.30 6.35 mm
SNJ5400J,
SNJ54LS00J, CDIP (14) 19.56 mm 6.67 mm
SNJ54S00J
SNJ5400W,
SNJ54LS00W, CFP (14) 9.21 mm 5.97 mm
SNJ54S00W
SN54LS00FK,
LCCC (20) 8.89 mm 8.89 mm
SN54S00FK
SN7400NS,
SN74LS00NS, SO (14) 10.30 mm 5.30 mm
SN74S00NS
SN7400PS,
SO (8) 6.20 mm 5.30 mm
SN74LS00PS
Home Theater
MP3 Players or Recorders
Personal Digital Assistants (PDAs)
(1) For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram, Each Gate (Positive Logic)

A
Y
B

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical
applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
SDLS025C DECEMBER 1983 REVISED NOVEMBER 2016
www.ti.com

Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ......................................... 8
2 Applications ........................................................... 1 8.3 Feature Description................................................... 8
3 Description ............................................................. 1 8.4 Device Functional Modes......................................... 8
4 Revision History..................................................... 2 9 Application and Implementation .......................... 9
5 Pin Configuration.........................................................andFunctions......................................................................................................... 3 9.1 Application
...................................................................
Information
....................................................................................................................... 9
9.2 Typical Application 9
6 Specifications 4
6.1 Absolute Maximum Ratings 4 10 Power Supply Recommendations 10
6.2 ESD Ratings: SN74LS00 4 11 Layout 11
6.3 Recommended Operating
..................................................
Conditions
............................
.......................
4 11.1 Layout Guidelines...................................................................................................................... 11
6.4 Thermal Information 5 11.2 Layout Example 11
6.5 Electrical Characteristics: SNx400 5 12 Device and Documentation Support 12
6.6 Electrical Characteristics: SNx4LS00 ....................... 5 12.1 Documentation Support ........................................ 12
6.7 Electrical Characteristics: SNx4S00 ......................... 5 12.2 Related Links ........................................................ 12
6.8 Switching Characteristics: SNx400 ........................... 6 12.3 Receiving Notification of Documentation Updates 12
6.9 Switching Characteristics: SNx4LS00....................... 6 12.4 Community Resources.......................................... 12
6.10 Switching Characteristics: SNx4S00....................... 6 12.5 Trademarks ........................................................... 12
6.11 Typical Characteristics ............................................ 6 12.6 Electrostatic Discharge Caution............................ 12
7 Parameter Measurement Information .................. 7 12.7 Glossary ................................................................ 12
Detailed Description .............................................. Mechanical, Packaging,andOrderable
8 ................................................................... 8 13 ...........................................................
8.1 Overview 8 Information 13

4 Revision History
Changes from Revision B (October 2003) to Revision C
Page

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.........................................................................................................
1
Changed Ordering Information table to Device Comparison Table; see Package Option Addendum at the
end of the
data sheet......................................................................................................................................................................................
1
Changed Package thermal impedance, RJA, values in Thermal Information table From: 86C/W To:
90.9C/W (D),
From: 96C/W To: 102.8C/W (DB), From: 80C/W To: 54.8C/W (N), and From: 76C/W To: 89.7C/W (NS)............................
5
2 Submit Documentation Feedback Copyright 19832016, Texas
Instruments Incorporated

Product Folder Links: SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00

SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
www.ti.com SDLS025C DECEMBER 1983 REVISED
NOVEMBER 2016

5 Pin Configuration and Functions

SN5400 J, SN54xx00 J and W, SN74x00 D, N, and NS, or SN74LS00 D, DB, N, and NS Packages
14-Pin CDIP, CFP, SOIC, PDIP, SO, or SSOP Top View

V
1A 1 14 CC
1B 2 13 4A

1Y 3 12 4B

2A 4 11 4Y

2B 5 10 3A

2Y 6 9 3B

GND 7 8 3Y

NOT TO SCALE

SN5400 W Package
14-Pin CFP
Top View

1A 1 14 4Y

1B 2 13 4B

1Y 3 12 4A

V
CC 4 11 GND
2Y 5 10 3B

2A 6 9 3A

2B 7 8 3Y

NOT TO SCALE

SN74xx00 PS Package
18-Pin SO
Top View

V
1A 1 8 CC
1B 2 7 2B

1Y 3 6 2A

GND 4 5 2Y
NOT TO SCALE

SN54xx00 FK Package
20-Pin LCCC
Top View

VCC
NC
1A
1B

4B
20

19
3

1Y 4 18 4A

NC 5 17 NC

2A 6 16 4Y

NC 7 15 NC

2B 8 14 3B
12

13
10

11
9

GND

NOT TO SCALE
NC
2Y

3Y

3A

Pin Functions
PIN
CDIP, CFP, SOIC, SO CFP I/O DESCRIPTION
NAME LCCC
PDIP, SO, SSOP (SN74xx00) (SN5400)
1A 1 1 1 2 I Gate 1 input
1B 2 2 2 3 I Gate 1 input
1Y 3 3 3 4 O Gate 1 output
2A 4 6 6 6 I Gate 2 input
2B 5 7 7 8 I Gate 2 input
2Y 6 5 5 9 O Gate 2 output
3A 10 9 13 I Gate 3 input
3B 9 10 14 I Gate 3 input
3Y 8 8 12 O Gate 3 output
4A 13 12 18 I Gate 4 input

Copyright 19832016, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Links: SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00
SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
SDLS025C DECEMBER 1983 REVISED NOVEMBER 2016
www.ti.com

Pin Functions (continued)

PIN
CDIP, CFP, SOIC, SO CFP I/O DESCRIPTION
NAME LCCC
PDIP, SO, SSOP (SN74xx00) (SN5400)
4B 12 13 19 I Gate 4 input
4Y 11 14 16 O Gate 4 output
GND 7 4 11 10 Ground
1, 5, 7,
NC No connect
11, 15, 17
V
CC 14 8 4 20 Power supply

6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
(2)
Supply voltage, VCC 7 V
SNx400 and SNxS400 5.5
Input voltage V
SNx4LS00 7
Junction temperature, TJ 150 C
Storage temperature, Tstg 65 150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond
those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
(2) Voltage values are with respect to network ground terminal.

6.2 ESD Ratings: SN74LS00

VALUE UNIT
(1)
V Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 500
(ESD) (2) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 2000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as 2000 V may
actually have higher performance. Tested on SN74LS00N package.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V SN54xx00 4.5 5 5.5
CC Supply voltage SN74xx00 4.75 5 5.25 V
V
IH High-level input voltage 2 V
V SNx400, SN7LS400, and SNx4S00 0.8
IL Low-level input voltage SN54LS00 0.7 V

I SN5400, SN54LS00, and SN74LS00 0.4

OH High-level output current SNx4S00 1 mA

SNx400 16
I SN5LS400 4
OL Low-level output current SN7LS400 8 mA

SNx4S00 20
SN54xx00 55 125
TA Operating free-air temperature C
SN74xx00 0 70

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SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
www.ti.com SDLS025C DECEMBER 1983 REVISED
NOVEMBER 2016

6.4 Thermal Information

SN74LS00
(1)(2)
THERMAL METRIC D (SOIC) DB (SSOP) N (PDIP) NS (SO) UNIT
14 PINS 14 PINS 14 PINS 14 PINS
R
JA Junction-to-ambient thermal resistance 90.9 102.8 54.8 89.7 C/W
R
JC(top) Junction-to-case (top) thermal resistance 51.9 53.3 42.1 48.1 C/W
R
JB Junction-to-board thermal resistance 48 53.4 34.8 50.1 C/W

JT Junction-to-top characterization parameter 18.6 16.5 26.9 16.7 C/W

JB Junction-to-board characterization parameter 47.8 52.9 34.7 49.8 C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal
Metrics application report.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.

6.5 Electrical Characteristics: SNx400

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IK VCC = MIN and II = 12 mA 1.5 V
V
OH VCC = MIN, VIL = 0.8 V, and IOH = 0.4 mA 2.4 3.4 V
V
OL VCC = MIN, VIH = 2 V, and IOL = 16 mA 0.2 0.4 V
II VCC = MAX and VI = 5.5 V 1 mA
I
IH VCC = MAX and VI = 2.4 V 40 A
I
IL VCC = MAX and VI = 0.4 V 1.6 mA
I SN5400 20 55
OS VCC = MAX SN7400 18 55 mA
I
CCH VCC = MAX and VI = 0 V 4 8 mA
I
CCL VCC = MAX and VI = 4.5 V 12 22 mA

6.6 Electrical Characteristics: SNx4LS00

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IK VCC = MIN and II = 18 mA 1.5 V
V
OH VCC = MIN, VIL = MAX, and IOH = 0.4 mA 2.5 3.4 V
IOL = 4 mA 0.25 0.4
V
OL VCC = MIN and VIH = 2 V IOL = 8 mA (SN74LS00) 0.35 0.5 V
II VCC = MAX and VI = 7 V 0.1 mA
I
IH VCC = MAX and VI = 2.7 V 20 A
I
IL VCC = MAX and VI = 0.4 V 0.4 mA
I
OS VCC = MAX 20 100 mA
I
CCH VCC = MAX and VI = 0 V 0.8 1.6 mA
I
CCL VCC = MAX and VI = 4.5 V 2.4 4.4 mA

6.7 Electrical Characteristics: SNx4S00

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IK VCC = MIN and II = 18 mA 1.2 V
V
OH VCC = MIN, VIL = 0.8 V, and IOH = 1 mA 2.5 3.4 V
V
OL VCC = MIN, VIH = 2 V, and IOL = 20 mA 0.5 V
I
I VCC = MAX and VI = 5.5 V 1 mA
I
IH VCC = MAX and VI = 2.7 V 50 A
I
IL VCC = MAX and VI = 0.5 V 2 mA

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SDLS025C DECEMBER 1983 REVISED NOVEMBER 2016
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Electrical Characteristics: SNx4S00 (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
OS VCC = MAX 40 100 mA
I
CCH VCC = MAX and VI = 0 V 10 16 mA
I
CCL VCC = MAX and VI = 4.5 V 20 36 mA

6.8 Switching Characteristics: SNx400

VCC = 5 V, TA = 25C, and over operating free-air temperature range (unless otherwise noted). See Figure 2.
PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
t
PLH 11 22
t A or B Y RL = 400 and CL = 15 pF ns
PHL 7 15

6.9 Switching Characteristics: SNx4LS00

VCC = 5 V, TA = 25C, and over operating free-air temperature range (unless otherwise noted). See Figure 2.
PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
t
PLH 9 15
t A or B Y RL = 2 k and CL = 15 pF ns
PHL 10 15

6.10 Switching Characteristics: SNx4S00

VCC = 5 V, TA = 25C, and over operating free-air temperature range (unless otherwise noted). See Figure 2.
PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
t RL = 280 and CL = 15 pF 3 4.5
PLH A or B Y RL = 280 and CL = 50 pF 4.5
ns
RL = 280 and CL = 15 pF 3 5
t
PHL A or B Y RL = 280 and CL = 50 pF 5

6.11 Typical Characteristics

CL = 15 pF
16

14

12
T PHL (ns)

10

4 TPHLtyp D1 '00,D2 'LS00,D3 'S00

TPHLmax D1 '00,D2 'LS00,D3 'S00
2
1 2 3
Device D001
Figure 1. TPHL (Across Devices)

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www.ti.com SDLS025C DECEMBER 1983 REVISED NOVEMBER 2016

7 Parameter Measurement Information

V
CC TestRL
Test Point
V S1
Point CC From Output
V
CC Under Test (see Note B)
C
RL L
R (see Note A) 1 k
From Output L
Under Test (see Note B) From OutputTest
CL Under TestPoint
C
(see Note A) L
(see Note A) S2

LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS

3V
High-Level Timing
Pulse 1.5 V 1.5 V Input 1.5 V
0V
t w t th
su
3V
Low-Level Data
1.5 V 1.5 V 1.5 V 1.5 V
Pulse Input
0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATIONS SETUP AND HOLD TIMES

Output 3V
Control
(low-level 1.5 V 1.5 V
3V
Input 1.5 V 1.5 V enabling) 0V
t t
0V PZL PLZ
t t
PLH PHL
Waveform 1 1.5 V
V
In-Phase OH (see Notes C 1.5 V
Output 1.5 V 1.5 V and D) V VOL + 0.5 V
(see Note D)
V OL
OL
t t
t t PZH PHZ
PHL PLH V
OH
V
Out-of-Phase OH Waveform 2 VOH 0.5 V
Output (see Notes C 1.5 V
1.5 V 1.5 V 1.5 V
 (see Note D) V and D)
OL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the
output control. Waveform 2 is for an output with internal conditions such that the output is high except when
disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and t PLZ; S1 is open and S2 is closed for t PZH; S1 is closed and S2 is open
for t PZL.
E. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 ; tr and tf 7 ns for Series
54/74 devices and tr and tf 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.

Figure 2. Load Circuits and Voltage Waveforms

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www.ti.com

8 Detailed Description

8.1 Overview
The SNx4xx00 devices are quadruple, 2-input NAND gates which perform the Boolean function Y =
A B or Y = A + B in positive logic.

8.2 Functional Block Diagram

A
Y
B

8.3 Feature Description

The operating voltage of SN74xx00 is from 4.75-V to 5.25-V V CC. The operating voltage of
SN54xx00 is from 4.5-V to 5.5-V V CC. The SN54xx00 devices are rated from 55C to 125C
whereas SN74xx00 device are rated from 0C to 70C.
8.4 Device Functional Modes
Table 1 lists the functions of the devices.

Table 1. Functional Table (Each Gate)

INPUTS OUTPUT
A B Y
H H L
L X H
X L H
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www.ti.com SDLS025C DECEMBER 1983 REVISED
NOVEMBER 2016

9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers
should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SNx4xx00 devices are quadruple, 2-input NAND gate, and can be configured as dual 3-input
NAND gate as shown in Figure 3.

9.2 Typical Application

A1
B1
Y1
C1

A2
B2
C2

Y2

Figure 3. Typical Application Diagram

9.2.1 Design Requirements

These devices use BJT technology and have unbalanced output drive with I OL and IOH specified as
per the Recommended Operating Conditions. It can be configured as a dual 3-input NAND gate as
shown in Figure 3.
9.2.2 Detailed Design Procedure
Recommended Input Conditions:
The inputs are TTL compliant.
Because the base-emitter junction at the inputs breaks down, no voltage greater than 5.5 V must
be applied to the inputs.
Specified high and low levels: See VIH and VIL in Recommended Operating Conditions.
Recommended Output Conditions:
No more than one output must be shorted at a time as per the Electrical Characteristics: SNx400
for thermal stability and reliability.
For high-current applications, consider thermal characteristics of the package listed in Thermal
Information.
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www.ti.com

Typical Application (continued)

9.2.3 Application Curves
CL = 15 pF
25
TpLHmax D1 '00, D2 'LS00, D3 'S00
TpLHtyp D1 '00, D2 'LS00, D3 'S00
20

TPLH (ns) 15

10

0
1 2 3
Device D001

Figure 4. TPLH (Across Devices)

10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating
located in Recommended Operating Conditions for each of the SNx4LS00, SNx4S00, and SNx400
devices.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a
single supply, 0.1 F is recommended; if there are multiple V CC pins, then 0.01 F or 0.022 F is
recommended for each power pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. A 0.1 F and a 1 F are commonly used in parallel. The bypass
capacitor must be installed as close to the power pin as possible for best results.
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SN5400, SN54LS00, SN54S00
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www.ti.com SDLS025C DECEMBER 1983 REVISED
NOVEMBER 2016

11 Layout

11.1 Layout Guidelines

When using multiple bit logic, devices inputs must never float.
Devices with multiple-emitter inputs (SN74 and SN74S series) need special care. Because no
voltage greater than 5.5 V must be applied to the inputs (if exceeded, the base-emitter junction at
the inputs breaks down), the inputs of these devices must be connected to the supply voltage, V CC,
through series resistor, R S (see Figure 5). This resistor must be dimensioned such that the current
flowing into the gate or gates, which results from overvoltage, does not exceed 1 mA. However,
because the high-level input current of the circuits connected to the gate flows through this resistor,
the resistor must be dimensioned so that the voltage drop across it still allows the required high
level. Equation 1 and Equation 2 are for dimensioning resistor, RS, and several inputs can be
connected to a high level through a single resistor if the following conditions are met.
R + VCCP * 5.5 V
S(min)
1 mA
V * 2.4 V
R + CC(min)
S(max)
nIIH
where
n = number of inputs connected
IIH = high input current (typical 40 A)
VCC(min) = minimum supply voltage, VCC
VCCP = maximum peak voltage of the supply voltage, VCC (about 7 V)

(1)

(2)

11.2 Layout Example

R
S
V &
CC
Output
Input

Figure 5. Series Resistor Connected to Unused Inputs of Multiple-Emitter Transistors

Copyright 19832016, Texas Instruments Incorporated Submit Documentation
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SDLS025C DECEMBER 1983 REVISED NOVEMBER 2016
www.ti.com

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:
Designing With Logic (SDYA009)

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and
community resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN5400 Click here Click here Click here Click here Click here
SN54LS00 Click here Click here Click here Click here Click here
SN54S00 Click here Click here Click here Click here Click here
SN7400 Click here Click here Click here Click here Click here
SN74LS00 Click here Click here Click here Click here Click here
SN74S00 Click here Click here Click here Click here Click here

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In
the upper right corner, click on Alert me to register and receive a weekly digest of any product
information that has changed. For change details, review the revision history included in any
revised document.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's
views; see TI's Terms of Use.
TI E2E Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore
ideas and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design
support tools and contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive
foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

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www.ti.com SDLS025C DECEMBER 1983 REVISED
NOVEMBER 2016

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is
the most current data available for the designated devices. This data is subject to change without
notice and revision of this document. For browser-based versions of this data sheet, refer to the left-
hand navigation.
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PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Sa
(1) Drawing Qty (2) (6) (3) (4/5)

JM38510/00104BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
00104BCA
JM38510/00104BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
00104BDA
JM38510/07001BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
07001BCA
JM38510/07001BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
07001BDA
JM38510/30001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
30001B2A
JM38510/30001BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30001BCA
JM38510/30001BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30001BDA
JM38510/30001SCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/30001S
CA
JM38510/30001SDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/30001S
DA
M38510/00104BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
00104BCA
M38510/00104BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
00104BDA
M38510/07001BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
07001BCA
M38510/07001BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
07001BDA
M38510/30001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
 30001B2A
M38510/30001BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30001BCA
M38510/30001BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30001BDA
M38510/30001SCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/30001S
CA

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 17-Mar-2017

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Sa
(1) Drawing Qty (2) (6) (3) (4/5)

M38510/30001SDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/30001S
DA
SN5400J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN5400J

SN54LS00J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS00J

SN54S00J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54S00J

SN7400D ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 7400

& no Sb/Br)
SN7400DG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 7400
& no Sb/Br)
SN7400N ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 SN7400N
(RoHS)
SN7400NE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 SN7400N
(RoHS)
SN74LS00D ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00
& no Sb/Br)
SN74LS00DBR ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00
& no Sb/Br)
SN74LS00DG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00
& no Sb/Br)
SN74LS00DR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00
& no Sb/Br)
SN74LS00DRE4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00
& no Sb/Br)
SN74LS00N ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS00N
(RoHS)
SN74LS00NE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS00N
(RoHS)
 SN74LS00NSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS00
& no Sb/Br)
SN74LS00NSRG4 ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS00
& no Sb/Br)
SN74LS00PSR ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00
& no Sb/Br)

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Mar-2017

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Sa
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LS00PSRG4 ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS00

& no Sb/Br)
SN74S00D NRND SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 S00
& no Sb/Br)
SN74S00DE4 NRND SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 S00
& no Sb/Br)
SN74S00N NRND PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 SN74S00N
(RoHS)
SN74S00NE4 NRND PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 SN74S00N
(RoHS)
SNJ5400J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5400J

SNJ5400W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5400W

SNJ54LS00FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54LS00FK

SNJ54LS00J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS00J

SNJ54LS00W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS00W

SNJ54S00FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54S
00FK
SNJ54S00J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S00J

SNJ54S00W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S00W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not
recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples
may or may not be available.
 OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6
substances,including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI
Pb-Free products are suitable for use in specified lead-free processes.

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

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Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die
adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed
0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if
the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and
belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information
from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may
not be available for release.

In no event shall TI's liability arising out of such information exceedthe total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN5400, SN54LS00, SN54LS00-SP, SN54S00, SN7400, SN74LS00, SN74S00 :
Catalog: SN7400, SN74LS00, SN54LS00, SN74S00
Military: SN5400, SN54LS00, SN54S00
Space: SN54LS00-SP

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

 Military - QML certified for Military and Defense Applications

Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 4
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Mar-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LS00DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LS00DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LS00NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LS00PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Mar-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LS00DBR SSOP DB 14 2000 367.0 367.0 38.0
SN74LS00DR SOIC D 14 2500 367.0 367.0 38.0
SN74LS00NSR SO NS 14 2000 367.0 367.0 38.0
SN74LS00PSR SO PS 8 2000 367.0 367.0 38.0
Pack Materials-Page 2
 MECHANICAL DATA

MSSO002E JANUARY 1995 REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC
SMALL-OUTLINE
28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0 8 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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TRIPLE 3-INPUT NAND GATE

TRIPLE 3-INPUT NAND GATE

V
CC LOW POWER SCHOTTKY
14 13 12 11 10 9 8

J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
14
GND 1

N SUFFIX
PLASTIC
14 CASE 646-06
1

D SUFFIX
SOIC
14
1 CASE 751A-02

ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
V
CC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 55 25 125 C
74 0 25 70
I
OH Output Current High 54, 74 0.4 mA
I
OL Output Current Low 54 4.0 mA
74 8.0

FAST AND LS TTL DATA

5-1
 SN54/74LS10

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
V Guaranteed Input HIGH Voltage for
IH Input HIGH Voltage 2.0 V All Inputs

V 54 0.7 Guaranteed Input LOW Voltage for

IL Input LOW Voltage 74 0.8 V All Inputs
V
IK Input Clamp Diode Voltage 0.65 1.5 V VCC = MIN, IIN = 18 mA

V 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH

OH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table
54, 74 0.25 0.4 V I = 4.0 mA VCC = VCC MIN,
V OL
OL Output LOW Voltage VIN = VIL or VIH

74 0.35 0.5 V IOL = 8.0 mA per Truth Table

I 20 A VCC = MAX, VIN = 2.7 V

IH Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
I
IL Input LOW Current 0.4 mA VCC = MAX, VIN = 0.4 V
I
OS Short Circuit Current (Note 1) 20 100 mA VCC = MAX
Power Supply Current
I 1.2
CC Total, Output HIGH mA VCC = MAX
Total, Output LOW 3.3
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
t
PLH Turn-Off Delay, Input to Output 9.0 15 ns V= 5.0 V
CC

t
PHL Turn-On Delay, Input to Output 10 15 ns CL = 15 pF
 SN54/74L
S20
DUAL 4-INPUT NAND GATE

DUAL 4-INPUT NAND GATE

V
CC LOW POWER SCHOTTKY
14 13 12 11 10 9 8

J SUFFIX
CERAMIC
1 2 3 4 5 6 7 CASE 632-08
14
GND
1

N SUFFIX
PLASTIC
14 CASE 646-06
1

D SUFFIX
SOIC
14
1 CASE 751A-02

ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
V
CC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 55 25 125 C
74 0 25 70
 I
OH Output Current High 54, 74 0.4 mA
I
OL Output Current Low 54 4.0 mA
74 8.0

FAST AND LS TTL DATA

5-29
 SN54/74LS20

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
V Guaranteed Input HIGH Voltage for
IH Input HIGH Voltage 2.0 V All Inputs

V 54 0.7 Guaranteed Input LOW Voltage for

IL Input LOW Voltage 74 0.8 V All Inputs
V
IK Input Clamp Diode Voltage 0.65 1.5 V VCC = MIN, IIN = 18 mA

V 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH

OH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table
54, 74 0.25 0.4 V I = 4.0 mA VCC = VCC MIN,
V OL
OL Output LOW Voltage VIN = VIL or VIH

74 0.35 0.5 V IOL = 8.0 mA per Truth Table

I 20 A VCC = MAX, VIN = 2.7 V

IH Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
I
IL Input LOW Current 0.4 mA VCC = MAX, VIN = 0.4 V
I
OS Short Circuit Current (Note 1) 20 100 mA VCC = MAX
Power Supply Current
I 0.8
CC Total, Output HIGH mA VCC = MAX
Total, Output LOW 2.2
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
t
PLH Turn-Off Delay, Input to Output 9.0 15 ns VCC = 5.0 V
t
PHL Turn-On Delay, Input to Output 10 15 ns CL = 15 pF
FAST AND LS TTL DATA
5-30
 10. REFERNCIAS

TOCCI, WIDMER & MOSS. Sistemas Digitais: Princpios e

Aplicaes, 11 Edio, 2011.
www.alldatasheet.com
karnaugh.shuriksoft.com