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8 general purpose LEDs
Background Theory 1 reset button
The game of life by John Conway 1 LED to show when the
runs on simple rules as follows: FPGA is correctly configured
1. A live cell with fewer than On board voltage regulation
two live neighbours dies, as if that can handle 4.8V - 12V
caused by under-population.
2. A live cell with two or three A microcontroller
live neighbours lives on to the (ATmega16U4) used for
next generation. configuring the FPGA, USB
3. A live cell with more than communications, and reading
three live neighbours dies, as the analog pins
if by overcrowding.
4. A dead cell with exactly three On board flash memory to
live neighbours becomes a store the FPGA configuration
live cell, as if by reproduction. file
2
are not required for lighting it up. HS and VS (horizontal and
Following is the pin description of vertical synchronization)
the LED matrix used:
All we needed to do is get a monitor
for VGA display and a female VGA
connector and connect the 15 pins in
the following manner:
3
We have used ISE(Integrated switches and lighting a single
Software Environment) design LED in the LED matrix.
suite 14.7 by XilinxXilinx
Following is the entire code
ISE(Integrated Software
used for this version of the
Environment) is a software tool
game of life:
produced by Xilinx for synthesis
and analysis of HDL designs, In the main module, in which all
enabling the developer to modules are instantiated and
synthesize their designs, perform from where input/outputs from
timing analysis, examine RTL external hardware of the set-up
diagrams, simulate a design's are taken, we have three modules
reaction to different stimuli, and instantiated, namely pin, copy
configure the target device with and light in the following
the programmer. One can manner:
simulate the hardware using pin p(
iSim. However the coding in
.clk(c1),
iSim does not work on FPGA.
Testbenches /Test-fixtures are .arr(arr),
meant for simulation part only. .next(next),
.rst(rst)
);
We descried small blocks of
hardware named modules. Inputs
and outputs of each module are copy c(
needed to be specified in the .rst(rst),
beginning and way it processes
.clk(clk),
the inputs and outputs are needed
to be specified after that. For .arr(arr),
more on syntax and rules see .next(next)
section on code. A module once );
created can be instantiated in any
other module keeping in mind the
hardware feasibility. light pov(
.clk(clk),
.test(next),
Code for Version 1:
.R(R),
Initially the team wrote small .C(C)
modules to light internal/ external
);
LEDs with internal/external
4
Here R and C are the arrays of i.e. the next state of our cellular
I/O pins in mojo board to which grid. The module copy assigns
row and column pins of the LED the values in next to
matrix (16X16) are connected. R corresponding cells in arr.
and C are defined as outputs from
The module light is for POV.
the mojo-top. We had to
Any state of the game of life is
configure these pins in the
being displayed using Persistence
mojo.ucf file; mojo.ucf is where
of Vision. This is the module
we configure the I/O pins of the
which sends output to R and C
mojo board with some pins
pins. This module takes as input a
configured by default to internal
256 bit array and depending on
elements of the board.
the state of each LED lights up
The default clock of the board each of them one by one at a
(clk) is a 50 MHz clock which is frequency of 50 MHz.
too fast to have a noticeable
The module pin takes as input
updating of present state of the
the array arr, i.e. the present state
cell to the next. C1 is a 1 Hz
of the LED matrix and its
clock which has been slowed
function is to give the next state
down using the following
of the matrix in form of output
module:
next following the rules of the
module count (clk, b); game of life. In other words,
input clk; // synthesis according to the present state of
attribute PERIOD clk "50 MHz" the neighbouring cells of the cell
reg [25:0] count = 0; under consideration, it assigns
output reg b = 0; // one pulse per
the next state of the cell in the
second array next. For checking the
rules, we simply add the states
(1-live, 0-dead) of the neighbours
always @ (posedge clk) begin
and compare. For e.g. if arr[x] is
b <= (count == 50000000 - 2); live and the neighbours add upto
count <= b ? 0 : count + 1; 5, we assign next[x] to be a dead
cell.
end
endmodule The matrix is refreshed to its
initial seeding each time the reset
For reference to any LED in the button on the mojo board is
LED matrix we used a 256 bit pressed. As mentioned earlier, the
array. The LED (i, j) is referred updating of the state occurs at a
by arr[i*8+j]. The other 256 bit frequency of 1 Hz.
array, next is the updated state,
5
All these modules run parallel to CounterX <= CounterX + 1;
give fast execution. If always @(posedge clk)
summarized, the pin module if(CounterXmaxed)
initializes and updates the states.
CounterY <= CounterY + 1;
The light module implements
POV for displaying the current endmodule
state. The module copy copies Module vga:
the array next onto array arr.
module vga(input clk, input [9:0]
Code for Version 2: CounterX, input [9:0] CounterY, output
vga_HS, output vga_VS
This version of Conways game
);
of life gets displayed on a VGA
screen. This is not as elegantly reg vga_HS, vga_VS;
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Block Diagram:
16X16 LED
Matrix
Mojo V2
Female VGA
Connector
Out to VGA
Monitor
7
Limitations and Compromises There are several more
applications of FPGAs.
There are some limitations to the
One of the ideas we were
latest version of the project:
considering is making a
The code for initial seeding genetic algorithm solver
needs to be changed whenever using FPGAs.
a different initial seed is FPGAs can be used in bots
needed. making their execution
The code is not robust at faster due to parallel
present. For scaling up the processing.
display, the code has to be To emphasize on the scope
changed significantly, of FPGA: it can be used to
especially when it comes to design any circuit be it a
VGA display which mainly simple AND gate or a
involves hard coding. microprocessor.
We havent been able to
implement user interfacing to
the game till now. Once the References
game is set on, user can not
http://embeddedmicro.com/tut
change the state of a desired
orials/mojo/
cell.
https://www.youtube.com/wat
Future Prospects and Scope ch?v=pkJAWpkaiHg
User interfacing can be
http://www.asic-world.com/
added to the game. This
would mean the user can http://www.fpga4fun.com/Pon
set the initial seeding and
gGame.html
further user can access any
cell and change its state in
run-time of the game.
There can be more than
two states associated with
each cell corresponding to
growth and aging using a
color gradient instead of
just one color.
Another idea is to simulate
spread of diseases and
mutation at cellular level.
8
Team: E_Trix
Acknowledgements:
Sanjari Srivastava