module receive (

rec_in, //serial input

data_out, //8 bits output data
data_ready, //the state whether the data is recieved complete
format_error, //the interrupt sugnal , don't have 2 end bits
parity_error, //the interrupt sugnal , parity error
clk16x, //the clock;
rst //reset
);

input clk16x,rec_in;
input rst;
output [7:0] data_out ;
output data_ready ;
output format_error ;
output parity_error ;

reg [3:0] num_receive; // the counter recorded the number of bits recieved
reg data_ready ;
reg parity ;
reg parity_error ;

reg format_error1 ; // the first end bit error

reg format_error2; // the second end bit error
reg[3:0] begin_number; //detect s
reg read_enable; //the flag of that has detected the begin bit
reg [7:0] data_reg; //the reg to store the recieved data
reg [7:0] data_out;
reg end_label; //recieved end bit
reg parity_label; //recieved parity bit

assign format_error=format_error1|format_error2; //end bit error means the first end bit error or the
second end bit error

always @(posedge clk16x or posedge rst)

begin
if(rst)
begin
begin_number <=0;

end
else if(rec_in&&!read_enable) // when not receiving and serial is 1 ,don't counter
begin
begin_number <=0;
end
else if (begin_number==8&&!read_enable)// detect 8 bits 0 begin to recieve
begin
begin_number<=0;
end
else if(!rec_in||read_enable)//when detect begin bit or recieving data ,start counter
begin
begin_number <=begin_number+1;
end
end

always @(posedge clk16x or posedge rst)

begin
if (rst) //initial
begin
data_out<=8'b11111111;
data_reg<=8'b11111111;
read_enable<=0;
data_ready<=0;
parity <= 1'b1 ;
format_error1 <= 1'b0 ;
format_error2 <= 1'b0 ;
parity_error <= 1'b0 ;
num_receive<= 4'b0000;
parity_label<=0;
end_label<=0;
end
else if (begin_number==8&&!read_enable) //begin to recieve
begin
read_enable<=1;
end
else if (!read_enable) //if it isn't recieving ,reset the counter
num_receive <= 4'b0000 ;

else if (begin_number==15&&read_enable) //recieve a bit

begin
num_receive <= num_receive + 1 ;
if (num_receive >= 4'b0000 && num_receive <= 4'b0111) //8 bits data
begin
data_reg[6:0] <= data_reg[7:1] ;
data_reg[7]<=rec_in;
parity <= parity ^ rec_in ;
end

else if (num_receive == 4'b1000) //recieve parity bit

begin
parity_label <= rec_in ;

end
else if (num_receive == 4'b1001) //recieve the first end bit
begin
parity_error<=(parity_label==parity)? 0:1;
end_label <= rec_in ;

end
else if (num_receive == 4'b1010) //recieve the second end bit
begin
format_error1<=(end_label==1)? 0:1;
end_label <= rec_in ;
end
else if (num_receive == 4'b1011)
begin
 format_error2<=(end_label==1)? 0:1;
end
else if (num_receive == 4'b1100) //judge whether exist a error
begin
if(!format_error1&&!format_error2&&!parity_error)
begin
data_ready<=1;
data_out<=data_reg;
end
end
else if (num_receive == 4'b1110) //recieve end
begin
data_ready<=0;
read_enable<=0;
data_reg<=8'b11111111;
data_out<=8'b11111111;
end_label<=0;
parity_label<=0;
format_error1 <= 1'b0 ;
format_error2 <= 1'b0 ;
parity_error <= 1'b0 ;
num_receive<=0;
end
end

end
endmodule