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How to write to two output ports from inside architecture in VHDL?

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asked 4 years, 9 months ago

viewed 5796 times

active 4 years, 9 months ago

I encountered a problem when trying to connect a component to two output ports of parent hierarchy in
VHDL. Since the physical connection can be done only via "port map" statement, there is no way to
0 connect local signal to more than one output port. Here is an example:

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............
. .
..........
........
Linked
1
[VHDL]Using signal to drive output ports,why are
the output ports not visible?

The description of the above circuit should be smth. like this:


Related

entity HIER is 5
port (
IN1 : in bit;
OUT1, OUT2 : out bit); How to specify an integer array as generic in
end hier; VHDL?

architecture HIER_IMPL of HIER is


1
component BUF is
port (a : in bit; o : out bit);
end component; How to assign multiple values to multiple ports in
begin VHDL
BUF1 : BUF port map (a => IN1, o => OUT1, o => OUT2);
end HIER_IMPL;
1
However, double assignment of output port "o" to both OUT1 and OUT2 won't work as it is prohibited Top level using port maps with records in VHDL
in VHDL.
0
variable-assignment instantiation vhdl
VHDL Component Port Mapping Issues
share improve this question asked Aug 27 '12 at 14:29
0
Port Map-ing to ground in VHDL
mkostya
193 4 13
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193 4 13
1

Wouldn't it be better to have just one OUT port and connect OUT to both ports where OUT1 and OUT2 are
connected to? simon Aug 28 '12 at 7:10 [VHDL]Using signal to drive output ports,why are
the output ports not visible?
add a comment

0
1 Answer active oldest votes How to map a port in VHDL?

3
Is there a reason why you cannot create an internal signal and use that signal to drive the two output
ports like this? VHDL - Port mapping - Map different ports of a
7 component into different entities
entity HIER is
port (
IN1 : in bit; 0
OUT1, OUT2 : out bit);
end hier; Warning of an unconnected output port in UART's
VHDL code
architecture HIER_IMPL of HIER is
signal temp : bit;
component BUF is 1
port (a : in bit; o : out bit);
end component;
How to implement a 4 bit ALU in VHDL using an
begin
opcode
BUF1 : BUF port map (a => IN1, o => temp);
OUT1 <= temp;
OUT2 <= temp; Hot Network Questions
end HIER_IMPL; Remove spaces from macro argument

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If this is not possible, how about this? arms?

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entity HIER is with absolutely no luck?
port (
IN1 : in bit; Why is my understanding of unbalanced forces
OUT1, OUT2 : out bit); wrong?
end hier; How many parabolas can be formed from 3
points? (If we allow rotation)
architecture HIER_IMPL of HIER is
component BUF is RAII vs. Garbage Collector
port (a : in bit; o : out bit);
end component; What is the alternate way to eliminate our Bad
Karmas equal in doing Penance?
begin
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BUF1 : BUF port map (a => IN1, o => OUT1); How do I say in German "It doesn't matter"?
BUF2 : BUF port map (a => IN1, o => OUT2);
end HIER_IMPL; Can I pour a solution into another vessel with no
air bubbles?

share improve this answer answered Aug 27 '12 at 14:50 Covfefify a string

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Josh Different number, same weight


2,731 14 33
Security implication of telling the user they can't
login because of too many attempts from IP
2 The first piece of code should work just fine. One just needs a signal to connect more than two IOs together. Security concerns issuing wildcard certificates to
Kamil Domaski Aug 27 '12 at 14:57 individual employees

Thanks! My intension was assignment-free solution. It looks like it is impossible to do it without assignments. Sum of Squares of odd numbers
The second option is not acceptable as it involves two buffers. mkostya Aug 28 '12 at 10:18
Worth writing, if end is obvious
@mkostya Please accept this answer if it solves your problem. Josh Aug 31 '12 at 12:40
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