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2001 Future Energy Challenge

Texas A&M University


Fuel Cell Inverter
- 10 kW Design & Cost Analysis

Texas A&M University, College Station, Texas


August 27, 2001

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TABLE OF CONTENTS: Page
1. INTRODUCTION ........................................................................... 3
2. TOPOLOGY AND OPERATION ................................................. 3
3. DESIGN AND CALCULATIONS ................................................. 6
4. SCHEMATICS................................................................................. 16
5. BILL OF MATERIALS .................................................................. 17
6. COST EVALUATION .................................................................... 19
7. CONCLUSIONS .............................................................................. 22

APPENDICES:
A. SCHEMATICS................................................................................. 23
B. SIMULATION RESULTS.............................................................. 31
C. UC3825B DATASHEET ................................................................. 34
D. COST INFORMATION ON TEXAS INSTRUMENTS
TMS320C24X DSP .......................................................................... 39

LIST OF TABLES:
1. Bill Of Materials For DC-DC Converter And Bulk Capacitors. 17
2. Bill Of Materials For DC-AC Inverter And Output Filter ......... 18
3. Bill Of Materials For DSP Control Board .................................... 19
4. DC-DC Converter Subsystem Costs .............................................. 21
5. DC-AC Inverter Subsystem Costs ................................................. 22

Page 2 of 40
1.0 Introduction
The report outlines the technical approach and the cost analysis to achieve the objectives

proposed by the 2001 Future Energy Challenge organizing committee. The Texas A&M team

believes it has developed an efficient and cost-effective inverter system. The team has developed

a low cost analog control solution for the DC-DC converter, an efficient 3-terminal DC-DC push

pull topology, a unique DSP control for DC-AC inverter control, and a rigorous cost reduction

approach for the 2001 Fuel Cell inverter project.

The Texas A&M team provides a rigorous cost savings approach by reducing the number

of power switches in the design. Incorporating fewer power resistors enhances cost savings and

efficiency. The 3-terminal push-pull DC-DC converter topology provides isolation for safety,

suitable boosting of the fuel cell voltage to 400 volts, reduced cost and reduced size of the energy

storage elements in the converter.

2.0 Topology and Operation


Figure 1 shows the schematic for the TAMU fuel cell inverter system which comprises of

a DC-DC boost circuit, a DC-AC inverter circuit and an output filter besides battery banks

floating on the high voltage DC bus.

The DC input from the fuel cell (48 VDC nominal, +50%, -12.5%) is first converted to a

regulated 400 VDC using a high frequency 3-terminal Push-Pull DC-DC converter. The DC-DC

conversion stage consists of a high-frequency transformer. Isolation is provided for safety, system

protection, and to meet the stringent FCC Class-A standards. The 400V DC-DC converter output

is converted to 120V/240V, 50/60 Hz, single-phase AC by means of a PWM driven inverter

stage. To obtain independent single phase outputs, two half-bridge inverters are used. An output

LC filter stage is employed to produce a low THD AC waveform. Low loss, high switching

Page 3 of 40
frequency MOSFET and IGBT switches have been employed to achieve a higher efficiency,

lower size and volume of the fuel cell inverter system.

DC-DC converter and inverter topologies were designed to achieve ease of

manufacturability and mass production. Another unique aspect of the design is the use of the

TMS320C2407 DSP to control the inverter. The DSP reduces printed circuit board layout

complexity. Readily programmable, the DSP adds flexibility and intelligence to implement

various control aspects by means of software. (See Appendix D for DSP cost information)

Two sets of lead-acid batteries are provided on the 200V DC bus to supply sudden load

demands. By floating the standby battery off the 400V instead of at the 48V level, we avoid

processing the battery power via two stages. Efficient and smooth control of the power drawn

from the fuel cell and the high voltage battery is achieved by controlling the front end DC-DC

converter in current mode.

Page 4 of 40
TR1
i i L1 I
1:5 D1 L DC

+ i
A
T1 i
C
Fuel Cell Input K1
i C2 L S1 L2
48VDC I in T1 D1 D3 b
S3
N2 A
A C4 3
V V N
in N1 batt i
AO
+ AC Output
C1
V N 120/240V , 60 Hz
- DC
N1 L B C5 B
C3 b i
BO 3
N2 N
V i
D4 D2 batt L3 B
I K2
T2
- S2 S4
T2

Page 5 of 40
Battery Backup
48VDC / 400VDC, 40KHz PUSH PULL CONVERTER 120V/240VAC, 20KHz PWM INVERTER

Note: Components shown in dotted boxes are not considered for cost evaluation

Figure 1: Schematic of the TAMU Fuel Cell Inverter System


Fuel Cell Fuel Cell
Power Available Signal DC Power Input

Voltage Ref. Current Ref. +


+ Voltage + Current To Inverter
- Controller - Controller
+
-

variable limiter -

DC-DC Converter
Current
Feedback

Voltage
Feedback

Figure 2: Block Diagram for DC-DC Converter Control

Figure 2 shows the block diagram for the current control of the DC-DC converter. The

Power Available signal (analog) from the fuel cell is used to adjust the current limit setting of the

DC-DC converter. This ensures that the power drawn from the fuel cell does not exceed its

capability. The remaining power is then provided by the battery backup system (Figure 1). The

inverter, on the other hand, determines the actual power drawn by the loads and communicates to

the fuel cell to either increase or decrease its power output. This ensures that the fuel cell has

sufficient time to adjust its power generation to meet the changes in load demand.

3.0 Design and Calculations


3.1 DC-DC Converter Design For The 10kW TAMU Fuel Cell Inverter System

In this section design of the DC-DC Converter is detailed. Figure 1 shows the circuit

diagram of the push-pull DC/DC converter. Fuel cell output is connected to the DC/DC

converter as shown. MOSFETs T+ and T- are turned on and off alternately at a switching

frequency of 40kHz.

The power output Po of the inverter is 10000W. Assuming an efficiency of 95% for the

inverter and the DC-DC converter, we have an input power Pin,

Page 6 of 40
10000W
Pin   11050W (1)
0.95  0.95

A nominal fuel cell input voltage, Vin= 48VDC, is assumed.

Output voltage, Vo= 400VDC

Designing for the low input line condition (Vin=42VDC), input current Iin from the fuel cell is,

11050W
I in   263 A (2)
42V

The push pull DC/DC converter shown in Figure 1 comprises of two switches, T+ and T-. At the

maximum duty ratio of 0.45, rms current rating IT of the switches are,

I T  I in 0.45  176 A (3)

IRFP260N (200V, 50A) MOSFETs with 4 devices in parallel in each leg are then chosen.

High frequency transformer:

For obtaining an output voltage of 400VDC for the push-pull converter, a turns ratio of K=5 is

selected for the transformer. Center taps are available on both the primary and secondary sides as

shown in Figure 1.

The VA rating of the transformer is defined as the sum of the total primary and secondary

winding VA divided by two,

1
Vin I in I 
VATr     2 Vin  K  in  2   1.5Vin  I in  1.5  42  263  16600W  17.0kVA
2 2 2 K 
(4)

Voltage ratings of the transformer are selected as,

Primary voltage=80V, Secondary voltage=400V

Diode ratings:

The reverse blocking voltage is equal to the DC link voltage 400V. Since each diode is clamped

to the mid-point of the DC-link (200V), each diode can be rated for 300V.

The rms current through the diode, ID, is given by

Page 7 of 40
I in
ID   37.2 A (5)
K 2

Therefore, 60EPU04 (400V, 60A), fast recovery diodes are selected.

Design of Current Mode PWM Controller:

The DC-DC Converter uses the 3-terminal push-pull topology to boost the 48V from the fuel cell

to 200V at a switching frequency of 40kHz. The push-pull DC-DC converter is controlled by

means of a high speed PWM controller UC3825B (datasheet attached in Appendix C). The special

features of this controller are: suitability for current control; soft start; over current and under

voltage protection; low propagation delay; high current dual outputs and low cost.

Current mode control has numerous advantages over simple voltage mode control,

including making the converter respond faster to load changes. In particular the UC3825B is

suitable for the fuel cell inverter application because it allows direct control over the power drawn

from the fuel cell. The error amplifier output in the outer voltage loop defines the level at which

the primary current (in the inner current loop) will regulate the pulse width and output voltage.

Pulse-by-pulse symmetry correction is a feature of current mode control and thus is essential for

flux balancing the transformer in the push-pull topology.

Design methodology for the current mode controller is as follows,

Timing section:

Oscillator frequency=40kHz; period=25 s

From the UC3825B data sheet, for a maximum duty cycle of 0.9, we have

3V 3
RT   2  3k
10mA(1  DMAX ) 10 (1  0.9)
1.6 DMAX 1.6(0.9)
CT    12nF
RT F 3(103 )(40)(103 ) (6)

which yields a TON=22.5 s, TOFF=2.5 s.

Power input to the DC-DC converter, Pin is

Page 8 of 40
Pin  11050W

The primary current under minimum fuel cell input voltage (42V) conditions, Iin is

I in  263 A

For a duty cycle of 0.9, RMS of the primary current is

263
I in ,rms  0.9  278 A (7)
0.9

Current sensing:

To obtain 1.0V at 400A, current sensing resistor Rs = 0.0025 is used. We shall use 4 power

resistors rated 0.01 , 75W in parallel (See DC-DC converter schematic in Appendix A).

Accounting for voltage drops on the secondary side, the transformer secondary voltage is 410V.

Hence a transformation ratio of 1:10 is selected. This would result in a transformer turns ratio of

1:5 for the push-pull topology.

The output current Io,

10500
Io   26 A (8)
400

Assuming the RMS ripple of Io to be 15%, the peak-to-peak ripple is 8A.

Thus the required value of inductor can be computed as,

dt 11.25s
L  Vsec  410V  576H  600 H (9)
dI 8A

PWM control section:

Slope compensation is required to compensate for the peak to average differences in primary

current as a function of the pulse width. The downslope of the inductor current is,

dI 8A
  0.71 A s (10)
dt 11.25s

This value when reflected to the primary side (multiplying by the transformation ratio) yields

0.71  10  7.1 A s

Page 9 of 40
Equivalent ramp downslope voltage VSL available across the sense resistor is,

VSL'  7.1  2.5  10 3  0.01775V s (11)

Slope of the oscillator waveform VOSC is,

1.8V
VOSC   0.08V s (12)
22.5s

If the amount of inductor downslope voltage to be added to the oscillator waveform is 75%, then

a resistive divider with resistors 10k and 30k can be selected.

Input Capacitor :

Selecting a proper input capacitor C1 (Figure 1) contributes to the reduction in fuel cell input

current ripple. In this section, the selection of C1 is detailed.

The average input current Iavg at full load is 263A.

Assuming a square wave input current, for a duty ratio of 0.9, the peak current I,

263
I  292 A (13)
0.9

and the RMS current Irms is,

I rms  292 0.9  277 A (14)

Therefore the RMS capacitor current Ic,rms ,

I c ,rms  I rms
2
 I avg
2
 92 A (15)

Based on the rated ripple current, 4 Rubycon Aluminum electrolytic capacitors 22000 F, 100V

each are selected.

The simulation results for a 10kW load on the system are presented in Appendix B. Vds1,

Vds2 are the drain to source voltage across the MOSFETs T1 and T2 respectively. VDC is the

output voltage.

Page 10 of 40
3.2 Inverter Design Procedure for the 10kW TAMU Fuel Cell Inverter System

The schematic of the DC-AC Inverter circuit is shown in Figure 1. The inverter produces

two single-phase outputs, Phase-A and Phase-B. It is comprised of two half bridge inverters each

supplying a separate single-phase load at 120VAC, 60Hz. Consider the case when Phase-B is not

loaded and Phase-A is supplying full load (5000VA). The peak amplitude of the fundamental

frequency component is the product of ma and ½VDC, where ma is the modulation index. A

modulation index of 0.9 is assumed for this design.

The fundamental component of the inverter Phase-A output voltage VAO is,

VDC
V AO ,1  ma  sin( 1t ) 0  ma  1 (16)
2

The switching function sw1 of the half bridge inverter is

0.9
sw1  0.5 sin1t higher frequency terms (17)
2

The Phase-A output current (iAO) is assumed to contain fundamental and third harmonic

current components due to presence of nonlinear load. The current iAO can be expressed as,

i AO  2 I 1 sin(1t  1 ) 3I 3 sin(3 1t   3 ) ... (18)

The current through the IGBT, S1 (isA) is given by

isA  sw1  i AO
2 3
 I 1 sin(1t  1 ) I 3 sin(31t   3 ) ... (19)
2 2
0.9 0.9
2 I 1 cos 1  cos(21t  1  3I 3 cos  3  cos(31t   3 ) ...
2 2
Assuming the load current iA to consist of only fundamental (I1) and third harmonic component

(I3), we have,

I A,rms  I 12 I 32 (20)

Page 11 of 40
Further, assuming I3=0.7 I1 (which is typical of a single phase rectifier type nonlinear load) we

have,

I A,rms  1.22  I1

Since

5000
I A, rms   41.7 A (21)
120

the current I1 is,

41.7
I1   34 A (22)
1.22

Therefore, the largest component of the DC-link capacitor current ic is the fundamental frequency

current, the rms value of which equals

1
ic ,rms   I 1  17 A (23)
2

For a voltage ripple Vc less than 5% or 10V we have,

ic ,rms
Vc  (24)
C

ic ,rms 17
C   4500 F (25)
 Vc 10  2  60

Panasonic Electrolytic capacitors rated 100V, 4500 F are selected for this design.

Inverter switch ratings:

The rms current isA is 41.7A. Thus, rms current rating IT of each switch is

41.7
IT   30 A (26)
2

IXSH24N60 (600V, 48A) IGBTs are selected.

Page 12 of 40
3.3 DC-AC Inverter Output Filter Design Procedure

Figure 3 shows the topology for the output L-C filter. A transfer function is developed

from the schematic. The assumptions used in the analysis are, the output filter is lossless and the

third current harmonic current is 70% of the fundamental current frequency.

jnX L

Vi,n -jXC
Vo,n ZL1n
n

Figure 3: Output Filter

The transfer function for this type of filter is described by the equation

Vo , n jX C  Z L , n
Hn   . (27)
Vi , n nX L X C jZ L , n (n 2 X L  X C )

Where
Hn - transfer function

Vo ,n - output voltage harmonic

Vi ,n - input voltage harmonic

XC - capacitive component of impedance

XL - inductive component of impedance

Z L,n - impedance

n - harmonic order
For H 1  1 ; or X L  X C , then

 jX C  Z L ,1
H1  1. (28)
 jZ L ,1  X C

Page 13 of 40
At no load, Z L ,1   , therefore equation (27) is

XC 1
Hn    (29)
n XL  XC
2
X
n2  L 1
XC

In order to satisfy a THD requirement of less than 3%

1 X 34.333 (30)
 0.03  L 
X X n2
n2  L 1 C
XC

Non-Linear Load

An equivalent circuit used in finding filter characteristics for a non-linear load is shown in

Figure 4.

jhXL

-jXC
Vh Ih
h

Figure 4: Equivalent Circuit for a Non-Linear Load

The transfer function for this schematic is described by equation

jhX L  X C
Vh   Ih . (31)
X C  h2 X L

Where
Vh - equivalent voltage

h - harmonic order
Ih - current at h harmonic

XC - capacitive component of impedance

XL -inductive component of impedance


equation (31) can then be shown as

Page 14 of 40
hX L
Vh   Ih . (32)
2 XL
1 h
XC

XL X
Here is very small making h 2 L  1 , therefore
XC XC

Vh  hX L  I h (33)

For the third harmonic h  3 , we have

V3 3X L  I 3 V3
 , where THD is  0.03 or 3% . Inductor impedance can be found by
V1 V1 V1

0.03  V1
XL  (34)
3* I 3

Output Filter Design

Let f s be defined as the switching frequency and f1 be defined as the fundamental


fs X
frequency. Then for f s  20kHz , f1  60Hz , and n   333.33 , L  3.09 x10  4 the
f1 XC
filter resonant frequency f r can be found with

fr XC n2
   56.89 . (35)
f1 XL 34.333

f r  3413 Hz

The 10 KW inverter (5 KW per Phase) with V1  120V , produces I rms  41.67 A ,

I 3  25.95 A . Use equation (34) to find X L  0.046 . Then, using

XL
L (36)
2 f1

Where
L - inductance
f1 - fundamental frequency

XL - inductance component of impedance

Page 15 of 40
where f 1  60Hz , the inductance will be L  123H .

To find the capacitor impedance use the equation (30), to get X C  148.9 , then using

1
C (37)
2 f1  X C

where
C - capacitance
XC - capacitor component of impedance

f1 -fundamental frequency

and f 1  60Hz , capacitance will be C  18 F .


Simulation results for a 10kW load on the system are presented in Appendix B.

4.0 Schematics
The following detailed schematics are attached in Appendix A.

A1. DC-DC Converter: complete design schematic

A2. DC-DC Converter voltage feedback and protection circuit details

A3. Inverter power circuit and gate control

A4. Inverter voltage and current sensing and protection circuitry (Sheet 1)

A5. Inverter voltage and current sensing and protection circuitry (Sheet 2)

A6. DSP Control board schematic (Sheet 1)

A7. DSP Control board schematic (Sheet 2)

Page 16 of 40
5.0 Bill of Materials
In this section, a detailed bill of materials is developed for the DC-DC converter and DC-

AC inverter subsystems. The components in the bill of materials are shown in schematics in

Appendix A.

Table 1: Bill of Materials for DC/DC Converter, Bulk Capacitors and its associated control
& protection circuitry (refer Figures A1-A2 in Appendix A)

Description Type Rating Quantity


MOSFETs IRFP260N 200V, 50A 8
PWM Controller UC3825B 1
Opto-isolated gate HCPL3120 2
driver
Power Diodes 60EPU04 400V, 60A 4
Input Capacitor Electrolytic 100V, 22000 F 4
Bulk Capacitors Electrolytic 250V,4500 F 2
Transformer 17kVA, 1
400V,38Arms
Inductors Coupled 300 H, 38A 2
Sense resistors 0.01ohm,75W 4
High frequency Film 1200V, 0.1 F 1
capacitor
Snubber resistor 500ohm, 10W 2
Snubber capacitor 1000V, 150pF 1
Power resistors 56k, 7W 2
Power diode 600V,15A 1
DC Input connector 1
Control input connectors 6
Op-amp LF347 1
Op-amp LF356 1
3-input NOR gates CD4023 1
2-input NOR gates C4011 1
Thermal switch 5R13-90M 1
Power supply 48IMP12-051515-7 1
Heatsink 1
LEDs 5
Switches 2
LCD Display 1
Zener diodes 4
Resistors 2W 4
Resistors 1W 2
Resistors 0.25W 37
Potentiometers 10k 1
Potentiometers 2k 2
Capacitors 50V 17

Page 17 of 40
Table 2: Bill of Materials for DC/AC Inverter, Output Filter and its associated control &
protection circuitry (refer Figures A3-A5 in Appendix A)

Description Type Rating Quantity


IGBT IXSH24N60 600V, 48A 4
Gate Drive IC IR2110 4
Filter Inductors 123 H, 42A 2
Filter Capacitors 18 F, 200V 2
Diodes FR104 4
Capacitors Film 0.22 F, 1600V 4
Control input connector 1
AC output connectors 2
Thermal switch F11U 2
Current Transformer D1871 4
Current sensor LA55-P 2
Isolation Amplifier AD202JN 2
Opto-isolator 6N137 7
Op-amps LF347 3
Op-amps LM358 1
CMOS NAND gates CD4001 1
Potentiometers 10k 6
Schottky diodes LN4148 27
Zener diodes 3
Diodes 1N5401 2
Power supply 48IMP12-051515-7 15V,5V 3
Heatsinks 4
LED 5
Switches 3
Resistors 0.25W 66
Capacitors 50V 24

Page 18 of 40
Table 3: Bill of Materials for DSP Control Board
(refer DSP Schematics in Appendix A)

Description Type Quantity


DSP TMS320LF2407 1
CMOS AND gate 74LCX08 1
Serial communication Max232 1
IC
Signal translator P15C3245 1
D/A converter TLV5619 1
Voltage regulator TPS7333 1
7.372MHz oscillator Xc263 1
Zener diode LM4040 1
Ferrite beads 3
Resistors 0.25W 11
Jumpers 5
Capacitors 19
RS232 header 1
Headers 1

6.0 Cost Evaluation


With the practical experience gained by the working budget, the team’s industry partners

and the faculty advisors, the team was able to make well-informed design decisions to

aggressively lower the cost of the final 10kW design and 1.5kW prototype. The TAMU fuel cell

inverter team’s approach to reducing the cost of the inverter by reducing the number of high cost

switching devices by adopting push-pull topology, using a low cost PWM DC-DC controller and

including an efficient DSP DC-AC control board.

By use of the push–pull topology the number of MOSFETs was minimized to half that

needed by a full bridge topology. IGBT’s were reduced in the inverter by use of the half bridge

topology as opposed to the full bridge topology. The analog PWM controller provided a low cost

solution to control of the DC-DC converter. It provides a single chip control solution opposed to

complex discrete analog hardware. DSP control of the DC-AC inverter provides sophisticated

control at low cost. Further, the DSP enables software control of the inverter and adaptability for

stand-alone and utility interface modes. Software control translates into efficiency in human

capital reducing costs of analysis, troubleshooting, development and manufacturing of the fuel

Page 19 of 40
cell inverter. The use of the DSP allows a seamless interface with other components of a power

management system, saving integration time and human resources. The topology of the TAMU

Fuel cell Inverter System employs a high voltage battery floating on the DC-link. This approach

does not add any additional power processing cost for load management.

The cost for the power components of the TAMU Fuel Cell Inverter system were

calculated by developing the cost of the DC-DC converter and the DC-AC inverter and adding

the two components together. The cost analysis was based on the schematic shown in Figure 1

and the 10kW design procedure detailed in this report. The results of the cost analysis for the

DC-DC converter are seen on the normalized spreadsheet Table 4 and the results of the DC-AC

inverter costs are seen in Table 5.

As per the cost analysis spreadsheet provided by the 2001 Future Energy Challenge

Committee, the cost of the DC-DC converter was $598.09. The cost of the DC-AC inverter

$198.69. The total cost of the TAMU Fuel Cell System was $796.78. It should be noted that the

cost analysis spread sheet (Tables 4 & 5) do not give the absolute cost and assumes a fixed cost

for control and packaging. These costs are highly dependent on the type of design and the

number of units manufactured per month.

The TAMU inverter control is based on a low cost DSP (TMS320C24X). Our design and

experimental prototype has demonstrated that sophisticated control algorithms can be

implemented on this DSP platform. Appendix D details a press release from Texas Instruments

and lists a cost of $2.98 for the TMS320C24X DSP employed in the TAMU inverter design.

The TAMU Fuel cell Inverter Team believes that with a detailed analysis of the control

circuit and the ancillary components, this design can be mass produced and marketed for an

amount below the target cost of $500.

Page 20 of 40
2001 FUTURE ENERGY CHALLENGE

UNIVERSITY: Texas A&M University


NAME OF MAIN CONTACT: Dr. Prasad Enjeti
PROJECT NAME: TAMU Fuel Cell Inverter (10kW)
DATE: 24-Aug-01

VOLT VOLT CUR CUR UNIT EXTENDED


QTY DESIG UNIT MEASURE (Vpk) (Vrms) (Avg) (Arms) COST COST
DIODE
DIODE 4 D1,2,3,4 300 40 3.15 12.59
DIODE - DUAL MODULE
DIODE - DUAL MODULE
IGBT
IGBT
TRANSISTOR
MOSFET 8 T1,2 200 54 9.62 76.92
MOSFET
SCR
CAP (ALUM) uF
CAP (ALUM) 2 C2,3 4500 uF 250 39.04 78.09
CAP (ALUM) 4 C1 22000 uF 100 30.56 122.25
CAP (ALUM) uF
CAP (FILM) uF
CAP (FILM) uF
CAP (FILM) uF
CAP (FILM) uF
CAP (FILM) uF
CAP (FILM) uF
POWER RESISTOR W
POWER RESISTOR W
POWER RESISTOR W
CHOKE 2 L1 300 UH 38 65.09 130.18
CHOKE UH
TRANSFORMER 1 TR1 400 38 23.01 23.01
TRANSFORMER
TRANSFORMER
CONTACTORS
CONTACTORS
LOSSES W
CONTROL 88.61
PACKAGING 66.45
OTHER (EXPLAIN)
TOTAL 598.09
Table 4: DC-DC Converter Subsystem Costs

Page 21 of 40
2001 FUTURE ENERGY CHALLENGE

UNIVERSITY: Tesax A&M University


NAME OF MAIN CONTACT: Dr. Prasad Enjeti
PROJECT NAME: TAMU Fuel Cell Inverter (10kW)
DATE: 24-Aug-01

VOLT VOLT CUR CUR UNIT EXTENDED


DEVICE QTY DESIG UNIT MEASURE (Vpk) (Vrms) (Avg) (Arms) COST COST
DIODE
DIODE - DUAL MODULE
DIODE - DUAL MODULE
IGBT 4 S1,2,3,4 600 35 8.42 33.68
IGBT
IGBT
MOSFET
CAP (ALUM) uF
CAP (ALUM) uF
CAP (FILM) 2 C4,5 18 uF 200 3.94 7.88
CAP (FILM) uF
POWER RESISTOR W
POWER RESISTOR W
CHOKE 2 L2,3 123 UH 42 52.81 105.63
TRANSFORMER
CONTACTORS
CONTACTORS
LOSSES W
CONTROL 29.44
PACKAGING 22.08

OTHER (EXPLAIN)
TOTAL 198.69
Table 5: DC-AC Inverter Subsystem Costs

7.0 Conclusions

This report has discussed the design methodology and cost analysis for the 10kW Texas

A&M Fuel Cell Inverter System. The topology and control strategy for this design has been

adopted keeping in mind the specific objectives of the 2001 Future Energy Challenge Committee.

Keeping the cost of the product low and obtaining the best performance for the given cost have

been the most important objectives that were pursued throughout this design procedure.

However, we believe that with sophisticated manufacturing techniques available today in the

industry it is possible to further reduce the cost of the system.

Page 22 of 40
Appendix A

SCHEMATICS

Page 23 of 40
A B C D E

CN2

OH2 1 YELLOW
2 NC
3 NC
P15 4 NC
+BUS V 5 RED
N15
BUS FB P15A 6
4 7 GREEN 4

10k 8
30k 100uF YELLOW
P15 9
18k -BUS V 10
1 16 11 RED
2 INV VREF 15
42k 12 WHITE
3 NI VCC 14 0.1uF
120pF EA OUT OUTB SD 13 GREEN
4 13 DC VREF 14 NC
3k RT 5 CLOCK VC 12 0.1uF
RT PGND BUS FB 15 CYAN
R 6 11
7 CT OUTA 10
RAMP GND CN2
4.8nF 8 9
CT SS ILIM/SD
THD1
UC3825B
10k 1 2
OH2
SD

3 OHD5R13-90M 3
30k
30k
L6A
300uH
25A + BUS V

D1 D4 D6 R8
40A 40A 15A 56k
3

3
300V 300V 1200V C3
Q1 Q2 Q3 7W
4500uF
J1 54A 54A 54A 250V
1 C20
1 2 200V 1 200V 1 200V 1 Q4
54A 0.1uF C4
JUMPER R1 R2 R3 R4 1200V 4500uF
PC1 200V
P15A D2 D3 R9 56k 250V
10 10 10 10
2

2
1 8 40A 40A
2 7 300V 300V 7W
2 3 6 2
4 5 C22 L6A
0.1uFR12 300uH
- BUS V
50V 47K 1 T2
R22 HCPL-3120 25A
47K CN1 C5 C6
J3 C3 5
1 2 10uF 300uF 4700uF
1
100Vdc 100Vdc 100V 2 6
JUMPER 2
4 x 0.01ohm, 3 4 8
C7 C8 C4
75W each 4 4700uF
10uF 300uF 7
100Vdc 100Vdc 100V
J2 3
1 2 C10
3

3
JUMPER Q7 R10 150pF
Q5 Q6 Q8 500
54A 1000V
PC2 P15A 54A 54A 54A 10W
200V 200V 200V
1 8 1 1 1 1 200V
1 2 7 1
3 6
R5 R6 R7 R8
4 5 C21 Title
10 10 10 10
2

0.1uF Fig. A1: DC-DC CONVERTER - COMPLETE DESIGN SCHEMATIC


R24 50V
47K HCPL-3120
Size Document Number Rev
A 1.01 1
R11
47K Date: Friday, August 31, 2001 Sheet 1 of 5
A B C D E
A B C D E
+Vbw
C3 470pF
+200V

+
-15V
R14 6.8k
R1 U1C R7 10K
75k,1W POT1 2k

11
LF347 R13
POT1 2k 33k
5 + C1
9 -
8 5
R2 10 + U1B
470pF

11
1.2k LF347 -15V
R5 10k 6 - R15 1k

4
7 U2
R3 5 +
LF356

4
5
1.2k C2 +15V R6 10k
+
470pF R26 R16 2 - Power IN
2.2k 6

4
10k CN1
3 +
R4 Voltage Feedback 48G 1
75k, 1W U1D 2

11

7
1
LF347 +15V 3
13 - 48V 4
-200V 14 +15V
POT1 4 PIN HEADER
-Vbw 12 + +15V
10k
Outputs
CN2
4 4
4
D2
R9 470k LED +15V 1
CN5 G 2
FB 3
+15V 1 C4 SD
D1 4
G15 2 0.1uF OT
1N753 U1A 5
ON 3
6.2V R12 6
OV 4 LF347

4
+15V
OT 5 R10 10k 1.2k 6 PIN HEADER
3
+200V 6 Thermal Protection +
1
N 7
-200V D5 2 LCD
8 - Overvoltage Protection
R11 10k CN3
LED
8 HEADER 48V 1

11
+15V 48G 2
+200V 9V 3
R22 48G 4
R21
1.2k 4 PIN HEADER
1.5k ***Note: Reset pushbutton is
R17
10k,2W on the faceplate.

3 3
Switches
+15V CN4

R18 ***Note: Thermal 1


10k, 2W switch on DC R25 ON(SW) 2
OH2 90 deg C make RST
Boost.
330 ohm 3
+15V 4
U3 +15V U4 +15V
D3
1 14 1 14 4 PIN HEADER
Healthy +200V Indicator LED 2 13 2 13
3 12 3 12
4 11 4 11 Voltage Feedback
5 10 5 10 CN6
+15V 6 9
D4 6 9
Healthy -200V Indicator 7 8 7 8 -200V 1
LED N 2
3
CD4023 CD4011 +200V 4
***Note: On/Off switch
on faceplate. SPST SWITCH 4 PIN HEADER
R10 1k
R19 Shut Down
10k, 2W
2 R24 D1 2
R23 1N4733
1.2k 5.1V
R20 510
15V
10k, 2W
D6
-200V LED
R28 9V for
510 LCD
1/2W Display

9V
D7
1N747A
3.6V + C4
0.1uF

D8
1N753A
1 6.2V
GND
Title
1
FIG. A2: DC-DC CONVERTER VOLTAGE FEEDBACK AND PROTECTION SCHEMATIC

Size Document Number Rev


A4 {Doc} 0

Date: Friday, August 31, 2001 Sheet 2 of 5

A B C D E
A B C D E

+ 15v E10 RAILPOS


C9 C8
0.22uF 0.22uF
C12 C5 1600Vdc 1600Vdc
+
10uF 0.1uF
50V 50V
4 4
FR104
U1 Q1
R1 IGBT
9 7 1 2
VDD HO 600V,35A
10

1
10 6

1
G+ C1 C2
HIN VB 1uF 1uF
11 5 50V R13
SHUTDOWN SD Vs 50V FR104
10k

2
12 3 OUTPUT TO FILTER
G- LIN VCC

2
13 2 FR104
VSS COM
1
LO CR6
FR104
IR2110

Q2
1

C14 C7 R4
1 2 IGBT
10uF 0.1uF
10 600V,35A
50V 50V

1
2

R10
3 FR104 10k 3

E9 RAILNEG

J1

+15V 1 2
3 4
G+ 5 6
G- 7 8
SHUTDOWN 9 10
11 12
drnI 13 14 RET

Thermal switch 90C


SWT1
2 2

1 1

Title
FIG. A3: INVERTER POWER CIRCUIT AND GATE CONTROL

Size Document Number Rev


A 2.01 0

Date: Friday, August 31, 2001 Sheet 3 of 5


A B C D E
A B C D E
+15V
+15V

R16
680

4
OPAMP1
3
+
5 2
-
1
+3.3V 5
D0
+5VDSP Optocouplers

11
R19
ISO1 +15V2
-15V 390
8
2 7
R20
U8A C7 1k
Voltage Sensor 1 R5 10k 1 2 3 6
0.1uF
35V
PWM2
+15V 3.3V
5 Gate Driver 1
74LS14
POT1 50k D1 6N137
ISOAMP1

4
R4 10k OPAMP1
38 19 5
FB HI +
7
R1 R2 VSENSE1 +5VDSP
3 6
4 470k 470k 1 -IN
+IN LO
18 R3 10k -
D2 4
Vout1 R21
2 15V 50k POT2
ISO2 +15V2

11
IN COM 20 3.3V 390
+15DC 8
36 2 7
37 +VISO 22
-VISO PWR RET C1 -15V R22
C2 22p U8B
0.1uF C8 1k
35V
AD202JN 35V 0.1uF
3 4 3 6 35V
PWM1
5 Gate Driver 2

Voltage Sensor 2 R10 10k


3.3V
74LS14
6N137
+15V

POT3 50k D3
ISOAMP2 +5VDSP

4
R8 10k OPAMP1
38 19 10
FB HI +
8
R6 R7 VSENSE2 R23
3 3
1 -IN 18 R9 10k
9
-
D4 390
ISO3 +15V2 3
470k 470k +IN LO 8
Vout2
2 15V 50k POT4 2 7

11
IN COM 20 3.3V R24
+15DC U8C C9
36 1k
37 +VISO 22 0.1uF
-VISO PWR RET C3 -15V 5 6 3 6
C4 22p 35V
PWM4
0.1uF 35V
AD202JN 35V 5 Gate Driver 3
74LS14
6N137

Current Sensor 1 R14 10k +5VDSP

+15V
T1 +15V -15V 3.3V
R25
1 ISO4 +15V2
+ 390 8
4

R12 10k OPAMP2 D5 2 7


11

2 3 OPAMP2
R13 10k R26
M +
1 6 U8D C10 1k
2 2
-
-15V R11 C5 2 7 0.1uF
3 680p
-
5 ISense1
82 + 9 8 3 6 35V
- 35V D6 PWM3
50k
3.3V 5 Gate Driver 4
11

LA 55-P
4

POT5 74LS14
6N137
-15V
+15V

Current Sensor 2 R18 10k

+15V
T1 +15V -15V 3.3V
1
+
4

R16 10k OPAMP2 D7


11

2 10 OPAMP2
M + R17 10k
8 13
1 1
-
-15V R15 C6 9 14
3 680p
-
12 ISense2 Title
- 82 +
35V D8 FIG. A4: INVERTER VOLTAGE & CURRENT SENSING AND PROTECTION CIRCUITRY (1 OF 2)
POT6
3.3V
11

LA 55-P
Size Document Number Rev
4

50k
Custom 2.02
-15V
+15V
Date: Friday, August 31, 2001 Sheet 4 of 5

A B C D E
A B C D E
J1
JP3
+15V 1 2
34 33 ISENSE2 3 4
32 31 ISENSE1 Gate Driver 1 5 6
30 29 Gate Driver 2 7 8
28 27 SHUTDOWN 9 10
26 25 VSENSE2 Temperature1 11 12
24 23 +15V
13 14
5 22
20
21
19
VSENSE1
Inverter A Header 5
18 17
16 15 POT
14 13 50k
12 11
10 9 ***There is only one SHUTDOWN
8 7 PWM4 OPAMP6D signal shared between both
6 5 PWM3 R37 inverter boards.

11
PWM2 10k LF347
4 3
PWM1 13 U?A
2 1 -
14 1 U?C
R36 NOR1
DSP Header 12 + 3 8 +15V
2 10 1 14
150 ohm 9 2 13
J2
3 12 C17

4
4071
+15V 1 2 Current sensor1 4 11 104
4071
3 4 5 10
Current sensor2 6 9
Gate Driver 3 5 6
Gate Driver 4 Current sensor return 47 ohm 7 8
7 8 D13 +15V
SHUTDOWN 9 10 1N4148
4 Temperature2 11
13
12
14
MC14001BCP
4
R43 +15V JP?
Inverter B Header 680
1
2
3
4
D9 +15V
C14 R44 HEADER 4
1N4148
221 47k
ISense1

D10 POT
1N4148 R27 10k R28 10k R33 R34 50k
***Pins 3 and 4 connect to an external NOPB switch on the
10k 10k
+15V Inverter Box interface. Pins 1 and 2 connect to an LED on
R37 OPAMP6C the Inverter Box interface for shutdown notification.

11
OPAMP6B
10k LF347

11
OPAMP6A LF347
R29 10k 9
11

D13
-
LF347 C13
1N4148 6 - R35 10k 8
152 R36
3 C11
152
2 -
1
R31
5 +
7
10k
10 +
D15 3
3 +
C15 1N4148
10k
D14

4
R32 221
R30 1N4148 C12
4

10k +15V
4

10k 221

D11 -15V R19


D12 ISO1
1N4148 +15V2
2k
ISense2 8
2 7
1N4148 R20
C7 10k
0.1uF
3 6 35V SHUTDOWN
Fuel Cell Ready 5
R19
ISO1 +15V 6N137
390
8
2 2 7
R20
2
C7 10k
0.1uF
3 6 35V
5

U?B
6N137
5
4
6

R19 390
4071
Fuel cell input
D?
ISO1 +15V
DIODE ZENER 8
2 7
R20
1 C7
0.1uF
10k
Title
1
3 6 35V FIG. A5: INVERTER PROTECTION CIRCUITRY (2 OF 2)
5
Size Document Number Rev
6N137 A4 {Doc} 0

Date: Sunday, September 02, 2001 Sheet 5 of 5

A B C D E
1 2 3 4

U1A U1B U1C EVA


ADC 37 83 cap1
tclkina cap1
adc0 112 109 adc10 CAN/SCI/SPI 14 79 cap2
ADCIN00 ADCIN10 tdira cap2
adc1 110 108 adc11 70 33 iopc5 18 75
ADCIN01 ADCIN11 CANRX SPISTE* t2pwm cap3
adc2 107 106 72 32 16 56 pwm1
ADCIN02 ADCIN12 CANTX SPISOMI t1pmw pwm1
adc3 105 104 iopa0 25 30 pwm6 40 54 pwm2
ADCIN03 ADCIN13 SCITXD SPISIMO pwm6 pwm2
103 101 iopa1 26 35 iopc4 pwm5 44 52 pwm3
ADCIN04 ADCIN14 SCIRXD SPICLK pwm5 pwm3
102 98 33V 47 pwm4
D ADCIN05 ADCIN15 pwm4 D
100 115
ADCIN06 VREFHI
99 114
ADCIN07 VREFLO
adc8 113 116 33V External Interrupts, Clock EVB
ADCIN08 VCCA
adc9 111 117 rs 133 137 88 55
ADCIN09 VSSA RS* PKPINTB CAP4 PWM10
23 73 81 46
R7 XINT1 CLKOUT CAP5 PWM11
L2 7 21 69 38
PDPINTA* XINT2 CAP6 PWM12
Fbead 10k 65 8
PWM7 T3PWM
pdpa 62 6
PWM8 T4PWM
33V 59 2
PWM9 TDIRB
Power 126
TCLKINB
cc1 33V 29 140 GND Oscillator, PLL, Flash, Boot, Misc 10k
VDD VSS0
33V 50 125 GND clkin 123 119
VDD VSS0 XTAL1 BIO* R6
33V 86 94 GND 124 63
VDD VSS0 XTAL2 TP2
cc2 33V 129 76 GND 12 60 Address, Data, Memory Control 33V J8
VDD VSS0 33V PLLV TP1
33V 4 66 GND 131 58 87 97 1
VDD0 VSS0 IOPF6 VCCP(5) DS* VIS_OE
33V 42 41 GND 121 10 82 122 2
VDD0 VSS0 BOOTEN* PLLF2 IS* ENA144
cc3 33V 67 3 GND 11 .33uF C2 84 118 3
VDD0 VSS0 PLLF PS* MP/MC*
33V 77 128 GND 92 120
VDD0 VSS0 R/W* READY
cc4 33V 95 85 GND iopc0 19 96
VDD0 VSS W/R* STRB*
33V 141 49 GND C1 93 89 we 5V 5V
VDD0 VSS RD* WE*
28 GND
VSS R5
C 6800pF C

11
DSP 16 ohm C4
TLV5619 / 296-1925-5 U2 0.1uF
80 127 19
A0 D0 D0

VDD
78 130 20 C3
A1 D1 D1
74 132 1 470pF
A2 D2 D2
71 134 2
A3 D3 D3
Emulation and test / JTAG 68 136 3 12
A4 D4 D4 VREF
trst 1 64 138 4 13 DACout
TRST* A5 D5 D5 AnalogOut
tck 135 61 143 5 14
TCK A6 D6 D6 GND
tms 144 57 5 6
TMS A7 D7 D7
36 53 9 7 L3
TMS2 A8 D8 D8
tdi 139 51 13 8 Fbead

LDAC*
TD1 A9 D9 D9
tdo 142 48 15 9

WE*
TD0 A10 D10 D10

PD*
CS*
emu0 90 45 17 10
EMU0 A11 D11 D11
emu1 91 43 20
EMU1 A12 D12
39 22
A13 D13
DSP 34 24
A14 D14

18
we 17
16
15
R3 R2 31 27
A15 D15 5V
10k 10k
DSP
TMS320LF2407, 144 pin device broken into its functional blocks
B 33V B

33V
H3
tms 1 2 trst R1

3
2
1
tdi 3 4 10k J7
5 6 5V C30
5V R4 .1uF
tdo 7 8
tck 9 10 10k
11 12
3
2
1

3
2
1
emu0 13 14 emu1 J4 J3

Header / s2212-07

A A
Title
TAMU Fuel Cell Inverter / DSP Layout
Size Number Revision
Letter
Date: 3-Sep-2001 Sheet of
File: C:\Mark\ee405\doe_ieee\protel\doe_v2.ddb Drawn By: M. Yeary
1 2 3 4
1 2 3 4 5 6

C24
33V U6 C26
D 1 D
c1+
C25 0.1uF 3 2 0.1uF
c1- v+
R8 6
v-
1.62k 4 0.1uF
c2+ H5
0.1uF 5
c2-
U12 33V C27 1
1 14 6
1A VCC
2 13 iopa0 11 14 2
1B 4B T1in T1out
rs 3 12 iopc0 10 7 7
2

1Y 4A T2in T2out
4 11 3
2A 4Y
5 10 13 12 8
2B 3B R1in R1out
6 9 8 9 4
2Y 3A R2in R2out
7 8 9
GND 3Y
15 16 5
VSS VCC 5V
J9 74LCX08
jumper max232 a23303 / rs232header
1

5V
R10
4.7k
5V
C C
R12
U4 1.62k
TPS7333 / 296-8066-5 U10
1 8 20
GND RESET* VCC
5V 2 7 H4 1 19
EN* FB/NC NC BE* C29 D2
3 6 33V pwm1 1 2
IN OUT 0.1uF LM4040AIM3-4.1
4 5 pwm2 3 4 iopa1 2 18
IN OUT A0 B0
pwm3 5 6 clkin 3 17
A1 B1
pwm4 7 8 4 16
A2 B2
pwm5 9 10 cap1 5 15
A3 B3
pwm6 11 12 cap2 6 14
A4 B4
13 14 iopc4 7 13
A5 B5
15 16 iopc5 8 12
A6 B6
Text DACout 17 18 pdpa 5V 9 11
A7 B7
19 20
21 22 10
GND
23 24
25 26 PI5C3245
27 28
29 30
31 32
33 34
B B
Header
5V U7
L4 R13
8 5
Fbead Vcc out
1 4 33
C28 nc GND
0.1uF xc263

decoupling caps
cc1

cc2

cc3

cc4

C16 C17 C18 C19 C20 C21 C22 C23


0.1uF 470pF 0.1uF 470pF 0.1uF 470pF 0.1uF 470pF

A A

Title
TAMU Fuel Cell Inverter / DSP Layout
Size Number Revision
B
Date: 3-Sep-2001 Sheet of
File: C:\Mark\ee405\doe_ieee\protel\doe_v2.ddb Drawn By: M. Yeary
1 2 3 4 5 6
Appendix B

SIMULATION RESULTS

Page 31 of 40
Simulation Results for the inverter system on 10kW load are presented here.

A. DC-DC Converter Performance

Figure B1: Voltages of the DC-DC converter


Where, Vds1,Vds2 – Drain to Source voltages across the MOSFETs
VDC – Output voltage of DC-DC converter

Figure B2: Currents of the DC-DC converter


where, IT1, IT2 – Current through the MOSFETs
Iin – Input current to DC-DC converter

Page 32 of 40
Figure B3: Currents of the DC-DC converter (contd.)
where, I(D1) – Current through diode D1
Io+, Io- – Output currents of the DC-DC converter

Figure B4: Inverter output voltages and currents


where, Va,Vb – Phase-A and Phase-B output voltages
Ia, Ib – Phase-A and Phase-B load currents

Page 33 of 40
Appendix C

UC3825B DATASHEET

Page 34 of 40
application UC1823A,B/1825A,B
INFO UC2823A,B/2825A,B
available
UC3823A,B/3825A,B
High Speed PWM Controller
FEATURES DESCRIPTION
• Improved versions of the The UC3823A & B and the UC3825A & B family of PWM control ICs are
UC3823/UC3825 PWMs improved versions of the standard UC3823 & UC3825 family. Performance
enhancements have been made to several of the circuit blocks. Error ampli-
• Compatible with Voltage or
Current-Mode Topologies fier gain bandwidth product is 12MHz while input offset voltage is 2mV. Cur-
rent limit threshold is guaranteed to a tolerance of 5%. Oscillator discharge
• Practical Operation at Switching current is specified at 10mA for accurate dead time control. Frequency ac-
Frequencies to 1MHz curacy is improved to 6%. Startup supply current, typically 100µA, is ideal
• 50ns Propagation Delay to Output for off-line applications. The output drivers are redesigned to actively sink
current during UVLO at no expense to the startup current specification. In
• High Current Dual Totem Pole addition each output is capable of 2A peak currents during transitions.
Outputs (2A Peak)
Functional improvements have also been implemented in this family. The
• Trimmed Oscillator Discharge Current UC3825 shutdown comparator is now a high-speed overcurrent comparator
• Low 100µA Startup Current with a threshold of 1.2V. The overcurrent comparator sets a latch that en-
sures full discharge of the soft start capacitor before allowing a restart.
• Pulse-by-Pulse Current Limiting While the fault latch is set, the outputs are in the low state. In the event of
Comparator continuous faults, the soft start capacitor is fully charged before discharge
• Latched Overcurrent Comparator With to insure that the fault frequency does not exceed the designed soft start
Full Cycle Restart period. The UC3825 Clock pin has become CLK/LEB. This pin combines
the functions of clock output and leading edge blanking adjustment and has
been buffered for easier interfacing.
(continued)
BLOCK DIAGRAM

UDG-95101
* Note: 1823A,B Version Toggles Q and Q are always low

SLUS334A - AUGUST 1995 - REVISED NOVEMBER 2000


UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
DESCRIPTION (cont.) ABSOLUTE MAXIMUM RATINGS
The UC3825A,B has dual alternating outputs and the Supply Voltage (VC, VCC) . . . . . . . . . . . . . . . . . . . . . . . . . 22V
same pin configuration of the UC3825. The UC3823A,B Output Current, Source or Sink (Pins OUTA, OUTB)
outputs operate in phase with duty cycles from zero to DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A
less than 100%. The pin configuration of the UC3823A,B Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2A
Power Ground (PGND). . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.2V
is the same as the UC3823 except pin 11 is now an out- Analog Inputs
put pin instead of the reference pin to the current limit (INV, NI, RAMP). . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 7V
comparator. “A” version parts have UVLO thresholds (ILIM, SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 6V
identical to the original UC3823/25. The “B” versions Clock Output Current (CLK/LEB) . . . . . . . . . . . . . . . . . . . –5mA
have UVLO thresholds of 16 and 10V, intended for ease Error Amplifier Output Current (EAOUT) . . . . . . . . . . . . . . 5mA
of use in off-line applications. Soft Start Sink Current (SS) . . . . . . . . . . . . . . . . . . . . . . . 20mA
Oscillator Charging Current (RT) . . . . . . . . . . . . . . . . . . . –5mA
Consult Application Note U-128 for detailed technical Power Dissipation at TA = 60°C . . . . . . . . . . . . . . . . . . . . . . 1W
and applications information. Contact the factory for fur- Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
ther packaging and availability information. Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . . 300°C
Device UVLO Dmax All currents are positive into, negative out of the specified ter-
UC3823A 9.2V/8.4V < 100% minal. Consult Packaging Section of Databook for thermal limi-
UC3823B 16V/10V < 100% tations and considerations of packages.
UC3825A 9.2V/8.4V < 50%
UC3825B 16V/10V < 50%

CONNECTION DIAGRAMS

DIL-16, SOIC-16, (Top View) PLCC-20, LCC-20, (Top View)


J or N Package; DW Package Q, L Packages

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for
the UC1823A,B and UC1825A,B; –40°C to +85°C for the UC2823A,B and UC2825A,B; 0°C to +70°C for the UC3823A,B and
UC3825A,B; RT = 3.65k, CT = 1nF, VCC = 12V, TA = TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Reference Section
Output Voltage TJ = 25°C, Io = 1mA 5.05 5.1 5.15 V
Line Regulation 12 < VCC < 20V 2 15 mV
Load Regulation 1mA < IO < 10mA 5 20 mV
Total Output Variation Line, Load, Temp 5.03 5.17 V
Temperature Stability TMIN < TA < TMAX (Note 1) 0.2 0.4 mV/°C
Output Noise Voltage 10Hz < f < 10kHz (Note 1) 50 µVRMS
Long Term Stability TJ = 125°C, 1000 hours (Note 1) 5 25 mV
Short Circuit Current VREF = 0V 30 60 90 mA

2
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for
the UC1823A,B and UC1825A,B; –40°C to +85°C for the UC2823A,B and UC2825A,B; 0°C to +70°C for the UC3823A,B and
UC3825A,B; RT = 3.65k, CT = 1nF, VCC = 12V, TA = TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Oscillator Section
Initial Accuracy TJ = 25°C (Note 1) 375 400 425 kHz
Total Variation Line, Temperature (Note 1) 350 450 kHz
Voltage Stability 12V < VCC < 20V 1 %
Temperature Stability TMIN < TA < TMAX (Note 1) 5 %
Initial Accuracy RT = 6.6k, CT = 220pF, TA = 25°C (Note 1) 0.9 1 1.1 MHz
Total Variation RT = 6.6k, CT = 220pF (Note 1) 0.85 1.15 MHz
Clock Out High 3.7 4 V
Clock Out Low 0 0.2 V
Ramp Peak 2.6 2.8 3 V
Ramp Valley 0.7 1 1.25 V
Ramp Valley to Peak 1.6 1.8 2 V
Oscillator Discharge Current RT = Open, VCT = 2V 9 10 11 mA
Error Amplifier Section
Input Offset Voltage 2 10 mV
Input Bias Current 0.6 3 µA
Input Offset Current 0.1 1 µA
Open Loop Gain 1V < VO < 4V 60 95 dB
CMRR 1.5V < VCM < 5.5V 75 95 dB
PSRR 12V < VCC < 20V 85 110 dB
Output Sink Current VEAOUT = 1V 1 2.5 mA
Output Source Current VEAOUT = 4V –0.5 –1.3 mA
Output High Voltage IEAOUT = –0.5mA 4.5 4.7 5 V
Output Low Voltage IEAOUT = 1mA 0 0.5 1 V
Gain Bandwidth Product F = 200kHz 6 12 MHz
Slew Rate (Note 1) 6 9 V/µs
PWM Comparator
RAMP Bias Current VRAMP = 0V –1 –8 µA
Minimum Duty Cycle 0 %
Maximum Duty Cycle 85 %
Leading Edge Blanking R = 2k, C = 470pF 300 375 450 ns
LEB Resistor VCLK/LEB = 3V 8.5 10 11.5 kohm
EAOUT Zero D.C. Threshold VRAMP = 0V 1.1 1.25 1.4 V
Delay to Output VEAOUT = 2.1V, VRAMP = 0 to 2V Step (Note 1) 50 80 ns
Current Limit/Start Sequence/Fault Section
Soft Start Charge Current VSS = 2.5V 8 14 20 µA
Full Soft Start Threshold 4.3 5 V
Restart Discharge Current VSS = 2.5V 100 250 350 µA
Restart Threshold 0.3 0.5 V
ILIM Bias Current 0 < VILIM < 2V 15 µA
Current Limit Threshold 0.95 1 1.05 V

3
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for
the UC1823A,B and UC1825A,B; –40°C to +85°C for the UC2823A,B and UC2825A,B; 0°C to +70°C for the UC3823A,B and
UC3825A,B; RT = 3.65k, CT = 1nF, VCC = 12V, TA = TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Current Limit/Start Sequence/Fault Section (cont.)
Over Current Threshold 1.14 1.2 1.26 V
ILIM Delay to Output VILIM = 0 to 2V Step (Note 1) 50 80 ns
Output Section
Output Low Saturation IOUT = 20mA 0.25 0.4 V
IOUT = 200mA 1.2 2.2 V
Output High Saturation IOUT = 20mA 1.9 2.9 V
IOUT = 200mA 2 3 V
UVLO Output Low Saturation IO = 20mA 0.8 1.2 V
Rise/Fall Time CL = 1nF (Note 1) 20 45 ns
UnderVoltage Lockout
Start Threshold UCX823B and X825B only 16 17 V
Stop Threshold UCX823B and X825B only 9 10 V
UVLO Hysteresis UCX823B and X825B only 5 6 7 V
Start Threshold UCX823A and X825A only 8.4 9.2 9.6 V
UVLO Hysteresis UCX823A and X825A only 0.4 0.8 1.2 V
Supply Current
Startup Current VC = VCC = VTH(start) –0.5V 100 300 µA
Icc 28 36 mA
Note 1:Guaranteed by design. Not 100% tested in production.

APPLICATIONS INFORMATION
OSCILLATOR Oscillator
The UC3823A,B/3825A,B oscillator is a saw tooth. The
rising edge is governed by a current controlled by the RT
pin and value of capacitance at the CT pin. The falling
edge of the sawtooth sets dead time for the outputs. Se-
lection of RT should be done first, based on desired
maximum duty cycle. CT can then be chosen based on
desired frequency, RT, and DMAX. The design equations
are:
3V
RT =
(10mA)(1 – D MAX )

(1.6 • DMAX )
CT =
(RT • F )

Recommended values for RT range from 1k to 100k.


Control of DMAX less than 70% is not recommended.
UDG-95102

4
Appendix D

COST INFORMATION ON TEXAS INSTRUMENTS


TMS320LF24X DSP

Page 39 of 40
Texas A&M University
2001 Future Energy Design Team
Final Report

Texas A&M University


Fuel Cell Inverter

Faculty Advisors

Dr. Prasad Enjeti


Dr. Mark Yeary
Dr. Jo Howze
Dr. Charles Culp
Texas A&M University, College Station, Texas
June 15, 2001
TAMU Fuel Cell Inverter Development Team

Student Members

Oscar Montero Nick Denniston


Samsung Kim Matt Campbell
Rajesh Gopinath Jared Machala
Eugene Song Wes Weibel
Randall Jones Cody Sicking
Mike Spence Nick Denniston
Gary Tobola Cory Cress
Phillip Briggs Andy Hale
David Leschber Jon Burghardt
Matthew Webster Mark Arldt
Lori Dalton Phillip Coleman
Douglas Becker David Payne
Justin Busse Steven Campbell

ii
Faculty Advisors

____________________________________ ___________________________________
Dr. Prasad Enjeti Dr. Mark Yeary
Department of Electrical Engineering Department of Electrical Engineering
e-mail: enjeti@ee.tamu.edu e-mail: mbyeary@ee.tamu.edu

_______________________________________ ______________________________________
Dr. Jo Howze Dr. Charles Culp
Department of Electrical Engineering Department of Mechanical Engineering
e-mail: howze@ee.tamu.edu e-mail: cculp@esl.tamu.edu

iii
Report Authors

___________________________________ ___________________________________
Rajesh Gopinath Matthew Webster
Department of Electrical Engineering Department of Electrical Engineering

______________________________________ ______________________________________
Phillip Briggs Douglas Becker
Department of Computer Engineering Department of Chemical Engineering

____________________________________ ___________________________________
Steven Campbell Jon Burghardt
Department of Electrical Engineering Department of Electrical Engineering

____________________________________ ___________________________________
Samsung Kim Chiranjib Mukherjee
Department of Electrical Engineering Department of Electrical Engineering

___________________________________
Justin Busse
Department of Electrical Engineering

iv
Table of Contents

List of Figures ...........................................................................................................................vii

List of Tables ............................................................................................................................viii

1. Summary ..................................................................................................................................1

2. Introduction.............................................................................................................................2

3. Design Rational and Feature Description .......................................................................3


3.1 Fuel Cell Rational and Requirements .........................................................................3
3.2 Inverter Application for a Fuel Cell..............................................................................4
3.3 TAMU Fuel Cell Inverter..................................................................................................6
3.4 DC-DC Converter..............................................................................................................7
3.4.1 Description and Approach......................................................................................7
3.4.2 DC-DC Converter Control Mechanism (Analog) .............................................10
3.4.3 DC-DC Converter Feedback System..................................................................11
3.4.4 DC-DC Converter Protection Circuitry ..............................................................12
3.4.5 Filtering Process (Noise Issues) .........................................................................13
3.4.6 DC-DC Converter Control Signal Conditioning...............................................13
3.4.7 DC-DC Converter DC- Link Design.....................................................................14
3.4.8 DC-DC Converter Design For The 10kW TAMU Fuel Cell Inverter System
................................................................................................................................................14
3.4.9 DC-DC Converter Specifications.........................................................................14
3.4.10 Design of the Control Circuit for the DC-DC Converter..............................15
3.5 DC-AC Inverter Design..................................................................................................17
3.5.1 Inverter Design Procedure for the 10kW TAMU Fuel Cell Inverter System
................................................................................................................................................18
3.5.2 DC-AC Inverter Subsystem Control ...................................................................20
3.5.3 Voltage Feedback....................................................................................................21
3.5.4 TAMU Fuel Cell Inverter Closed Loop Control Approach ............................22
3.5.5 Over Current Protection & Over Temperature Protection for DC-AC .......25
3.5.6 Output Filtering........................................................................................................25
3.5.7 DC-AC Inverter Output Filter Design Procedure.............................................26
3.5.8 Non-Linear Load ......................................................................................................27
3.5.9 Output Filter Design Example ..............................................................................28
3.5.10 Test Results ............................................................................................................29
3.6 Output: Monitoring and Computer Interface Via RS-232.....................................32
3.6.1 Transfer Protocol.....................................................................................................33
3.6.2 Software Functionality ...........................................................................................34
3.6.3 Testing, Implementation, and Analysis .............................................................35
4. Cost Evaluation ....................................................................................................................36

v
4.1 Tracking Chart & Budget..............................................................................................36
4.2 DC-DC Converter Costs................................................................................................40
4.3 DC-AC Inverter Costs....................................................................................................41
5. Demonstration of Operational success of the 1.5kW Prototype ............................42
Design of the Battery Backup System: ...........................................................................44
6. Responsibility Matrix & Organizational Approach .....................................................46
6.1 Institutional Commitment and Sources of Added Support ................................47
6.2 Impact on Undergraduate Education........................................................................47
7. Nomenclature .......................................................................................................................50

8. List of Acronyms .................................................................................................................51

9. Bibliography..........................................................................................................................52

10. References ..........................................................................................................................53

11. Appendices .........................................................................................................................54


Appendix A: Schematics for the TAMU Inverter ..........................................................55
Appendix B: Schematics for DSP Control .....................................................................60
Appendix C: DSP code (All .c and .h files) ...................................................................64

vi
List of Figur es
Figure 1: Block Diagram of the TAMU Fuel Cell Inverter ......................................................... 6

Figure 2: TAMU Fuel Cell Inverter System................................................................................. 7

Figure 3: Push-Pull Converter..................................................................................................... 8

Figure 4: Motorola SG3525A Control chip for the TAMU DC-DC Inverter............................ 10

Figure 5 : Schematic for the Feedback Board......................................................................... 11

Figure 6: Phase Compensation Circuit.................................................................................... 16

Figure 7: Circuit Diagram of the TAMU Inverter and Output Filter....................................... 17

Figure 8: Equivale nt Circuit for Single-Phase Inverter Output Filter Stage and Load....... 22

Figure 9: Control block diagram. .............................................................................................. 23

Figure 10: Simulation Result for Linear Load ......................................................................... 24

Figure 11: Simulation result for nonlinear load. ..................................................................... 24

Figure 12: Topology of the DC-AC Output Filter..................................................................... 26

Figure 13: Equivalent Circuit for a Non-Linear Load.............................................................. 27

Figure 14: DC Input into to the DC-AC Inverter and a Single Phase AC Output................. 30

Figure 15: Two PWM Gating Signals Leading to One IGBT................................................... 31

Figure 16: RS-232 Operation ..................................................................................................... 32

Figure 17: Display of RS-232 ..................................................................................................... 35

Figure 18: Quantity and Power Schematic and Rating Take-Off Sheet............................... 39

Figure 19: DC-DC Test Results ................................................................................................. 42

Figure 20: DC Input into to the DC-AC Inverter and a Single Phase AC Output................. 43

Figure 21: Two PWM Gating Signals Leading to One IGBT................................................... 44

Figure 22: DC-DC Boost Converter .......................................................................................... 45

Figure 23 Single Phase DC-AC inverter................................................................................... 46

Figure 24: Design Development Teams ................................................................................... 48

vii
List of T ables

Table 1: 10kW Design Results and Ratings............................................................................. 17

Table 2: Voltage Rating of the IGBTs...................................................................................... 20

Table 3: RS-232 Transfer Protocol Bit Identification.............................................................. 33

Table 4: Budget for the TAMU Fuel Cell Inverter Development............................................ 37

Table 5: DC-DC Converter Costs .............................................................................................. 40

Table 6: DC-AC Inverter Costs .................................................................................................. 41

Table 7: Organizational Gantt Chart......................................................................................... 49

viii
1 . S u mma r y

This report describes the development of a low cost fuel cell inverter with DSP control to meet

the 2001 Future Energy Challenge competition. A one-year project under EE-405 Electrical Design

Laboratory course to address the 2001 Future Energy Challenge was launched with undergraduate student

participation. The Texas A&M team was comprised of competent senior undergraduate students along

with faculty advisors.

The proposal outlines the technical approach to achieve the objectives proposed by the 2001

Future Energy Challenge organizing committee. The Texas A&M team believes it has developed an

efficient and effective inverter system. The team has developed a unique digital signal processor (DSP)

control mechanism for DC-AC control, an efficient push pull topology DC-DC converter and a rigorous

cost reduction approach for the 2001 Energy challenge inverter project.

A low cost Texas Instruments, TMS320F2407, DSP provides the control scheme for the DC-AC

inverter system. The DSP provides closed loop control for the DC-AC converter allowing easy

compliance to the total harmonic distortion (THD) specification of less than 5%. The DSP allows

convenient communication between the fuel cell and the inverter, and, through the RS232 port, allows

communication of information to data collection software or to the Internet. Since the DSP is

programmable, control algorithms are easily updated as opposed to traditional hard wire devices.

The Texas A&M team provides a rigorous cost savings approach by reducing the number of

metal-oxide-semiconductor-field-effect transistors (MOSFETS) and insulated gate bipolar transistors

(IGBT) in the design. Incorporating many small-power rated resistors and fewer power resistors

enhances cost savings. The push-pull DC-DC converter topology provides isolation for safety, suitable

boosting of the fuel cell voltage to 400 volts, reduced cost and reduced size of the energy storage

elements in the converter.

1
2. Intr oduction
Distributed power systems including fuel cells, microturbines, flywheels and wind turbines offer

a potential increase in energy efficiency by localizing power generation and eliminating the need for line

transmission of electricity [1]. Even though these environmentally friendly, highly efficient energy

resources are promising, several barriers must be overcome. A Department of Energy (DOE) study,

Making Connections, completed in May 2000 addressed the technical, business practice, and regulatory

barriers affecting distributed power systems. Since the barriers have been identified, rapid progress has

been made in removing or overcoming those barriers.

The Future Energy Challenge 2001 has identified the fuel cell as a distributed energy technology

that will soon be affecting the energy market. One of the main barriers for fuel cell technology is the cost

of manufacturing and the cost of power conditioning and control. Currently, fuel cell production costs are

decreasing, and have nearly achieved energy costs that are competitive with local utility rates. To further

assist the reduction of cost, the price of the power-conditioning portion of the fuel cell system must also

decrease, while at the same time increasing efficiency, reliability, and power quality. Lower cost will

enable the fuel cell systems to achieve a production cost at a more competitive rate than that offered by

many local utility companies, thus triggering rapid penetration into the utility market.

The 2001 Future Energy Challenge has resolved that one of the main components in the power

conditioning system is the inversion of direct current (DC) power from the fuel cell to consumer usable

alternating current (AC). The challenge requires the inverter design to be small, efficient, environmentally

compatible and low cost. A low cost inverter approach will help enable small-scale fuel cell system

commercialization and will encourage the development of distributed power systems. The 2001 Energy

Challenge invited participants to design and develop a low cost fuel cell inverter system that will perform

to at least the following specifications.

• Reduce the manufacturing cost to less than $500 for a 10 kW unit

• Achieve minimum efficiency and size and weight requirements


2
• Maintain acceptability in the areas of performance, reliability and safety

3. Design Rational and Featur e Descr iption

3.1 Fuel Cell Rational and Requirements

Fuel Cells for distributed power have many advantages. Environmental acceptability, efficiency,

distributed capacity; fuel flexibility and cogeneration are reasons why the fuel cell should be promoted as

the next generation of power. The following is a list of advantages of fuel cells:

• Environmental Acceptability - Because fuel cells are so efficient, CO2 emissions are reduced

for a given power output. Fuel cell power plants are projected to decrease CO2 emissions by a significant

amount in the next few years. The fuel cell is quiet, emitting only 60 decibels at 100 feet. Emissions of

SOx and NOx are 0.003 and 0.0004 pounds/megawatt-hour respectively. Fuel cells theoretically can be

designed as water self-sufficient. Since fuel cell exhaust is primarily water and CO2 natural gas fuel cell

power plants have a blanket exemption from regulations in California's South Coast Air Quality

Management District. These emission restrictions are possibly the strictest in the nation.

• Efficiency - Dependent on type and design, the fuel cells direct electric energy efficiency

ranges from 40 to 60 percent low heating value (LHV). The fuel cell operates at near constant efficiency,

independent of size and load. Fuel cell efficiency is not limited by the Carnot Cycle. For the fuel cell/gas

turbine systems, electrical conversion efficiencies are expected to achieve over 70 percent (LHV). When

by-product heat is utilized, the total energy efficiency of the fuel cell systems approach 85 percent.

• Distributed Capacity - Distributed generation reduces capital investment and improves the overall

conversion efficiency of fuel to end use electricity by reducing transmission losses. In high growth, or

remotely located load demands, distributed generation can reduce transmission and distribution problems

by reducing the need for new capacity or siting new lines. Presently, 8-10 percent of the generated

electrical power is lost between the generating station and the end user. Distributed generation will result
3
in many smaller units distributed throughout the United States. Many smaller units are statistically more

reliable since the probability of all distributed units failing at once is negligible.

• Permitting - Permitting and licensing schedules are short due to the ease in siting. In fact, natural

gas fuel cell power plants have been exempt from many of California's environmental regulations.

• Modularity - The fuel cell is inherently modular. The fuel cell power plant can be configured in a

wide range of electrical outputs, ranging from a nominal 0.025W to greater than 50-megawatt (MW) for

the natural gas fuel cell to greater than 100-MW for the coal gas fuel cell.

• Fuel Flexibility - The primary fuel source for the fuel cell is hydrogen, whic h can be obtained from

natural gas, coal-gas, methanol, landfill gas, and other fuels containing hydrocarbons. This fuel flexibility

means that power generation can be assured even when a primary fuel source is unavailable.

• Cogeneration Capability - High-quality heat is available for cogeneration, heating, and cooling.

Fuel cell exhaust heat is suitable for use in residential, commercial, and industrial cogeneration

applications .

3.2 Inverter Application for a Fuel Cell


In order to optimize the inverter design it is important to understand the dynamics of the fuel cell. In

general, fuel cells produce a rectified voltage from an electrochemical reaction between a hydrogen-rich

fuel gas and an oxidant (air or oxygen). The principal by-products are water, carbon dioxide, and heat.

Fuel cells are similar to batteries in that both produce a DC voltage by using an electrochemical process.

Two electrodes separated by an electrolyte make up an anode and a cathode pair called a cell. Groups of

cells are called stacks and produce useable voltage and power output. Unlike batteries, however, fuel cells

do not release stored energy; instead they convert energy from hydrogen-rich fuel directly into electricity.

Fuel cells operate as long as they are supplied with fuel. Further, fuel cells have a large time constant

(several seconds) to respond to an increase or decrease in power output. In view of this, a stand-alone fuel

4
cell power system requires some amount of battery backup to accommodate fluctuating electric loads.

TAMU Fuel Cell inverter incorporates this feature and is detailed in later parts of this report.

The inverter and the fuel cell have some unique interdependencies. The inverter and the fuel cell

must work together to produce AC power and therefore must communicate with each other. For the 2001

Future Energy Challenge, four basic controls were required: A digital, 0-5 volt, on/off request from

inverter to fuel cell, a 0-5V analog signal to the fuel cell requesting power, (5V corresponds to 1500W in

2001 Challenge), a 0-5 volt, analog output proportional to the power available and a digital, ready/trip, 0-

5 volt signal, and a ground.

The amount of energy a fuel cell can produce is dependent on the total potential of the stack and

the current demanded from the stack. The fuel cell will only provide current in the amount available from

the total chemical reaction within the fuel cell stack. This reaction is dependent on the quantity of fuel

and oxidant available to the fuel cell stack. In general, the fuel cell stack must have the fuel and oxidant

available prior to any load increase. The fuel cell controller will control the high fuel utilization and the

low fuel utilization limits. This leading indicator characteristic required by the fuel/oxidant flows

requires a signal of load increase prior to the fuel cell actually seeing the load increase. A decrease in

fuel/oxidant flows is not as critical and can be reduced directly as load reduces. A digital, 0-5 volt, on/off

request from inverter to fuel cell will tell the fuel cell to turn on or off. The TAMU fuel cell inverter

generates a 0-5V signal to the fuel cell requesting power from a minimum condition (idle) to a maximum

level. A 0-5 volt, “power-available”, analog signal from fuel cell to the inverter, as an indicator, is

supplied to the DSP.

The fuel cell must not exceed its maximum allowable limits of heat and load. In the case of over

heating or short circuit seen by to fuel cell a digital, ready/trip, 0-5 volt signal from fuel cell to Inverter

will tell the inverter if the fuel cell is ready. Since the fuel cell response to an increase in power is large

(several seconds), the TAMU fuel cell inverter incorporates battery backup system for sudden load

increases at the output. This feature is further detailed in Section 5.


5
3.3 TAMU Fuel Cell Inverter

Figure 1 shows the block diagram for the TAMU fuel cell inverter. In general an inverter system

consists of a DC-DC boost circuit, a DC-AC inverter circuit and a filter. This section will briefly describe

how the boost circuit works, how an inverter creates an AC output from a DC source, what types of

control methods are employed and discuss basic filtering concepts.

Fuel Cell High Frequency DC-link & Output 120V/240V,


Inverter
Energy DC-DC Battery Filter 60 Hz
Source Converter Backup AC output

+ +
48V Load
- -

Vo*
SG3525A DSP
TMS 320C2407 io

Figure 1: Block Diagram of the TAMU Fuel Cell Inverter

The DC input from the fuel cell (48 VDC nominal, +50%, -12.5%) is first converted to a regulated

400 VDC using a high frequency DC-DC converter. The DC-DC conversion stage consists of a high-

frequency transformer. Isolated primarily for safety, system protection, and to meet the stringent FCC

Class-A standards. The 400V DC-DC converter output is converted to 120V/240V, 50/60 Hz, single -

phase AC by means of a pulse width modulation (PWM) driven IGBT, inverter stage. An output-LC

filter stage is employed to produce a low THD-AC waveform. Low loss, high switching frequency

MOSFET and IGBT components have been employed to achieve a higher efficiency, lower size and

volume of the fuel cell inverter system. The circuit topology of the TAMU inverter system is shown in

Figure 2 below.

6
1:5 L IDC
+
T+ AC Output
Iin C Lb TA+ TB+ 120/240V , 60 Hz
FUEL CELL N2 D1 D3 LF
VC+ ia
Vin Vbatt A
N1
42-72V DC + C VDC 240V, 60Hz
48V nom. LF ib
-
N1 C Lb B
N2 VC - Va
D4 D2 Vbatt CF C F
- TA - TB - Vb 120V, 60Hz
T-
L
N
Battery Backup

48VDC / 400VDC, 40KHz PUSH PULL CONVERTER 120V/240V, 20kHz PWM INVERTER

Figure 2: TAMU Fuel Cell Inverter System

DC-DC converter and inverter topologies were designed to achieve ease of manufacturing and

facilitate production in large volume. Another unique aspect of the design is the use of the

TMS320C2407 DSP to control the inverter. The DSP reduces printed circuit board layout complexity.

Readily programmable, the DSP adds flexibility to implement various control aspects by means of

software. In addition, the DSP incorporates imbedded intelligence into the design.

3.4 DC-DC Converter

3.4.1 Description and Approach

The TAMU fuel cell inverter employs a push-pull type DC-DC converter to suitably boost the

fuel cell voltage from 48V to 400V. Figure 3 shows the topology of the push pull DC-DC converter.

The push-pull, full bridge and flyback converters belong to the family of isolated buck converters.

This family of converters may be used in conjunction with a high frequency transformer to boost the

output voltage with the additional advantage of providing isolation between the input and output stages.

Isolation of the input and output stages provide safety of personnel accessing the output terminals and

enhance short circuit protection for the inverter. The DC-DC converter operates at high switching

frequency (40 kHz), which produces high frequency AC across the isolation transformer. The secondary

output of the transformer is rectified and filtered to produce 400VDC. The design is rated for 10 kW and
7
consists of parallel-connected MOSFETs, a full-bridge rectifier, a Motorola SG3525A control chip for

feedback control, snubber circuitry, a high frequency transformer, a coupled inductor and bulk capacitors.

The output voltage is regulated by means of feedback control employing a low cost Motorola

SG3525A PWM controller. The push-pull converter is shown in Figure 3 below.

I in 1:K ID L IO
> > >
IT
<
D1 D4 C
T+
N2
Vin + N1
PWM RL
- CONTROL VO
N1 C

T- N2 D3 D2

Figure 3: Push-Pull Converter

The push-pull converter consists of two forward converters driven by anti-phase inputs. The two

diodes D1 and D2 in the secondary of the transformers act as both forward and flywheel diodes. Ideally,

conduction times of T+ and T- are equal and the transformer is driven symmetrically. The primary side

conduction losses are lower since at any given instant only one transistor is connected in series with the

DC source. Since in the full bridge push-pull converter, both the halves of the secondary winding

conduct, the turn ratio (N2/N1) can be minimized, reducing the transistor currents.

The transistors T+ and T- are switched alternately with a pulse width modulated signal to produce

a high frequency AC at the input of the transformer. A center-tapped secondary is used. The neutral of

the center-tapped secondary is connected to the center point of the bulk capacitor. When T+ is on, D1

and D2 conduct whereas D3 and D4 are reverse biased. This results in voltage

N2
vL = 2 V −V 0 < t < t ON (1)
N1 D 0
where

8
vL - inductor voltage

N1 - primary turns

N2 -secondary turns

VD -input voltage

Vo - dc output voltage

t - time

and the inductor current increases linearly. During the interval ∆ when both the switches are off, the

current splits equally between the secondary half windings and v0 = 0.

v L = − V0 tON < t < t ON + ∆

The next half cycle consists of tON (during which T- is on) and the interval ∆. The waveforms

repeat with a period of ½ Ts

1
t ON + ∆ = Ts (2)
2

From the above equations,

V0 N2
=4 D 0 < D < 0 .5 (3)
VD N1

where D = tON /Ts is the duty ratio of the switches T+ and T- and has the maximum value of 0.5.

The duty ratio D through the controller regulates the output voltage V0 . An efficient control scheme will

eliminate the effect of disturbances, i.e. reject the input power supply variations and transient load

changes.

A challenge that arises with the push-pull topology is that the transformer core may saturate if the

characteristics of the forward-voltage drop and conduction times of the transistors are not precisely

matched. Small imbalances can cause the DC component of voltage applied to the transformer-primary to

be nonzero. Consequently, during every switching period, there is a net increase in the magnetizing

9
current. If this imbalance continues, then the magnetizing current can eventually become large enough to

saturate the transformer. Core saturation results in rapid thermal runaway and destruction of one of the

transistors. To ensure that there is no significant imbalance between the two switch currents a coupled

inductor is employed on the secondary of the transformer. The coupled inductor balances the currents in

the two halves of the center-tapped transformer. Additionally, the choke filters out the switching

frequency components off the DC output current and balances the power output of each inverter phase,

(which are specified to be capable of being loaded independently), and helps generate a clean 400VDC

voltage for the inverters.

3.4.2 DC-DC Converter Control Mechanism (Analog)

A low cost Motorola SG3525A Pulse Width Modulator controller is used for the control of the

DC-DC converter. The SG3525A is particularly suited for the push-pull converter application because it

has two output terminals. The two output terminals work perfectly with the two transistors used in this

converter design. The block diagram of the Motorola SG3525A is shown below in Figure 4.

Figure 4: Motorola SG3525A Control chip for the TAMU DC-DC Inverter

10
The Motorola SG3525A provides this design with other features that enhance control and safety.

The SG3525A provides for an input under-voltage lockout that automatically shuts off the chip in case of

low voltage. The modulator has a soft start capability, which allows it to be protected from capacitor

inrush currents.

3.4.3 DC-DC Converter Feedback System

The feedback board is a voltage divider that scales the 400V output to a level that can be

managed by the pulse width modulation (PWM) controller. Since the ground is at the midpoint of the

400V, the output voltage appears as a +200V signal and a -200V signal. Both of these voltages are scaled

down to a few volts by a resistive divider. The parallel combination of the resistors at the +200V divider

is equal to the parallel combination of the resistors at the -200V level. The schematic for the feedback

board is shown below in Figure 5.

N15 C8
0.1uF
50V

U9B
11

6 - TA75074P R18
R1 R2 R12 7
5
+BUS V +
22 K
200K 200K 39 K
4

C23 U9A
R13 C7
4
470pF P15 3 TA75074P
5.1 K 50V 0.1uF + 1
50V 2
- BUSFB
11

C34 R17
R14
470pF
7.5 K 16 K R21
50V
U9C 16 K
11

R3 R4 R15 R16 9 TA75074P


- BUS V -
8
R19
16 K 10 +
200K 200K 39 K 22 K
4

R20 R22
22 K 5.2 K

Figure 5 : Schematic for the Feedback Board

A small positive signal and a small negative signal are produced. The signals are the same

polarity in order that they can be added together. The added signal is buffered from the resistive divider

so other circuit resistances do not affect the scaling factor. This is achieved by using a unity-gain op-amp

11
for the positive signal and an inverting unity-gain op-amp for the negative signal. These signals are

mixed and fed into a non-inverting op-amp with a variable gain such that the controller sees a single

ended 6V signal at the feedback input when the output voltage is 400V.

3.4.4 DC-DC Converter Protection Circuitry


The TAMU DC-DC converter provides the capability to detect any over-currents, over-

temperatures or shut down conditions in the circuit to prevent damage to the DC/DC boost stage. A user

signaled shutdown and fuel cell signaled shut down are provided for as well.

Op-amp comparators and sensors are used to monitor operation and provide a shutdown signal to

the controller. The protection circuit uses a reference voltage for each signal to set the maximum limit

and a signal representing the measured quantity. Whenever any of the measured signals exceeds their

reference, the controller SD (shutdown) pin is pulled low which blocks the gating signals to the transistors

and shuts down the converter. Indications for over current, thermal overload and fuel cell interrupt

conditions are provided through light emitting diodes (LED) mounted on the faceplate.

Each signal is fed to a separate comparator with a separate reference voltage. When the measured

quantity exceeds the maximum threshold, the comparator output is pulled high. This forward biases a

series LED, which is mounted on the front of the enclosure as a visual indicator. Each signal has an op-

amp/LED combination, and the cathodes of all the LEDs are connected together to the base of a bipolar

junction transistor (BJT) pull-down transistor. If any signal exceeds the threshold the LED lights and the

base gets a high signal. The collector is pulled to ground, which sends a low voltage to the shutdown

input on the board and turns off the controller.

While the references are obtained with potentiometers connected to the control supply, the signals

need some external circuitry. A DC current sensor is needed on the output line of the converter to provide

a voltage proportional to the current. The over current threshold is set to 110% of the full load current.

Any current above 110% of full current will shut down the converter.

12
A negative temperature coefficient (NTC) thermistor is mounted on the heatsink for thermal

protection of the converter. As the temperature varies, the resistance of the thermistor will change and

force a small differential voltage at the output of the Wheatstone bridge. This voltage needs to be

buffered and converted to a single -ended voltage with amplitude of a few volts. The circuit is designed to

provide a shutdown reference corresponding to 80 degrees (Celsius).

The fuel cell or a user-defined shutdown is simple to accomplish. Because this signal will be a

relatively low voltage (~5V), it will need boosting to properly light its LED. Feeding this signal directly

to a comparator and providing a reference of 1V accomplished the user defined shut down. Whenever the

signal is high, the comparator will provide +15V to light the LED. If the signal is low, the comparator

will provide -15V to keep the LED reverse biased and unlit.

3.4.5 Filtering Process (Noise Issues)


The DC-DC converter output ideally should not contain any noise. However, as a result of the

switching on the DC-DC board, the output of the DC-DC inverter exhibits some switching noise (40kHz).

The noise is present in the signal sent to the DC-DC controller and in the DC voltage sent to the DC-AC

inverter. The Texas A&M team’s design includes filtering of both the control signal and the DC voltage

sent to the inverter.

3.4.6 DC-DC Converter Control Signal Conditioning

Switching noise should be removed from the control signal sent back to the comparator so the

accuracy of the control loop is not compromised. Two ceramic capacitors are included in the circuit prior

to the resistive divider of the feedback board. The capacitors filter out the switching noise from the

feedback circuit. Wire leads that implement the summing of the signal can pick up noise easily, therefore

the wire leads are as short as possible. These features provide a clean DC control signal.

13
3.4.7 DC-DC Converter DC- Link Design

Two high frequency film capacitors rated at 0.22µF capacitors provide the filtering for the DC

voltage sent to the DC-AC inverter. The series capacitors remove the 40 kHz voltage noise and provide

the DC-DC converter with a clean 400 V output. The bulk (electrolytic) capacitors provide additional

conditioning for the DC-AC inverter and serve to balance the ±200V voltages for the single -phase

inverters. In addition, two 47KΩ, 2W resistors are connected across the DC link for safe discharge of the

capacitors upon shut down.

3.4.8 DC-DC Converter Design For The 10kW TAMU Fuel Cell Inverter System

Figure 3 in the beginning of this section shows the circuit diagram of the push-pull DC/DC

converter. Fuel cell output is connected to the DC/DC converter as shown. The operation of the push

pull converter is described in detail in section 3.4.1 above. MOSFETs T+ and T- are turned on and off

alternately under duty ratio control at a switching frequency of 40kHz.

3.4.9 DC-DC Converter Specifications

Inverter power output= 10000W

Assuming an overall efficiency of 90%, we have an input power

10000 W
Pin = = 11111 W (4)
0 .9

A nominal fuel cell input voltage, Vin = 48VDC-nom., is assumed.

Output voltage, Vo = 400VDC

Switching frequency= 40kHz (duty ratio control)

Designing for the low input line condition (Vin =42VDC), input current from fuel cell,

11111 W
I in = = 265 A (5)
42V

The push pull DC/DC converter shown in Figure X. comprises of two switches, T+ and T-. At the

maximum duty ratio of 0.5, rms current rating IT of the switches


14
I in
IT = = 188 A (6)
2

MOSFETs rated 100V, 100A with 2 devices in parallel in each leg are selected.

High frequency transformer:

For obtaining an output voltage of 400VDC for the push-pull converter, a turns ratio of K=5 is selected

for the transformer. Center taps are available on both the primary and secondary sides as shown in Figure

2 at the beginning section 3.3.

The VA rating of the transformer is defined as the sum of the total primary and secondary

winding VA divided by two,

1  Vin Iin I 
VATr =  ⋅ ⋅ 2 + Vin ⋅ K ⋅ in ⋅ 2  = 1. 5 Vin ⋅ Iin = 1. 5 ⋅ 42 ⋅ 265 = 16695 W ≅ 17. 0kVA (7)
2 2 2 K 

Voltage ratings of the transformer are selected as: Primary voltage=80V, Secondary voltage=400V

Diode ratings:

The reverse blocking voltage is equal to the DC link voltage 400V,

Current rating is the rms current through the diode, ID ,

I in
ID = = 37 .5 A (8)
K⋅ 2

3.4.10 Design of the Control Circuit for the DC-DC Converter

The PWM controller SG3525A is used for the control of the push-pull DC-DC converter. The block

diagram of the SG3525A is shown in Figure 6. The error amplifier used for implementing the closed loop

voltage control is a part of the SG3525A. The resistors and capacitors shown below are external to the

chip and were selected as follows. Phase compensation is achieved by a type-2 amplifier.

15
C2

R2 C1
Vfdbk R1
- Vout

Rbias +

Vref

Figure 6: Phase Compensation Circuit

To achieve a phase boost of 82° and dB gain (G) of 2.83 at the center frequency (f) of 455Hz, we select

 π  boost 
k = tan   + 45   = 14. 3 (9)
 180  2 

Selecting R1=18kΩ, we can determine R2, C1 and C2 as follows:

1
C2 = = 453 pF ≅ 470 pF
2π f G k R1
C1 = C 2( k 2 − 1) = 0 .092 µF ≅ 0 .1µF (10)
k
R2 = = 54 kΩ ≅ 51 .1kΩ
2 π f C1

For the oscillator section, a timing resistor RT and capacitor CT are selected to obtain a switching

frequency of 40kHz using the SG3525A datasheet,

RT= 5110 Ω and CT= 3300 pF

The 10kW design was verified by simulation.

16
Component Type Rating Quantity

MOSFET 100V, 100A 4

Input capacitor Electrolytic 4500uF, 250V 2

Transformer High frequency, with 17kVA, 400V, 37A 1

center taps on both sides

Diode 600V, 37.5A 4

Table 1: 10kW Design Results and Ratings

The voltage ripple on the 400VDC bus as obtained by simulation is less than 1%.

3.5 DC-AC Inverter Design

The DC-AC subsystem consists of the circuitry between the DC-DC converter and the load. A

block diagram of the system topology is available in Figure 7.

IDC is

+
ic AC Output
TA+ TB+ 120/240V , 60 Hz
LF ia
VC+ i sA i sB i oA
A
C
400VDC O
VDC 240V, 60Hz
LF ib
i oB
B
C
VC - Vb
CF CF 120V, 60Hz

TA - TB - Va
-

Figure 7: Circuit Diagram of the TAMU Inverter and Output Filter

17
Since the DC-DC converter maintains equal ±200V on the dc-link capacitors, two inverter legs are

sufficient to generate 120V/240Vac output. The inverter has two PWM modules, which can each

accomplish a task such as centered and/or edge-aligned PWM generation. The 400 V output of the DC-

DC boost is used across two parallel switching legs. Each leg consists of two IGBT’s connected in series

across the 400 V input. The IGBTs are switched by the DSP. The DSP uses PWM by means of a

software-controlled algorithm to emulate a sine wave to determine when to open and close the gates.

An LC filter is used to filter out harmonics above 60 Hz out of the PWM output. The voltage sensor

senses the output voltage across the external load. This sensed voltage is fed back into the DSP for use in

the PWM algorithm. If the voltage is too high the voltage will be decreased and if the voltage is to low it

will be increased. The current sensor serves as over-current protection for the load. This subsystem can

be broken down into two main components, the control circuitry and the passive output AC filter.

Schematics for the DC-AC subsystem can be found in Appendix A.

3.5.1 Inverter Design Procedure for the 10kW TAMU Fuel Cell Inverter System
The inverter produces two single -phase outputs Phase-A and Phase-B. It is comprised of two half

bridge inverters each supplying separate single -phase loads at 120VAC, 60Hz. Consider the case when

Phase-B is not loaded and Phase-A is on full load (5000W). The peak amplitude of the fundamental

frequency component is the product of ma and ½ VDC, where ma is the modulation index. A modulation

index of 0.9 is assumed for this example.

V DC
(VAO )1 = m a ⋅ sin(ω1t ) 0 < ma < 1 (11)
2

The switching function sw1 of the half bridge inverter is

0.9
sw1 = 0.5 + sin ω1t + higher frequency terms (12)
2

and the Phase-A output current is assumed to contain fundamental and third harmonic component due

to nonlinear load.

18
ioA = 2 I1 sin(ω1t − φ1 ) + 3 I 3 sin(3ω1t − φ3 ) + ... (13)

The current through the switch TA+ is given by

isA = sw1 ⋅ ioA


2 3
= I1 sin(ω1t − φ1) + I3 sin( 3ω1t − φ3 ) + ... (14)
2 2
2 I1 [cos φ1 − cos(2ω1t − φ1 ] + 3I 3 [cos φ3 − cos(3ω1t − φ3 )] + ...
0.9 0.9
+
2 2

If Irms is the rms value of the Phase-A output current, neglecting higher frequency terms, we have

I rms = I12 + I 32 (15)

Assuming I3 =0.7 I1 which is typical of single phase rectifier type nonlinear loads,

I rms = 1 .22 ⋅ I 1

When supplying full load of 5000W at unity power factor,

5000
I rms = = 41 .7 A
120

which gives

41 . 7
I1 = = 34 A (16)
1 .22

Therefore, the largest component of the capacitor current ic is the fundamental frequency current, the rms

value of which equals

1
ic , rms = ⋅ I1 = 17 A (17)
2

For a voltage ripple ∆Vc less than 5% or 10V,

ic, rms
∆Vc = (18)
ωC

ic , rms 17
C= = ≅ 4500 µF (19)
ω ∆ Vc 10 ⋅ 2π ⋅ 60

Bulk capacitors 4500µF are selected for this design.

19
Inverter switch ratings:

The rms current isA is 41.7A. Thus, rms current rating of each switch is

41 .7
IT = = 30 A (20)
2

Voltage rating of the IGBTs is 600V.

Component Rating Quantity

IGBT 600V, 30A 4

Table 2: Voltage Rating of the IGBTs

3.5.2 DC-AC Inverter Subsystem Control

Digital systems are becoming more ubiquitous in industry as a consequence of automated design

tools becoming more prevalent. Also, the accuracy that digital systems offer may be efficiently verified

on a mass production basis.

Unlike analog circuits, sophisticated algorithms can be implemented and updated digitally in a

short period of development time. Furthermore, digital circuits are less likely to be influenced by

temperature, aging, process technology, or chip layout. In contrast, analog circuits typically require

additional tuning circuits. In order to avoid use of tuning circuits and non-linearities associated with

analog circuits, a digital signal processor (DSP) has been utilized.

A Texas Instruments TMS320C2407 DSP platform was implemented to obtain the closed loop

control and PWM functions via software that maximize overall performance of the fuel cell inverter

system, while allowing the low cost objective to be achieved. The TMS 320C240X is a high-speed

processor designed for power electronic control. The DSP has on-chip memory to store and run the

program. Essential to the decision to implement DSP control, the cost of the Texas Instruments

TMS320C2407 is approximately $3.00 in high quantity.

20
The DSP system has a high-speed A/D converter, 9 PWM output channels and serial

communication capabilities. In addition, the TMS 320C240X series contains a 10-bit analog-to-digital

converter (ADC) having a minimum conversion time of 500 ns that offers up to 16 channels of analog

input. The auto sequencing capability of the ADC allows a maximum of 16 conversions to take place in a

single conversion session without any central processing unit (CPU) overhead [2]. This capability is

important for exploring ideas such as sensing outputs and inputs, programmable dead band to prevent

shoot-through faults, and synchronized analog-to-digital conversion [2]. By implementing the control via

DSP, the proposed approach will offer increased flexibility, insensitivity to temperature drifts and will

minimize component cost. Here, control is defined to mean how the DSP is used to: 1) modulate the

firing angles of the IGBT’s that will be used in the inverter stage, 2) provide supervisory protection

against system over-voltage, over-current, and over-temperature conditions, and 3) examine critical fuel

cell integration control parameters, 4) and provide tight output voltage regulation to meet THD

specifications under varying linear and nonlinear loading conditions. Appendix C shows the code

generated to produce the output voltage.

The system involves high-speed feedback loops that force the actual output voltage, Vout , to

follow the reference sinusoidal voltage Vref. Vref is 170V and is internally generated by the DSP

(numerically). The following sections describe the inverter control in detail.

3.5.3 Voltage Feedback

The voltage feedback configuration takes Vo (output of inverter) and divides out sin(ωt). This

gives DC component or the peak voltage for the output. The peak is then compared to the 120√(2)V or

~170V. The error is given to the PI controller where a voltage compensation amount is output into the

summer. The summer adds the correction to the reference and multiplies sin(ωt) back into the DC output

making it an AC signal again. The AC signal is then entered into a voltage limiter, which constrains the

voltage to a range of 0.0 to +3.3V. All intermediate values are linearly scaled into the range +3.3V to 0V.

21
The signal has a DC bias (offset) of 1.65V. This provides a range that covers the whole output spectrum

and limits it to a more manageable range for the DSP. The DSP can handle an input ranging from 0V to

3.3V.

3.5.4 TAMU Fuel Cell Inverter Closed Loop Control Approach

In this section, a closed-loop control strategy to maintain sinusoidal voltage at the output

terminals for varying loads is discussed. According to the specifications the 120V and 240V terminals of

the inverter could be connected to linear and nonlinear loads. In addition, the load can be considerably

unbalanced between the two outputs. Figure 8 shows the equivalent circuit of the output filter (LC) stage

of the inverter. Section 3.5.6 of this report details the output filter selection procedure along with a design

example. Figure 9 on the next page shows the block diagram of the output voltage control.

iL L io
ic
vinv C vo

Figure 8: Equivalent Circuit for Single -Phase Inverter Output Filter Stage and Load

The output voltage of the inverter is sampled and transformed to the synchronous reference frame

in order to cancel higher harmonic components employing low pass filter (LPF). The transformation

matrices are given by,

 sin θ cosθ 
T(θ ) = 
− cosθ sin θ  , (21)

22
 sin θ − cosθ 
T(θ ) −1 = 
cosθ sin θ  . (22)

The transformation matrix T can be used for a system which might have two phases with 90° phase shift

to be represented by dc component. Since the output voltage is only available, another phase input is

e*
determined by v od cos ωt . As shown in Figure 9, the control system is designed on the synchronous

reference frame to increase the performance for nonlinear loads. Inverter input command is obtained by a

repetitive controller with predicted output voltage. During the fundamental cycle period, PI controller

output is calculated, applied to the next cycle period by integrating all the previous controller output.

i
veod* = 120 2 ∫0 ℜinv(i + 1)n −1 dt
*
M sin ωt
vo veod +
LPF _ PI ℜ*inv (i )n −1 ℜ*inv(i + 1)n +
v*o cos ωt T (θ ) e
voq T (θ )−1 ∫ +
LPF _ PI v*inv(i + 1) n
+
e*
voq =0

Figure 9: Control block diagram.

Finally, the inverter reference voltage is calculated by

*
v inv ( i + 1 ) n = M sin ω t + ℜ *inv ( i + 1 ) n (23)

ℜ*inv (i + 1) n = I ℜ ∫ ℜ*inv (t ) n −1 dt
i

0 (24)

Where, M is the modulation index, n denotes the step of a fundamental period; i represents the sampling

period in the fundamental period, and I ℜ is the integral gain factor.

23
Results:

Figure 10 and Figure 11 show the simulation results of the inverter output voltage control

scheme. It is clear from the results that the inverter output voltage maintains a sinusoidal wave shape

during linear and nonlinear loading conditions.

Figure 10: Simulation Result for Linear Load


(a) output voltage, (b) control signal, (c) output current(linear)

Figure 11: Simulation result for nonlinear load.


(a) output voltage, (b) control signal, (c) output current(linear)
24
3.5.5 Over Current Protection & Over Temperature Protection for DC-AC

Current and temperature protection are important for the output load and the inverter

itself. High current and high temperature can cause unexpected and serious damage to the fuel

cell and the inverter.

Over-current protection is implemented by using a current transformer that translates 1A

into 1V. A full bridge rectifier and a capacitor are used to obtain a DC level corresponding to the

measured current. The DC voltage proceeds to an op-amp in a voltage follower configuration.

Another op-amp uses the voltage and compares it to a reference voltage by means of a

comparator configuration. If the voltage measured is larger than the reference, then a signal is

sent to the gate driver for shutdown.

Temperature protection is implemented by using a thermistor that is mounted onto one

heat sink per leg of the inverter. The thermistor is used in a Wheatstone bridge. The voltage

difference across the bridge proceeds to an op-amp in a voltage follower configuration. Another

op-amp compares it to a reference voltage. If the voltage measured is larger than the reference, a

signal is sent to the gate driver to shutdown.

A manual push button reset is used to restart the system after the current or the

temperature has reached its limit and the gate driver has shutdown.

3.5.6 Output Filtering

The output filter of the power inverter is used to smooth out the waveforms generated from our

DC-AC stage. If monitored, the pure output of the inverter is a square wave with varying duty cycles.

This signal contains many unwanted frequencies including multiples of the 20kHz pulse width modulation

(PWM) switching frequency. Total harmonic distortion (THD) can be affected by these harmonics,

therefore, the THD of the inverter can be reduced by using an output filter. The THD requirement for this

25
design requires the system to have a THD < 5%. This low-pass filter is designed to meet the THD and

power requirements of this project. The following section will describe the procedure used to find the

appropriate values of the components of the filter.

3.5.7 DC-AC Inverter Output Filter Design Procedure


Figure 12 below shows the topology for the output filter. A transfer function is developed from

the schematic. The assumptions used in the analysis are, the output filter is loss less and the third

current harmonic current is 80% of the fundamental current frequency.

jnXL

Vi,n -jXC
Vo,n ZL1n
n

Figure 12: Topology of the DC-AC Output Filter

The transfer function for this type of filter is described by the equation

Vo , n jX C ⋅ Z L, n
Hn = =− . (25)
Vi , n nX L X C + jZ L ,n ( n 2 X L − X C )

Where

Hn - transfer function

Vo , n - output voltage harmonic

Vi , n - input voltage harmonic

XC - capacitor component of impedance

XL - inductance component of impedance

26
Z L, n - impedance

n - harmonic

For H1 → 1 ; or X L << X C , then

− jX C ⋅ Z L ,1
H1 ≤ ≅ 1. (26)
− jZ L ,1 ⋅ X C

Also, for a no load condition, Z L,1 → ∞ , therefore equation (25) is

XC 1
Hn = − = (27)
n X L − X C n 2 ⋅ L −1
2
X
XC

To satisfy a THD requirement of less than 5%

1 X 23.222 (28)
≤ 0.045 = L ≥
X XC n2
n 2 ⋅ L −1
XC

3.5.8 Non-Linear Load


An equivalent circuit used in finding filter characteristics for a non-linear load is shown in Figure 13.

jhXL

-jX C
Vh Ih
h

Figure 13: Equivalent Circuit for a Non-Linear Load

The transfer function for this schematic is described by equation

jhX L ⋅ X C
Vh = ⋅ Ih . (29)
X C − h2 X L

Where

27
Vh - equivalent voltage

h - harmonic

Ih - current at h harmonic

XC - capacitor component of impedance

XL -inductance component of impedance

equation (29) can then be shown as

hX L
Vh = ⋅ Ih . (30)
2 XL
1−h
XC

XL X
Here is very small making h 2 L << 1 ∴
XC XC

Vh ≤ hX L ⋅ I h (31)

For the third harmonic h = 3 ∴

V3 3 X L ⋅ I 3 V3
= , where THD is = 0.03 or 3% . Inductor impedance can be found by
V1 V1 V1

0.03 ⋅V1
XL = (32)
3* I 3

3.5.9 Output Filter Design Example

Let f s be defined as the switching frequency and f 1 be defined as the fundemental frequency.
fs X
Then for f s = 20kHz , f 1 = 60 Hz , and n = = 333.33 , L ≥ 2.09 x10 − 4 the filter resonant
f1 XC
frequency f r can be found with

fr XC n2
= ≤ ≤ 69 .17 . (33)
f1 XL 23 .22 2

fr ≈ 4150 Hz

28
The 10 KW inverter (5 KW per Phase) with V1 = 120V , produces I rms = 41.67 A , I 3 = 25.95 A . Use

equation (32) to find X L = 0.046 . Then, using

XL
L= (34)
2π f1

Where

L - inductance

f1 - fundemental frequency

XL - inductance component of impedance

where f 1 = 60 Hz , the inductance will be L = 123µH .

To find the capacitor impedance use the equation (28), to get X C = 221.26 , then using

1
C= (35)
2π f1 ⋅ X C

where

C - capacitance

XC - capacitor component of impedance

f1 -fundemental frequency

and f 1 = 60 Hz , capacitance will be C = 12µF .

3.5.10 Test Results

Figure 14 below shows the DC input into to the DC-AC inverter and a single phase AC output of

the inverter stage of the 1.5kW prototype. With the DC input voltage at 390V, the voltage that appears

across the drain and source of the IGBT S1 is shown above. The ACRMS waveform shown is the

sinusoidal output voltage VAO after the filter stage. This voltage equal to 121 volts RMS, which meets

29
the required specification of 120 ± 6% volts. This output is realized with a modulation index (M) equal to

0.88. The measured frequency of the AC output is within the 60 ± 0.1 Hz requirement.

Figure 14: DC Input into to the DC-AC Inverter and a Single Phase AC Output

Figure 15 below shows the two PWM gating signals driving the IGBT of one phase of the

inverter. Channel 1 shows the PWM output from the DSP and Channel 2 shows the same PWM output

from an isolation opto-coupler. This image highlights clean PWM switching of the IGBT via the opto-

isolators controlled by the DSP. This clean switching translates to a cleaner output signal, which is

necessary to meet the THD < 5% specification. Please note that both Figure 14 and Figure 15 were

captured during same test.

30
Figure 15: Two PWM Gating Signals Leading to One IGBT

31
3.6 Output: Monitoring and Computer Interface Via RS-232

The inverter uses an RS-232 cable to link the DSP’s serial port to a Windows PC. This interface

is used to transfer voltage and current values from the inverter to the PC so they can be displayed for real

time viewing. Data is also stored into text files for data processing. An overview is given in Figure 16

below.

Figure 16: RS-232 Operation

Data is output from the DSP in a predefined transfer protocol that can be recognized by the PC.

In the DSP, the data is coded according to the protocol, and then transferred out of the SCI pin of the chip.

After the data reaches the other end of the cable, the software on the PC reads the correct serial port and

inputs the data into the computer’s software. The data is stored into a temporary 32 bit buffer. The

software reads the buffer and collects the data before the next piece of data is transferred. When new data

is transferred, it is stored in the same buffer as the old data, and the old data is destroyed. After the

software reads and stores the data, it must decode the data in order to know what it is and how it is to be

used. This is done with algorithms that are written based on the transfer protocol that is discussed in the

next section. When all of the needed data values are coded, transferred, read into the computer port, and

decoded, then the data can be processed.

32
3.6.1 Transfer Protocol

The protocol that is used to transfer the data is designed to use as few data transfers as necessary,

but enough to accurately monitor the data. The data to be transferred is the Leg A voltage and current,

as well as the Leg B voltage and current.

The voltages on Leg A and B will almost always be about 120 V, it was decided that the range of

measurable values that could be represented were from 0 to 180. Likewise, the currents of each leg will

almost always be between 0 and 12.5 A. It was decided to use a range of 0 to 55 to represent the current.

If physical values go beyond this range, only the upper values, (55 for current and 180 for voltage) will be

processed.

The RS-232 transfer protocol has a maximum data transfer of 8 bits per transfer. This does not

including the other start, stop, and parity bits. Within these 8 bits is the information that will be used to

identify the data as well as the actual value of the data. This can be more clearly seen in Table 3 below.

Data Bits Value

00XXXXX Upper 5 bits of Leg A Voltage

001XXXXX Lower 5 bits of Leg A Voltage

010XXXXX Upper 5 bits of Leg B Voltage

011XXXXX Lower 5 bits of Leg B Voltage

100XXXXX Upper 5 bits of Leg A Current

101XXXXX Lower 5 bits of Leg A Current

110XXXXX Upper 5 bits of Leg B Current

111XXXXX Lower 5 bits of Leg B Current

Table 3: RS-232 Transfer Protocol Bit Identification

33
Using this method, each of the four values that are transferred has 10 total bits worth of data. The

10 bits are enough to approximate the actual current and voltage values. The formula’s used to code and

decode the data are given below.

Coding

coded value = ( uncoded value * max size)/ upper range

where uncoded value = the value that the sensors pick up

max size = (2^10 –1) =1023

upper range = 180 for voltage values and 55 for current values

Decoding

decoded value = (coded value * upper range)/max size

Approximately every .5 to 1 second, the DSP will code all 4 data values and then break up the

coded values according to the table above. The extra bits that represent what the actual data is will also

be added to the 8-bit transfer block. Then all 8 of the 8 bit blocks will be sent to the computer to be

decoded. This process then repeats itself every .5 to 1 second.

3.6.2 Software Functionality

Once all of the data values are transferred and decoded, it is up to the software to display the data,

write the data to files, and perform all of the computations that are on the display. Given the four data

values that are transferred from the DSP, the display software also computes the maximum and average

values that were seen for the current, voltage, and power, and also computes the current power. This can

be seen more clearly in Figure 17 below which illustrates the TAMU Fuel Cell Inverter system under

non-operating conditions.

34
Figure 17: Display of RS-232

As the DSP keeps updating the display, the inverter’s operators can see real time data of its

performance. There are also limit arrows placed on the Current and Voltage data fields. These limits are

set to give an up or down arrow if the current value falls out of the range of the limits. Currently the

current limit is set to go off if the value goes above 12.5 A or equals zero, and the voltage limits will go

off if the voltage falls out of the range of 120 V plus or minus 6%. These limits can also be interpreted

and an overall status of the inverter given at the lower right of the display. The software has the ability to

periodically write data to output text files. These files can later be used to import into other data

processing programs. For example, data can be imported into Excel and the data plotted in graphs.

3.6.3 Testing, Implementation, and Analysis

Test software had to be written, before the interface could be implemented. Software modules

were written using a Microsoft Visual C compiler. Software was written to simulate the DSP coding the

data and then the Display software was written.

35
4. Cost Evaluation
4.1 Tracking Chart & Budget
The cost evaluation of the Texas A&M Fuel Cell Inverter considers two types of costs. First, the

cost of the development process and second the cost evaluation based on the normalized system cost

projection worksheet provided for by the 2001 Future Energy Committee. The development budget

helped guide the design team in organizing and prioritizing time and resources for optimum use. The

working budget allowed team members to make the best cost-design decisions by showing the team

actual costs of the specific components for the fuel cell inverter.

The development budget, in Table 4 on the next page, was prepared at the initiation of the Texas

A&M 2001 Future Energy Challenge team. The budget takes in consideration a team of nine

undergraduate students and three graduate students who designed the inverter system. Funds and supplies

were provided from the Department of Electrical Engineering at Texas A&M, Texas Instruments, 3M,

Toshiba, Lucent Technologies, and Reliant Energy. The chart outlines how time was spent. Hours have

been estimated.

With the practical experience gained by the working budget, the team’s industry partners and the

faculty advisors the team was able to make well-informed design decisions to aggressively lower the cost

of the final 10kW design and 1.5kW prototype. The TAMU fuel cell inverter team’s approach to reducing

the cost of the inverter by reducing the number a high cost switching devices by adopting push-pull

technology, using a low cost Motorola SG3525A PWM DC-DC controller and including an efficient DSP

DC-AC control board.

36
Materials E s t i m a t e d L a b o r
Hours @ $35/hr
Labor
Research $0 800 $28,000
Design $0 5000 $175,000
Debugging $0 1900 $66,500
Prototype Testing $0 200 $7,000
Final Assembly $0 100 $3,500
Equipment
Computer $2,000 0 $0
Software $1,000 0 $0
DSP Bundle $3,990 0 $0
Books/References $1,000 0 $0
Parts
Inverter (DSP Design) $200 0 $0
DSP Chip $100 0 $0
Board $500 0 $0
Inverter Electronic Components $500 0 $0
Energy Source (Fuel Cell) $4,000 0 $0
Travel
Company Presentations $1,000 200 $7,000
Orlando, Florida $5,000 30 $1,050
West VA $10,000 70 $2,450
Miscellaneous
Materials $750 0 0

SubTotals $30,040 8300 $290,500


$320,540
Overhead -44% $141,038
Total Expenditures: $461,578

Table 4: Budget for the TAMU Fuel Cell Inverter Development

By use of the push–pull topology the number of MOSFETs was minimized to half needed by a

full bridge topology. IGBT’s were reduced in the inverter by use of the half bridge topology opposed to

the full bridge topology. The Motorola SG3525A PWM controller provided a low cost solution to control

of the DC-DC converter. It provides a single chip control solution opposed to complex discrete analog

hardware. DSP control of the DC-AC inverter provides efficiency of time and control. Readily

programmable, the DSP enables easy design changes to account for differing power applications.

Program capability translates into efficiency in human capital reducing costs of analysis, troubleshooting,

development and manufacturing of the fuel cell inverter. The use of the DSP allows a seamless interface

with other components of a power management system, saving integration time and human recourses. The

topology of the TAMU Fuel cell Inverter System employs a high voltage battery floating on the on the

DC-link. This approach does not add any additional power processing cost for sudden load management.

37
The cost for the power components of the TAMU Fuel Cell Inverter system were calculated by

developing the cost of the DC-DC converter and the DC-AC inverter and adding the two components

together. The Costs were based on the schematic and the quantity and power ratings take-off sheet shown

in Figure 18. The results of the cost analysis for the DC-DC converter are seen on the normalized

spreadsheet Table 5 and the results of the DC-AC costs are seen in Table 6.

The cost of the DC-DC converter was $290.51. The cost of the DC-AC inverter $206.79. The

total cost of the TAMU Fuel Cell System was $497.30. Following the cost analysis guild and spreadsheet

provided by the 2001 Future Energy Committee, the TAMU Fuel cell Inverter Team believes the power

processing components proposed by this design can be produced for less than the required $500.00

38
TR1
1:5 L1 I DC
+ ia
T1
Fuel Cell Input K1
48VDC Iin D1 D3 C2 Lb S1 S3 L2
N2 C4 3 A
Vin N1 Vbatt N
+ AC Output
C1 120/240V , 60 Hz
- VDC
N1 Lb C5 B
C3 3
N2 Vbatt ib N
D4 D2 L3 K2
- S2 S4
T2

Battery Backup
48VDC / 400VDC, 40KHz PUSH PULL CONVERTER 120V/240VAC, 20KHz PWM INVERTER

Note: Components shown in dotted boxes are not considered for cost evaluation

39
Component Designation Rating Quantity

MOSFET T1,T2 100V, 100A 4

Input capacitor C1 1000uF,100V 1

Bulk capacitor C2,C3 4500uF, 250V 2

Transformer TR1 17kVA, 400V, 38A 1

Diode D1,D2,D3,D4 600V, 38A 4

Figure 18: Power Schematic and Rating Take-Off Sheet


Choke L1 250µH, 38A 1

IGBT S1,S2,S3,S4 600V, 30A 4

Output filter capacitor C4,C5 12µF, 200V 2

Output filter inductor L2,L3 123µH, 42A 2

Contactor K1, K2 120V, 42A 2


4.2 DC-DC Converter Costs

2001 FUTURE ENERGY CHALLENGE

UNIVERSITY: Texas A&M University


NAME OF MAIN CONTACT: Dr. Prasad Enjeti
PROJECT NAME: TAMU Fuel Cell Inverter
DATE: June, 15 2001

VOLT VOLT CUR CUR UNIT EXTENDED


QTY DESIG UNIT MEASURE (Vpk) (Vrms) (Avg) (Arms) COST COST
DIODE
DIODE 4 D1,2,3,4 600 38 4.13 16.50
DIODE - DUAL MODULE
DIODE - DUAL MODULE
IGBT
IGBT
TRANSISTOR
MOSFET 4 Q1,2,3,4 100 100 9.18 36.74
MOSFET
SCR
CAP (ALUM) uF
CAP (ALUM) 2 C3,4 4500 uF 250 39.04 78.09
CAP (ALUM) 1 1000 uF 100 1.49 1.49
CAP (ALUM) uF
CAP (FILM) uF
CAP (FILM) uF
CAP (FILM) uF
CAP (FILM) uF
CAP (FILM) uF
CAP (FILM) uF
POWER RESISTOR W
POWER RESISTOR W
POWER RESISTOR W
CHOKE 1 L6A 250 UH 38 60.99 60.99
CHOKE UH
TRANSFORMER 1 T2 400 38 23.01 23.01
TRANSFORMER
TRANSFORMER
CONTACTORS
CONTACTORS
LOSSES W
CONTROL 43.36
PACKAGING 32.52
OTHER (EXPLAIN)
TOTAL 292.69

Table 5: DC-DC Converter Costs

40
4.3 DC-AC Inverter Costs

2001 FUTURE ENERGY CHALLENGE

UNIVERSITY: Tesax A&M University


NAME OF MAIN CONTACT: Dr. Prasad Enjeti
PROJECT NAME: TAMU Fuel Cell Inverter
DATE: June, 15 2001

VOLT VOLT CUR CUR UNIT EXTENDED


DEVICE QTY DESIG UNIT MEASURE (Vpk) (Vrms) (Avg) (Arms) COST COST
DIODE
DIODE - DUAL MODULE
DIODE - DUAL MODULE
IGBT 4 600 30 7.23 28.93
IGBT
IGBT
MOSFET
CAP (ALUM) uF
CAP (ALUM) uF
CAP (FILM) 2 12 uF 200 2.84 5.67
CAP (FILM) uF
POWER RESISTOR W
POWER RESISTOR W
CHOKE 2 123 UH 42 52.81 105.63
TRANSFORMER
CONTACTORS 2 120 42 6.48 12.95
CONTACTORS
LOSSES W
CONTROL 30.64
PACKAGING 22.98

OTHER (EXPLAIN)
TOTAL 206.79

Table 6: DC-AC Inverter Costs

41
5. Demonstr ation of Oper ational success of the 1.5kW Pr ototype
In this section an overall summary of the preliminary results obtained for our 1.5kW inverter

prototype is presented.

Figure 19: DC-DC Test Results

DC-DC converter: Figure 3. shows the DC-DC converter topology. Figure 19 shows the test

results and the input & output waveforms. The 42VDC input from the high current DC power supply is

at 49V. Figure 19 shows the DC-DC converter output voltage Vd1 and Vd2 obtained during the

experiment. It is clear that the DC-DC converter output is ±200V.

DC-AC Inverter: Figure 20 below shows the DC input into to the DC-AC inverter and a single

phase AC output of the inverter stage of the 1.5kW prototype. With the DC input voltage at 390V, the

42
voltage that appears across the drain and source of the IGBT S1 is shown above. The ACRMS waveform

shown is the sinusoidal output voltage VAO after the filter stage. This voltage equal to 121 volts RMS,

which meets the required specification of 120 ± 6% volts. This output is realized with a modulation index

(M) equal to 0.88. The measured frequency of the AC output is within the 60 ± 0.1 Hz requirement.

Figure 20: DC Input into to the DC-AC Inverter and a Single Phase AC Output

Figure 21 below shows the two PWM gating signals driving one IGBT of one phase of the

inverter. Channel 1 shows the PWM output from the DSP and Channel 2 shows the same PWM output

from an isolation opto-coupler. This image highlights clean PWM switching of the IGBT via the opto-

isolators controlled by the DSP. This clean switching translates to a cleaner output signal, which is

necessary to meet the THD < 5% specification. Please note that both Figure 20 and Figure 21 were

captured during same test

43
Figure 21: Two PWM Gating Signals Leading to One IGBT

Design of the Battery Backup System:


As specified in the Fuel Cell inverter design guidelines, a battery backup system is essential to

manage sudden load changes at the inverter output. Figure18 shows the TAMU Fuel Cell inverter

integrated with battery backup system on the DC-link. The TAMU Fuel Cell inverter employs a ±192V

battery backup system connected to the DC-link. A string of sixteen (16), 12V, 1.2Ah YUASA sealed

rechargeable lead-acid batteries are employed to form +192V. Another string of sixteen batteries of the

same rating form –192V. The entire string of 32 batteries are connected to the 400V DC-link via two

inductors (Figure. X). The string of 32 batteries provides 460.8Wh capacity in the DC-link to support

load increases. The purpose of the inductors is to block the DC-AC inverter ripple current from flowing

into the battery circuit. Since the DC-DC converter stage regulates the inverter to ±200V, ±192V battery

44
bank will essentially float on the DC-bus. In the event of sudden load increase, the ±192V battery bank

will supply the additional required power.

Below are photographs of the experimental setup. Figure 22 is of the DC-DC boost converter. Figure 23

is the single phase DC-AC inverter module.

Figure 22: DC-DC Boost Converter

45
Figure 23: Single Phas e DC-AC inverter

6. Responsibility Matrix & Organizational Approach

The Texas A&M Fuel Cell Inverter was a combined effort of undergraduate, graduate, faculty

and industry personnel primarily organized by Texas A&M faculty advisors; Drs. Enjeti, Yeary, Howze

and Culp. The team approach to the design solutions was implemented over several semesters. A wide

range disciplines including electrical engineering, computer engineering, chemical engineering and

mechanical engineering were utilized. A substantial commitment from all members of the design team

was required and a thank-you is forwarded to all those who committed funding, resources and time.

46
6.1 Institutional Commitment and Sources of Added Support
The Texas A&M team was fortunate to have secured the sponsorship and commitment from a

variety of corporations for the project. The resources and technical direction from industry professionals

proved useful in determining the feasibility, manufacturability, and cost factors involved in the teams

decisions. Several companies such as Toshiba, Texas Instruments, Reliant Energy, 3M, were helpful in

their support.

6.2 Impact on Undergraduate Education

The undergraduate students involved in the challenge were participants by virtue of enrollment in

the required electrical engineering senior design course at Texas A&M University. Students taking

electrical engineering directed studies course that involves research have also participated. The students

in the electrical engineering directed studies course earned three hours of course credit towards the their

undergraduate degrees. The students received an enriched experience of the engineering project process

including exposure to practical research, design, and manufacturing issues and techniques. The

opportunity to present their ideas and designs to industry was a valuable experience for all the students.

Undergraduate students worked in tandem with graduate students throughout the project. The

teams were lead by the graduate students under the supervision of the faculty advisors. The design

development teams are shown below in Figure 24 (the names of graduate level students are in Italics).

47
DSP/Inverter Team Integration Team:
Phillip Briggs Matt Campbell
David Leschberg Jared Machala
Matthew Webster Wes Weibel
Lori Dalton Cody Sicking
Oscar Montero Douglas Becker
Sansung Kim Rajesh Gopinath

Controls/DC-DC Converter Team:


Nick Denniston
Cory Cress
Andy Hale
Jon Burghardt
Mark Arldt
Rajesh Gopinath
Eugene Song

Figure 24: Design Development Teams

48
A plan for the work over the duration of the project was written in the form of a Gantt chart.
Gantt Chart

Date Activity
September Formation of Fall Student Team (consisting of an Inverter and DSP Design Teams)
2000 Commence Industrial Presentations for company sponsorship
Commence Proposal Preparation
Begin Research and Planning Phase

October Submit Proposal on Oct 2nd


Continue seeking further industry sponsorship
DSP Team will train on new TI DSP and begin testing DSP with Off-the-Shelf 2.5 kW Inverter
Inverter Team completes design simulations
Commence prototype construction and testing

November The Student Team attends Springboard Meeting in Orlando, FL


Inverter Team – Commence Final Buildout of the Inverter Prototype
DSP Team – incorporate DSP into Prototype

December 1.5 kW prototype completed


Prototype Engineering report completed

January Turnover to spring student team


2001 Organization of project sub-teams
Familiarization with project

February Familiarization with previous DSP code and PWM theory


Open-loop testing of control chip
Transformer characterization and testing
Design of sensing/isolation and conditioning circuits
Choose and order hardware/bus bars
Decide on methodology of chip power supply circuits
Setup XDRIVE and listserv for communication among team members
Investigate current spike problem and possible solutions

March Finish design of sensing/isolation and conditioning circuits


Layout of control circuit boards
Modify DSP control code to incorporate sensing and PWM requirements
Construct and test converter and inverter in open-loop
Test converter and inverter with control circuitry
Learn code for RS232 interface
Begin final report

Continued evaluation and modification of prototype


Complete packaging and RS232 interfacing requirements
April Write Final report including design and cost analysis
Peer review of package and report
May Project Completed
June Final Report Submitted
July All Texas A&M Team members attend Final Competition in Morgantown, W. Va.

Table 7: Organizational Gantt Chart

49
7. Nomenclatur e
Iin - input current
vL - inductor voltage VATr -Transformer VA rating

N1 - primary turns K -Turns ratio of transformer

N2 -secondary turns ID -bridge rectifier diode current

VD -input voltage RT -timing resistor


CT -timing capacitor
Vo - dc output voltage
VAO -Fundamental component of output
t - time
voltage
Hn - transfer function
ma - modulation index
Vo , n -output voltage harmonic VDC -DC link voltage
Vi , n -input voltage harmonic S w1 -switching function of inverter leg

XC -capacitor component of impedance IsA -current through inverter switch


IoA -output current of phase A
XL -inductance component of impedance
Irms -DC link current in rms
ZL ,n -impedance
Ic,rms -Capacitor current in rms
n -harmonic ∆Vc -Voltage ripple on capacitor
Vh - equivalent voltage IT -Current through the MOSFET
h - harmonic Vref -reference voltage
Ih - current at h harmonic T -transfer function

L - inductance
C - capacitance
f1 - fundamental frequency
Pin - power input
Vin - voltage input

50
8. List of Acr onyms

AC - alternating current

ADC - analog-to-digital converter

BJT - bipolar junction transistor

CPU - central processing unit

DC - direct current

DOE - Department of Energy

DSP - digital signal processor

EVM - evaluation module

IGBT - insulated gate bipolar transistors

LED - light emitting diodes

LPF - low pass filter

LHV - low heating value

MOSFET - metal oxide semiconductor field effect transistors

MW - megawatt

NTC - negative temperature coefficient

PWM - pulse width modulation

TAMU - Texas A&M University

THD - total harmonic distortion

51
9. Bibliogr aphy
National Fuel Cell Research Center at the University of California, Irvine. Fuel Cell Technology Comes of Age.
Available: http://www.nfcrc.uci.edu/journal/article/fcarticleE.htm.

Texas Instruments web site.


http://dspvillage.ti.com/docs/prod/productfolder.jhtml?genericPartNumber=TMS320LF2407

2001 Future Energy Challenge.


http://www.energychallenge.org

52
10. References

[1] Jiang, H.J., Qin, Y., Du, S.S., Yu, Z.Y., Choudhury, S., DSP based Implementation of a Digitally-
Controlled Single Phase PWM Inverter for UPS, Telecommunications Energy Conference, 1998,
INTELEC. Twentieth International, 1999, Page(s): 221 -224

[2] Abdel-Rahim, N., Quaicoe, J.E. Multiple feedback loop control strategy for single-phase voltage
source UPS inverter, Power Electronics Specialists Conference, PESC '94 Record., 25th Annual IEEE ,
1994 , Page(s): 958 -964 vol.2

[3] Abdel-Rahim, N.M., Quaicoe, J.E. Analysis and Design of a Multiple Feedback Loop Control
Strategy for Single-Phase Voltage-Source UPS Inverters, Power Electronics, IEEE Transactions on
Volume: 11 4 , July 1996 , Page(s): 532 -541

[4] Shih-Liang Jung, Hsiang-Sung Huang, Meng-Yueh Chang, Ying-Yu Tzou,


DSP-based Muliple-Loop Control Strategy for Single-Phase Inverters Used in AC Power Sources, Power
Electronics Specialists Conference, 1997. PESC '97 Record., 28th Annual IEEE
Volume: 1 , 1997 , Page(s): 706 -712 vol.1

[5] Robert W. Erickson, Dragon Maksimovic,


Fundamentals of Power Electronics, Kluwer Academic Publishers, 2001

[6] Ned Mohan, Tore M. Undeland, William P. Robbins,


Power Electronics, Converter Applications and Design
John Wiley and Sons, 1995

53
11. Appendices

54
Appendix A: Schematics for the TAMU Inverter

55
56
57
58
59
Appendix B: Schematics for DSP Control

60
61
62
63
Appendix C: DSP code (All .c and .h files)

evmgr2407.c

/*----------------------------------------------------------------------|
| |
| File: evmgr2407.c |
| Target Processor: TMS320LF2407 |
| Compiler Version: 6.6 |
| Assembler Version: 6.6 |
| Date: 11/2/00 |
| Programmer: SSKIM |
|---------------------------------------------------------------------|*/

#include "LF2407.h"

#define PS2 0x0800


#define PS1 0x0400
#define PS0 0x0200

#define FREQIN4 ( 0 )
#define FREQIN2 ( ( PS0 ) )
#define FREQIN1_33 ( ( PS1 ) )
#define FREQIN1 ( ( PS1 ) | ( PS0 ) )
#define FREQIN_8 ( ( PS2) )
#define FREQIN_66 ( ( PS2) | ( PS0) )
#define FREQIN_57 ( ( PS2) | ( PS1) )
#define FREQIN_50 ( ( PS2) | ( PS1) | ( PS0) )

#define SCSR1 0x7018


#define SCSR1_PTR ((unsigned int*)SCSR1)
volatile unsigned int configdata;

#define IOWSB0 0x0048


#define IOWSB1 0x0080
#define IOWSB2 0x0100

#define ADC_CLKEN 0x0080


#define SCI_CLKEN 0x0040
#define SPI_CLKEN 0x0020
#define CAN_CLKEN 0x0010
#define EVB_CLKEN 0x0008
#define EVA_CLKEN 0x0004

#define MS_TIME_LOOP 0x0900

ioport unsigned port0ffff;

Continued

64
2001 Future Energy Challenge Competition

Thank You !
And our Sponsors:
2001 Future Energy Challenge
Competition
Undergraduate Student Team Members
Matt Campbell Andy Hale Cory Cress
Jon Burghardt David Leschber Cody Sicking
Phillip Briggs Wes Weibel Gary Tobola
Matthew Webster Nick Denniston David Payne
Jared Machala Matt Campbell David Leschber
Wes Weibel Nick Denniston Dao Le
Douglas Becker Justin Busse Randall Jones
Steven Campbell Lori Dalton Mike Spence
Mark Arldt
2001 Future Energy Challenge
Competition

Graduate Student Team Members


Oscar Montero
Sangsun Kim
Jaehong Hahn
Rajesh Gopinath
Leonardo Palma
2001 Future Energy Challenge
Competition

Faculty Advisors
Dr. Prasad Enjeti
Email: enjeti@tamu.edu Tel: 979-845-7466
Dr. Mark Yeary
Dr. Jo Howze
Dr. Charles Culp
Development of a Low Cost Fuel Cell Inverter
with DSP Based Control

Department of Electrical Engineering


September 2000 - August 2001
Inverter Packaging
Cooling Fans
Heat Sinks

DC-DC
Converter DSP Control
DC – AC Board
Inverter
Inverter Performance
Single Phase on 500 W Resistive Load

Inverter Output Voltage


(linear load)

THD < 1%
Vol. Reg.= ±1%

Collector to Emitter Voltage


Inverter Performance
Phase A on Resistive Load, THD = 2.5%
Phase B on Non-Linear Load Vol. Reg.= ±3%

Linear Load, Phase A Voltage

Non-Linear Load Phase B


Voltage

Non-Linear Load Current


TAMU Inverter Undergoing
Testing on NETL Fuel Cell 8/14/01
TAMU Inverter Powering 900W
Load on NETL Fuel Cell 8/14/01
Data Collected from NETL Fuel
Cell 8/14/01
• THD=1.2%
• 450W/phase
Texas A&M University
2001 Future Energy Challenge Team
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