Single Channel

//NLC_4sec_8th_order_1ch
module NLC_4sec_8th_order_1ch(
input clk,
input GlobalReset,
output srdyo, // ufix1
input srdyi, // ufix1
//NLC ports for channel 0

output [20:0] ch0_x_lin, // sfix21
input [20:0] ch0_x_adc, // sfix21
input [19:0] ch0_section_limit, // ufix20
input [31:0] ch0_select_section_coefficients_stdev_4_porty, // ufix32
input [31:0] ch0_select_section_coefficients_mean_4_porty, // ufix32
input [31:0] ch0_select_section_coefficients_coeff_4_8_porty, // ufix32
input [31:0] ch0_select_section_coefficients_coeff_1_0_porty // ufix32
);
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
reg [31:0] ch0_select_section_coefficients_mean_1_porty_r; reg [31:0]

ch1_select_section_coefficients_mean_1_porty_r;
reg [31:0] ch0_select_section_coefficients_stdev_1_porty_r; reg [31:0]

ch1_select_section_coefficients_stdev_1_porty_r;
reg [31:0] ch0_select_section_coefficients_coeff_1_0_porty_r; reg [31:0]

ch0_select_section_coefficients_coeff_2_0_porty_r;
reg [20:0] ch0_x_adc_r; reg [19:0] ch0_section_limit_r;
///////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
/////input data storage
latch//////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
always @ (posedge srdyi) begin
ch0_select_section_coefficients_mean_1_porty_r<=ch0_select_section_coefficients_mea
n_1_porty;
n_2_porty;
n_3_porty;
n_4_porty;
ch0_select_section_coefficients_stdev_1_porty_r<=ch0_select_section_coefficients_st
dev_1_porty;
dev_2_porty;
dev_3_porty;
dev_4_porty;
ch0_select_section_coefficients_coeff_1_0_porty_r<=ch0_select_section_coefficients_
coeff_1_0_porty;
coeff_1_1_porty;
coeff_1_2_porty;
coeff_1_3_porty;
coeff_1_4_porty;
coeff_1_5_porty;
coeff_1_6_porty;
coeff_1_7_porty;
coeff_1_8_porty;
coeff_2_0_porty;
coeff_2_1_porty;
coeff_2_2_porty;
coeff_2_3_porty;
coeff_2_4_porty;
coeff_2_5_porty;
coeff_2_6_porty;
coeff_2_7_porty;
coeff_2_8_porty;
coeff_3_0_porty;
coeff_3_1_porty;
coeff_3_2_porty;
coeff_3_3_porty;
coeff_3_4_porty;
coeff_3_5_porty;
coeff_3_6_porty;
coeff_3_7_porty;
coeff_3_8_porty;
coeff_4_0_porty;
coeff_4_1_porty;
coeff_4_2_porty;
coeff_4_3_porty;
coeff_4_4_porty;
coeff_4_5_porty;
coeff_4_6_porty;
coeff_4_7_porty;
coeff_4_8_porty;
ch0_x_adc_r<=ch0_x_adc; ch0_section_limit_r<=ch0_section_limit;
end
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
initial begin
$monitor("c:%b, \t o_add:%b, \t addo:%d, \t i_mult:%b,\t mullto: %d,o_smctofp:%b,
smctofpo_: %d \t %d,\t %b, \t %d, \t %b",
clk,srdy_o_add,add_o_w,srdy_o_mult,mult_o_w,srdy_o_smctofp,smctofp_o_w,add_i2_r,srd
y_i_add,smctofp_o_w,srdyo);
end
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
//////////////PORT REGISTOR
DEFINITIONS////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
reg [20:0] fptosmc_i_r; reg srdy_i_fptosmc; wire srdy_o_fptosmc; wire [31:0]

fptosmc_o_w;
reg [31:0] feedback_r; reg [19:0] secsel_i_r;
reg sysreset; reg process_reset; wire RESET; reg srdyo_r; reg process; reg op_en;
reg [3:0] coef_sel;
wire gclk0; wire gclk1; wire gclk2; reg gate0; reg gate1; reg gate2; reg gate3;
wire gclk3;
reg [31:0] smctofp_i_r; wire [20:0] smctofp_o_w; reg srdy_i_smctofp; wire

srdy_o_smctofp;
wire [31:0] add_o_w; wire [31:0] add_i1_w; reg [31:0] add_i1_r; reg [31:0]
add_i2_r; wire [31:0] add_i2_w;
wire [31:0] add_o_w_0; wire [31:0] add_o_w_1; reg srdy_i_add; wire srdy_o_add; wire
[31:0] coef_o_w; wire [31:0] mean_o_w;
reg [31:0] mult_i_r; wire [31:0] mult_i_w; wire [31:0] mult_o_w_1; wire [31:0]
mult_o_w; reg srdy_i_mult;
wire srdy_o_mult; wire [31:0] std_o_w; wire [31:0] store_w;
reg [31:0] store_r; reg store_en; reg flag;
reg [20:0] ch0_x_lin_r;
always @ (*) begin

if (RESET==1'b1) begin
if (GlobalReset) begin
ch0_x_lin_r=32'h00000000;
end
if (GlobalReset==1'b1 || sysreset==1'b1) begin
ch0_x_lin_r=21'd0;
gate0=1'b0;
gate1=1'b0;
gate2=1'b0;
gate3=1'b0;
process=1'b0;
end
flag=1'b0;
fptosmc_i_r=32'h00000000;
feedback_r=32'h00000000;
op_en=1'b0;
srdyo_r=1'b0;
sysreset=1'b0;
process_reset=1'b0;
coef_sel=4'b0000;
smctofp_i_r=32'h00000000;
add_i1_r=32'h00000000;
add_i2_r=32'h00000000;
mult_i_r=32'h00000000;
store_en=1'b0;
end
end
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
//////////SECTION SELECT
LOGIC//////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
reg [1:0] sec_0;

always @ (*) begin
if (srdyi==1'b1) begin
if (ch0_x_adc_r [20] == 1'b0) begin
secsel_i_r=ch0_x_adc_r[19:0];
if (secsel_i_r >= 20'd0 && secsel_i_r < ch0_section_limit_r) //section 3
sec_0=2'b10;
else if (secsel_i_r >= ch0_section_limit_r)
sec_0=2'b11;
end
else if (ch0_x_adc_r [20] == 1'b1) begin
secsel_i_r=~(ch0_x_adc_r[19:0])+1'b1;
if (secsel_i_r > 20'd0 && secsel_i_r <= ch0_section_limit_r) //section 3
sec_0=2'b01;
else if (secsel_i_r > ch0_section_limit_r)
sec_0=2'b00;
end
end
end
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
//////////////PORT AND REGISTOR
CONNECTIONS////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
assign gclk0=(clk) & (gate0); assign gclk1=(clk) & (gate1); assign gclk2=(clk) &
(gate2); assign gclk3=(clk) & (gate3);
assign RESET=(process_reset) | (GlobalReset) | (sysreset); assign srdyo=srdyo_r;
always @ (posedge gclk0) begin
fptosmc_i_r<=ch0_x_adc_r;
add_i1_r<=add_i1_w;
add_i2_r<=add_i2_w;
end
fp_to_smc_float U03(
.clk(gclk0),
.GlobalReset(RESET),
.y_o_portx(fptosmc_o_w),
.x_i(fptosmc_i_r),
.srdyo_o(srdy_o_fptosmc),
.srdyi_i(srdy_i_fptosmc)
);
MUX_2ch_32bit
MUXADD_i1(.inp1(fptosmc_o_w),.inp2(mult_o_w_1),.out(add_i1_w),.sel(process));
MUX_2ch_32bit
MUXADD_i2(.inp1(mean_o_w),.inp2(coef_o_w),.out(add_i2_w),.sel(process));
MUX_2ch_32bit
MUXMULT_i(.inp1(std_o_w),.inp2(store_r),.out(mult_i_w),.sel(process));
MEANMUX
MEAN1(.ch0_select_section_coefficients_mean_1_porty_r(ch0_select_section_coefficien
ts_mean_1_porty_r),
.ch0_select_section_coefficients_mean_2_porty_r(ch0_select_section_coefficients_mea
n_2_porty_r),
n_3_porty_r),
n_4_porty_r),
.sec_sel(sec_0),.mean_o_w(mean_o_w));
STDMUX
STD1(.ch0_select_section_coefficients_stdev_1_porty_r(ch0_select_section_coefficien
ts_stdev_1_porty_r),
.ch0_select_section_coefficients_stdev_2_porty_r(ch0_select_section_coefficients_st
dev_2_porty_r),
dev_3_porty_r),
dev_4_porty_r),
.sec_sel(sec_0),.std_o_w(std_o_w));
COEFMUX
COEF1(.ch0_select_section_coefficients_coeff_1_0_porty_r(ch0_select_section_coeffic
ients_coeff_1_0_porty_r),
.
ch0_select_section_coefficients_coeff_1_1_porty_r(ch0_select_section_coefficients_c
oeff_1_1_porty_r),
.
oeff_1_2_porty_r),
.
oeff_1_3_porty_r),
.
oeff_1_4_porty_r),
.
oeff_1_5_porty_r),
.
oeff_1_6_porty_r),
.
oeff_1_7_porty_r),
.
oeff_1_8_porty_r),
.
oeff_2_0_porty_r),
.
oeff_2_1_porty_r),
.
oeff_2_2_porty_r),
.
oeff_2_3_porty_r),
.
oeff_2_4_porty_r),
.
oeff_2_5_porty_r),
.
oeff_2_6_porty_r),
.
oeff_2_7_porty_r),
.
oeff_2_8_porty_r),
.
oeff_3_0_porty_r),
.
oeff_3_1_porty_r),
.
oeff_3_2_porty_r),
.
oeff_3_3_porty_r),
.
oeff_3_4_porty_r),
.
oeff_3_5_porty_r),
.
oeff_3_6_porty_r),
.
oeff_3_7_porty_r),
.
oeff_3_8_porty_r),
.
oeff_4_0_porty_r),
.
oeff_4_1_porty_r),
.
oeff_4_2_porty_r),
.
oeff_4_3_porty_r),
.
oeff_4_4_porty_r),
.
oeff_4_5_porty_r),
.
oeff_4_6_porty_r),
.
oeff_4_7_porty_r),
.
oeff_4_8_porty_r),
.sec_sel(sec_0),.coef_sel(coef_sel),.coef_o_w(coef_o_w));
smc_float_adder U00(
.clk(gclk0),
.x_i_porty(add_i1_r),
.y_i_porty(add_i2_r),
.z_o_portx(add_o_w),
.srdyo_o(srdy_o_add),
.srdyi_i(srdy_i_add)
);
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
reg [31:0] store_w_r; reg [31:0] mult_o_w_1_r; reg [31:0] add_o_w_0_r; reg [31:0]
add_o_w_1_r;
assign store_w=store_w_r; assign mult_o_w_1=mult_o_w_1_r; assign
add_o_w_0=add_o_w_0_r; assign add_o_w_1=add_o_w_1_r;
always @ (*) begin
if (op_en==1'b1)
add_o_w_1_r=add_o_w;
else
add_o_w_0_r=add_o_w;
end
always @ (*) begin

if (process==1'b1)
mult_o_w_1_r=mult_o_w;
else
store_w_r=mult_o_w;
end
///////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
if (op_en==1'b0) begin
feedback_r<=add_o_w_0;
end
end
mult_i_r<=mult_i_w;
end
if (store_en==1'b1) begin
store_r<=store_w;
store_en<=1'b0;
end
end
smc_float_multiplier U01(
.clk(gclk1),
.x_i_porty(mult_i_r),
.y_i_porty(feedback_r),
.z_o_portx(mult_o_w),
.srdyo_o(srdy_o_mult),
.srdyi_i(srdy_i_mult)
);
assign ch0_x_lin=ch0_x_lin_r;

if (srdyo_r==1'b1)
srdyo_r=1'b0;
end

smctofp_i_r<=add_o_w_1;
if (srdy_o_smctofp==1'b1) begin
ch0_x_lin_r<=smctofp_o_w;
end
end
smc_float_to_fp U02(
.clk(gclk2),
.x_i_porty(smctofp_i_r),
.y_o(smctofp_o_w),
.srdyo_o(srdy_o_smctofp),
.srdyi_i(srdy_i_smctofp)
);
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
//////////////FSM
CONTROLLER/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
reg [3:0] state; reg [3:0] next_state;
parameter START=4'b0000;
parameter FPTOSMC=4'b0001;
parameter MEANADD=4'b0010;
parameter STDMULT=4'b0011;
parameter LOAD=4'b0100;
parameter HORN_MULT1=4'b0101;
parameter HORN_ADD=4'b0110;
parameter HORN_MULT2=4'b0111;
parameter SMCTOFP=4'b1000;
parameter OUTPUT=4'b1001;
// reset logic
always @ (*) begin
if (GlobalReset) begin
state=START;
next_state=START;
end
end
always @ (posedge clk) begin

if (srdy_i_fptosmc==1'b1) begin
srdy_i_fptosmc=1'b0;
end
if (srdy_i_add==1'b1) begin
srdy_i_add=1'b0;
end
if (srdy_i_mult==1'b1) begin
srdy_i_mult=1'b0;
end
if (srdy_i_smctofp==1'b1) begin
srdy_i_smctofp=1'b0;
end
if (srdyo_r==1'b1) begin
srdyo_r=1'b0;
end
end
///////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
//Memory
element ///////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
always @ (posedge clk) begin
state<=next_state;
end
///////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
//next state
logic /////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
always @ (*) begin
case (state)
4'b0000: begin
if (srdyi==1'b1) begin
next_state=4'b0001;
gate0=1'b1;
end
end
4'b0001: begin
if (srdy_o_fptosmc==1'b1) begin
next_state=4'b0010;
end
end
4'b0010: begin
if (srdy_o_add==1'b1) begin
next_state=4'b0011;
gate1=1'b1;
gate3=1'b1;
end
end
4'b0011: begin
if (srdy_o_mult==1'b1) begin
next_state=4'b0100; // LOAD
store_en=1'b1;
end
end
4'b0100: begin
if (store_en==1'b0) begin
next_state=4'b0101; // HORN_MUL
end
end
4'b0101: begin
next_state=4'b0110;
gate3=1'b1;
end
end
4'b0110: begin
if (srdy_o_add==1'b1) begin
next_state=4'b1000;
gate2=1'b1;
end
else begin
next_state=4'b0111;
end
end
end
4'b0111: begin
next_state=4'b0110;
if (coef_sel==4'b1000)
op_en=1'b1;
end
end
4'b1000: begin
if (srdy_o_smctofp==1'b1)
next_state=4'b1001;
end
4'b1001: begin
if (flag==1'b1)
next_state=4'b0000;
end
default: next_state=state;
endcase
end
///////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
//current state and output
logic /////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
always @ (state) begin
case (state)
4'b0000: begin
sysreset=1'b1;
end
4'b0001: begin
srdy_i_fptosmc=1'b1;
end
4'b0010: begin
srdy_i_add=1'b1;
end
4'b0011: begin
srdy_i_mult=1'b1;
end
4'b0100: begin
store_en=1'b0;
process_reset=1'b1;
process=1'b1;
gate3=1'b0;
end
4'b0101: begin
srdy_i_mult=1'b1;
end
4'b0110: begin
srdy_i_add=1'b1;
end
4'b0111: begin
srdy_i_mult=1'b1;
coef_sel=coef_sel+1;
end
4'b1000: begin
srdy_i_smctofp=1'b1;
end
4'b1001: begin
srdyo_r=1'b1;
flag=1'b1;
end
endcase
end
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
endmodule
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
//////////////////MODULE DEFINITIONS
///////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
module DEMUX_2ch_32bit (out1,out2,inp,sel);

input [31:0] inp; output [31:0] out1; output [31:0] out2; input sel;
reg [31:0] out1_r; assign out1=out1_r;
reg [31:0] out2_r; assign out2=out1_r;
always @ (*) begin
case (sel)
1'b1: out2_r=inp;
1'b0: out1_r=inp;
endcase
end
endmodule
module MUX_2ch_32bit (inp1,inp2,out,sel);
input [31:0] inp1; input [31:0] inp2; output [31:0] out; input sel;
reg [31:0] out_r; assign out=out_r;
always @ (*) begin
case (sel)
1'b1: out_r=inp2;
1'b0: out_r=inp1;
endcase
end
endmodule
module MEANMUX (
ch0_select_section_coefficients_mean_1_porty_r,ch0_select_section_coefficients_mean
_2_porty_r,
ch0_select_section_coefficients_mean_3_porty_r,ch0_select_section_coefficients_mean
_4_porty_r,
sec_sel,mean_o_w);
input [31:0] ch0_select_section_coefficients_mean_1_porty_r;

output [31:0] mean_o_w; input [1:0] sec_sel;
reg [31:0] mean_o_w_r;
assign mean_o_w=mean_o_w_r;
always @ (*) begin
case (sec_sel)
2'b00: mean_o_w_r=ch0_select_section_coefficients_mean_1_porty_r;
endcase
end
endmodule
module STDMUX (
ch0_select_section_coefficients_stdev_1_porty_r,ch0_select_section_coefficients_std
ev_2_porty_r,
ch0_select_section_coefficients_stdev_3_porty_r,ch0_select_section_coefficients_std
ev_4_porty_r,
sec_sel,std_o_w);
input [31:0] ch0_select_section_coefficients_stdev_1_porty_r;

output [31:0] std_o_w; input [1:0] sec_sel;
reg [31:0] std_o_w_r;
assign std_o_w=std_o_w_r;
always @ (*) begin
case (sec_sel)
2'b00: std_o_w_r=ch0_select_section_coefficients_stdev_1_porty_r;
endcase
end
endmodule
module COEFMUX (
ch0_select_section_coefficients_coeff_1_0_porty_r,
ch0_select_section_coefficients_coeff_4_4_porty_r, sec_sel, coef_sel, coef_o_w);
input [31:0] ch0_select_section_coefficients_coeff_1_0_porty_r;




input [1:0] sec_sel; input [3:0] coef_sel;

output [31:0] coef_o_w;
reg [31:0] coef_o_w_r;
assign coef_o_w=coef_o_w_r;
always @ (*) begin
case (sec_sel)
2'b00:
begin
case (coef_sel)
4'b0000: coef_o_w_r=ch0_select_section_coefficients_coeff_1_8_porty_r;
endcase
end
2'b01:
begin
case (coef_sel)
endcase
end
2'b10:
begin
case (coef_sel)
endcase
end
2'b11:
begin
case (coef_sel)
endcase
end
endcase
end
endmodule
///////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////

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Single Channel

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//NLC_4sec_8th_order_1ch

//NLC ports for channel 0

reg [31:0] ch0_select_section_coefficients_mean_1_porty_r; reg [31:0]

reg [31:0] ch0_select_section_coefficients_stdev_1_porty_r; reg [31:0]

reg [31:0] ch0_select_section_coefficients_coeff_1_0_porty_r; reg [31:0]

always @ (posedge srdyi) begin

reg [20:0] fptosmc_i_r; reg srdy_i_fptosmc; wire srdy_o_fptosmc; wire [31:0]

reg [31:0] smctofp_i_r; wire [20:0] smctofp_o_w; reg srdy_i_smctofp; wire

reg [20:0] ch0_x_lin_r;

always @ (*) begin

reg [1:0] sec_0;

always @ (*) begin

always @ (posedge gclk2) begin

always @ (posedge gclk2) begin

always @ (posedge clk) begin

module DEMUX_2ch_32bit (out1,out2,inp,sel);

input [31:0] ch0_select_section_coefficients_mean_1_porty_r;

input [31:0] ch0_select_section_coefficients_stdev_1_porty_r;

input [31:0] ch0_select_section_coefficients_coeff_1_0_porty_r;

input [31:0] ch0_select_section_coefficients_coeff_2_0_porty_r;

input [31:0] ch0_select_section_coefficients_coeff_3_0_porty_r;

input [31:0] ch0_select_section_coefficients_coeff_4_0_porty_r;

input [1:0] sec_sel; input [3:0] coef_sel;

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