Vhdl principal

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity seguridad is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
s0 : inout STD_LOGIC;
s1 : inout STD_LOGIC;
s2 : inout STD_LOGIC);
end seguridad;

architecture Behavioral of seguridad is

signal tmp1, tmp2 : std_logic;

begin

---llamo a la entidad dekl contador de errores

contador_3: entity work.contador
PORT MAP(
clk => clk,
reset => tmp2,
x => s1,
y => s2
);
---llamo a la entidad de verificacion de codigo
comprobacion: entity work.sistema
PORT MAP(
clk => clk,
reset => tmp1,
E0 => x,
E1 => y,
E2 => z,
y0 => s0,
y1 => s1
);
---entidad de multiplicacion
and_gate_1: entity work.and_gate
PORT MAP(
x => not s2,
y => reset,
o => tmp1
);

and_gate_2: entity work.and_gate

PORT MAP(
x => not s0,
y => reset,
 o => tmp2
);
end Behavioral;

maquina secuencial de verificacion de codigo

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sistema is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
E0 : in STD_LOGIC;
E1 : in STD_LOGIC;
E2 : in STD_LOGIC;
y0 : out STD_LOGIC;
y1 : out STD_LOGIC);
end sistema;
architecture Behavioral of sistema is
signal d0,d1,d2,q0,q1,q2: STD_LOGIC;
begin
--instanciacion de las entidades de un flip flop tipo d
ff_d0: entity work.ff_d
PORT MAP(
clk => clk,
reset => reset,
d => d0,
q => q0
);

ff_d1: entity work.ff_d

PORT MAP(
clk => clk,
reset => reset,
d => d1,
q => q1
);

ff_d2: entity work.ff_d

PORT MAP(
clk => clk,
reset => reset,
d => d2,
q => q2
);
--revision de codigo
d0 <= ((not E0) and (not q2) and (not q1) and q0) or (q2 and (not q0)) or((not E2)and (not
E1)and E0 and(not q1)and(not q0))or((not E2)and (not E1)and E0 and q1 and q0)or(E1 and (not
q2)and (not q1)and q0)or((not E2)and E1 and E0 and q1 and (not q0))or(E2 and (not q2)and
(not q1)and q0);
d1 <= (q1 and (not q0))or(q2 and (not q1)and q0)or((not E2)and (not E1)and E0 and (not
q1)and q0);
d2 <= ((not E1)and q1 and (not q0))or(q2 and(not q1))or(E1 and (not q1))or(E1 and
q0)or(E2)or( not E0)or(q2 and (not q0));
--salidas---
y0 <= ((not q2)and q1 and q0);
y1 <= (q2 and q1 and q0);
end Behavioral;

entidad contador mod 3

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity contador is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
x : in STD_LOGIC;
y : out STD_LOGIC);
end contador;

architecture Behavioral of contador is

signal da,db,qa,qb : STD_LOGIC;
begin
--llamo a las entidades del flip flop tipo d
ff_d3: entity work.ff_d
PORT MAP(
clk => clk,
reset => reset,
d => da,
q => qa );
ff_d4: entity work.ff_d
PORT MAP(
clk => clk,
reset => reset,
d => db,
q => qb );
--contador
da <= (x and (not qa))or((not x)and qa)or(x and qb);
db <= ((qb)or(x and qa));
-- salidas
y <= qb and qa;
end Behavioral;

entidad de un flip flop tipo d

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ff_d is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
end ff_d;

architecture Behavioral of ff_d is

begin
process (clk,d,reset)
begin
if clk'event and clk='1' then
if reset='1' then
q <= d;
else
q <= '0';
end if;
end if;
end process;

end Behavioral;