EE 619

Radio Frequency
Microelectronics Chip Design

PROJECT 1 : LNA DESIGN

GROUP NO. 11
Nitin S. Panchmani (15307R007)
Sourya Dewan (15307R004)
 Specification Achieved
Parameters Required Achieved
Operating frequency 2.49 GHz 2.49 GHz
LNA Bandwidth 100 MHz 200 MHz
Voltage Gain ( ) 20 dB (min) 30 dB
Noise Figure 3 dB (max) 2.785 dB
Source Impedance 50 ohm 52.42 ohm
Desired S11 < -10 dB - 27.69 dB
IIP3 -6 dBm (min) 554m dBm
1-dB compression point -16 dBm (min) -13.64 dBm
8 mW (max) . =
Power Dissipation
.
 Topology Used
Common Source with inductive degeneration

Note: Ls and L1 are modeled in Asitic . The load resistor is considered to be the modeled
equivalent resistance of L1. While Lg is considered to be the Off chip Inductor. Cg is
modeled to be pad capacitance and Cs is the blocking capacitor .
 Design Values

Design Parameter Value

L1 and C1 4.088nH and 989fF
1 , 2 45 nm
1 5*8.73 um
2 5*8.485 um
711fF
and 1.45nH and 10 nH
50fF
622fF
3 , 3 300nm
 Inductor model

ASITIC COMMANDS
1. For 1.45nH
SQ NAME=A100:LEN=87:W=6:S=0.3:N=4:METAL=M4:EXIT=M5:XORG=200:YORG=200

2. For 4.08nH
SQ NAME=A100:LEN=156:W=8:S=0.5:N=4:METAL=M4:EXIT=M5:XORG=200:YORG=200
 Design Flow
TRANSISTOR SIZING AND INPUTS
Simulated Single transistor with L= 45nm, w= 1 um and Vdd = 0.55 V and
= ().

Plotting = ( = over-drive Voltage of transistor) versus

and versus .

Now, By plotting versus in matlab so that we can

extract maximum efficiency of the transistor by deciding value of for

the maximum value of coming to be 130 mV .

 Single transistor simulation with ideal current source (Ids) equal to 3 mA
and forcing Vds=0.55V.
transistor width (w) value can be find out by sweeping w and will give
corresponding Vgs.
The Design parameter of cascode transistor M2 and M1 are same i.e.


1 2

CIRCUIT LOAD DESIGN (L1 AND C1)

1
We know 0 = 2 2.49 =
1 (1 + )

Let = therefore + = .
And for = 4.088nH (Effective inductance value from Asitic)
1 + = 999 fF and = .
While in simulation 1 is tuned to value 989fF as there is other effective
capacitances also at the output node which has not been considered while
calculation.
 , AND VALUE DESIGN
For 50 ohm input matching,
2
1 1 1
= 50 = + + + || +
+
Hence in resonance
2


+
Here is the effective capacitance between gate and source of the transistor

M1.
Considering = 50, = 25 /, = 1.5, = 650 will

result in 49.74ohms.
Values of external and modeled value of are little bit tuned to get the
the desired results as there so many parasitics acting at each node like at
the gate node will reduce the effective cap.
Knowing the above values value of Lg can be calculated for the corresponding
value of Cs.
Waveforms of the Specification
Achieved
1. Gain Bandwidth
2. Input Matching
3. P1 dB

4. Noise Figure
5. S11

6.IIP3