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SethJai Parkash Mukandlal


JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:1

B. Tech. 4th Semester


Digital Electronics Lab
(ECE 210E)

List of Experiments
1. Familiarization with Digital Trainer Kit and associated equipment.
2. Study of TTL gates AND, OR, NOT, NAND, NOR, EX-OR, EX-NOR.
3. Design and realize a given function using K-Maps and verify its performance.
4. To verify the operation of Multiplexer and Demultiplexer.
5. To verify the operation of Comparator.
6. To verify the truth table of S-R, J-K, T, D Flip-flops.
7. To verify the operation of Bi-directional shift register.
8. To design and verify the operation of 3-bit asynchronous counter
9 To design and verify the operation of synchronous UP/DOWN counter using J-K
flip flop.
10. To design and verify the operation of asynchronous Decade counter.
11. Study of TTL logic family characteristics.
12. Study of Encoder and Decoder.
13. Study of BCD to 7 segment Decoder.
Additional Practicals:-
1. To study Binary to Gray Code converter.
2. To verify the truth table of Half Adder.
3. To verify the truth table of Full subtractor
4 To design and verify the operation of Johnson counter.
Note: At least 7 experiments are to be performed from the above list of 13 practicals and
remaining 3can be set from the list of additional practicals.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:2

EXPERIMENT NO. 1

AIM:- Familiarization with Digital Trainer Kit and associated equipment.

APPARATUS:- Digital Trainer Kit.

THEORY:-
Tbe system combines simple, easy to use, ICs for gates, arithmatic operations flip flops,
power supply, input and output states with a versatile solderless bread board.

FEATURES
The Logic computer consists of the following built-in-parts:-

1. DC power suppy with indicator.


a) iutput voltage Fixed 5v+ 1%.
b) Output current 0.1 Amp
c) Load Regulation 50 mv.
d) Line Regulation 50 mv
e) Ripple 25 mv.
2. Clock Input Device Clock pulse of 1 second.
3. 10 Logic Switches; Hi/LO. Input voltage of Hi Level 4.75-5.25v
Input voltage of Lo level = Ov.
4. 10 LED output Indicator Maximum input voItageless than or
equal to 5v DC.
5. Solderless Bread board Bread board having one main strip, total inter
connected 640 tie points for lCs and two half
340 tie main strip, total inter connect points in
each half main strip. One half strips used for
power supply, clock input and output states
second half strips used for input states. Each
strip having length 173 mm and accepting Dia
0.56mm/22-26 5W 4Recommended.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:3

6. Mains on/off switch and LED indicator. A common anode seven segment display is also
provided on the right side of the logic computer. The device is operative on 230 v + 10% at 50
Hz AC only.

STANDARD ACCESSORIES
The following integrated circuits & patchcords are supplied with the logic
computer.

1. 7400 :- Quad 2 input NAND gate


2. 7402 :- Quad 2 input NOR gate.
3. 7404 :-Hex invertor
4. 7408 :- Quad 2 input AND gate
5. 7411 :-Triple- 3 input AND gates
6. 7420 :-4 input NAND gate.
7. 7427 :-Triple.3 Input NOR gates.
8. 7430 :- 8 - input NAND gate.
9. 7432 :-Quad 2 inputs OR gate-
10. 7442 :- BCD to decimal decoder.
11. 7447 :- BCD to 7 segment decoder.
12. 7472 :- AND- Gates JK flip-flop.
13. 7474 :- Dual D type flip flops
14. 7476 :- Dual J-K flip flops (2pcs)
15. 7486 :- Quad exclusive - OR gate.
16. 7490 :- Decade counter.
17. 7495 :- Shift register.
18. 74153 :- 1to 4 line Demultiplexer.
19. 74155 :- 4 to 1 line Multiplexer
20. 74193 :-Synchronous couritr

4 Colours of Single strand wire 5 mt. each suitable for Bread Board. 18 no. of Patchcords with 2
mm Plug on single side.

APPLICATIONS :-

1. Study of OR7 AND, NOT, NAND, NOR, EX-OR gates & Vertification of their truth tables.
2. \ierification of Boolean Identities & Demorgans theorem.
3. Study &Vedfication of truth tables of Digital Adders & Subtractors.
4. Study of flip flps and verification of their truth tables.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:4

5. Study of Counters& Shift registers and verification of their truth tables.


6. Study of Encoders & Decoders and verification of their truth tables.
7. Study of Multiplexers, Demultiplexers and verification of their truth tables.

PANEL DESCRIPTION :-

On the left side of the bread board, one second clock pulse by pulser switch is provided. ON-
OFF switch is provided on the top at the left side of bread -board. At the top of the breadboard
10 toggle switches as well as 10 sockets are provided for logic input. 10 sotkets for output are
provided at the bottom side of the bread board with 10 LED s on the right side of the bread
board One common anode seven segment display is provided with seven sockets below seven
segment display. A fixed 5v DC + 1% of 0.1 Amp. supply is terminated on the panel. These
terminating points of the supply are further connected to the bread board slots by using 24 SW9
wires.
The panel is provided with the bread board set. This bread board consists of two half
main strips and one full main strip (Approx. 173 mm long) The holes which are provided on the
bread board are vertically shorted.

RESULT:- Digital trainer kit has been studied.


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:5

EXPERIMENT NO. 2

AIM:- Study of TTL gates AND, OR, NOT, NAND, NOR, EX-OR, EX-NOR

APPARATUS:-Trainer kit ,IC (7432,7408,7404,7400,7402),Connecting wires, high /low


pulses Power supply

THEORY:- A gate is a circuit with one output and two or more input channels, an output
signal occurs only for certain combination of input signals.
The gate act as an ON /OFF switch . ON means high and OFF means low in Digital electronics.

Symbol and truth table:-


OR Gate:-IC 7432

BOOLEAN EXPRESSION:- Y=A+B

A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:6

AND gate:- IC 7408

BOOLEAN EXPRESSION:- Y=A*B

A B Y
0 0 0
0 1 0
1 0 0
1 1 1

NOT GATE:- IC 7404

BOOLEAN EXPRESSION:-Y=A
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:7

A Y
0 1
1 0

NAND GATE:- IC 7400

BOOLEAN EXPRESSION:- Y=A*B

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

NOR GATE:- IC 7402

BOOLEAN EXPRESSION:- Y=A+B


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:8

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

EX-OR GATE:- IC 7486

BOOLEAN EXPRESSION:- Y=AB+AB

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

EX-NOR gate:- IC 7486,IC 7404


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:9

BOOLEAN EXPRESSION:- Y=AB+AB

A B Y
0 0 1
0 1 0
1 0 0
1 1 1

PROCEDURE:-
1.Give input signal (low/ high) to logic gate inputs pins and observe (high or low)
indicator.
2.verified the truth table for various combinations.

PRECAUTIONS:-
1. The connections should be tight.
2. The pins of IC should not be shorted
3. Circuit should be check by prescribed authority.

RESULT:- The truth table for various gates is verified.


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:10

EXPERIMENT NO. 3

AIM:- Design and realize a given function using K-Maps and verify its performance.

APPARATUS :- NAND gate IC, Connecting wires.


__ _ _ __
EQUATION FORMED:- f(A,B,C,D)=ABCD + BC + BD + AD + AB

K-MAP & LOGIC DIAGRAM FORMED


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:11

CIRCUIT DIAGRAM:-

THEORY: -The k-map of equation is shown in fig. The equation is minimized in the
following steps:
1. Encircl 1 in cell 14 which cant be combined with any other 1.The term
corresponding to this is ABCD.
2. There are at least two possible ways for every 1 forming groups of two adjacent ones.
therefore we ignore it for the time being & go to next step.
3 There is only one possible group of 4 adjacent ones involving each of the cell 8,11,5 or 7 &
2.these are(8,9,0,1) , (11,9,1,3) ,(5,7,3,1) & (2,3,1,0) resp. encircle these groups. The
terms corresponding to these groups are B C, B D,A D & A B resp.
since all the ones have been encircled therefore the minimized equation is :
_ __ _ _ __
f(A,B,C,D)=ABCD + BC + BD + AD + AB

Procedure:-

1. Connect the circuit according to circuit diagram


2. Verify the result by making various combinations of logic 0 and logic 1.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:12

PRECAUTION:
1 The connections should be tight.
2 The pins of IC should not be shorted
3 Circuit should be check by prescribed authority.

RESULT:- The minimized equation is verified with the help of logic gates.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:13

EXPERIMENT NO. 4(A)

AIM:- To verify the operation of Multiplexer

APPARATUS:- IC-74153,Connecting wires , high/low pulses , power supply ,LED.

CIRCUIT DIAGRAM:-

TRUTH TABLE :-

Select I/P
S.No. Strobe S1 S1 Output
Go Y
1. 0 0 0 A1
2. 0 0 1 B1
3. 0 1 0 C1
4. 0 1 1 D1
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:14

THEORY :- Multiplexer means many into one i.e. multiplexer is a logic circuit which has
many inputs but single output . A multiplexer accepts several data inputs but allow only one of
them at a time to get through to the output . The inputs and outputs are indicated by means of
broad allow to indicate that there may be one or more inputs. Depending upon the digital code
applied at the select inputs ,one out of the N data sources (D0,D1,---------Dn-1) is selected
and transmitted the single output channel . A 4 to 1 line multiplexer has four inputs but only
single output .

To perform 4 to 1 line multiplexer experiment . We have used IC 74153 .It has 4 line inputs
(A1,B1,C1,D1) and only one outputs Y1.Go is the strobe input (active low )S0 and S1 are select
input lines ,select one out of four inputs at output for e.g. S0,S1 =00 then A1 will be selected .

PROCEDURE :-
1. Connect circuit according to S.No. 1 of truth table .
2. Connect output of the circuit to output indicator. .
3. Switch on the instrument by using ON/OFF switch provided on the front panel
4. Verify the truth table for other sets of input and observe the output indicator , compare
that output with truth table .

PRECAUTIONS:-
1 The connections should be tight.
2 The pins of IC should not be shorted
3 Circuit should be check by prescribed authority.

RESULT :- The truth table for multiplexer is verified


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:15

EXPERIMENT NO. 4(B)

AIM:- To verify the operation of Demultiplexer

APPARATUS:- IC-74155, Connecting wires , high/low pulses ,power supply ,LED.

CIRCUIT DIAGRAM:-

IC
-
74
15
5

TRUTH TABLE:-

Select I/P
S.No. Strobe S0 S1 Output
Ga Y
1. 0 0 0 Y0
2. 0 0 1 Y1
3. 0 1 0 Y2
4. 0 1 1 Y3
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:16

THEORY:- Demultiplexer means One into many i.e. demultiplexer is a logic circuit which has
single input but many output . It accepts a single I/P and distribute it over several outputs. The
block diagram of a demultiplexer is shown in circuit diagram . The select I/P code determines to
which O/P the data I/P will be transmitted .A 1 to 4 line demultiplexer has 1 input & 4 outputs.
To perform 1 to 4 demultiplexer experiment . We used IC 74155.It has 2 data select line inputs
(S0 & S1) and strobe input Ga (active low).

PROCEDURE:-

1. Connect the circuit according to S.N. 1 of truth table given above .


2. Switch on the instrument by using ON/OFF switch provided on the front panel.
3. Apply data inputs at data inputs Da & also connect Ga to O level .
4. Verify the truth table for other sets of input and compare that output with truth table

PRECAUTIONS:-
1 The connections should be tight.
2 The pins of IC should not be shorted
3 Circuit Should be check by prescribed authority.

RESULT:- The truth table of demultiplexer is verified.


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:17

EXPERIMENT NO. 5

AIM:- To verify the operation of Comparator.

APPARATUS:-IC 7485, Connecting wires, Ex-NOR gate, Digital trainer kit

CIRCUIT DIAGRAM:-
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:18

THEORY:- Four bit comparators are available in msi (7485) which can compare straight
binary and natural bcd codes . These ics can be cascaded to compare words of greater lengths
of without external gates . The a > b , a = b and a< b outputs of a stage handling less significant
bit are connected to the corresponding a > b, a < b and a = b cascading inputs of the the next
stage handling more significant bits . The stage handling the least significent bits must have a = b
input connected to logic 1 level and a > b and a < b inputs connected to logic 0 and 1 level.

Figures shows the block diagram of n-bit comparator .it receives two n-bit numbers a and b as
inputs and out puts and a > b , a < b , a =b , depending upon the relative magnitude of two
numbers , one of out put will be high .

INPUT

A1 AO B1 BO
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:19

OUTPUTS

A>B A<B A=B


0 1 0
0 0 1
0 0 1
0 0 1
1 0 0
0 1 0
0 0 1
0 0 1
1 0 0
1 0 0
0 1 0
0 0 1
1 0 0
1 0 0
1 0 0
0 1 0

PROCEDURE:-
1. Connect the input to the circuit as per the Pin out diagram.
2. Consequently apply the input.
3. Check the output according to the table given.

PRECAUTIONS :-

1 The connections should be tight.


2 The pins of IC should not be shorted
3 Circuit Should be check by prescribed authority.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:20

RESULT :- The truth table of comparator is verified .


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:21

EXPERIMENT NO. 6

AIM:- To verify the truth table of S-R, J-K, T, D Flip-flops.


APPARATUS:- NAND gate, Low / High Pulse, clock, connecting wires.

TRUTH TABLE (SR Flip-Flop)

Input Output
Sn Rn Qn+1
0 0 Qn

1 0 1
0 1 0
1 1 Uncertain

THEORY: - The circuit responds to the inputs S and R only when the clock is preset two
terminal are designed as set and reset because S=1 brings circuit n set state and R=1 brings the
circuit in reset state. Or clear state.
If S=R=1 both outputs q and complement of q will try to become 1 which is not allowed and
therefore this input condition is prohibited.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:22

CIRCUIT DIAGRAM:-

TRUTH TABLE (J K Flip-Flop)

input input output


jn kn Qn+1
0 0 qn
0 1 0
1 0 1
1 1 Complement qn

THEORY :- The uncertainty in the state of an S-R flip flop .when Sn = Rn = 1 can be
eliminated by converting it into a J-K which are ANDED with coplement q and q respectively to
S and R inputs i.e.
S = J. complement Q
R= k.q
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:23

CIRCUIT DIAGRAM:-

TRUTH TABLE (D FLIP FLOP)

Input (D) Output


0 0
1 1

THEORY:- The idle two rows of the truth table S-R or J-K flip flop .we obtain a D type Flip
Flop .It has only one input referred to as D-input or data input. The transfer of data from the
input to the output is delayed and hence the name delay flip-flop.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:24

CIRCUIT DIAGRAM:-

TRUTH TABLE (T FLIPS FLOP)

Input (t) Output


0 qn
1 Complement
qn

THEORY :- In a J-K flip flop , if J = K , the resulting flip flop is referred to as a T-flip flop .It
has only one input, referred to as T flip flop. Its acts as a toggle switch .for every clock pulse, the
output q changes.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:25

CIRCUIT DIAGRAM:-

PROCEDURE:-
1. Connect the S, R (J, K / T / D) input to logic input switches.
2. Connect Clock terminals.
3. Connect Q & complement terminals to output indicators.
4. Verify the truth table for other sets of input and observe the output indicators .Compare
that output with truth table.

PRECAUTIONS:-
1 The connections should be tight.
2 The pins of IC should not be shorted
3 Circuit should be check by prescribed authority.

RESULT:- The truth table of S - R ,J- K , D and T flip flop are verifed.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:26

EXPERIMENT NO. 7

AIM:- To verify the operation of Bi-directional shift register..

APPARATUS:- IC 7495, Connecting wires, High and low pulses, power supply.

THEORY:-A bi-directional shift register is one in which data can be shifted to the right or
left. Therefore register is capable of performing binary multiplication and division. A bi-
directional shift register can be implemented. By using gates which enables the transfer of data
bit fro one flip flop to another to right or to left. A high on direction control input enable data to
be shifted to the right while a low input allows data to be shifted left. When a high is applied to
the right/left. When a high is applied to right/ left control, gates g1 through g4 are enabled and
the logic state at the q output of each flip flop is passed to input of next flip flop. Data are shifted
one place to right when the negative edge of clock occurs. When a low is applied to the right?
Left control, gates gs through g8 are enabled and logic state of q output of each flip-flop located
at immediate left. The data are effectively shifted one place to the left at the negative edge of
clock..
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:27

CIRCUIT DIAGRAM:-

FOR RIGHT SHIFT REGISTER:-


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:28

TRUTH TABLE:-

PROCEDURE:-
1. Connect both pins SO & S1 to logic input 1.
2. Connect. the four output to four logic output indicators through patch chords.
3. Switch ON the instrument using ON/OFF toggle switch provided on the front panel.
4. Apply logic 0 at clear pin to reset the outputs to 0. Now apply logic 1at clear input.
5. Apply logic 0 or 1 at SR & SL inputs as shown in Table No. (1).
6. Apply one clock pulses by pressing pulsar switches once & obserye that all the outputs are set
at logic level 1.
7. Apply logic O at SI and SR input as shown in TableNo. (1) to shift the DATA towards right
Side.
8. Apply tour clock pulses and observe the Right Shift operation. Compare the results as
shownin Table No. (1).

FOR LEFT SHIFT OPERATION:-


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:29

TRUTH TABLE:-

PROCEDURE:-

Connect the inputs & outputs according to Table No.(2) & verify the different combinations.
Similarly we can also verify the different combinations as given in Table NO. (3) & (4).

PRECAUTIONS :-
1 The connections should be tight.
2 The pins of IC should not be shorted
3 Circuit should be check by prescribed authority.

RESULT:- The operation of bi direction shift register is verified.


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:30

EXPERIMENT NO. 8

AIM:- . To design and verify the operation of asynchronous counter.


APPARATUS:- Counter kit, Connecting Wires,

THEORY:- Each flip-flop is triggered by the previous flip-flop that is why it is also called as a
serial counter For the 4 bit ripple counter we have used two 7476 ICs each comprise of two flip-
flop For up counting counter counts the no of clock transition up to maximum of 15. Clock
pulses are applied at the clock input of first flip-flop & output of first flip-flop QA is used to
drive flip-flop B & QB is used to drive flip-flop C and so on The counter begins at count 0000
& advances one count for each clock transition until it reaches count 1111. At this point it resets
back to 0000 & begins the count cycle all over again.For down counting, clock pulses are applied
at the clock input of first flip flop & compliment of A is used to drive flip-flop B & QB is used to
drive flip flop C &so on. The counter begins at countllll & counter contents are reduced by 1
count with each clock transition until it counts 0000. At this point it resets back to 1111 &
begins the counts cycle all over again.

CIRCUIT DIAGRAM:-

Forward Counter
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:31

TRUTH TABLE:-

PROCEDURE:-

Forward Counter:
1.Connect the circuit as shown in Fig. (1) through patchcords i.e. connect clock output to ck
(clock pulse) input of first flip flop, connect Q output of first flip flop to ck input of second flip
flop, Q output of second flip flop to ck input of third flip flop, Q output of third flip flop to ck
input of fourth flip flop as shown in Fig. (1). Also connect au the four Q outputs to output
indicators. Connect reset (R) points of all the flip flops together.
2. Keep all the J&K inputs open as in open condition they assume the state to be 1.
3. Switch ON the instrument using ON/OFF
- toggle switch provided on the front panel.
4. To reset the outputs (Q) of flip-flops connect the reset pins (R) to ground point (logic 0) once.
Check the status of output indicators, they should show 0000 level.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:32

5. For Forward counting, open the reset inputs (or apply logic input 1) and Apply clock pulses
one by one using pulse switch. Note down all the four outputs at thc application of each pulse &
verify the Truth Table No.

CIRCUIT DIAGRAM:-

TRUTH TABLE:-
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:33

PROCEDURE:-

Reverse Counter:
1.Connect the circuit as shown in Fig.through patchcords i.e. connect clock output to ck input of
first flip flop connect Q output of first flip flop to ck input of second flip flop Q output of second
flip flop to ck input of third flip flop, Q output of third flip flop to ck input of fourth flip flop as
shown in Fig.. Also connect all the four 0 outputs to output indicators. Connect set (S) points of
all the flip flops together through patchcords.
2. Keep all the J & K inputs open, as in open condition they assume the state to be 1.
3. Switch ON the instrument using ON/OFF toggle switch provided on the front panel.
4. To set the outputs (0) of flip-flops connect the set pins (S) to ground point (logic 0) once.
Check the status of output indicators, they should show 1111 level.
5. For Down counting, open the et (S) inputs (or apply logic input 1) and apply clock pulses one
by one using pulse switch. Note down all the four outputs at the application of each pulse &
verify the truth Table.

PRECAUTIONS :-
1 The connections should be tight.
2 The pins of IC should not be shorted
3 Circuit should be check by prescribed authority.

RESULT:-The truth table of asynchronous counter is verified


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:34

EXPERIMENT NO. 9

AIM:- . To design and verify the operation of synchronous UP/DOWN counter Using J-K flip
flop.
APPARATUS:- Counter kit, Connecting Wires,

THEORY:-The term Synchronous as applied to counter operation means that the counter is
clocked such that each flip flop in the counter is triggered at the same time. This is
accomplished by connecting the clock line to each stage of the counter .

CIRCUIT DIAGRAM:-
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:35

TRUTH TABLE:-

PROCEDURE:-

(a)Up Counter:
1.Connect 4logic inputs to A,B,C&D inputs Of IC74l93 through patchcords. Set the 4 logic
inputs to 0000.
2. For Up counting, connect output of clock pulse to UP input of the IC.
3. Connect 4 logic outputs (QA, QB, QC, QD) to output indicators.
4. Switch ON the instrument using ON/OFF toggle switch provided on the front panel.
5. To reset the output on 0000, press clear switch (SWI) once.
6. Apply clock pulses one by one-using pulse switch. Note down all the-four outputs at the
application of each pulse & verify the Truth Table .

(b) Down Counter:


7. For Down counting, connect output of clock pulse to DN (Down) input of the IC.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:36

8. Apply clock pulses one by one using pulse switch. Note down all the four outputs at the
application of each pulse & verify the truth Table .

PRECAUTIONS :-
1 The connections should be tight.
2 The pins of IC should not be shorted
3 Circuit should be check by prescribed authority.

RESULT:-The truth table of synchronous UP/DOWN counter is verified


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:37

EXPERIMENT NO. 10

AIM:- . To design and verify the operation of asynchronous Decade counter.


APPARATUS:- IC 7420,IC 7476, Connecting Wires, Power supply

CIRCUIT DIAGRAM:-
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:38

TRUTH TABLE:-

Output

Input
QD QC QB QA

0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 0 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0

THEORY:-A 4 bit ripple counter counts up to 15 & then resets to 0But it can be made to
used at any clock pulse .For this purpose ,we operate the used connection automatically using 4
input NAND GATE As you know that out put of 0 NAND GATE is low if and only if all the
inputs are high .Suppose we want to convert 4bit forward counter .For decade counter it is
required that counter should count up to 9 & then resets to zero at tenth clock pulse So we
choose Q output of 2nd 7& 4th flip-flop & Q out put of 1st &3rd flip-flop for the inputs of 4 input
NAND Gate .Also connect output of NAND Gate to common reset of all the flip-flops .As you
can program the counter for any number of pulses.

PROCEDURE:-
1. Connect the circuit as shown in figure.
2. Switch on the instrument using on-off toggle switch provided on front-panel.
3. Press push to off reset switch once to reset the output at logic 0000.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:39

4. Apply Clock-pulse one by one-using pulses switch. Note down the states of all the four
output at each applying pulses and compare the results with truth table.

PRECAUTIONS: -
1. The connections should be tight.
2. The pins of IC should not be shorted
3. Circuit Should be check by prescribed authority.

RESULT:- The truth table of decade counter is verified.


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:40

EXPERIMENT NO. 11

AIM:- . . Study of TTL logic family characteristics

APPARATUS:- Resistors+4K,1.6K,130,1Kdiode,transistor Connecting Wires, Power


supply,C.R.O.

THEORY:- It is the fastest of the saturated logic families. The basic TTL logic circuit is the
NAND gate. Good speed, low manufacturing cost, wide range of circuits, and the availability in
SSI and MSI are its merits. Tight Vcc tolerance, relatively high power consumption, moderate
packing density, generation of noise spikes and susceptibility to power transients are its demerits.
In the circuit of the two-input TIL NAND gate shown in Figure, the input transistor Q1 is a
multiple emitter transistor. Transistor Q2 is called the phase splitter. Transistor Q3 sits above
Q4and, therefore, Q3 and Q4 make a totem pole arrangement. Diodes D1 and D2 protect Q1 from
being damaged by the negative spikes of voltages at the inputs. When negative spikes appear at
the input terminals, the diodes conduct and bypass the spikes to ground. Diode D ensures that Q3
and Q4 do not conduct simultaneously. Transistor Q3 acts as an emitter follower.
When both the inputs A and B are HIGH (+5 V), both the base-emitter junctions of Q1 are
reverse biased. So, no current flows to the emitters of Q1. However, the collector-base junction
of Q1 is forward biased. So, a current flows through R1 to the base of Q2, and Q2 turns on.
Current from Q2s emitter flows into the base of Q4. So, Q4 is turned on. The collector current of
Q2 flows through R2 and, so, produces a drop across it thereby reducing the voltage at the
collector of Q2. Therefore, Q3 is OFF. Since Q4 is ON, V0 is at its low level (VCE(sat)). So, the
output is a logic 0, When either A or B or both are LOW, the corresponding base-emitter
junction(s) is (are) forward biased and the collector-base junction of Q1 is reverse biased. So, the
current flows to ground through the emitters of Q1. Therefore, the base of Q1 is at 0.7 V, which
cannot forward bias the base -emitter junction of Q2. So, Q2 is OFF With Q2 OFF, Q4 does not
get the required base drive. So,Q4 is also OFF. Transistor Q3 gets enough base drive because Q2
is OFF, i.e. since no current flows into the collector of Q2, all the current flows into the base of
Q3, and therefore, Q3 is ON. The output voltage, V0 =Vcc -VR2 VBE3-VD~ 3.4 to 3.8 V, which is
a logic HIGH level. So, the cicuit acts as a two-input NAND gate. When Q4 is OFF, no current
flows through it, but the stray and output capacitances between the output terminal, i.e. the
collector of Q4, and ground get charged to this voltage of 3.4 to 3.8 V. The I/O characteristics of
a TTL NAND gate are shown in graph.

CIRCUIT DIAGRAM:-
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:41

GRAPH:-

PROCEDURE:-
1. Connect the circuit according to circuit diagram
2. Draw input-output characteristics.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:42

PRECAUTION:
1 The connections should be tight.
2 The pins of IC should not be shorted
3 Circuit should be check by prescribed authority.

RESULT:-TTL logic family has been studied..


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:43

EXPERIMENT NO. 12

AIM:- Study of Encoder and Decoder.

APPARATUS:- Encoder, Decoder kit , Connecting Wires

THEORY:- This type of encoder performs the same basic function of encoding the decimal
digits into 4 bit BCD outputs,as that performed by a normal decimal-to-BCD encoder.It ,however
,offers the additional facility of providing priority.That is, it produces a BCD output
corresponding to the highest order decimal digit appearing on the inputs and ignores all others.
Now,let us look at the requirements for the priority detection logic.The purpose of
this logic circuitry is to prevent a lower-order digit input from disrupting the encoding of a
higher-order digit.

CIRCUIT DIAGRAM:-
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:44

PROCEDURE:-

1. Connect nine logic inputs of IC 74147 to logic inputs 0 & 1 through


patchcords.
2. Connect four logic outputs to output indicators through patchcords.
3. Switch ON the instrument using ON/ OFF toggle switch provided on
the front paneL
4. Verify the Observation Table No. (1).

BCD to decimal decoder:-

Theory:- The BCD to decimal decoder is also called a 4-line to 10-line or 4 to 10


decoder or 1 of 10 decoder.It has 4 input lines(A,B,C,D)and 10 output lines.Only
one output line is active at time.6 of the 16 combinations are invalid and for input
combinations that are invalid for BCD none of the outputs will be activated.The
inputs and outputs can be active high or active low.IC 7442 is a BCD to decimal
decoder with active low inputs and outputs.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:45

CIRCUIT DIAGRAM:-

OBSERVATION TABLE:-
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:46

PROCEDURE:-
1. Connect four loqic inputs (A, B, C & D) of BCD to Decimal Decoder to logic inputs 0
& 1 through patchcords.
2 Connect ten logic outputs of the convertor to ten logic output nd;cators through
patchcords
3. Switch ON the instrument using ON/OFF toggle switch provided on front panel
4 Verify the Observation Table .

PRECAUTIONS :-
1 The connections should be tight.
2 The pins of IC should not be shorted
3 Circuit should be check by prescribed authority.

RESULT:- The truth table of encoder and decoder is verified.


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:47

EXPERIMENT NO. 13

AIM:- Study of BCD to 7-segment decoder

APPARATUS:- IC-7447,7 segment, connecting wires power supply, connecting wires,


high/low pulses.

CIRCUIT DIAGRAM: -

TRUTH TABLE:-
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:48

THEORY:- A BCD to 7 segment decoder circuit 7447 is a special form of decoder circuit that
accept the standard 8421 BCD input code and generate a special 7 bit output code that is used to
operate a 7 segment readout. The output transition in 7447 can stand up to 15V.It can link
enough current to drive common anode type LED-7 segment displays. In addition to BCD inputs
and 7 outputs for driving segments the IC have o lamp test input a blanking input/ripple blanking
output and a ripple blanking input.

PROCEDURE:-
1. Connect the circuit as shown in figure.
2. Switch on the instrument using on/off toggle switch provided on front panel. The 7-
segment display shows any arbitrary fig.
3. Connect lamp test (LT) of IC 7447 to ground. All LED segments should light up showing
fig 8.
4. Make lamp test input high. Apply clock pulses one by one and see that the fig displayed
by the LED repeat sequentially from 0 through 9.
5. Apply clock pulses till fig zero is displayed. Now connect input marked RBI to ground.
The display should disappear.
6. With pin 5 connected to ground, apply clock pulses and confirm that all figures except 0
are displayed sequentially.

PRECAUTIONS :-
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:49

1 The connections should be tight.


2 The pins of IC should not be shorted
3 Circuit should be check by prescribed authority.

RESULT:-The truth table of BCD to 7 segment is verified


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:50

EXPERIMENT NO. 1

AIM:-To study binary to gray code converter.

APPARATUS:- IC 7486,Digital bread board,Connecting wires.

THEORY:- The input to the 4-bit binary to gray code converter circuit is a 4 bit binary and
the output is a 4-bit Gray code.There are 16 possible combinations of 4-bit binary input and all
of them are valid.Hence no dont cares.The 4-bit binary and the corresponding Gray code are
shown in the table.

CIRCUIT DIAGRAM:-

TRUTH TABLE:-
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:51

PROCEDURE:-
3. Connect the circuit according to circuit diagram
4. Verify the result by using truth table.

PRECAUTION:
1 The connections should be tight.
2 The pins of IC should not be shorted
3 Circuit should be check by prescribed authority.

RESULT:- The truth table of binary to gray code has been verified.
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:52

EXPERIMENT NO. 2

AIM:- To verify the truth table of Half Adder..

APPARATUS:-IC 7486,7408, Connecting wires Digital trainer kit

THEORY:- The half adder is a combinational circuit which adds two binary numbers and
produces a sum and carry bit as output. If A and B are the input bits, then sum bit (S) is the X-
OR of A and B and the carry bit (C) will be the AND of A and B. Half adder is the simplest of
all adder circuit, but it has a major disadvantage. The half adder can add only two input bits (A
and B) and cannot add if there is a carry into the input.

CIRCUIT DIAGRAM:-

TRUTH TABLE:-
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:53

PROCEDURE:-
1.Give input signal (low/ high) to logic gate inputs pins and observe (high or low)
indicator.
2.verified the truth table for various combinations.

PRECAUTIONS:-

1. The connections should be tight.


2. The pins of IC should not be shorted
3. Circuit should be check by prescribed authority.

RESULT:- The truth table of Half Adder is verified


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:54

EXPERIMENT NO. 3

AIM:- To verify the truth table of Full Subtractor...

APPARATUS:-IC 7486,7408,7432,7404, Connecting wires Digital trainer kit

THEORY:- A combinational circuit which performs the subtraction of three input bits is
called full subtractor. The three input bits include two significant bits and a previous borrow bit.
A full subtractor circuit can be implemented with two half subtractors and one OR gate.

CIRCUIT DIAGRAM:-
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:55

TRUTH TABLE:-

PROCEDURE:-
1.Give input signal (low/ high) to logic gate inputs pins and observe (high or low)
indicator.
2.verified the truth table for various combinations.

PRECAUTIONS:-

1. The connections should be tight.


2. The pins of IC should not be shorted
3. Circuit should be check by prescribed authority.

RESULT:- The truth table of Full Subtractor is verified


Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:56

EXPERIMENT NO. 4

AIM:- To design and verify the operation of Johnson counter

APPARATUS:-Counter Kit, Connecting wires

THEORY:- Johnson counter is a modified ring counter in which the output from the last flip
flop is inverted and fed back as an input to the first. It is also called as Inverse Feedback Counter
or Twisted Ring Counter.

CIRCUIT DIAGRAM:-
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:57

TRUTH TABLE:-

PROCEDURE:-
1. Connect the circuit as shown in Fig through patchchords (a) connect clock input of all the flip
flops together and connect it to clock output (1Hz). (b) Connect J input of 1st flip-flop to Q
output of the 4th flip flop and K input of the 1st flip- flop to Q output of the 4th flip - flop. (C)
Connect J input of 2nd,3rd, 4th flip -flop to Q output of 1st, 2nd, 3rd flip - flop and Connect K
input of the 2nd, 3rd, 4th flip- flop to Q output of the 1st, 2nc3rd flip - flop. (d) Connect reset
pins of all the flip flops together as shown in Fig. . Connect 4 logic output indicators to 4 Q
outputs.
2. Switch ON the instrument using ON/OFF toggle switch provided on the front panel.
3. To reset the output connect reset pins to logic o (Ground) once. After that this pin will
remain open.
4. Apply clock pulses one by one using pulser switch. Note down all the four outputs at the
application of each pulse & verify the Truth Table .
5. Short all the Set & Reset sockets & connect it from Logic High i e (5V DC).

PRECAUTION:-

1 The connections should be tight.


2 The pins of IC should not be shorted
Doc:
SethJai Parkash Mukandlal
JMIT/ECE/ECE-
Institute of Technology,Radaur 210E

DIGITAL ELECTRONICS LAB Page:58

3 Circuit should be check by prescribed authority.

RESULT:-The truth table of Johnson counter is verified

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