CERTIFICATE

This is to certify that the project report entitled An Effcient Multiplication Algorithm
Using Nikhiloam Method which is being submitted by Sakti Prasanna Swain bearing
the University Regn. No.01507100106, towards the partial fulfillment of the
requirement for the award of the degree of Master of Technology in Microelectronics
Engineering (with specialization in VLSI and Embedded Systems Design) of the Biju
Patnaik University of Technology, Orissa, is a record of bonafide work carried out by the
above mentioned student.

In my opinion the report has fulfilled this partial requirement according to the Academic
Regulation of the University and be considered for award of the degree.

Further, it is certified that the matter embodied in this thesis has not been submitted to
any other University/ Institute for the award of any Degree/ Diploma.

DirectorSupervisor

Centre For Advanced PG Studies Mrs Subhashree Samal

BPUT,ODISHA Lecturer,Dept of Electronics & Telecom,

Centre For Advanced PG Studies

BPUT,ODISHA
 ACKNOWLEDGEMENT

I begin by expressing my deep sense of gratitude towards my supervisor

Mrs.Subhashree Samal whose constant support and guidance has helped me to
complete my thesis. She has taught me the importance of self-learning and the need to
keep abreast with emerging technologies.

I also express my sincere thanks to Mr. Priyanka Karmakar for giving me valuable
inputs during the initial part of my work.

I thank all those authors whose papers and articles I have gone through during
my entire thesis work. Due credit has been given for the figures and data used in
this thesis. Any omission, if any, is inadvertent and not deliberate.

I am grateful to all those friends who have given useful inputs and suggestions
during this work from time to time.

Sakti Prasanna Swain

 Abstract

Multiplication is one of the most important operations in computer arithmetic.

Many integer operations such as squaring, division and computing reciprocal
require same order of time as multiplication whereas some other operations
such as computing GCD and residue operation require at most of factor of log n
time more than multiplication. We propose an integer multiplication algorithm
using nikhilam method of Vedic mathematics which can be used to multiply two
binary numbers efficiently. Nikhilam is more useful for numbers close to base.
To comparison between Nikhilam and Uradhav Tiryakbhyam method. The
possibility of applying the Nikhilam Sutra of Vedic Mathematics
 Literature Review
In [1] the partial products were connected to minimize the activity for the the
generation of the power-efficient parallel multipliers and the reduction tree was
designed. Here using ModelSim the VHDL was simulated. The speed and
power of the parallel multipliers had always been the critical issues and
therefore the subject of the many many research projects was surveyed. Without
any noticeable area or speed overhead the comparison to a random reduction
tree was achieved by saving the energy. Here the resulting multipliers were
simulated and average number of transitions was reported by using ModelSim
for which the VHDL codes were generated automatically.

In [2] the low-power and high speed circuits were became more desirable due to
growing portable device markets and also became more applicable in
processors. Here in this paper the speed of 32 bit processor was improved. The
high speed, low power and minimum area adder architecture had been designed
by VLSI researchers and were resulted in large number of adder architectures.
To reduce the area and power of Carry Select Adder (CSLA) the design uses a
simple and efficient gate-level modification. Here the 16, 32, 64 bit Square-
Root Carry Select Adder (SQRT CSLA) architecture had been developed and
compared with the regular SQRT CSLA architecture. Using mentor graphics
tool suit and VHDL the entire adder architecture had been implemented and
simulated.

In [3] the Urdhva Triyagbhyam Vedic method for multiplication work had
proved the efficiency which strikes a difference in the actual process of
multiplication itself. By Xilinx Synthesis Tool on Spartan 3E kit the Verilog
HDL coding of Urdhva tiryakbhyam Sutra for 32x32 bits multiplication and
their FPGA implementation and the output had been displayed on LCD of
Spartan 3E kit. One of the key arithmetic operations in such applications was
multiplication and the development of fast multiplier circuit had been a subject
of interest over decades. Reducing the time delay and power consumption was
Very essential. A large propagation delay was associated with this case, due to
the importance of digital multipliers in DSP, it had always been an active area of
research and a number of interesting multiplication algorithms had been
reported in the literature. The designs of 32x32 bits Vedic multiplier had been
Implemented on Spartan XC3S500-5-FG320. The design was based on Vedic
method of multiplication
In [4] In CSLA, the 16, 32, 64 and 128-bit square-root Carry Select Adder
(SQRT CSLA) architectures had been developed and compared with the regular
SQRT CSLA architecture. The proposed design had reduced area and delay to a
great extent when compared with the regular SQRT CSLA. The sum for each
bit position in an elementary adder was generated sequentially only after the
previous bit position had been summed and a carry propagated into the next
position. The final sum and carry was selected by the multiplexers (mux), due to
the use of two independent RCA the area would increase which leads an
increase in delay. The Regular CSLA of 128-bits had been developed ripple
carry adders and multiplexers. An efficient approach was proposed in this paper
to reduce the area and delay of SQRT CSLA architecture. The reduction in the
number of gates was obtained by simply replacing the RCA with BEC in the
structure.

In [5] the basic operation of all computer arithmetic, adders was one of the
widely used components in digital integrated circuit design. Since propagation
of carry was of major concern in designing efficient adders, this paper presents
different fast adders and their performance analysis. All the adders discussed
Square root Carry Select Adder (SQCSA) provides a good compromise between
cost and performance. As, Conventional SQCSA is still area consuming due to
dual Ripple Carry Adder(RCA)structures, modifications was done at gate level
to reduce area. Micro processors speed of Operation constraints was difficult to
achieve so depending on application compromise between constraints had to be
made. In this paper three new architectures was presented for SQRT MCSA
(Modified Carry Select Adder). Comparisons were made between different
adders in terms of logic levels and delay.

In [6] many modifications over the standard algorithm had been made to
enhance the speed. Methods like Wallace tree, Booth algorithm and several
others techniques was being worked upon to increase Speed. Amongst this
Vedic multipliers based on Vedic sutras was under focus for being fastest and
low power multiplier. Low power multiplier design, hence development of high
speed low power multiple had been subject of focus over recent years in this
paper possibility of applying the Nikhilam sutra of Vedic Mathematics had been
explored. This sutra had an advantage of converting large digit multiplication to
corresponding small digit multiplication. This sutra was basically more effective
when both the multiplier and multiplicand are near to same base power.
In [7] the performance of high speed multiplier was designed and compared
using these sutras for various NxN bit multiplications and implemented on the
FFT of the DSP processor. Anurupye Vedic multiplier on FFT was made
efficient than Urdhva tiryabhyam. Multiply and Accumulate (MAC) was one of
the frequently used Computation- Intensive Arithmetic Functions (CIAF) that
was implemented in many Digital Signal Processing (DSP) applications. One of
the arithmetic operations in such application was multiplication and the
development of fast multiplier circuit. Urdhva tiryabhyam and Nikhilam
Navatashcaramam Dashatah sutras, multipliers were designed. Anurupye Vedic
multiplier on FFT was made efficient than Urdhva tiryabhyam and Nikhilam
Navatashcaramam Dashatah sutras by more reduction in computation time.

In [8] Thirty-two bit divider architecture was implemented using this sutra &
synthesized and simulated using Xilinx ISE simulator and implemented on
virtex4 FPGA device XC4VLX15. This architecture could be implemented in
many applications such as digital signal processing, cryptography, processor
arithmetic unit design etc. ALU unit had greatest importance. In design of
processor arithmetic units was always based on addition, subtraction, division
operations. Swami Bharati Krishna Tirthaji Maharaj sankaracharya of
govardhan peath was introduced Vedic mathematics to this world in the form of
16 sutras (formulae) which was very significant for calculations. Bharati
Krishna, who was himself a scholar of Sanskrit, Mathematics, History and
Philosophy, was able to reconstruct the mathematics of the Vedas. Divider was
one of the important hardware blocks which were applicable in most of
applications such as digital signal application, encryption, and decryption
algorithms in cryptography & also in various mathematical computations. It
was seen that the speed of the proposed divider was higher than that of the
restoring division method i.e. the delay had been drastically reduced. This
divider could be used in applications such as digital signal processing,
cryptography & processor ALU.

In [9] a new 4-bit adder was proposed which when used in multiplier, reduces
its delay. This multiplier could be used in applications such as digital signal
processing, encryption and decryption algorithms in cryptography, and in other
logical computations. This design is simulated using VHDL. This work, we
present multiplication operations based on Urdhva tiryabhyam in binary,
designed using a new proposed 4-bit adder and implemented in HDL language.
4 bit adder had been proposed in this paper and implemented in 4X4 multiplier
using Vedic sutras. It was seen that the speed of the proposed multiplier was
higher than that of normal array multiplier i.e. the delay had been drastically
reduced.
In [10] the multiplication of two large operands was reduced to the
multiplication of their compliments and addition. It was more efficient when the
magnitude of both operands were more than half of their maximum values.
These methods and ideas could be directly applied to arithmetic, trigonometry,
plain and spherical geometry, calculus, hydraulics and applied mathematics of
various kinds. They have tested and compared various multiplier
implementations such as Array multiplier, Multiplier macro, Vedic multiplier
with full partitioning, Vedic multiplier using 4-bit macro, fully Recursive Vedic
multiplier and Vedic multiplier using 8-bit macro for optimum speed. A new fast
multiplier architecture based on Vedic mathematics was presented in
Pushpangadan, Sukumaran, Innocent, Sasikumar, and Sundar (2009). They had
compared their both 8 8 and 16 16 architecture with the corresponding
Booth multiplier. A new high-speed Vedic multiplier had been proposed in this
article. The proposed design had been evaluated in terms of combinational path
delay and device utilisation. Results were compared with the state-of-the-art
Vedic multipliers and straightforward CSA multiplier.

In [11] thirty-two bit divider architecture was implemented using this sutra
&synthesized and simulated using Xilinx ISE simulator and implemented on
virtex4 FPGA device XC4VLX15. The output parameters such as propagation
delay and device utilization was calculated from synthesis results. ALU unit had
greatest importance. In design of processor arithmetic units were always based
on addition, subtraction, multiplication division operations. High speed Vedic
multiplier was used for design of the proposed squaring circuit. The key to our
success was that only one Vedic multiplier was used instead of four multipliers
reported in the literature. Vedic multiplier and reversible divider modules had
been written in Verilog HDL and then synthesized and simulated using Xilinx
ISE 9.2i. This literature presents a novel design & an algorithm to construct a
new high speed thirty two bit divider. It also discusses example to how the
method was implemented & which was evaluated in terms of the path delay &
device utilization. This divider could be used in applications such as digital
signal processing, cryptography & processor ALU design.
List of Figures

Fig 1. Dataflow 1 half adder

Fig 2. Data flow 2 1 half adder

Fig 3 schematic diagram 1 half adder

Fig4. Simulation of 1 half adder

Fig6. Dataflow 1 full adder

Fig6. Schematic of full adder

Fig7. Schematic and RTL of full adder

Fig8. Schematic of full adder

Fig9. Simulation of full adder

Fig10. Synthesis report of full adder

Fig11. Post map route synthesis

 INTRODUCTION

Vedic mathematics is ancient methodology of Indian mathematics which has

distinctive technique of arithmetic computation based on 16 Sutras.

Multiplier is essential component of computer system. The array multiplier

performs parallel multiplication. Array multiplier is the fast multiplication of
two numbers since the delay it takes, is the time for the signal to propagate
through the gates that form multiplication carry

.Karatsuba multiplication divide- and-conquer technique to multiply two n bits

integers in O (nlog3) bit operations. In this paper we use Nikhiliam Sutra or
method From Vedic mathematics also applying and compare two methods.
Nikhiliam Sutra Performs large multiplication along with some addition and
Shifting operations

In two method Nikhiliam sutra and vedic multiplier for binary number
multiplication and adding urdhva triyakbhyam method. It is also using on
karatasutra algorithm by muliplication . Nikhilam method is also applying also
square root of multiplication by binary digit numbers.
 (A) BINARY MULTIPLICATION

Nikhilam Sutra is one of the 16 sutras of Vedic mathematics It can be used to

convert large-digits multiplication to small-digits multiplication with the help of
few extra add,subtract and shift operations. In so cases

We can perform binary digit multiplication using Nikhilam sutra by converting

n-bit multiplication to (n - 1)-bit multiplication and some additional add/subtract
and shift operation. We can apply this conversion repeatedly until we get trivial
multiplicand/multiplier or 1-bit multiplication. We can also put some threshold
limit m where 1 < m < n up to which we would like to do this conversion2-bit
multiplication can be performed using single 1-bit multiplication.

Shortcut method of multiplication using vedic mathematics when numbers are

close to power of 10(10, 100, 1000).

1ST Method:-
Multiply those deficiencies or excesses
Do cross addition of numbers with deficiencies or exceses
2nd compartment always needs to have same number of digits as that of
zeroes of the selected base.
If less then pre append zeros. If more carry forward intial digits to ist
compartments.
This type of Nikhilam Sutra can be applied when numbers slightly *less
than power of 10(10, 100, 1000 etc).
Formula used : (x-a)(x-b )=x(x-a-b)+ab

2nd Method:-
Numbers slightly *less than power of 10(10, 100, 1000 etc).
Formula used : (x+a)(x+b )=x(x+a+b)+ab
nd
3 Method:-
Numbers closer to*present on either side of power 10(10,
100,1000,etc).This types of Nikhilam will require understanding of 2
vinculoum process.
(x+a)(x+b )=x(x+a-b)-ab
(x-a)(x+b )=x(x-a+b)-ab

For example if we have to multiply 11 * 11.Here multiplicand M = 11, and

multiplier N = 11. We can proceed as follows:
1. Compute A = 11 - 10; Subtract the multiplicand from nearest base2. Compute
B = 11-10; Subtract the multiplier from the
same base
3. Compute C = B * A = 1 * 1 = 1
4. Compute D = M + B = N + A = 11 + 1 = 100
Integer Base difference

Multiplicand 11 (11-10)=1

Multiplier 11 (11-10)=1

(11+1)=100 (1*1)=1

Result 1001

5. Result 10 * D + C = 1001Two digit multiplicationcan be performed using

only 1 one digit multiplication instead of 3 one-digit multiplication as required
by Karatsuba algorithmSuppose we have to perform same multiplication 95 *96
using this method. We can use the Nikhilam sutra as follows:

1. Compute A = 100-95; Subtract the multiplicand from

nearest base
2. Compute B = 100 -96; Subtract the multiplier from
the same base
3. Compute C = B * A = 5* 4 = 20
4. Compute D = 95- 4 = 96- 5 = 91
5. Result 100 * D + C = 9120

Integer Base difference

Multiplicand 95 (100-95)=5

Multiplier 96 (100-96)=4

(95-4)=91 (96-5)=91

Result 9120

(B) Uradhav Tiryakbhyam Sutra-

The ancient Indian Vedic mathematics sutra (formula) called Urdhva-
Tiryabhyam (Vertically and crosswise) which has traditionally used for decimal
system in ancient India. Some architecture based on Vedic mathematics based
on decomposition has proposed that was better than traditional multipliers.
Both for the multiplicand and multiplier and thereafter the algorithm of Vedic
Mathematics called Urdhva Tiryabhyam (Vertically and crosswise) is called to
give the efficient multiplier architecture and increase the speed of multiplication
and reduce the time delay. The advantage here is that parallelism reduces the
need of processors to operate at increasingly high clock frequencies. A higher
clock frequency will result in increased power of processor

Example

14*12

Step-1

Step-1

Step-1

3digit no multiplication 234*3166

Step-

4*6 =24:2, carried over digit is placed below the second digit
(3*6)+(4*1) = 18+4 =22;2, the carried over digit is placed below third
digit
(2*6)+(3*1)+(4*3) =12+3+12 =27;2, the carried over digit is paced
below fourth digit.
(2*1)+ (3*3) = 2+9= 11; 1, the carried over digit is placed below fifth
digit.
(2*3) =6
Respective digits are added

Design in Half Adder: for purpose 1 bit multiplication in gate level

Figure [1] data flow

Figure [2] data flow

Figure [3] schmatic diagram

Figure 5] simulation
Design in full Adder: 1bit multiplication gate level

Figure [6] datafloow

Figure [7] schematic

Figure [8] Rtl and schematic

Figure [9] datafloow

Figure [10] simulation and run

Figure [11] senthesis report

Figure [11] post map route senthesis report

Results and discussions:

We got that no of delays and no of input buffers and output buffers in time
calculated by simulation. We also found no of area *delay to specifies power
consumption Here in discuss about half adder and full adder in observe that the
gate delay 6.236 ns and net delay is 5.194 ns in half adder and 6.236 , where
is net delay is 5.194 ns so after we do 4 bit multiplier by using 4 bit adder
which connected in 4 full adder and sum =0 and cin =0. Then using Nikhilam
sutra by 1 bit square and 2 bit square and 3 bit square multiplication and
compare nikhilam method and Uradhav Tiryakbhyam method.

Conclusion:-

In this paper we have explored the possibility of applying the Nikhilam sutra of
Vedic mathematics to binary number multiplication. We can take advantage of
the fact that this sutra can convert large-digit multiplication to corresponding
small digit multiplication. Nikhilam method is particularly efficient when both
multiplicand and multiplier are near to some base (radix) power. Uradhav
Tiryakbhyam is same but is different method we get result same.

Future Scope:-

Nikhilam sutra can be extending this method to large digit multiplication and
exploit .its property to perform fast integer multiplications we conclude this
case area and delay power performance is better or not. It is more efficiency or
consumes power delay time by hardware Xilinx FPGA implementation showing
results.
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