VLSI Grader Information

LTSpice and Electric

This document is aimed at providing guidelines for experiments related to Back end VLSI. It
contains technology information used for grading and submission guidelines for Electric and
LTSpice. It also contains installation steps for Electric and LTSpice.
1 VLSI Grader Information

TECHNOLOGY INFORMATION

The grader supports the AMI Semiconductors C5 Process.

The supply voltage is 5 volts.

The lambda() for the process is 300nm and follows the MOSIS rules for layout. This is
also the technology scale.

The minimum Length(L) for the process is 600nm i.e 2 and minimum width(W ) is
3000nm i.e 10.

Possible values of L are multiples of between 2 and 500. Possible values of W are
multiples of and in between 10 and 10000.

The C5 technology models specifies the SPICE models required for simulation.

The transient analysis of the circuit is done only with an input of rise time and fall time
of 5ns and Ton of 50ns by the gradeME engine. This is the fastest time to which the
circuit can respond without the output getting invalid. Any time below 5ns, the output
is not considered valid. Hence, please make sure that whatever analysis is performed, is
done with a rise and fall time of 5ns.

FLOATING NODE LOAD CAPACITANCE

The minimum capacitance at the output (Cload ) which will act as input capacitance to another
circuit is calculated here. Transient Analysis of the circuit needs to be done in consideration
with that capacitive load 1 .

Consider the simplest circuit possible with the CMOS technology, i.e inverter with minimum
length and minimum width i.e L = 600nm; W = 3000nm

Cload = N M OSgate + P M OSgate

N M OSgate = CGSOn + CGDOn + W LCoxn
P M OSgate = CGSOp + CGDOp + W LCoxp
r o
Cox = ; r = 3.9 for SiO2 for both PMOS and NMOS.
Tox
Substituting values from the C5 models file, we have Cload 42.22f F .

This load can be approximated to 50f F at the output node. Including this capacitor at the
output node is required for proper transient analysis.

1
Kang. S.M, Leblebici. Y, CMOS Digital Integrated Circuits

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2 VLSI Grader Information

SUBMISSION GUIDELINES

GENERAL GUIDELINES

The grader expects a zip file in all submissions with specific file names.

Two main softwares are used for submissions:

Electric - Schematic and/or Layout - .jelib files

LTSpice - Schematic Only - .asc files

In case of Electric, the .jelib file along with the library name, cell name have to be of
the name specified in question. In case of Schematic the .asc file has to be of the name
specified in question. If these conditions are not met, an user error is raised.

If you have used any other jelib file as a dependency, for e.g.EX-OR would use inverter
which was previously made and used. When submitting, both the EX-OR and inverter
.jelib files have to be submitted otherwise grader will raise user error.

In case of transient analysis, a capacitor of the name load with value of 50f F is expected
at the output node . If it is not found, an user error is raised.

SUB-CIRCUITS

LTSpice

Each subcircuit has its own .asc and .asy(Symbol) file. Both the .asc and .asy need
to be submitted for grading along with the main .asc file which has imported the
symbols. The main .asc file needs to have the name specified in the question.
All the files are required to be zipped for submission.

Electric

Let us consider an example of a 1-bit half adder. It requires an EX-OR gate and an
AND gate.
The previously made jelib files(of EX-OR and AND) for creation of the 1-bit half
adder can be used. In this case, all the jelib files need to be in the same folder for
running.
You have to submit all the supporting jelib files for grading in a single zip file.

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3 VLSI Grader Information

INSTALLATION INSTRUCTIONS

LTSPICE

1. Download LTSpice from this link.

2. Start the installation by double clicking on the installer.

3. Preferably install 32 bit version of LTSpice.

4. Once installed, keep a note of the installation directory LTSpice.

Figure 1: LTSpice Installation

ELECTRIC

1. Download Electric JAR file from this link. Electric uses JAVA for running, hence update
your JAVA version from their official site.

2. Copy the downloaded electric-9.07.jar and paste it in a folder called Electric in C drive.

3. Double clicking on the downloaded jar file will open Electric.

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4 VLSI Grader Information

INCREASING JVM FOR ELECTRIC

1. Click on preferences under the File Tab in the main window.

2. Under General, select General in the tree view.

Figure 2: Electric JVM Increase

3. On the right side, under the Memory section, change the Maximum memory and Maximum
permanent space to 512 MB.

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5 VLSI Grader Information

LINKING LTPSICE WITH ELECTRIC

1. Under preferences in File Tab, select Tools and select Spice/CDL in tree view.

2. Make sure to change all the options as shown in the image.

3. In the Running Spice Section, Enter -i ${FILENAME} -r ${FILENAME NO EXT}.raw

-o ${FILENAME NO EXT}.out and the installation path of the LTSpice exe file from
Program files. For example, C:\Program Files\LTC\LTspiceXVII\XVIIx86.exe

Figure 3: Configuring LTSpice

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