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First A. Author, Second B. Author, Jr., and Third C. Author, Member, IEEE
A highly reliable and efficient differential type
Buck-Boost DC-AC converters.

Abstract With Buck Boost inverter we can achieve output voltage with peak value greater or smaller than the dc input
voltage in a single stage. The conventional structure of Buck Boost inverter uses current bidirectional IGBT. IGBT has
features like long tail current, fixed voltage drops and thats why its switching losses are relatively higher. In this
paper, we have proposed switching cells structure in Buck Boost inverter instead of using current bidirectional IGBT.
In switching cell structure, mosfets and external diodes with very fast reverse recovery characteristics are used, while
the body diodes will have no chance of conducting current. As a result, switching and conduction losses will be
reduced and diode performance will be improved. This new structure will have an additional advantage of having no
shoot through problem so we can eliminate dead time or in other words reliability is increased. In order to further
increase the efficiency, a modified switching scheme is also proposed. In conventional switching strategy, all the
power switches operate in high frequency all the time and suffer from high voltage/current stresses which results in
high switching and conduction losses. While in the proposed switching scheme for modified inverter power mosfets of
each leg of differential buck boost inverter will operate in high frequency for only half cycle which will result in
improved efficiency.

(Note that the organization of the body of the paper is at the authors discretion; the only required sections are Introduction,
Methods and Procedures, Results, Conclusion, and References. Acknowledgements and Appendices are encouraged but optional.)

Index Terms Bidirectional IGBT, Buck Boost inverter, switching cell, switching/conduction losses. For a list of suggested keywords,
send a blank e-mail to keywords@ieee.org or visit http://www.ieee.org/organizations/pubs/ani_prod/keywrd98.txt\

Note: There should no nonstandard abbreviations, acknowledgments of support, references or footnotes in in the abstract.

voltage of photo voltaic cells varies in wide range, so

such an inverter system is needed which can perform
I. INTRODUCTION1 both buck and boost function.
The conventional voltage source inverter (VSI) which

F Or dc-ac power conversion there exists two

well-known converters: the voltage-source inverter
is shown in Fig.1, is seemingly the most valuable
power converter topology. It is used in variety of
(VSI) and the current source industrial and commercial applications in which
inverter(CSI).[1],[2],[3],[4]. We can achieve only buck uninterruptible power supply (UPS) and ac motor
function from VSI, while only boost function from drives are most significant. Full bridge inverter is
current source inverter. However, in some applications commonly used as Buck inverter. However, using buck
e.g. in the photovoltaic power conditioning system, the inverter, we can achieve output voltage whose
1 This paragraph of the first footnote will contain the date on which you
instantaneous average output value is always less than
submitted your paper for review. It will also contain support information, the input dc voltage.
including sponsor and financial support acknowledgment. For example,
This work was supported in part by the U.S. Department of Commerce
under Grant BS123456.
The next few paragraphs should contain the authors current affiliations,
including current address and e-mail. For example, F. A. Author is with the
National Institute of Standards and Technology, Boulder, CO 80305 USA
(e-mail: author@ boulder.nist.gov).
S. B. Author, Jr., was with Rice University, Houston, TX 77005 USA.
He is now with the Department of Physics, Colorado State University, Fort
Collins, CO 80523 USA (e-mail: author@lamar.colostate.edu).
T. C. Author is with the Electrical Engineering Department, University
of Colorado, Boulder, CO 80309 USA, on leave from the National Research
Institute for Metals, Tsukuba, Japan (e-mail: author@nrim.go.jp).
 advantage, which is that output voltages of the two
S2 S4
individual buckboost converters are not required to be
greater than the direct input voltage. Which also results

Vin
L V0 in lower voltage stress across filter capacitors. The
structure of this buck boost inverter is composed of
R
two current bidirectional dc-dc buck boost converters
S1 C S3 and the load is connected differentially across the two
converters as shown in Fig.4.
Fig. 1. The conventional voltage source inverter or buck inverter
v0
R
In order to cope with this complication there are two S2 S1 S3 S4
possible solutions. The first one is to make an addition
of a line-frequency step-up transformer in the
full-bridge inverter [5], as shown in Fig. 2. But this
C1 v1 L1 Vin + L2 v2 C2
structure results in increased volume, cost and weight -
and the power density is also reduced greatly with
noise pollution.
Another possible solution is to use a two-stage cascade Fig.4. The Buck Boost inverter.
structure, as depicted in Fig. 3. In which dc-dc boost
converter is used between dc source and inverter [6]. Each converter generates a sinusoidal output voltage
But in this structure the combined efficiency losses with same dc offset. The modulation of each converter
contribute unnecessarily to low efficiency levels. The is 180 degrees out of phase with respect to each other.
cascaded two stage structure has also greater system Since the load is connected differentially, dc offsets are
size, weight and cost. cancelled out and pure sinusoidal output voltage is
achieved.Fig.5. shows the output voltage of each
Transformer
converter and the voltage across the load.
Renewable Converter 1
AC load
energy DC/AC 0
or grid VDC
source.
-v
Converter 2
0
VDC
Fig.2. Inverter with a transformer.
-v
Voltage across the load
v

Boost DC-DC -v

converter Fig.5. Basic waveforms to attain dc-ac boost conversion.

Q1 Q3 Q5

L1 L2 vo In this paper, we proposed switching cell structure in

C1
Vin
C2
Q2 Q4
Fig.3. Inverter with cascade structure.
Alternative design was proposed in [5], [7], [8], [9].
known as Buck Boost DC-AC inverter, which could
generate an output voltage higher or lower than input
dc voltage. Other advantages were reduced number of
switches as compared to cascade two-stage inverter.
The buck-boost inverter when compared with boost
inverter [should be written] has a supplementary
conventional buck boost inverter i.e. switching cells
structure is introduced in buck boost inverter and the
Q6 resulting buck boost inverter is given the name of Dual
Buck type buck-boost inverter. In comparison with the
conventional Buck Boost inverter the suggested
inverter has some noticeable improvements. First of
all, it wipes out shoot-through worries, which is a
prime failure of conventional Buck Boost inverter.
And the second one is that we have no need of dead
time between the complimentary switches. The third
one is that power MOSFETs are used instead of using
IGBTs which results in improved efficiency.
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However, for conventional PWM strategy the two buck v0

boost converters of modified structure need to operate
concurrently. Due to which switching losses are quite R
higher. In order to mitigate the above shortcoming, in C0
this paper we have proposed a new PWM strategy, in
which for half cycle only the power switches of the 1st
buck/boost converter operate at higher frequencies and S2 S1 S3 S4
for the next half cycle only the power switches of 2nd
buck/boost converter operate at higher frequencies. It
means that for each half cycle only two of the four
C1 v1 L1 Vin + L2 v2 C2
switches operate at higher frequencies. As a result, -
switching losses will be significantly reduced and
hence efficiency will be improved. Detail analysis that
are equally approved with experimental results are
This problem is resolved by switching cell structure as
shown in subsequent sections. depicted in Fig () []. Two types of switching cells are
presented in this paper commonly known as P-cell and
II. COMMUTATION PROBLEM IN CONVENTIONAL N-cell. Each cell consists of a power switch and a
BUCK-BOOST INVERTER AND SWITCHING diode in series while an inductor or current source is
CELL STRUCTURE connected to the common junction of power switch and
diode. Power switches used are commonly IGBTs or
mosfets, but mosfets are preferred for its better
In conventional buck boost inverter when there is
performance. In P-cell the power switch is connected
overlap time between complementary switches, current
to the positive terminal of voltage while current is
shoot through problem occurs. Overlap time occurs
leaving away from the common junction point of diode
either due to EMI noise or miss-triggering of the gate
and power switch. While in the N-cell the power
signals. The current shoot through problem with
switch is connected to the negative terminal and
switching states is depicted in fig ().
current enters to the common junction point of diode
and power switch.
S1
t

S2
t
Overlap time

S4 t

S3 t P-cell N-cell

= or

III. PROPOSED BUCK BOOST INVERTER

The circuit topology of the proposed Buck Boost

inverter is depicted in Fig. 6. Like traditional Buck
Boost inverter, the proposed structure also consists of
two parallel combinations of Buck Boost converters
and we get pure sinusoidal voltage by connecting the
load differentially across the two converters. But
unlike traditional buck boost inverter, switching cell IV. MODULATION STRATEGY FOR THE PROPOSED
structure is proposed in each individual buck boost BUCK BOOST INVERTER
converter as shown in Fig. 6. Each individual buck The schematics of proposed inverter is shown in Fig.6.
boost converter is composed of P-cell and N-cell. In this paper v1 and v2 , which are 180 out of phase
v0 having same dc offsets and magnitude, represents
voltages across C1 and C2 . Vdc is offset or average
R
S2 S4 voltage while A represents magnitude of both
D2 D4
v1 and v2 . The duty ratio of switches S1 and S3 is
S1 S3 D3 d1 & d2 . Vin Input DC voltage and V0 magnitude
D1
of sinusoidal output voltage. In case of conventional
C1 v1 L2 L1 Vin + v2 C2 voltage source inverter, the voltage gain versus duty
-
ratio curve is straight line, so SPWM modulation
strategy is applicable. However, in the Boost and Buck
Fig. 6. Proposed Buck Boost inverter. Boost converter the voltage gain curve is not a straight
line as depicted in Fig.7, from which we can easily
In the proposed topology because of switching cell deduce that the proposed inverter output and input
structures power MOSFETs are used as active devices voltage is not in linear relationship with duty cycle of
while the conventional hard switching inverter is switch S1 . So, if we change the duty cycle in a
designed using IGBTs. The reason behind this is that in sinusoidal manner we cant realize a sinusoidal output
the conventional structure body diodes conduct current voltage. In the figure the voltage gains characteristics
and MOSFETs body diode has poor reverse recovery of both the individual boost converters and the inverter
features hence we cant use mosfet in conventional outputs are shown. Also, the inverter input to output
structure. Here in the proposed topology the voltage gain for two different mean operating duty
arrangement is such that no current will pass through cycle values (or offset values) are shown. Figure shows
the body diodes of active switches. Preference is given that around the mean operating point the duty cycle and
the output voltage gain has linear relationship. In this
to MOSFET over IGBT because its switching speed is
approximate linear region SPWM strategy can be used
faster and switching losses are lower than IGBT. IGBT
however if high gain is required then modified SPWM
has almost fixed voltage drop while the mosfet strategy should be used because of non-linearity.
experiences resistive conduction voltage drop. So in
the conditions where resistive conduction drop of
MOSFET is smaller than IGBT fixed voltage drop, we
can make full use of benefits of power MOSFETS as
active switch. Another catastrophic failure of
conventional structure is possible existence of current
shoot through problem, due to which finite dead time
was necessary for complimentary switches. While the
proposed structure has no shoot through problem
which makes the system more reliable. [10] Since the
proposed topology has no shoot through problem so
dead time between the complimentary switches can be Fig. 7. Voltage gain vs duty cycle curve for individual boost converters and
proposed inverter.
eliminated. Hence the problems related to dead time,
such as distortion of output waveforms and less energy The basic waveforms for the proposed inverter under
transfer, are eliminated. Body diodes of power mosfets revised modulation strategy is shown in Fig. 8.
experience reverse recovery problem but that will not
create any trouble for us in this case because no current
flows through body diodes and hence we can cash the
benefits of external diodes (fast and low reverse
recovery problem) with both hands.
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1 vref 1 1 d1 S 4 respectively. Because it requires less calculation of DSP

carrier
and that is why it is preferred.
0.5

0
V. AC GAIN OF THE PROPOSED BUCK BOOST INVERTER
S2
S1
vref 1
carrier Peak value of output voltage can be calculated from (2) and
vref 2 1 d 2
1
(3) as:
carrier

0.5
V0 2V2 2VDC
Where V2 is maximum negative voltage that appears
0
S4
S3
across the capacitor of 2nd buck boost converter and is
v1
0
VDC V sin t calculated as
VDC V D
V2 in .
VDC V sin t (V ) : t ( s ) 1 D
v2
0
VDC V sin t
D=maximum duty cycle of switch S3 or S1.
VDC
For minimum voltage stress across semiconductor
VDC V sin t
(V ) : t ( s )
V
v0 V0 sin t
devices VDC 0 is chosen.
2
0
Vin D V
Henc V0 2 2 0
1 D 2
(V ) : t ( s )

V0 D
v0 v1 v2 2 A sin t (1) Ac gain=
Vin 1 D
d2 (Vin ) (2)
v2 VDC A sin t Calculated ac gain is equally verified with simulation
1 d2
v0 v1 v2 2 A sin t results that are included in fig. (). The circuit
OR v0 V0 sin t where V0 2 A.
parameters along with its results are also summarized
(3) in table[].
V
In above equations VDC 0 .
2
V INPUT VOLTAGE Vin 90V
But the best case is VDC 0 because in this case the
2 Maximum duty of switch 0.6
voltage stress across the semiconductor devices will be S1 Dmax1
minimum. Hence for further calculations this value will be
considered. Maximum duty of switch S3 0.6
From equations (1) -(3): Dmax 3
v0 v
0 sin t Switching frequency 20KHz
Inductors L1 , L2 , L3 , L4
2Vin 2Vin
d1 . (4) 500uH
v0 v
0 sin t 1
2Vin 2Vin Capacitors C1 , C2 10uF
1
1 d1
v0

v0
sin t 1
. (5) Load R 50
2Vin 2Vin AC gain 1.5
v0 v Maximum output voltage 135V
0 sin t
d2
2Vin 2Vin
v0 v
. (6) V0 Ac gain Vin
0 sin t 1
2Vin 2Vin
1
1 d2 . (7)
v0 v0
sin t 1
2Vin 2Vin
The voltage reference which is derived in (4) and (6) can be
used to generate the gate signals for switch S1 and S3
respectively. While gate signals of S 2 is complement of S1
and gate signals of S 4 is complement of S3 . But in Fig.8.
we have used (5) and (7) to generate gate signals for S 2 and
 di2 V
Similarly, in (3)
dt L1
di3 Vin
(4)
dt L3
di4 V
in (5)
dt L4

In steady state during this mode

iin1 i1 i2 & iin2 i3 i4
i01 & i02 0
Since i01 & i02 0 in this mode hence output current
VI. MODAL ANALYSIS OF PROPOSED BUCK BOOST i0 will flow through both capacitors C1 and C2 . As
INVERTER can be seen in figure (), that i0 flows into the positive
The modal analysis is organized in such a way that 1st terminal of C1 hence C1 is charged and as current
we will consider the positive portion of sinusoidal
flows away from positive terminal of C2 so it is
output voltage and then the negative portion. For the
positive portion d1 d3 which implies that v1 v2 discharged during this portion.
i0 v0
and hence v0 v1 v2 will be positive, because both R
v1 & v2 are negative voltages. The output voltage will S2 S4
D1 D3
be zero whenever d1 d3 . i01 iin1 iin2 i02
S1 S3
D2 D4

v1 C L2 L1 Vin + L3 L4

C2 v2
1 -
i2 i1 i3 i4

2) Mode 2: -
During this mode S1 is turned off while S2 is turned on.
While S3 remains in on state and S4 in off state as
shown in fig (). The body diodes of S1 and S4 are
reverse polarized by v1 Vin and v2 Vin
respectively. While since S 2 and S3 are conducting
hence their body diodes will also be reverse polarized
because of zero potential difference across diodes
For positive portion of output voltage.
ideally. The inductors current ripple during this mode
1) Mode 1: -
In this mode S1 and S3 are turned on while S2 and S4 are will be as given below while assuming voltage small
off. The body diodes of S1 and S3 are reverse polarized ripple approximation;
because S1 and S3 are on and ideally zero potential di1 v di v
1 , 2 1
difference appears across its body diodes. While the dt L1 dt L2
body diodes of S2 and S4 are reverse polarized by
di3 Vin di4 V
v1 Vin and v2 Vin respectively. Considering , in
dt L3 dt L4
that switches and diodes are ideal, voltage that appears
across L1 and L3 is Vin . In steady state during this mode
vL1 Vin (1) iin1 0 & iin2 i3 i4

di1 Vin i01 =i1 - i2 & i02 0

(2)
dt L1
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i0 v0 i0 v0
R R
S2 S4 S2 S4
D1 D3 D1 D3
i01 iin1 iin2 i02 i01 iin1 iin2 i02
S1 S3 S1 S3
D2 D4 D2 D4

v1 C L2 L1 Vin + L3 L4

C2 v2 v1 C L2 L1 Vin + L3 L4

C2 v2
1 - 1 -
i2 i1 i3 i4 i2 i1 i3 i4

6) Mode 6: -
3) Mode 3: - During this mode S3 and S 2 are in off state while
During this mode S1 and S3 are off while S 2 and S 4 S1 and S4 are in the on state. This mode only appears
are on as shown in fig (). Here again the body diodes of in negative portion of sinusoidal voltage. All the body
mosfets will be reverse polarized. Diodes D2 and diodes will be reverse polarized. External fast recovery
D4 are forward biased to provide free wheeling path to diodes D1 and D3 will be forward biased by
i1 and i3 respectively. While diodes D1 and D3 are freewheeling current. While assuming voltage small
reverse biased. Assuming output voltage small ripple ripple approximation the inductor current ripple will be
approximation inductor current ripple will be calculated as below.
calculated as, di1 Vin di2 V
, in
di1 v di2 v1 dt L1 dt L2
1 ,
dt L1 dt L2 di3 v di v
2 , 4 2
di3 v di v dt L3 dt L4
2 , 4 2
dt L3 dt L4 i0 v0

Also, iin 0 & iin 0 R

1 2 S2 S4
D1 D3
i01 i1 i2 & i02 i3 i4
i01 iin1 iin2 i02
v0 S1 S3
i0 D2 D4
R
S2
D1 D3
S4 v1 C L2 L1 Vin + L3 L4

C2 v2
1 -
i2 i1 i3 i4
i01 iin1 iin2 i02
S1 S3
D2 D4

7) Mode 7: -
v1 C L2 L1 Vin + L3 L4

C2 v2
1 - The operation is shown in Fig. (). Inductor current
i2 i1 i3 i4
ripple calculation will be same like mode 3. As can be
seen in the figure input current will be zero during this
4) Mode 4: - portion. But in this mode direction of i0 will be
Here the operating mode is exactly similar to mode 2.
opposite that of mode 3.
v0
For negative portion of output voltage i0

In this portion d3 d1 and as a result v2 v1 S2

R
S4
D1 D3
Which implies that v0 v1 v2 will be a negative i01 iin1 iin2 i02
S1 S3
value because both v1 and v2 are always negative. D2 D4

5) Mode 5: - v1 C L2 L1 Vin + L3 L4

C2 v2
1 -
The operation during this mode is shown in Fig. (). Its i2 i1 i3 i4
analysis is similar like mode 1. The difference is that
output current is flowing in other direction for pure
8) Mode 8: -
resistive load. Capacitor C1 is discharging while C2
This operating mode is exactly similar to mode 6.
is charging.
 ref1 1 d1
VII. FILTER CAPACITORS REARRANGEMENT FOR INPUT
carrier
CURRENT CONTINUITY

From modal analysis, it is obvious that during mode 3

S2
and mode 7 input current of dc voltage source is zero.
Similarly, iin1 is zero during modes 2,3,4 & 7 while
S1
iin2 is zero during modes 3,6,7 & 8. This implies that
input current, iin1 and iin2 are discontinuous. In the fig
ref 2 1 d 2

() we have rearranged the filter capacitors which carrier

results in quasi continuous current. Due to this

arrangement, the voltage stress across filter capacitors S4

will increase.
S3
i0 v0
R C2
C1
v1
S2 v1 v2 S4
D1 D3
i01 iin1 iin2 i02 v2
S1 S3
D2 D4
v0

Vin + L3
L2 L1 L4
-
i2 i1 i3 i4

The input current equations will be calculated as: In the positive portion of output voltage, S1 and S2 are
iin1 i1 i2 i0 complementary signals and will operate at higher
frequencies. S3 will be in off state and S4 in on state
iin2 i3 i4 i0
during this half cycle. Voltage across capacitor
From equations, above i1 , i2 , i3 , i4 & i0 are either quasi C1 and C2 will be.
continuous or continuous hence iin and iin will also be v1 0
1 2
0 t (6)
quasi continuous. v2 A sin(t )

In the negative portion of output voltage, S3 and S4

VIII. MODULATION STRATEGY FOR REDUCED
SWITCHING LOSSES will operate at high frequencies. S1 will be in off state
In the modulation strategy discussed earlier all the four and S2 in on state during this half cycle. Voltage
power switches operate at high frequencies due to across capacitors C1 and C2 will be.
which all the switches suffer from high voltage/current v1 A sin(t )
stresses. As a result, high conduction and switching t 2 (7)
losses take place. In this modulation strategy, the two v2 0
buck boost converters will operate one by one. In the From (6) and (7);
positive portion of output voltage one converter will d1 0

operate while in the negative portion of output voltage A sin(t ) 0 t (8)
another converter will operate. It means at a time only d 2 A sin(t ) V
in
two power switches will operate at higher frequencies
A sin t
d1
and the remaining two switches of the other converter
will operate at lower frequencies. As a result, both A sin t Vin t 2 (9)
switching and conduction losses are largely reduced. d 0
2
From (8) and (9)
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d1 0 0 t i0 v0

A sin t (10) R

d1 A sin wt V t 2 S2
D1 D3
S4
in iin1 iin2
A sin(t ) S1 S3
d 2 0 t D2 D4
A sin( wt ) Vin (11)
d =0 v1 C + L3
2 t 2 1
L2
i2
L1
i1
Vin
-
L4 C2 v2

i3 i4

IX. MODAL ANALYSIS FOR POSITIVE PORTION OF 3) Mode 3: -

OUTPUT VOLTAGE In this mode S2 and S4 are in on state. The operation is
shown in fig. (). Current i3 freewheels through D4
S1 while i0 flows through D2 and S2 .
t v0
i0
S2 t S2
R
S4
D1 D3
iin1 iin2
S3 t S1 S3
D2 D4

S4 v1 C
t 1
L2 L1 Vin +
-
L3 L4 C2 v2

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 i2 i1 i3 i4

Fig. Modified switching strategy for reduced switching losses.

1) Mode 1: -
In this mode S3 and S2 are on while S1 and S4 are
off. The input voltage appears across L3 . Capacitor
C2 will supply load current io , which passes through
S2 and D2 .
4) Mode 4: -
This operating mode is same as mode 2.
In the period the output voltage is negative
5) Mode 5: -
In this mode S1 and S4 are on while other switches are
off. The schematics is shown in fig. (). The input
voltage appears across L1 . Capacitor C1 will supply
load current io , which passes through S4 and D4 .

i0 v0
i0 v0
R
S2 S4 R
D1 D3 S2 S4
D1 D3
iin1 iin2
S1 S3 iin1 iin2
D2 D4 S1 S3
D2 D4

v1 C
v1 C
L2 L1 Vin + L3 C2 v2
1 -
L4 + L3
L2 L1 Vin L4 C2 v2
i2 i1 i3 i4 1 -
i2 i1 i3 i4

6) Mode 6: -
2) Mode 2: -
The operation during this mode is shown in Fig. (). This In this mode S1 , S2 and S3 are in off state while S4 is
period is a result of dead time between the two on. The operation is shown in fig. (). In this mode
complementary signals S3 and S4 . In this mode S1 and S2 are in off state simultaneously because of
S1 ,S3 and S4 are in off state. Diodes D3 and D4 are dead time between complementary signals. D1 and D2
forward biased by freewheeling current i4 and i3 are forward biased by freewheeling current i2 and i1
respectively. Since S1 is in off state and D1 is reverse respectively. Since S3 is in off state and D3 is reverse
polarized i0 will pass through S2 and D2 .
polarized i0 will pass through S4 and D4 . [26] P.W. Sun, J.-S. Lai, H. Qian, W.S. Yu, C. Smith, J. Bates, B. Arnet, A.
Litvinov, and S. Leslie, Efficiency evaluation of a 55kW
i0 v0 soft-switching module based inverter for high temperature hybrid
R electric vehicle drives application, in Proc. 25th IEEE Applied Power
S2 S4 Electron. Conf. and Expo., 2010, pp. 474--479.
D1 D3
iin1 iin2
S1 S3 However, the delayed responses of gate
D2 D4 drive circuits and switching devices produce overlap time
and/or dead time among the switches. The overlap [see Fig.
v1 C L2 L1 Vin + L3 L4

C2 v2
1 - 2(a)] and dead time [see Fig. 2(b)] cause current spikes
i2 i1 i3 i4
(di/dt) and voltage spikes (dv/dt), respectively, often
damaging the semiconductor devices. Thus, overlap and
7) Mode 7: - dead time among the switches severely impair the reliability
In this mode S2 and S4 are in on state while the other of traditional acac converters, which limits their practical
switches are in off state. The operation is shown in fig. applications. Soft commutation strategies for smooth current
(). Current i1 freewheels through D2 while i0 passes transition have been researched in [22] and [39] for the
through D4 and S4 . purpose of providing safe commutation and to avoid the use
of lossy snubber circuits. All of these strategies use
i0 v0
voltage/current sensing modules to enable the switching
R devices to conduct according to the polarity of the input
S2 S4
D1 D3 voltage/current. The sensing modules, however, increase the
iin1 iin2 cost and control complexity of the converter, and these
S1 S3
D2 D4 methods still cannot provide safe and reliable commutation
when the input voltage is highly distorted, especially around
v1 C L2 L1 Vin + L3 L4

C2 v2 the zero crossing point [13]. Similar to the method
1 -
i2 i1 i3 i4 using RC snubber circuits, these methods also cannot protect
the switching devices from high current spikes when
8) Mode 8: - shoot-through caused by EMI noises misgating-on
This period is dead time and same as mode 6. occurs.Body (or antiparallel) diodes of standard
metaloxide semiconductor field-effect transistors
(MOSFETs) exhibit poor reverse recovery characteristics
In addition, when it operates [23], [24]; therefore, insulated gate bipolar junction
at higher dc bus voltage of each cell, it loses the benefit of transistors (IGBTs) are commonly used as
employing power switching devices in the traditional hard switching acac
MOSFETs as the active switches for fast switching speed and converters. Fig. 3 illustrates the effect of reverse recovery
efficiency improvement because of the reverse recovery problem
issues of the MOSFETs body diode in the traditional buck-type
of the body diode [21]-[23] unless people employ acac
soft-switching techniques [24]-[26]. For example, when the converter. Switches S3 and S4 are turned on for vin > 0 for the
cell safe commutation. To avoid current shoot-through, finite
dc bus voltage goes up to 300V to 600V, people can not dead
simply time between S1 and S2 is required and the output inductor
adopt high voltage power MOSFETs (600V to 900V rated current freewheels through the body diode DB of S2 during the
voltage, such as CoolMOS or MDmesh series) to work at dead time. When S1 is turned on after the dead time, DB flows
hard-switched situation like traditional cascade H-bridge current in reverse direction for a short interval due to its
inverter. reverse
recovery as shown in Fig. 3(b). Due to this, the reverse
[21] S.-Y. Park, P.W. Sun, W. Yu and J.-S. Lai, Performance evaluation of
high voltage super junction MOSFETs for zero-voltage soft-switching recovery current creates a short circuit of input voltage,
inverter applications, in Proc. 25th IEEE Applied Power Electron. which causes
Conf. and Expo., 2010, pp. 387--391. large current spikes in the switches and diodes. [24].
[23] C.M. Johnson, and V. Pickert, Three-phase soft-switching voltage [23] L. Saro, K. Dierberger, and R. Redl, High-voltage MOSFET behavior
source converters for motor drives. II. Fundamental limitations and in soft-switching converters: Analysis and reliability improvements, in
critical assessment, IEE Proceedings on Electric Power Applications, Proc. 20th IEEE Telecom. Energy Conf., 1998, pp. 3040.
vol. 146, no. 2, pp. 155162, 1999 [24] X. D. Huang, H. J. Yu, J.-S. Lai, A. R. Hefner, and D. W. Berning,
[24] P.W. Sun, J.-S. Lai, H. Qian, W.S. Yu, C. Smith, and J. Bates, High Characterization of paralleled super junction MOSFET devices under
efficiency three-phase soft-switching inverter for electric vehicle hard and soft-switching conditions, in Proc. 32nd IEEE Power Electron.
drives, in Proc. IEEE Vehicle Power and Propulsion Conf., 2009, pp. Spec. Conf., 2001, vol. 4, pp. 21452150. [39] J. H. Kim, B. D. Min, B. H.
761--766. Kwon, and S. C. Won, A PWM buckboost ac
> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 11

chopper solving the commutation problem, IEEE Trans. Ind. Electron., however, increase the cost and control complexity of the
vol. 45, no. 5, pp. 832835, Oct. 1998. H. Shin, H. Cha, H. Kim, and D.
converter, and these methods still cannot provide safe and
Yoo, Novel single-phase PWM AC
AC converters solving commutation problem using switching cell structure reliable
and coupled inductor, IEEE Trans. Power Electron, vol. 30, no. 4, commutation when the input voltage is highly distorted,
pp. 21372147, Apr. 2015. especially around the zero crossing point [13]. Similar to the
method
using RC snubber circuits, these methods also cannot protect
The traditional direct PWM acac converters are the simplest the
converters, and they have been derived from the traditional switching devices from high current spikes when
dc shoot-through
dc converters by adaption of ac switches. The traditional caused by EMI noises misgating-on occurs.
singlephase boost-type dcdc converter is shown in Fig. 1(a), Body (or antiparallel) diodes of standard metaloxide
and semiconductor field-effect transistors (MOSFETs) exhibit
its counterpart traditional boost type acac converter is poor
shown reverse recovery characteristics [23], [24]; therefore,
in Fig. 1(b). The switching devices of the converter shown in insulatedgate bipolar junction transistors (IGBTs) are
Fig. 1(b) are connected in series, thereby causing commonly used as
commutation switching devices in the traditional hard switching acac
problem. The switches (S1, S4) and (S2, S3) are gated on/off converters. Fig. 3 illustrates the effect of reverse recovery
complementarily, and the converter can be operated properly problem
with ideal gate signals. However, the delayed responses of of the MOSFETs body diode in the traditional buck-type
gate acac
drive circuits and switching devices produce overlap time converter. Switches S3 and S4 are turned on for vin > 0 for the
and/or safe commutation. To avoid current shoot-through, finite
dead time among the switches. The overlap [see Fig. 2(a)] dead
and time between S1 and S2 is required and the output inductor
dead time [see Fig. 2(b)] cause current spikes (di/dt) and current freewheels through the body diode DB of S2 during the
voltage dead time. When S1 is turned on after the dead time, DB flows
spikes (dv/dt), respectively, often damaging the current in reverse direction for a short interval due to its
semiconductor devices. Thus, overlap and dead time among reverse
the switches recovery as shown in Fig. 3(b). Due to this, the reverse
severely impair the reliability of traditional acac converters, recovery current creates a short circuit of input voltage,
which limits their practical applications. which causes
A common approach to address the aforementioned problem large current spikes in the switches and diodes. [24]. The SC
is to add bulky and lossy resistorcapacitor (RC) snubbers structure shown in Fig. 4 can inherently overcome this
and allow finite dead time in the gate signals. However, this problem.
method decreases converter efficiency and achievable There are two types of SCs: P-type and N-type, as shown in
voltage Fig. 4 [25], [26]. Both SCs consist of one switching device
gain [20], [21] and causes distortion of the output voltage such
waveforms because energy is dissipated in the resistor of RC as IGBT/MOSFET and one externally selected freewheeling
snubber diode connected in series. In the P-type SC, the common
circuits and is not transferred to output during the dead time. point
Furthermore, the snubber approach cannot protect the is connected to positive terminal of current source or
switching inductor,
devices from high current spikes when shoot-through caused and in the N-type SC, the common point is connected to
by negative
EMI noises misgating-on occurs. terminal of current source or inductor [26]. Therefore,
Soft commutation strategies for smooth current transition designing
have been researched in [22] and [39] for the purpose of converters/inverters/rectifiers with the SC structure can
providing safe commutation and to avoid the use of lossy eliminate the current shoot-through problem. Many power
snubber electronics
circuits. All of these strategies use voltage/current sensing topologies, including multilevel dcac inverters [20], [21],
modules to enable the switching devices to conduct highefficiency dcac inverters [28][37], and acdc rectifier
according to [37] are
the polarity of the input voltage/current. The sensing implemented with the SC structure.
modules,
In [13], the SC structure is successfully employed in the tra B. Dead Time
ditional single-phase acac converters for the first time. The The dead time in which all the switching devices are turned
boost-type example is shown again in Fig. 1(c). As shown, off is shown in Fig. 11(a). The capacitors C1 and C2 bypass
the the
converter is implemented with the SC structure and coupled inductors currents during the dead time. The bypass modes
inductors, and they have the following significant for
advantages. positive and negative half cycle of input voltage are shown
1) They do not require current/voltage sensing modules or in
lossy snubber circuits for the safe commutation, and can Fig. 11(b) and (c), respectively
be operated properly even with highly inductive load and
distorted input voltage.
2) They can be operated with high switching frequency
without the reverse recovery problem associated with
MOSFET body diode and the switching devices are not
damaged even with dead time or overlap time during
operation.

C. Overlap Time
In this interval, all the switching devices are turned on,
as shown in Fig. 12(a). The limiting inductors limit the
shoot-through current by providing a high impedance path
when
all the switches are turned on either by purpose or
mismatched
gate signals. Fig. 12(b) and (c) shows this mode for vin > 0
and
vin < 0, respectively.

D. Review Stage
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13
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Web Color Graphics
 TABLE I
UNITS FOR MAGNETIC PROPERTIES
Conversion from Gaussian and
Symbol Quantity
CGS EMU to SI a
magnetic flux 1 Mx 108 Wb = 108 Vs
B magnetic flux density, 1 G 104 T = 104 Wb/m2
magnetic induction
H magnetic field strength 1 Oe 103/(4) A/m
m magnetic moment 1 erg/G = 1 emu
103 Am2 = 103 J/T
M magnetization 1 erg/(Gcm3) = 1 emu/cm3
103 A/m
4M magnetization 1 G 103/(4) A/m
specific magnetization 1 erg/(Gg) = 1 emu/g 1 Am2/kg
j magnetic dipole 1 erg/G = 1 emu
moment 4 1010 Wbm
J magnetic polarization 1 erg/(Gcm3) = 1 emu/cm3
4 104 T
, susceptibility 1 4
mass susceptibility 1 cm3/g 4 103 m3/kg
Fig. 1. Magnetization as a function of applied field. Note that Fig. is
abbreviated. There is a period after the figure number, followed by two spaces. permeability 1 4 107 H/m
It is good practice to explain the significance of the figure in the caption. = 4 107 Wb/(Am)
r relative permeability r
w, W energy density 1 erg/cm3 101 J/m3
IEEE accepts color graphics in the following formats: N, D demagnetizing factor 1 1/(4)
EPS, PS, TIFF, Word, PowerPoint, Excel, and PDF. The Vertical lines are optional in tables. Statements that serve as captions for
resolution of a RGB color TIFF file should be at least 400 the entire table do not need footnote letters.
aGaussian units are the same as cgs emu for magnetostatics; Mx = maxwell,
dpi.
G = gauss, Oe = oersted; Wb = weber, V = volt, s = second, T = tesla, m =
Your color graphic will be converted to grayscale if no meter, A = ampere, J = joule, kg = kilogram, H = henry.
separate grayscale file is provided. If a graphic is to appear in
print as black and white, it should be saved and submitted as a
black and white file. If a graphic is to appear in print or on X. MATH
IEEE Xplore in color, it should be submitted as RGB color.
If you are using Word, use either the Microsoft Equation
Editor or the MathType add-on (http://www.mathtype.com)
Graphics Checker Tool
for equations in your paper (Insert | Object | Create New |
The IEEE Graphics Checker Tool enables users to check
Microsoft Equation or MathType Equation). Float over
graphic files. The tool will check journal article graphic files
text should not be selected.
against a set of rules for compliance with IEEE requirements.
These requirements are designed to ensure sufficient image
quality so they will look acceptable in print. After receiving a
XI. UNITS
graphic or a set of graphics, the tool will check the files
against a set of rules. A report will then be e-mailed listing Use either SI (MKS) or CGS as primary units. (SI units are
each graphic and whether it met or failed to meet the strongly encouraged.) English units may be used as
requirements. If the file fails, a description of why and secondary units (in parentheses). This applies to papers in
instructions on how to correct the problem will be sent. The data storage. For example, write 15 Gb/cm2 (100 Gb/in2).
IEEE Graphics Checker Tool is available at An exception is when English units are used as identifiers in
http://graphicsqc.ieee.org/ trade, such as 3-in disk drive. Avoid combining SI and
For more Information, contact the IEEE Graphics H-E-L-P CGS units, such as current in amperes and magnetic field in
Desk by e-mail at graphics@ieee.org. You will then receive oersteds. This often leads to confusion because equations do
an e-mail response and sometimes a request for a sample not balance dimensionally. If you must use mixed units,
graphic for us to check. clearly state the units for each quantity in an equation.
The SI unit for magnetic field strength H is A/m. However,
if you wish to use units of T, either refer to magnetic flux
H. Copyright Form density B or magnetic field strength symbolized as 0H. Use
An IEEE copyright form should accompany your final the center dot to separate compound units, e.g., Am2.
submission. You can get a .pdf, .html, or .doc version at
http://www.ieee.org/copyright. Authors are responsible for
obtaining any security clearances.
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XII. HELPFUL HINTS
A. Figures and Tables
Because IEEE will do the final formatting of your paper,
you do not need to position figures and tables at the top and
bottom of each column. Large figures and tables may span
both columns. Place figure captions below the figures; place
table titles above the tables. If your figure has two parts,
include the labels (a) and (b) as part of the artwork.
Please verify that the figures and tables you mention in the
text actually exist. Please do not include captions as part of
the figures. Do not put captions in text boxes linked to
the figures. Do not put borders around the outside of
your figures. Use the abbreviation Fig. even at the
beginning of a sentence. Do not abbreviate Table. Tables
are numbered with Roman numerals.
Figure axis labels are often a source of confusion. Use
words rather than symbols. As an example, write the quantity
Magnetization, or Magnetization M, not just M. Put
units in parentheses. Do not label axes only with units. As in
Fig. 1, for example, write Magnetization (A/m) or
Magnetization (Am1), not just A/m. Do not label axes
with a ratio of quantities and units. For example, write
Temperature (K), not Temperature/K.
Multipliers can be especially confusing. Write
Magnetization (kA/m) or Magnetization (103 A/m). Do
not write Magnetization (A/m) 1000 because the reader
would not know whether the top axis label in Fig. 1 meant
16000 A/m or 0.016 A/m. Figure labels should be legible,
approximately 8 to 12 point type.
B. References
Number citations consecutively in square brackets [1]. The
sentence punctuation follows the brackets [2]. Multiple
references [2], [3] are each numbered with separate brackets
[1][3]. When citing a section in a book, please give the
relevant page numbers [2]. In sentences, refer simply to the
reference number, as in [3]. Do not use Ref. [3] or
reference [3] except at the beginning of a sentence:
Reference [3] shows ... . Please do not use automatic
endnotes in Word, rather, type the reference list at the end of
the paper using the References style.
Number footnotes separately in superscripts (Insert |
Footnote). 2 Place the actual footnote at the bottom of the
column in which it is cited; do not put footnotes in the
reference list (endnotes). Use letters for table footnotes (see
Table I).
Please note that the references at the end of this document
are in the preferred referencing style. Give all authors
names; do not use et al. unless there are six authors or
more. Use a space after authors initials. Papers that have not
been published should be cited as unpublished [4]. Papers
2 It is recommended that footnotes be avoided (except for the
unnumbered footnote with the receipt date on the first page). Instead, try to
integrate the footnote information into the text.
15
that have been accepted for publication, but not yet specified
for an issue should be cited as to be published [5]. Papers
that have been submitted for publication should be cited as
submitted for publication [6]. Please give affiliations and
addresses for private communications [7].
Capitalize only the first word in a paper title, except for
proper nouns and element symbols. For papers published in
translation journals, please give the English citation first,
followed by the original foreign-language citation [8].
C. Abbreviations and Acronyms
Define abbreviations and acronyms the first time they are
used in the text, even after they have already been defined in
the abstract. Abbreviations such as IEEE, SI, ac, and dc do
not have to be defined. Abbreviations that incorporate
periods should not have spaces: write C.N.R.S., not C. N.
R. S. Do not use abbreviations in the title unless they are
unavoidable (for example, IEEE in the title of this article).
D. Equations
Number equations consecutively with equation numbers in
parentheses flush with the right margin, as in (1). First use the
equation editor to create the equation. Then select the
Equation markup style. Press the tab key and write the
equation number in parentheses. To make your equations
more compact, you may use the solidus ( / ), the exp function,
or appropriate exponents. Use parentheses to avoid
ambiguities in denominators. Punctuate equations when they
are part of a sentence, as in
(1)
Be sure that the symbols in your equation have been
defined before the equation appears or immediately
following. Italicize symbols (T might refer to temperature,
but T is the unit tesla). Refer to (1), not Eq. (1) or
equation (1), except at the beginning of a sentence:
Equation (1) is ... .
E. Other Recommendations
Use one space after periods and colons. Hyphenate
complex modifiers: zero-field-cooled magnetization.
Avoid dangling participles, such as, Using (1), the potential
was calculated. [It is not clear who or what used (1).] Write
instead, The potential was calculated by using (1), or
Using (1), we calculated the potential.
Use a zero before decimal points: 0.25, not .25. Use
cm3, not cc. Indicate sample dimensions as 0.1 cm 0.2
cm, not 0.1 0.2 cm2. The abbreviation for seconds is
s, not sec. Do not mix complete spellings and
abbreviations of units: use Wb/m2 or webers per square
meter, not webers/m2. When expressing a range of values,
write 7 to 9 or 7-9, not 7~9.
A parenthetical statement at the end of a sentence is
punctuated outside of the closing parenthesis (like this). (A
parenthetical sentence is punctuated within the parentheses.)
In American English, periods and commas are within
quotation marks, like this period. Other punctuation is
outside! Avoid contractions; for example, write do not
instead of dont. The serial comma is preferred: A, B, and
C instead of A, B and C.
If you wish, you may write in the first person singular or
plural and use the active voice (I observed that ... or We
observed that ... instead of It was observed that ...).
Remember to check spelling. If your native language is not
English, please get a native English-speaking colleague to
carefully proofread your paper.
XIII. SOME COMMON MISTAKES
The word data is plural, not singular. The subscript for
the permeability of vacuum 0 is zero, not a lowercase letter
o. The term for residual magnetization is remanence; the
adjective is remanent; do not write remnance or
remnant. Use the word micrometer instead of micron.
A graph within a graph is an inset, not an insert. The
word alternatively is preferred to the word alternately
(unless you really mean something that alternates). Use the
word whereas instead of while (unless you are referring
to simultaneous events). Do not use the word essentially to
mean approximately or effectively. Do not use the word
issue as a euphemism for problem. When compositions
are not specified, separate chemical symbols by en-dashes;
for example, NiMn indicates the intermetallic compound
Ni0.5Mn0.5 whereas NiMn indicates an alloy of some
composition NixMn1-x.
Be aware of the different meanings of the homophones
affect (usually a verb) and effect (usually a noun),
complement and compliment, discreet and discrete,
principal (e.g., principal investigator) and principle
(e.g., principle of measurement). Do not confuse imply
and infer.
Prefixes such as non, sub, micro, multi, and
ultra are not independent words; they should be joined to
the words they modify, usually without a hyphen. There is no
period after the et in the Latin abbreviation et al. (it is
also italicized). The abbreviation i.e., means that is, and
the abbreviation e.g., means for example (these
abbreviations are not italicized).
An excellent style manual and source of information for
science writers is [9]. A general IEEE style guide and an
Information for Authors are both available at
http://www.ieee.org/web/publications/authors/transjnl/index.html
XIV. EDITORIAL POLICY
Submission of a manuscript is not required for
participation in a conference. Do not submit a reworked
version of a paper you have submitted or published
elsewhere. Do not publish preliminary data or results. The
submitting author is responsible for obtaining agreement of
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strongly discourage courtesy authorship. It is the obligation
of the authors to cite relevant prior work.
The Transactions and Journals Department does not
publish conference records or proceedings. The
TRANSACTIONS does publish papers related to conferences
that have been recommended for publication on the basis of
peer review. As a matter of convenience and service to the
technical community, these topical papers are collected and
published in one issue of the TRANSACTIONS.
At least two reviews are required for every paper
submitted. For conference-related papers, the decision to
accept or reject a paper is made by the conference editors and
publications committee; the recommendations of the referees
are advisory only. Undecipherable English is a valid reason
for rejection. Authors of rejected papers may revise and
resubmit them to the TRANSACTIONS as regular papers,
whereupon they will be reviewed by two new referees.
XV. PUBLICATION PRINCIPLES
The contents of IEEE TRANSACTIONS and JOURNALS are
peer-reviewed and archival. The TRANSACTIONS publishes
scholarly articles of archival value as well as tutorial
expositions and critical reviews of classical subjects and
topics of current interest.
Authors should consider the following points:
1) Technical papers submitted for publication must
advance the state of knowledge and must cite relevant
prior work.
2) The length of a submitted paper should be
commensurate with the importance, or appropriate to the
complexity, of the work. For example, an obvious
extension of previously published work might not be
appropriate for publication or might be adequately
treated in just a few pages.
3) Authors must convince both peer reviewers and the
editors of the scientific and technical merit of a paper;
the standards of proof are higher when extraordinary or
unexpected results are reported.
4) Because replication is required for scientific progress,
papers submitted for publication must provide sufficient
information to allow readers to perform similar
experiments or calculations and use the reported results.
Although not everything need be disclosed, a paper must
contain new, useable, and fully described information.
For example, a specimens chemical composition need
not be reported if the main purpose of a paper is to
introduce a new measurement technique. Authors should
expect to be challenged by reviewers if the results are not
supported by adequate data and critical details.
5) Papers that describe ongoing work or announce the latest
technical achievement, which are suitable for
presentation at a professional conference, may not be
appropriate for publication in a T RANSACTIONS or
> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 17

JOURNAL. Congress, 1998. CIEP 98. VI IEEE International Year: 1998

Pages: 126 131.

[8] A comparison between the buck, boost and buck-boost inverters.

XVI. CONCLUSION
Please include a brief summary of the possible clinical
implications of your work in the conclusion section.
Although a conclusion may review the main points of the
paper, do not replicate the abstract as the conclusion.
Consider elaborating on the translational importance of the
work or suggest applications and extensions.
J.Almazan; N. Vazquez; C. Hernandez; J. Alvarez; J. Arau Power
Electronics Congress, 2000. CIEP 2000. VII IEEE International Year:
2000 Pages: 341 - 346
[9] Analysis and experimental study of the buck, boost and buck-boost
inverters N. Vazquez; J. Almazan; J. Alvarez; C. Aguilar; J. Arau
Power Electronics Specialists Conference, 1999. PESC 99. 30th
Annual IEEE Year: 1999, Volume: 2 Pages: 801 - 806
[10] Z. Yao, L. Xiao, and Y. Yan, Dual-Buck Full-Bridge Inverter With
Hysteresis Current Control, IEEE Trans. Ind. Electron., vol. 56,
no.8, pp. 31533160, Aug. 2009.

APPENDIX
Appendixes, if needed, appear before the
acknowledgment.
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[1] IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27,
professional societies other than the IEEE. Finally, list any awards and work
NO. 2, FEBRUARY 2012 Fault-Tolerant Voltage Source Inverter for
for IEEE committees and publications. If a photograph is provided, the
Permanent Magnet Drives Rammohan Rao Errabelli and Peter
biography will be indented around it. The photograph is placed at the top
Mutschler, Member, IEEE.
left of the biography. Personal hobbies will be deleted from the biography.

[2] IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26,

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[4] Active Buck-Boost Inverter. yu tang, member iee, xianmei dong, and
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September 2014.

[5] IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19,

NO. 5, SEPTEMBER 2004 1305 Topologies of Single-Phase
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[6] Boost-Derived Hybrid Converter With Simultaneous DC and AC Ou

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[7] A buck-boost DC-AC converter: operation, analysis, and control R.
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