Application Note AN2098

FSK Generator using the PSoCTM Device

By: Andrew Page

Associated Project: Yes
Associated Part Family: CY8C25xxx, CY8C26xxx

Summary
TM
This Application Note demonstrates how to configure the PSoC device to implement a Frequency Shift
Keying (FSK) generator.

Introduction
There are two major ways to send digital data. A cos(2f 1t ), if d (t ) = 1
The digital data may be sent digitally or s (t ) =
converted to an analog form. In digital signaling, A cos(2f 2 t ), if d (t ) = 0
the data is represented as square pulses. While
digital signaling is simple, it possesses one major
(2)
disadvantage. The Fourier analysis of a square
wave consists of a sinusoid at a fundamental
The data and its corresponding FSK signal for a
frequency (f) and an infinite number of odd
digital byte of 01011010 are represented in
harmonics. This is illustrated in Equation (1):
Figure 1:

4 1
f (t ) =
n=1,3,5,... n
sin(2nft ) 0 1 0 1 1 0 1 0

(1)

This is very demanding of bandwidth, nominally

infinite.

On the other hand, analog signaling does not

require infinite bandwidth. Analog signaling, at a
basic level, involves modulating the digital data
onto an analog carrier. The analog carrier uses Figure 1: Digital Data and Corresponding FSK
Signal
only a specified band of the transmission
medium. A common technique used with analog
signaling is Frequency Shift Keying (FSK). This
type of modulation involves the use of two Implementation with PSoC
frequencies. One frequency is used to represent It is possible to implement an FSK generator
a digital 1, while another frequency is used to using only the PSoC device. The following PSoC
represent a digital 0. FSK can be mathematically Designer User Modules are required in order to
modeled by Equation (2): build the application:

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 AN2098

Two 8-Bit Pulse Width Modulators The band-pass filter controls the level of the
(PWM) fundamental and attenuates the harmonics to an
One 2-Pole Band-Pass Filter (BPFV2) acceptable level.

Along with the required encoding resources, it is PSoC Designer version 3.20 (or later) includes
necessary to generate the FSK signal. This is filter wizards and spreadsheets to aid in the filter-
possible through a variety of User Modules design process. For this particular application,
available including an 8-Bit Transmitter (TX), SPI, the following parameters are desired for the
or directly through software. band-pass filter when the data is a digital 1:

In this FSK generator example, a digital 1 is 150 kHz Center Frequency

represented by a sinusoid of 150 kHz and a 20 kHz Bandwidth
digital 0 is represented by a sinusoid of 75 kHz. -6 dB Mid-Band Gain
Figure 2 shows the block diagram of the PSoC- Over Sampling Ratio of 10
implemented FSK generator:
With these parameters, the following capacitor
and clock values are calculated by the
6MHz 1
spreadsheet:
PWM8_1
PWM8_2
48MHz clock 3MHz 0
40
8 for digital 1
16 for digital 0 C1 = 1
(Software Controlled)
C2 = 21
75kHz 0 150kHz 1 C3 = 18
C4 = 31
BPF2V_1
CA = 32
Band Pass Filter
FSK Out CB = 32
Center Frequency of
150kHz for digital 1
Center Frequency of
Sample Clock = 1.5 MHz
75kHz for digital 0

The magnitude frequency response of the band-

Figure 2: Block Diagram of FSK Generator pass filter is shown in Figure 3:

The two PWMs are combined to generate

transmitted square waves. These square waves
are then fed into the band-pass filter. The center
frequency of the band-pass filter is adjusted from
75 kHz to 150 kHz. The output of the filter is a
sinusoid of either 150 kHz or 75 kHz.

Pulse Width Modulators

As shown in Figure 2, PWM8_1 divides the input
clock (in this case, 48 MHz) to a fixed multiple of
the output carrier. The division of PWM8_1 is
adjusted in an interrupt routine, which is
dependent on the data to be transmitted.
PWM8_2 divides the output of PWM8_1 by a
fixed number (in this case, 40). The output of
PWM8_2 feeds the band-pass filter. The output Figure 3: Magnitude Frequency Response of the
of PWM8_1 also clocks the band-pass filter. Band-Pass Filter
Note that PWMs divide by N+1, where N is the
value written to the period parameter.
Using the attached spreadsheet, note that the
center frequency of the filter is designed a few
Band-Pass Filter percent high to compensate for finite gain
The PWM output is a square wave with a bandwidth effects in the filter. Lower center
fundamental frequency as set by the period frequencies do not require this compensation.
parameter. The fundamental level is 4/ * peak
voltage. The square wave also includes odd
harmonics of the fundamental.

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 AN2098

Main Routine GPIO Interrupt

Modification for a Digital 0 Initialize all user

modules
Receive GPIO
interrupt

At this point, it might look like this application will

only produce a 150 kHz sinusoid. How many Check the state of
the external pin
modifications are needed to produce a 75 kHz (output of the third
PWM)
sinusoid? Fortunately, the answer is only one!
Enable GPIO
interrupt for
One of the nice features of the PSoC band-pass change of state
and enable all Digital 1
Write a 16 to the
period of the first

filter is that the sampling clock controls the center interrupts No

PWM (75kHz
sinusoid)

frequency. If the sampling frequency is halved, Yes

the center frequency is subsequently halved. Write an 8 to the
Therefore, in order to obtain a 75 kHz center period of the first
PWM (150kHz
frequency (half of 150 kHz), the sampling clock of sinusoid)

the band-pass filter should be halved. This is Loop forever

achieved by setting PWM8_1 to divide by 16 End Interrupt

instead of 8.

Generating Data Figure 4: Software Flow Chart

This FSK generator example uses a third pulse

width modulator to generate mock digital data.
PWM8_3 is placed in digital block DCA07. The
output is routed to Global Output #7 on pin 5. In
actual applications, the mock data produced by
the PWM is substituted by real data. To make
this change, the user only has to replace
PWM8_3 with the desired data source. The FSK
generator needs no further modification.
Software
The software required to run this FSK generator
is simple and short. First, the User Modules need
to be initialized and started. Next, a polling loop
or interrupt must be established in order to
control the transmission of a digital 1 or 0. In this
example, the General Purpose I/O (GPIO)
interrupt is enabled to control the FSK generator.
The GPIO interrupt is set up for trigger on
change. It monitors the output of the third PWM
(pin 5). The basic flow chart is illustrated in
Figure 4:
Main Routine
In this FSK generator example, main.asm
includes several breakpoints. These breakpoints
are intentionally placed in order to allow the user
to view the FSK waveforms on an oscilloscope.
In the Debugging subsystem of PSoC Designer,
the FSK generator will begin transmitting at 150
kHz. After encountering the first breakpoint and
continuing, the FSK generator will transmit at 75
kHz. Finally, after continuing past the final
breakpoint, the FSK generator will toggle
between 150 kHz and 75 kHz, following the
digital data provided by PWM8_3.
Evaluation
At this point, the PSoC-implemented FSK
generator has been built. Now it is time to test the
project and confirm proper functionality. With the
use of an oscilloscope, the following two figures
illustrate the 150 kHz and 75 kHz output of the
band-pass filter:

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Figure 5: 150 kHz Sinusoid Output of the Band-Pass
Filter
Figure 6: 75 kHz Sinusoid Output of the Band-Pass
Filter
It is evident through the above figures that the
output sinusoids are not perfect, but are they
good enough for the application? In order to
answer this question, it is necessary to study the
frequency content of these sinusoids. The
following two figures show the frequency
spectrum of the output sinusoids:
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AN2098
Figure 7: Spectral Plot of the 150 kHz Sinusoid
Figure 8: Spectral Plot of the 75 kHz Sinusoid
The arrows in the previous figures point to the
first harmonic on both of the sinusoids (n=3 in
Equation (1)). In both sinusoids, the first
harmonic is attenuated by a factor of 30 dB,
which is more than adequate for an FSK
generator. Even though the output sinusoids are
not pure, the harmonics are attenuated enough to
meet the requirements of this application.
Additional filtering with a single, external high-
pass, RC filter at three times the band-pass filter
center frequency will further reduce the upper
harmonic content.
The final requirement that needs to be verified is
if the output of the FSK generator actually tracks
the input digital data. Figure 9 displays both the
digital data waveform (PWM8_3) and the FSK
signal:
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 AN2098

Figure 9: Digital Data and Corresponding FSK

Signal

As evidenced by the above figure, the output of

the FSK-generated signal does indeed track with
the input digital data.

Conclusion
With the use of two digital blocks, two switched
capacitor analog blocks, and minimal software,
the PSoC device successfully implements an
FSK generator.

Cypress MicroSystems, Inc.

22027 17th Avenue S.E. Suite 201
Bothell, WA 98021
Phone: 877.751.6100
Fax: 425.939.0999
http://www.cypressmicro.com/ / http://www.cypress.com/aboutus/sales_locations.cfm / support@cypressmicro.com
Copyright 2002 Cypress MicroSystems, Inc. All rights reserved.
PSoC (Programmable System on Chip) is a trademark of Cypress MicroSystems, Inc.
All other trademarks or registered trademarks referenced herein are property of the respective corporations.
The information contained herein is subject to change without notice.

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