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PD - 91810

SMPS MOSFET IRFIB7N50A


HEXFET Power MOSFET
Applications
l Switch Mode Power Supply ( SMPS )
VDSS Rds(on) max ID
l Uninterruptable Power Supply 500V 0.52 6.6A
l High speed power switching
l High Voltage Isolation = 2.5KVRMS

Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current GDS
TO-220 FULLPAK
l Effective Coss specified ( See AN 1001)

Absolute Maximum Ratings


Parameter Max. Units
ID @ TC = 25C Continuous Drain Current, VGS @ 10V 6.6
ID @ TC = 100C Continuous Drain Current, VGS @ 10V 4.2 A
IDM Pulsed Drain Current 44
PD @TC = 25C Power Dissipation 60 W
Linear Derating Factor 0.48 W/C
VGS Gate-to-Source Voltage 30 V
dv/dt Peak Diode Recovery dv/dt 6.9 V/ns
TJ Operating Junction and -55 to + 150
TSTG Storage Temperature Range C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting torqe, 6-32 or M3 screw 10 lbfin (1.1Nm)

Applicable Off Line SMPS Topologies:

l Two Transistor Forward


l Half & Full Bridge Convertors
l Power Factor Correction Boost

Notes through are on page 8


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6/15/99
IRFIB7N50A
Static @ TJ = 25C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 500 V VGS = 0V, ID = 250A
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient 0.61 V/C Reference to 25C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance 0.52 VGS = 10V, ID = 4.0A
VGS(th) Gate Threshold Voltage 2.0 4.0 V VDS = VGS, ID = 250A
25 VDS = 500V, VGS = 0V
IDSS Drain-to-Source Leakage Current A
250 VDS = 400V, VGS = 0V, T J = 125C
Gate-to-Source Forward Leakage 100 VGS = 30V
IGSS nA
Gate-to-Source Reverse Leakage -100 VGS = -30V
Dynamic @ TJ = 25C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 6.1 S VDS = 50V, ID = 6.6A
Qg Total Gate Charge 52 ID = 11A
Qgs Gate-to-Source Charge 13 nC VDS = 400V
Qgd Gate-to-Drain ("Miller") Charge 18 VGS = 10V, See Fig. 6 and 13
td(on) Turn-On Delay Time 14 VDD = 250V
tr Rise Time 35 ns ID = 11A
td(off) Turn-Off Delay Time 32 RG = 9.1
tf Fall Time 28 R D = 22,See Fig. 10
Ciss Input Capacitance 1423 VGS = 0V
Coss Output Capacitance 208 VDS = 25V
Crss Reverse Transfer Capacitance 8.1 pF = 1.0MHz, See Fig. 5
Coss Output Capacitance 2000 VGS = 0V, VDS = 1.0V, = 1.0MHz
Coss Output Capacitance 55 VGS = 0V, VDS = 400V, = 1.0MHz
Coss eff. Effective Output Capacitance 97 VGS = 0V, VDS = 0V to 400V
Avalanche Characteristics
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energy 275 mJ
IAR Avalanche Current 11 A
EAR Repetitive Avalanche Energy 6.0 mJ
Thermal Resistance
Parameter Typ. Max. Units
RJC Junction-to-Case 2.1
RJA Junction-to-Ambient 65 C/W
Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
D
IS Continuous Source Current MOSFET symbol
6.6
(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

44
(Body Diode) p-n junction diode. S

VSD Diode Forward Voltage 1.5 V TJ = 25C, IS = 11A, VGS = 0V


trr Reverse Recovery Time 510 770 ns TJ = 25C, IF = 11A
Qrr Reverse RecoveryCharge 3.4 5.1 C di/dt = 100A/s
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRFIB7N50A

100 100 VGS


VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
I D , Drain-to-Source Current (A)

I D , Drain-to-Source Current (A)


7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
BOTTOM 4.5V BOTTOM 4.5V
10

10

4.5V 20s PULSE WIDTH 20s PULSE WIDTH


TJ = 25 C 4.5V TJ = 150 C
0.1 1
0.1 1 10 100 1 10 100
VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

100 3.0
ID = 11A
RDS(on) , Drain-to-Source On Resistance
I D , Drain-to-Source Current (A)

2.5

10 2.0
(Normalized)

TJ = 150 C

1.5

TJ = 25 C
1 1.0

0.5

V DS = 100V
20s PULSE WIDTH VGS = 10V
0.1 0.0
4.0 5.0 6.0 7.0 8.0 9.0 -60 -40 -20 0 20 40 60 80 100 120 140 160
VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature ( C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance


Vs. Temperature
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IRFIB7N50A

2400 20
V GS = 0V, f = 1M Hz ID = 11A
6.6A
C is s = C g s + C g d , Cd s S H O R T E D
VDS = 400V
C rss = C gd

VGS , Gate-to-Source Voltage (V)


2000 VDS = 250V
C oss = C ds + C gd 16 VDS = 100V
C is s
C , C a pa c itan c e (p F )

1600
C oss 12

1200

8
800

C rs s 4
400

FOR TEST CIRCUIT


SEE FIGURE 13
0 A 0
1 10 100 1000 0 10 20 30 40 50
V D S , D rain-to-S ource V oltage (V ) Q G , Total Gate Charge (nC)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.


Drain-to-Source Voltage Gate-to-Source Voltage

100 1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
ISD , Reverse Drain Current (A)

100
I D , Drain Current (A)

10
10us
TJ = 150 C
10
100us

1 1ms
TJ = 25 C 1
10ms
TC = 25 C
TJ = 150 C
V GS = 0 V Single Pulse
0.1 0.1
0.0 0.4 0.8 1.2 1.6 10 100 1000 10000
VSD ,Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area


Forward Voltage
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IRFIB7N50A

7.0 RD
VDS

6.0 VGS
D.U.T.
RG
+
I D , Drain Current (A)

5.0 -VDD

4.0 10V
Pulse Width 1 s
Duty Factor 0.1 %
3.0

Fig 10a. Switching Time Test Circuit


2.0

VDS
1.0
90%

0.0
25 50 75 100 125 150
TC , Case Temperature ( C)
10%
VGS
Fig 9. Maximum Drain Current Vs. td(on) tr t d(off) tf
Case Temperature
Fig 10b. Switching Time Waveforms

10
Thermal Response (Z thJC )

D = 0.50
1

0.20

0.10
P DM
0.05
0.1
t1
0.02
t2
0.01
SINGLE PULSE Notes:
(THERMAL RESPONSE) 1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRFIB7N50A

600
1 5V ID

EAS , Single Pulse Avalanche Energy (mJ)


TOP 4.9A
500 7.0A
L D R IV E R BOTTOM 11A
VDS

400
RG D .U .T +
V
- DD
IA S A
300
20V
tp 0 .0 1

200
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D SS
tp 100

0
25 50 75 100 125 150
Starting TJ , Junction Temperature ( C)

IAS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
QG

10 V
660
QGS QGD
V D S a v , Avalanche V oltage (V)

VG
640

Charge
Fig 13a. Basic Gate Charge Waveform 620

Current Regulator
Same Type as D.U.T.

50K 600
12V .2F
.3F

+
V
D.U.T. - DS
580 A
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
VGS
I av , A valanche C urrent (A )
3mA

IG ID
Current Sampling Resistors Fig 12d. Typical Drain-to-Source Voltage
Fig 13b. Gate Charge Test Circuit Vs. Avalanche Current
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IRFIB7N50A

Peak Diode Recovery dv/dt Test Circuit

+ Circuit Layout Considerations


D.U.T
Low Stray Inductance
Ground Plane

Low Leakage Inductance
Current Transformer
-

+


- +
-


RG dv/dt controlled by RG +
Driver same type as D.U.T. VDD
-
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test

Driver Gate Drive


P.W.
Period D=
P.W. Period

VGS=10V *

D.U.T. ISD Waveform

Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD

Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent

Ripple 5% ISD

* VGS = 5V for Logic Level Devices

Fig 14. For N-Channel HEXFETS

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IRFIB7N50A
Package Outline
TO-220 Fullpak Outline
Dimensions are shown in millimeters (inches)
10 .6 0 (.41 7) 3.40 ( .1 33 )
4.8 0 (.1 89)
10 .4 0 (.40 9) 3.10 ( .1 23 ) 4.6 0 (.1 81)
2 .80 ( .110)
-A - 2 .60 ( .102)
3.70 ( .145 ) LE A D A S S IG N M E N T S
3.20 ( .126 ) 7.10 ( .280 ) 1 - GA TE
6.70 ( .263 ) 2 - D R A IN
3 - SO UR CE
1 6.00 (.630)
1 5.80 (.622)
1.1 5 (.04 5) NOT ES :
M IN .
1 D IM E N S IO N IN G & T O LE R A N C IN G
P E R A N S I Y 14 .5M , 19 82
1 2 3
2 C O N T R O LLIN G D IM E N S IO N : IN C H .
3.3 0 (.130 )
3.1 0 (.122 )
-B -
1 3.70 (.540)
1 3.50 (.530)
C
D

A
0.4 8 (.019 ) B
0.9 0 (.035 ) 3X
1.4 0 (.05 5) 3X 0.4 4 (.017 )
3X 0.7 0 (.028 )
1.0 5 (.04 2) 2.85 ( .112 )
0.25 (. 010) M A M B 2.65 ( .104 ) M IN IM U M C R E E P A G E
2.54 (.100 ) D IS T A N C E B E T W E E N
2X A - B - C -D = 4.80 (.1 89)

Part Marking Information


TO-220 Fullpak
E X A M P L E : T H IS IS A N IR F I8 4 0 G
W IT H A S S E M B L Y
A
LOT CODE E401
IN T E R N A T IO N A L PART NUMBER
R E C T IF IE R IR F I8 4 0 G
LO GO
E 401 9245
ASSEMBLY DA TE CO D E
LO T CO DE (Y YW W )
YY = YE A R
W W = W EEK
Notes:
Repetitive rating; pulse width limited by Pulse width 300s; duty cycle 2%.
max. junction temperature. ( See fig. 11 )
Coss eff. is a fixed capacitance that gives the same charging time
Starting TJ = 25C, L = 4.5mH as Coss while VDS is rising from 0 to 80% VDSS
RG = 25, I AS = 11A. (See Figure 12)
Uses IRFB11N50A data and test conditions
ISD 11A, di/dt 140A/s, VDD V(BR)DSS, t=60s,f=60Hz
TJ 150C

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IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
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IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 838 4630
IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
http://www.irf.com/ Data and specifications subject to change without notice. 6/99
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