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ECC-3231 Project Two-

Metal Oxide Semiconductor Field Effect
Transistor (MOSFET) Amplifier
Mary Romero, Undergraduate, and Quangvu Nguyen, Undergraduate
UNC-Charlotte Electrical and Computer Engineering Department
o o AC Gain
Abstract This report a o RInput
outlines the design and d o ROutput
implementation of a common
source amplifier circuit. The L Construction and
requirement specifications for i
the circuit were a minimum n Test in Lab
gain of 6 V/V, a voltage swing e o DC Biasing
of 5 V peak-to-peak, and o Transient Response
power consumption below 75 o o AC Gain
mW. The design and o RInput
implementation consisted of A o ROutput
DC and AC analysis, PSpice
C o Must
simulation, and build and test
circuit in the laboratory. demonstrat
G e to
a Professor
I. i
o ROutput ANALY
THE Metal Oxide
Semiconductor Field Effect
PSpice Simulation
A. DC Biasing

Transistor (MOSFET) Amplifier of Amplifier

is an four terminal device, which o DC Biasing To meet the requirement
has to be operated on the specifications for the
saturation region to provide a o Transient
linear amplification. The Response amplifier, a common-source
requirement specifications for amplifier was chose. The
the amplifier
are: circuit diagram is shown in
Submitted November 30, 2015. figure 1.
Av = Vo/Vi 6 V/V This work was supported in part by
the Electrical and Computer
oCox (W/L) = 650 Engineering Department of UNC
2 Charlotte.
Mary Romero is an
|VA| = 200 V undergraduate pursuing a Bachelor
of Science in Electrical Engineering,
RL = 20k University of North Carolina at
Charlotte, Charlotte, NC 28223 USA
VCC = 15V (rail (e-mail:
voltage) Quangvu Nguyen is an
undergraduate pursuing a Bachelor
Power Consumption of Science in Electrical Engineering,
= VDD*IDD 75 mW University of North Carolina at
Charlotte, Charlotte, NC 28223 USA
Swing 5V peak- (e-mail:

RInput = any value Fig. 1 Common-source Circuit
ROutput = any value
A commonly use design is
In order to meet the to make the gate voltage to
requirements for the design. be in the ratio between one-
The design was divided into fifth and one-third of V DD;
three parts consisting of the therefore, the gate voltage
following: was set to 5V. Applying
Hand Analysis voltage divider rule the value
o DC Biasing for R1 was calculated as
o follow:

A =


v =


(15 )(33 )


When VDS = 0
For linear amplification, the MOSFET has to operate in the
saturation region. The current through the drain and source in
saturation region is calculated as shown below. =

= 12 ( )( )2 = = 1.2

2.6 + 9.8

The project specification sheet gave the values of

2 When IDS = 0
oCox(W/L) and VT as 600 A/V and 1.40 V, respectively.
The gate-source voltage was calculated using the following == 15

equation: =

Where the source voltage (V S) was set equal to 2 V to help

DC Load Line
open the gate above the threshold voltage; therefore:
1 2
= (600 ) (3 1.4 ) = 768


In addition, a commonly used design to maximize the swing 0.5

of the output voltage is to set the drain voltage to be half of the
value of VDD. Kirchhoffs voltage and nodal analysis were
used to find the values of RD and RS, respectively. 0

= =
15 7.5
= 9.8 0 5 10 15 20
768 VDS (volts)

= = = 2.6 Fig. 3 DC Load Line Graph

The power consumption was calculated using the following
formula, which was under the requirement specification. A. AC Equivalent
In this step, the voltage gain of the amplifier circuit was
= ( +

) calculated. The original circuit shown in Fig. 2 was
transformed into a hybrid PI equivalent circuit to perform
the analysis. The model can be found in Fig 4.
15 5
= 15 (768 +
) = 1.38


The resulting resistors values led to the schematic shown

Fig. 4 Hybrib Pi Model For Common-source MOSFET Amplifier

The following calculations were made:

= = 600 ( )

= 600 (3 1.4) = 9.6 104

= = = 260.4

7.68 10

66 33
1 2

= = = 22

1 + 2 66 + 33

9.8 260

= = = 9.4

Fig. 2 Design Common-source Amplifier

+ 9.8 + 260

(( )) = = 6.6

B. DC Load Line +

The load line equation was found using Kirchhoffs voltage ( ( )=

= 6.6

law across the drain-source loop.

15 + ( + )+ =0

= = ( ( ) = 9.6 10 4 6.6

= 6.336
A. DC Analysis
B. AC Load Line A simulation was run to obtain the DC currents and
voltages. The schematic with the simulated DC currents and
Observed from reference 1, the equations to perform the voltages is shown in figure 7. The currents and voltages were
AC load line analysis were: found to be within the acceptable percent error from the
=+ ( )

calculated values.
= 5.5 + 7.60 10 (6.6 ) = 10.516

=+ = 7.60 104 +

( )

= 1.6

From these two points, the AC load line was plot,

AC Load Line
2 0, 1.6

1 y = -0.1524x + 1.6 Fig. 7 PSpice Simulated DC Currents and Voltages

0.5 10.5, 0 Table 1. Percent Error Calculations between Hand-calculated

0 and Simulated Values
0 5 10 15 Measurement Hand PSpice % Error
VDS (volts)
VG (V) 5 5 0
VS (V) 2 2.015 0.75
Fig 5. AC Load Line Plot VD (V) 7.5 7.406 1.25
IDS (A) 768 774.9 0.89
One of the parameters of interest during the designs process
was the quiescent point. To determine the point, the two load B. AC Analysis
lines were sketched on a same plot. The point of the For the AC analysis, the AC signal sweep was run. The
intersection between the two lines determined the quiescent plots of the gain vs. frequency in magnitude and dB are shown
point. The plot was shown below: in figures 8 and 9, respectively.

Fig. 8 Gain in Volts vs. Frequency

Fig 6. Queiscent Point

The quiescent point was determined when V DS = 5.525 V

and IDS = 0.758 mA. At these points, it was suggested the
signal can be amplified without any attenuation.
Fig. 9 Gain in dB vs. Frequency
PSpice simulation was used to verify that the hand The low 3dB frequency was found by subtracting 3 dB from
calculations made satisfy the requirement specifications before the frequency at which the output voltage star to being
building the circuit in the laboratory. Using PSpice, DC constant. The low 3 dB frequency was found to be 1.91 Hz.
analysis, AC analysis, and Transient analysis were performed. The maximum gain was found to be 6.26 V/V; which was
slightly higher than the hand calculated. The percent error

between the calculated and simulated gain was 1.19%. Fig. 12 Output Impedance vs. Frequency

The phase vs. frequency plot is shown in figure 10. This Table 2. Percent Error Calculations between Hand-calculated
plot shows the phase shift differences across the gain region of and Simulated Values
the amplifier. Measurement Hand PSpice % Error
Gain -6.16 -6.26 1.62
Rin 22 k 22 k 0
Rout 9.44 k 9.8 k 3.81

C. Transient Analysis
For the transient analysis the input signal was set to 1 V
peak-to-peak. The output voltage was found to be 6.16 V
peak-to-peak. The waveform show that the amplifier was
Fig. 10 Phase vs. Frequency providing a linear amplification with no clipping on the
The input impedance is the voltage divider equivalent
resistance looking at the gate and is calculated as follow:

(66 )(33 )
= 1 2
= = 22

(66 ) + (33 )

1 +2

The output impedance is calculated using the following

Fig. 13 Transient Analysis

| |
Where = = = 260

The circuit shown in Fig 2 was constructed. The signal
source was replaced by sinusoidal source. The source was set
Therefore, = 9.44
up with the amplitude of 800 mV peak-to-peak. The frequency
was at 1 kHz. Because a 9.8 k resistor (R D) was not
The plots of the input and output impedances versus available, a 10 k resistor was used instead. The circuit was
frequency are shown in figures 11 and 12, respectively. Input carefully inspected before the power supply was turned on.
impedance increases as frequency decreases because of the The following measurements were obtained.
low pass filter. The output impedance also increases as the Voltage Gain:
frequency decreases due to the RC time constant on the output. The voltage gain of the amplifier circuit was recorded and
shown below:

Fig. 11 Input Impedance vs. Frequency

Fig 14. Input and Output Signals

The above figure has shown that the voltage gain of the
amplifier was met the designs specification. Which was,
5.1mV/840 mV = 6.07 V.

Signals swing:

The amplitude of the signals swing can be seen from Fig 14. VG 5 4.87 2.60
It was indicated the signal successfully swing from a -2.71 V VGS 3 2.73 9.00
to a 2.44 V. From the experiment, it was observed that the
swing of the signal was approximately symmetric. IDS(mA) 0.768 0.77 0.26
Rin(K) 22 25 13.64
Input Resistance: Rout(K) 9.6 10.4 8.33
To calculate the input resistance, the circuit shown in Fig 2 Gain 6.33 6.07 4.11
was modified. A coupling capacitor and a 1K resistor were
added to the gate terminal of the MOSFET. The set up can be Discrepancies:
found in the below figure: From the above table, the results were within the expected
percent error. The gain of the amplifier circuit was
successfully archived within a 5 % error. The other parameters
were off by almost a 10 % error. This happened because the
resistor RD used in the lab was 10 k instead of 9.8 k. Also,
the Kn factor of the MOSFET were different from the


Fig 15. Input Resistance Measurement Setup
The design specifications were met. However, the percent
The voltage across the 1 k was measured. The input resistance was found error between the calculations and the measurements results of
by relating the resistance to the current of the branch. The input voltage Vin
was measured to be 1.01 V. Then, the current through the branch was some parameters were off. During the testing phase, it was
calculated, = observe that the capacitance value have affected on the gain of

1.05 1.01

= 4 105 . Thus, the input resistance the circuit. Thus, a small capacitor value (1F) was selected to

prevent the issue and yielded a better result.

was, = = 25 .

The result from the lab session has shown that the
Output Resistance: symmetrical swing of the signal was not observed. In the
future design, the designer should add a negative rail power
supply to the transistor. This can help to improve the
symmetry of the signals swing.

The objectives of this project were met. The gain of the
amplifier circuit was measured to be 6.07. The signal was able
to have a 5 V peak-to-peak swing. The power consumption
was less than 75 mW. The measurement results have shown
Fig 16. Output Resistance Measurement Setup that VD = 7.7V, this yielded a 2.67% of difference from the
initial assumption. VDS was measured to be a 5.02 V, which
A 1 k resistor and a 0.1 F coupling capacitor were added was matched to the assumption. The source voltage Vs was
to the drain terminal of the MOSFET amplifier circuit. The measured to be 2.14 V, which was within the expected error of
voltage Vout was measure to be 0.94 V. Then, the output 7%. In general, most of the assumptions that were made to
current was calculated as, =

1.03 0.94

= 0.09 . determine the resistor value were valid.


Thus the output resistance calculated as, = =

10.4 .

[1] Adel S. Sedra, MOS Field-Effect Transistors (MOSFETs), in

A table displayed the percent error between the calculations Microelectronic Circuits,6th ed. New York, United States
and the measurements results:
[2] ECE Lab 10 Manual, ECGR 3155, MOSFET Amplifier
Input/output Impedances,
Table 2. Calculations and Measurements % Error MOSFET
Theoretical Measured %Error Amplifier Input-Output Impedances.pdf

VD(V) 7.5 7.7 2.67

VDS 5.5 5.02 8.73
VS 2 2.14 7.00