DIgSILENT Modelling of Power Electronic
Converters for Distributed Generation Networks
under Unbalanced Voltage Conditions
R. Kabiri D. G. Homes
School of Electrical and Computer Engineering
RMIT University, Melbourne, Australia
roozbeh.kabiridehkordi@rmit.edu.au
Abstract Distributed generation systems have changed
the conventional electrical system topology while
incorporating small scale energy sources at distribution
level power electronic based. One of the side effects of
distributed generation in LV feeders is unbalanced voltages
that emerge due to unbalanced generation as well as
unbalanced loading. On the other hand, study of this type of
systems has become a challenge as it is required to consider
power system network as well as power electronic systems
together. Usually simulation packages that are being used
for modeling of these systems are only focused on one
aspect, power system or power electronics part. There are a
few packages that are capable of managing both aspects at
the same time but still there is a lack of studies for detailed
modeling of these systems. This paper investigates detailed
modeling in DIgSILENT for distributed generation systems
under unbalanced voltage conditions which can be used for
PV systems, energy storage systems and etc. in LV feeders
to support voltage profile of feeder. Detailed modeling and
time domain simulation results are provided in this paper.
Keywordsdistributed generation, unbalanced voltages,
DIgSILENT
I. INTRODUCTION
Distributed generation has changed the paradigm of
electrical system incorporating the new technologies to
take advantage of green energies such as wind and solar.
This has opened a new era to investigate the impact of
small scale production units on the voltage stability of the
grid [1].
Traditionally, Distributed Generation (DG) systems
are modelled as simplified models such as a reactance
behind a source and sometimes more detailed such as
average model in power system studies. The lack of
inclusion of detailed power electronic systems limits the
investigation domain such as investigating the adverse
interaction between DG units. Also, it is important to be
able to study the interaction between DG units and the
electrical system, interactions like impact on protection
system and harmonic contribution (both low and high
frequency harmonics). In addition, the control concepts,
strategies, and dynamic characteristics of power electronic
converters are significantly different from rotating
machine transients and dynamics, indicating that a more
detailed presentation of such inverters is necessary.
On the other side, in power electronic studies, the
detailed model of DG unit with corresponding controller
B. P. McGrath
algorithm are designed. This level of modelling increases
the complexity of the system and does not allow to extend
the simulation model by adding other elements such as
power systems components. It is a common practice to
consider an impedance connected to a voltage source to
model the grid side of a DG system. Thus, the DG impact
on the grid is only investigated at the Point of Common
Coupling (PCC).
To achieve the most accurate approach to investigate
the behavior of power systems, a time-domain simulation
is required. The dynamics of synchronous generators vary
from hundreds of milliseconds to a few seconds.
Meanwhile inverter based DG systems have very fast
dynamic responses varying from hundreds of
microseconds to several milliseconds. This time scale
differences requires special simulation platforms capable
of investigating the transient stability of power systems in
an accurate manner [2].
Therefore, it is required to create a platform which
allows investigation of impact of DG systems on electrical
distribution network, while the system is modelled as
detailed as possible. In particular, studies which are
investigating short periods of time/fault conditions and
unbalanced voltage conditions. The unbalanced voltage
conditions can be caused by unbalanced/nonlinear loads,
single phase DG units and remote grid faults. It is
considered as one of the most important issues of power
quality which can cause adverse effect on the power
system such as transformer overloading, electrical
machine overheating, increased losses, stability issues and
overloading power electronic devices [3].
In this paper these issues are addressed, by developing
a detailed model of a DG inverter system within the power
system analysis package DIgSILENT [4]. In this model a
DIgSILENT switch inverter block is used including a
detailed leading edge closed loop current regulator under
unbalanced voltage conditions. The model is based on an
existing inverter model developed in PSIM and then
experimentally validated [5]. The outcome of this detailed
model provides a platform that is capable of combining a
validated accurate inverter model with a detailed model of
a network grid. This platform allows to efficiently explore
the overall system and multiple DG responses to a variety
of network transient events, in particular, during
unbalanced voltage conditions.
 II. THREE-PHASE DG CONVERTER MODEL i inv ig PCC
VDC
The DG converter model is a standard three phase Lf Lfg Z grid
Voltage Source Inverter (VSI). The connection of the

Utility
Grid
converter to the grid network is via an LCL filter, as
shown in Fig. 1. Cf
VDC
The high level PQ controller calculates current
references to inject a certain amount of real and reactive
power based on the measured grid voltages. The low level
PWM Modulator Current and
current controller then generates the Pulse Width
(Switch Commands) Voltage Sensors
Modulator which creates the switching commands for
each phase leg of converter. Note that the PQ Controller
and current controller should be designed to operate PQ Controller with Integrated Current
smoothly under unbalanced voltage conditions. Controller

A three-wire system is modeled for this study rather Fig. 1. Structure of a three phase VSI used for a DG system.
than a four-wire system because only three-wire PWM
Converter model is available in DIgSILENT. However,
Finally, based on the method presented in [5], the SRF
it is shown that when the zero sequence currents are
target sequence current references can be determined
eliminated the three-wire scenario is consistent with four-
using:
wire topology [6]. Therefore, this paper conclusions can

be readily applied to a system with four-wire topology. __ + _ + _

There are different strategies in literature that can be __ + _ _
= [ ]
used for high level controller to generate current
__
_
+ _
references [5]-[8] which mainly corresponds to the frame
[__ ] [ _ _ ]
of reference to be stationary or rotating frame. For this
2 )2 (( )2 + ( )2 )
study, the presented method in [5] is used. Commonly, the = (_ ) + (_ _ _
{ 2 )2 + (( )2 + ( )2 )
low level controller (current controller) depends on higher = (_ ) + (_ _ _
level controller frame of reference. As synchronous
reference frame (SRF) is used for calculation of 1 < < +1 (5)
commanded currents, current controller also requires PSRF and NSRF denote the positive and negative
employing SRF. As unbalanced voltage conditions need frames of reference, d [q] identify the direct [quadrature]
negative sequence component control as well as positive axes; and p [n] identify the positive [negative] sequence
one, Double SRF (DSRF) is used in this study [9]-[12]. components. In (5) three objectives can be achieved: 1)
There are two common strategies used in DSRF: 1) eliminating real power ripple (K=+1), 2) eliminating
Decoupled DSRF (DDSRF) which requires extracting reactive power ripple (K=-1), 3) and balancing the three
positive and negative sequence components [9] and 2) phase currents injected into the unbalanced grid voltages
DSRF without sequence extraction [10] which is used in (K=0), can be achieved.
this study.
B. Low Level Current Controller
III. CONTROL SCHEME FOR THREE-PHASE DG SYSTEM The current controller in DSRF is based on the method
presented in [10] which requires no sequence separation
A. High Level PQ Controller
of sequence components of measued currents. It is
In order to extract the positive and negative sequence achieved by projection of the PSRF [NSRF] onto the
components of measured voltages, the stationary abc NSRF [PSRF]:
frame voltages are transformed to the stationary frame

and then extracted using: __ = [2 ]. [2 ]__ (6)

__ = [2 ]. [2 ]__ (7)
1 0.5 0.5
[ ] = [ ] [ ] (1)
0 3/2 3/2 and then adding this AC component to the DC component

of the corresponding frame of reference.
1 1
[ ] = [ ] [ ]
2 1 _ =
(2) __ +
__
1 1
[ ] = [ ] [ ]
(8)
2 1
_ =
__ +
__
where i denotes a 90 time domain shift at 50 Hz. To
o
{
operate in SRF, following equations can be used to
_ =
__ +
__
transform sequence quantities into their respective

positive and negative SRFs: (9)
_ =
__ +
__
cos() sin() {
[ ] = [ ] [ ] = (+)[ ] (3)
sin() cos()
Now, the measured currents are transferred to the
cos() sin() positive and negative SRF, then applying the PI controller
[ ] = [ ] [ ] = ()[ ] (4)
sin() cos() with active damping of the filter capacitor current,
modulation indexes are created. Fig. 2 presents the overal
 PSRF
P ref i dPSRF PmA
_ ref PmdPSRF PCC
uabc

Microgrid
Rf Lf iabc Rfg Lfg

dq_ PI
Q ref i PSRF
PSRF
d

i qPSRF PmqPSRF to abc PmB

K _ ref

Equation (5)

i PSRF
q
abc abc
PLL Seq.
dq+,dq- dq+,dq- Extraction
Cf
NSRF 1/s
i dNSRF
_ ref
PmdNSRF
H(s)

dq_ PI

icdNSRF
icdPSRF

i dNSRF
i dPSRF
idNSRF NSRF
i qNSRF PmqNSRF to abc

v dNSRF
v dPSRF
_ ref

i qNSRF
i qPSRF
icqNSRF
ic qPSRF

_n
_q
iqNSRF

v qNSRF
v dPSRF
_n
_ p
Fig. 2. Schematic diagram of the three-phase DG unit and its corresponding control architecture.

control system of grid connected inverter. The controller eliminated from forward pass, maintaining stable control
transfer function is while PI regulator gains are substantially increased.
1
() = (1 + ) (10) Using method presented in [13], the maximum and

minimum possible damping gains can be computed. Fig.4
Using the methodology proposed in [10], the shows the loci branches drawn for a full range of damping
maximum possible gains can be calculated. For the gains. The damping gain can be set to approximately
proportional gain the calculated value is midway between these two values.
( + )
(11) IV. IMPLEMENTATION IN DIGSILENT
2

where and are the inverter-side and grid-side filter The three phase inverter mentioned above is
implemented in DIgSILENT PowerFactory package. The
inductances, is half the DC bus voltage and is
power system model is shown in Fig. 5. The PWM
critical frequency, to achieve an adequate stability phase
Converter/2 DC-Connections model is used for the
margin. According to [13] the controller crossover
inverter modelling. For detailed modelling of the inverter
frequency should be set to = 0.3 ( is the
down to the switching system, in the EMT-Simulation tab
+
resonant frequency of the LCL filter: = ). of the PWM Converter the Detailed Model is selected. In

the same tab, the Modulation Frequency (switching
Lastly, the integral reset time can be computed by
10 = 12 (12)

Frequency responses of single loop and dual loop
current controller are shown in Fig. 3. The single loop one
shows the LCL resonance, introducing a sharp phase shift
with a large magnitude peak. This can lead to unstable
performance of the controller, unless limited PI gains are
used. On the other hand, with active damping resonance is

Fig. 4. Root locus gain selection for damping gain.

PCC DG Bus

Grid-side Filter Filter

External Grid

DC Source

Line
Inverter

Shunt

Fig. 5. Power stage of the three-phase DG unit (single line

Fig. 3. Bode plots of sinle and dual loop current controller. presentation).
frequency) should be set as well. Different modulation
methods can be set at the Basic Data tab. In this case a
Sinusoidal PWM is selected. A time domain study is
taking place, so the Load Flow window setting are not
important except that these setting will be used for initial
conditions.
The DC connections are connected to a DC source,
presenting the primary source of power. Two Terminals
are used for the connection of the DC source and the
inverter. It is important to check the Negative Voltage in
the Basic Data tab of the Terminal which is supposed to
be connected to the Terminal -. Then, for the LCL filter,
two Common Impedances are used for grid- and inverter-
side inductors and a Shunt/Filter model is placed in
between these impedances to act as the filter capacitance.
Note that the impedance values are being set in pu in the
Load Flow tab of the Common Impedances while the base
values are the parameters set in the Basic Data tab.
Finally, another impedance or a Line model can be used
for the connection to the grid. The grid can be presented
using an External Grid model or a three phase AC Voltage
Source where voltage sequence parameters can be easily
set in the Load Flow tab.
A. Block Definition
The control structure should be designed in the
Composite Model. Fig. 6 shows the created control
structure of the DG unit as implemented in DIgSILENT.
The composite frame consists of the Current 3ph block
and the Shunt Current block (which are the current
measurement devices located at the grid-side inductance
and on the filter capacitance respectively), Voltage 3ph
block (which is used to measure the PCC voltage),
measurement blocks (for voltage and current
measurement), Sample and Hold blocks, PLL block (for
synchronization with grid voltages), ab2dq block (for
synchronous reference frame transformations), PQ block
(for high level PQ controller which calculates the real and
Fig. 6. Scheme of the DG converter controller implemented in DIgSILENT.
reactive powers to generate the sequence current
references), Current block (for low level current
controller), Clock block (for sampling of measured
signals) and finally the modulation indexes are fed into the
Inverter block and power stage.
B. Sampling and Clock Blocks
The sampling blocks are needed to digitalize the
control system. It is important to make sure that the power
stage currents and voltages are measured exactly at the
transition point of each half carrier period achieving
synchronous sampling as shown in Fig. 7. This will avoid
sampling the switching ripple effects. The Sample and
Hold blocks (ElmSamp) are included into to the voltage
and current measurement blocks, keeping the quantities
constant over each half carrier period.
By setting the sampling frequency twice the switching
frequency of the inverter and sampling exactly at the
rising edge of the clock, the switching ripple current will
be eliminated. Therefore, the clock design is in a fashion
that the rising edge is located exactly at the minimum and
maximum points if the carrier signal.
There is a Clock block (ElmClock) in DIgSILENT
which can be used for the clock generation, but it is not
accurate for high switching frequencies. Therefore, as
shown in Fig. 6, the built in carrier signal in the PWM
converter is used. Then using a simple code in the This
clock model is used to have synchronous sampling in the
entire system. The Clock model is a Common Model
(ElmDsl) in DIgSILENT which takes the carrier signal
from PWM Converter as an input (the signal is called
mod), and then uses the following code to generate the
clock signal for sample and hold purposes:
dx=(yi-x)/0.000001 ! T=1us
x.=dx
yo=select(dx>0,select(yi<0,1,0),select(yi>0
,1,0))
 Note that in the following equation T should be the
Clock (rising edge)
same as the integration step size which has been set for +1
the EMT simulation in DIgSILENT.
t
C. PLL Block
The physical voltages and currents must always be
measured in the stationary abc reference frame. These PWM Carrier
-1
quantities must be transformed into the synchronous dq
frame before being used in the control loop calculations, Sampling point

and this requires continuous knowledge of the

synchronous frame reference angle. This is measured
Sampled current
using a phase locked loop as shown in Fig. 8. Essentially, Output current
the loop compares the angle of the positive sequence
quadrature axis voltage against zero, and forces the Fig. 7. Sampling procedure.
synchronous frame angle to the value that achieves this
result using a standard PI regulator to process the error.
As this controll stucture is supposed to consider
sequence components simuntaneously, it is required to
design a PLL system to be synchronized by positive
sequene component which allows extraction of the
positive and negative voltage components which is
necessary to achieve desired real and reactive power
ripple control as descrtibed in Section A.
D. ab2dq Block
Fig. 8. PLL Block.
This block takes the measured currents and voltages
and applies the appropriate transformations to make ready
these signals for the power controller and the current controller as shown in Fig. 9.
regulator. This block transforms the stationary frame ()
components to synchronous frame (dq). Also, it extracts E. PQ Block
the voltage sequence components to be used in the power Fig. 10 shows the high level PQ control implemented

Fig. 9. ab2dq Block.

 Fig. 10.
Fig. 11.
in DIgSILENT. The inputs to this block are the ab2dq
block outputs. In addition to these inputs, the real and
reactive power references and the K value are introduced
to this block as internal variables (these parameters are
used in Simulation Event/Fault section in order to apply
any step change to the system or change a variable
parameter).
Then, the Current_Reference_Generator block uses
Eq. (5) to compute the desired current references to
achieve commanded real and reactive power.
idPref=((UDP*PP/((UDP*UDP)+(UQP*UQP)-
(K_n*UDN*UDN)-
(K_n*UQN*UQN)))+(UQP*QQ/((UDP*UDP)+(UQP*UQP
)+(K_n*UDN*UDN)+(K_n*UQN*UQN))))*0.57803468
2 currents are fed into the current regulator as additional
iqPref=(((UQP*PP/((UDP*UDP)+(UQP*UQP)-
(K_n*UDN*UDN)-(K_n*UQN*UQN)))-
(UDP*QQ/((UDP*UDP)+(UQP*UQP)+(K_n*UDN*UDN)+
(K_n*UQN*UQN))))*0.578034682)
PQ Block.
Current Block.
idNref=-((K_n*UDN*PP/((UDP*UDP)+(UQP*UQP)-
(K_n*UDN*UDN)-
(K_n*UQN*UQN)))+(K_n*UQN*QQ/((UDP*UDP)+(UQP
*UQP)+(K_n*UDN*UDN)+(K_n*UQN*UQN))))*0.5780
34682
iqNref=(-((K_n*UQN*PP/((UDP*UDP)+(UQP*UQP)-
(K_n*UDN*UDN)-(K_n*UQN*UQN)))-
(K_n*UDN*QQ/((UDP*UDP)+(UQP*UQP)+(K_n*UDN*U
DN)+(K_n*UQN*UQN))))*0.578034682)
F. Current Block
Fig. 11 shows the implementation of the low level
current controller in DIgSILENT based on the method
proposed in [10]. PQ block provides the reference
currents. The current controller mathematics have been
already explained in Section B. The measured capacitor
feedback signals after PI regulators to apply the active
damping with a damping gain of .
 The commanded dq frame voltages are the outputs of
Current block. These voltages are required to be produced
by the PWM Converter (converter power stage). These
voltages are converted back into stationary frame
commands, which are suitable for converter system shown
in Fig. 5.
V. SIMULATION MODELS AND RESULTS
The explained control structure is implemented in
DIgSILENT power system analysis package, with the
power stage presented in Fig. 5. DigSILENT is a power
system analysis tool that is primarily used for electrical
network planning and operation optimization [4]. Detailed
simulation of DG inverter system with representation of
the inverter switching processes, requires validation of its
simulation results against the power electronic simulation
package PSIM. Previous works has already verified the
PSIM models against experimental test showing accurate
physical performance of real power converters.
For this study, the parameters of the system and the
controller gains are listed in Table I and Table II,
respectively.
Fig. 12 to Fig. 15 show results for both PSIM (left
hand column) and DIgSILENT (right hand column). An
active/reactive power control mode is applied to the DG
unit the reactive power setpoint is set to zero and the real
power has a setpoint of 8 kW during the simulation. The K
factor changes within intervals of 0.1 sec, starting from +1
to regulate the real power oscillations, then changing to 0
to produce balanced three phase currents injected to the
grid and finally changing to -1 to regulate reactive power
oscillations.
Fig. 12 and Fig. 13 show the simulated unbalanced
grid voltages for both simulation packages with and an
unbalanced condition where two phases sag to 80%.
Fig. 14 and Fig. 15 show the controller performance
for both packages. The first row results show the three
phase current injected to the grid and the second row of
the results shows the injected real and reactive power to
the grid. The Active Power Control ( = +1) is [2] C. Wang; K. Yuan; P. LI; B. Jiao; G. Song, "A Projective
implemented for the period 0.0 t < 0.1s. As expected
no real power oscillations appear in the injected power
while oscillations appear on the reactive power and the
injected currents to the grid are unbalanced. For the next
period 0.1 t < 0.2s, the Current Control ( = 0)
method is implemented resulting in injecting balanced
three phase currents to the grid with expense of
oscillations on both real and reactive powers. For the last
period 0.2 t < 0.3, the K factor is changed to =
1, to enable the Reactive Power Control. This has
eliminated the reactive power oscillations and introduced
higher oscillation to real power compare to Current
Control strategy. Same as Active Power Control strategy,
unbalanced three phase currents are injected to the utility
grid.
Comparing the results in Fig. 14 with results presented
in Fig. 15, an essentially identical results can be seen
(including in particular the transient responses). Matching
this pair of results confirm the validity of the DigSILENT
simulation response.
SYSTEM PARAMETERS
Symbol Nominal Value
Inverter rating 10
Inverter inductor 6
Grid-side inductor 2
Filter capacitance 15
Switching frequency 5 kHz
Sampling frequency 10 kHz
Grid voltage V 400 V (rms)
Grid frequency f 50 Hz
DC bus voltage 2 1000 V
CONTROLLER PARAMETERS
Symbol Value
Proportional gain 0.0192
Time constant 0.0042
Damping gain 0.04
VI. CONCLUSION
A DG converter modelling is presented in this paper
which is suitable for unbalanced voltage conditions as
well as large scale integration of DG systems into the
electrical grid. The fundamental inverter switching
modulation process is combined with a leading edge
current controller and high level power controller, to
create a detailed model that fully represents the inverter
transient and steady state responses to any grid events. An
LCL filter used for grid connection and a deterministic
calculation is used to set the maximum possible controller
gain values considering the modulation/control sampling
and transport delays, and filter component values. The
results of DIgSILENT package are compared against
PSIM package results to confirm the validity of the
proposed modelling. The outcome is a sufficiently
accurate model to match known experimental behavior of
DG inverters, while it is computationally efficient enough
for large scale network, knowing that the results reflect the
real physical system.
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