Low Power Reversible Comparator Circuit
Featured with fault tolerant
ABSTRCT
In order to overcome the disadvantages they are
occurred by using the irreversible gates can be
minimizes using the reversible gates for the
design. One of the major aspect need to be
consider for the design of the any circuit is
accuracy but in present trends the area is
decreases and architecture increases thereby
causing the faults and failures will occurs in
design there by different methods to detect but
they are not always not monitoring all operations
there by proper method is to be need to overcome
this problem is can be done through the fault-
tolerant gate s are used for the design. For the
better design using the reversible logic can be less
garbage inputs and less ancilla outputs. Those also
can be reduced from this concept
I INTRODUCTION
Comparator is one of the essential circuits in digital
system design it can be used in many circuits like
detectors, ADC/DAC, ALU, Device interfaces
encryption devices, sorting networks and
communications. Generally this comparator can be
designed using the irreversible gates like XOR,
NAND and NOR etc .when this comparator design
with this gates generally the pervious bits will be
erased and it stores the present values that causes the
heat dissipation at the junction in long run this causes
the damage of system and may provide the wrong
values.
Faults and errors are the important consideration in
present advanced systems. Errors can be alteration
with the original value at the output occurred by the
internal damage or faults. No other comparator
design with the feature of the fault coverage is
designed. This can be designed by adapting the
parity property for the input and output signals.
In previous, different methods are introduced to
design the reversible comparator but advancement in
the reduce of garbage outputs and ancilla inputs and
reduce in the reversible gate count
a) Reversibility Conditions
For the design of reversible gate it should satisfy the
important conditions they are stated below
A. Condition 1
One to One correspondence between input and
outputs, also known as Bijective Conditions.
B. Condition 2
Each output function must be equal to 1 for its half of
the inputs, known as Balance Conditions.
C. Condition 3
By inversing output, we must be able to reproduce
mapped input called as Dual or Inverse
Conditions.
a) Reversible Logic Circuit Optimization
Parameters
For the designing the any circuit by using the
reversible logic we need to considered the parameters
that are described in table I.
Different design researches are going on the
reduction of the above stated optimized parameters.
For the improved and advanced design by using the
reversible design
 TABLE-1 b) Reversible Logic Gates: Advantage
Reversible optimize parameters
If the design is constructed using the reversible gates
S.no Parameter Optimized Value these are the features and advantages can be obtained
1 Minimum It should be as and that are stated in table II. Not only above stated
number of minimum as possible
power calculations it also reduces the switching
reversible gates in order to reduce the
quantum cost and area power of the transistor and intermediate power loss
and moreover important the glitches are can be
2 Quantum Cost This can be minimum
avoided efficiently
as by as possible
3 Garbage Output Unused intermediate II PROPOSED DESIGN OF FAULT
and final outputs this
TOLERANT REVERSIBLE N-BIT
can be minimized
COMPARATOR
4 Constant Input Constant value that
(ancilla input) used for the operation
They are different reversible gates are available in the
design by the standard
reversible gates market but in our concept we need to design the fault
5 Fan-out Fan-out is not allowed tolerant design.

In order to achieve the fault tolerant mechanism we

need to take the gates in such a way there should be
TABLE-1
the parity relation between the input and the output.
Reversible logic advantages
The parity can be carried out by providing the extra
logic with reversible gates is the total input bit XOR
Types of power Reversible logic gate
is equal with total output XOR
loss advantage
PS Loss Almost zero switching I1I2I3In= O1O2O3On
power dissipation can be
obtained using the i) Proposed AG Gate
reversible gates in design
PSC Loss Short circuit power loss can A fault tolerant AG gate can be designed with the
be minimized by using the 55 input and outputs the propose AG gate and its
reversible logic gates even quantum realization can be shown in the below
for adiabatic circuits figure. In the quantum realized AG gate internally
PL Loss Even tank capacitor leakage consists of the combination of CNOT gates
power also can be reduced
for adiabatic reversible logic
PSTATIC Loss Reversible MOS that
inherently promises
asymptotically-zero power
consumption will minimizes
the static power
Power Reversible logic properties Fig1. Proposed Fault Tolerant Reversible AG Gate
Consumption shows no bit loss during
Reduction computation, unique output
to input port mapping etc
characteristics reduces the
power consumption

Fig2. Quantum Realization of Proposed AG Gate

 a) Proposed 1-nit comparator using AG Fig5. Extended Toffoli Gate as AND Gate
Gate

For the design of N-bit comparator the basic bulding

block can be 1-bit comparator circuit that can
designed efficiently with the AG gate the design is
shown below fig3

Fig6. 4-BIT AND Gate

iii) Modified Tofoli gate

The tofoli gate can be modified by adding the CNOT

at the each output connection to form th modified
Fig3 .AG Works as 1-bit Fault Tolerant Reversible tofoli gate the modified tofoli gate is shown in the
Comparator below fig
ii) Extended Toffoli Gate

The main feater of the toffoli agte is the gate legth

can extended based on the nessicity. Ther by the
example of thr extended toffoli gate with N- input
can be shown in below figure

Fig7. Modified Toffoli Gate

For the design of the comparator the OR logic also

nessicitate for the improved reversible design hence
we can design the OR logic form the modified tofoli
gate by connecting the MSB bit to 0

Fig4. Extended Toffoli Gate

For design of the comparator the easy method can be

designed by using the AND logic that can be fulfilled
by the extended Toffoli gate by taking the N-input as
0 (ancilla input).design of 4-bit AND logic design is
shown in below fig

Fig8. 4-BIT OR Gate

4-BIT COMPARATOR ALGORITHM DESIGN

Based on [8]-[9], a generalized algorithm for a 4-bit

comparator has been developed, which compares two
4-bit binary numbers A and B for EQ, GT and LT
conditions.

Fig9. 4-bit reversible comparator design

RESULTS AND DISCUSSION

The simulated wave forms are shown in below figure

the modular architecture can provide the efficient
output. Design simulations can be achieved for the
different inputs using the model-sim

Fig10: simulated wave form of comparator

Proposed fault tolerant reversible comparator can be

designed that produces the less ancilla inputs and less
garbage outputs previously it was 43 and 37 present
22 and 17 can be achieved by our design. Fault
coverage also can generated explicitly can that will
help the en d user easy to detect the faults occurred in
design elements
CONCLUSION Components, Circuits, Devices & Systems,
pp.1113-1116, 2010.
From the above discussions it can say that newly
designed fault tolerant gate designed comparator can
be used in various low power arithmetical and logical
operations and as an element. Based on these fault
tolerant gates a 4-bit comparator circuit has been
designed and it has been proved that the proposed
architecture design of 4-bit comparator circuit is
better than its counterpart.

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