A B C D E

COMPAL CONFIDENTIAL
MODEL NAME : KML50
PCB NO : LA-4596P (DA60000B710)
1 1

BOM P/N : 11

Half Penny Bridge 15.4

2 Compal Confidential 2

Schematic Document
Cantiga + ICH9
2009 / 01 / 14 Rev:1.0(A00)
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4592P
Date: Thursday, February 19, 2009 Sheet 1 of 43
A B C D E
 A B C D E

Compal confidential
File Name : LA-4596P
Half Penny Bridge 15.4
ZZZ1

Thermal Sensor Penryn -4MB (Socket P)

1
PCB EMC1402-2-ACZL-TR uFCPGA-478 CPU 1

+3VS +CPU_CORE
P.4 +VCCP
+1.5VS P.4,5,6
CK505 SM IC -72

Fan conn Clock Generator

P.4 H_A#(3..35)
+5VS FSB CS9LPRS387BKLFT
+CRT_VCC H_D#(0..63) 1066/800MHz 1.05V
CRT +1.05VS_CK505
P.16
DDR2 667/800MHz 1.8V DDR2-SO-DIMM X2 +3VS_CK505 P.15
BANK 0, 1, 2, 3
Intel Cantiga MCH +1.8V +0.9VS P.13,14

+3VS_DAC_CRT
LVDS Panel Interface +3VS_DAC_BG 1329pin BGA Dual Channel
+LCDVDD
+3VS +1.05VS_DPLLA
B+ P.16 +1.05VS_DPLLB P.7,8,9,10,11,12
+VCCP USB conn x 4
+1.8V_TXLVDS +5VALW P.28
2 2

CardBus Controller FingerPrinter

DMI X4 C-Link +3VS P.28
O2MICRO OZ888
+1.8VS_CB
+3VS_PHY P.29 Felica Conn
USB2.0 +5VS P.28

Intel ICH9-M Azalia

13 94 Media Card
+RTCVCC BT Conn
+1.5VS P.28
+3VS_CR
+VCCP
676pin BGA SATA 0
PCI-E BUS SATA 1
+3VALW
P.17,18,19,20 Camera Digital Mic
+5VS +3VS P.28 P.28

Mini-Card-2 Express Card

10/100/1000 LAN (WLAN) Express Card
+3VS +1.5VS P.25
REALTEK +1.5VS +1.5VS
LPC BUS
RTL8111C-GR +3VS P.23 +3VS P.25
T PM
3
+LAN_IO P.21 Mini-Card-2 3

+1.5VS +3VS P.23

SLB 9635
+3VALW P.27

RJ45/11 CONN
LPC BUS

Mini-Card-1 Audio CODEC Audio Jack

92HD81 P.24
+3VS +5VS P.24
+1.5VS
ENE KB926
+3VALW +EC_AVCC
+3VS P.23 P.26
SATA HDD Connector
+5VS P.22
Touch Pad CONN. Int.KBD BIOS(System/EC)
Power On/Off CKT. +5VS +3VALW
P.27 P.27 P.26
+3VALW P.27 CDROM Conn.
4
+5VS P.22 4

DC/DC Interface CKT.

+3VS +5VS P.30

Security Classification Compal Secret Data Compal Electronics, Inc.

2007/1/15 2008/1/15 Title
Power Circuit DC/DC RTC CKT. Issued Date Deciphered Date
Block diagram
+RTCVCC P.18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P.32~P.39 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 2 of 43
A B C D E
 A

O MEANS ON X MEANS OFF

Voltage Rails

power Symbol Note :

plane +5VS
+3VS
+5VALW +1.8V +1.5VS
: means Digital Ground
+B +0.9V
+3VALW +VCCP
+CPU_CORE : means Analog Ground
State +1.8VS @ : means just reserve , no build
CONN@ : means ME CONN compont.
TPM@:TPM compont

PCI EXPRESS DESTINATION SATA DESTINATION

S0
O O O O Lane 1 MINI CARD-1 WWAN Lane 0 HDD
S1
O O O O Lane 2 GLAN RTL8111DL Lane 1 ODD
S3
O O O X Lane 3 MINI CARD-2 WLAN Lane 4 NA
S5 S4/AC
O O X X Lane 4 EXPRESS CARD Lane 5 NA
S5 S4/ Battery only
O X X X Lane 5 CARD READER OZ888
S5 S4/AC & Battery
don't exist X X X X Lane 6 NA

USB PORT# DESTINATION SMBUS Control Table

1 1

THERMAL
0 JUSBP1 SERIAL SENSOR
SOURCE INVERTER BATT EEPROM (CPU) SODIMM CLK CHIP MINI CARD LCD

1 CAMERA
SMB_EC_CK1
SMB_EC_DA1
KB926 X V V X X X X X
2 JUSBP3 Top
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X
3 Felica
SMB_CK_CLK1

4 Blue Tooth
SMB_CK_DAT1 ICH9 X X X X V V V X
ICH9-M LCD_CLK
5 Finger Printer LCD_DAT Cantiga
X X X X X X X V
6 JMINI2-WLAN
7 Express card

8 JUSBP3 Bottom
9 JMINI1-WWAN

10 JUSBP4
11 NA

I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS
Security Classification Compal Secret Data Compal Electronics, Inc.
DDR SO-DIMM 0 A0 10100000 Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

DDR SO-DIMM 1 A4 10100100 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
CLOCK GENERATOR (EXT.) D2 11010010 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 3 of 43
A
 5 4 3 2 1

+VCCP

XDP_TDI R5 1 2 54.9_0402_1%

XDP_TMS R4 1 2 54.9_0402_1%
D D

XDP_TRST# R11 1 2 54.9_0402_1%

XDP_TCK R35 1 2 54.9_0402_1%

CONN@ This shall place near CPU

7 H_A#[3..16]
JCPU1A
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# 7

ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# 7
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# 7
H_A#6 K5
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# 7
H_A#8 N2 F21 H_DRD Y#
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# 7
H_A#10 N3
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# 7
H_A#12 P2
H_A#13 A[12]# H_IERR#

CONTROL
L2 A[13]# IERR# D20
H_A#14 P4 B3 H_INIT#
A[14]# INIT# H_INIT# 18
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# 7
H_ADSTB#0 M1
7 H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
RESET# H_RESET# 7
H_REQ#0 K3 F3 H_RS#0
7 H_REQ#0 REQ[0]# RS[0]# H_RS#0 7
H_REQ#1 H2 F4 H_RS#1
7 H_REQ#1 REQ[1]# RS[1]# H_RS#1 7
H_REQ#2 K2 G3 H_RS#2
7 H_REQ#2 REQ[2]# RS[2]# H_RS#2 7
H_REQ#3 J3 G2 H_TRDY#
7 H_REQ#3 REQ[3]# TRDY# H_TRDY# 7
H_REQ#4 L1
7 H_REQ#4 REQ[4]#
G6 H_HIT#
7 H_A#[17..35] HIT# H_HIT# 7
H_A#17 Y2 E4 H_HITM#
C A[17]# HITM# H_HITM# 7 C
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4
ADDR GROUP_1

H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]# +3VS
U4 AD1
H_A#22
H_A#23
Y5
A[21]#
A[22]#
BPM[2]#
BPM[3]# AC4 Thermal Sensor EMC1402-1-ACZL-TR
XDP/ITP SIGNALS

U1 A[23]# PRDY# AC2

H_A#24 R4 AC1
A[24]# PREQ#

0.1U_0402_16V4Z
H_A#25 T5 AC5 XDP_TCK 1
H_A#26 A[25]# TCK XDP_TDI
T3 A[26]# TDI AA6
H_A#27 W2 AB3 XDP_TDO C13
A[27]# TDO T84
H_A#28 W5 AB5 XDP_TMS
H_A#29 A[28]# TMS XDP_TRST# 2
Y4 A[29]# TRST# AB6
H_A#30 U2 C20 XDP_DBRESET# U2
A[30]# DBR# XDP_DBRESET# 19
H_A#31 V4 1 8 EC_SMB_CK2 EC_SMB_CK2 16,26
H_A#32 A[31]# VDD SCLK
W3 A[32]#
H_A#33 AA4 THERMAL H_THERMDA 2 7 EC_SMB_DA2
A[33]# D+ SDATA EC_SMB_DA2 16,26
H_A#34 AB2 H_PROCHOT# R146 2 1 68_0402_5% +VCCP C5
H_A#35 A[34]# H_THERMDC
AA3 A[35]# PROCHOT# D21 1 2 3 D- ALERT# 6
H_ADSTB#1 V1 A24 H_THERMDA_R R57 1 2 100_0402_5% H_THERMDA 2200P_0402_50V7K
7 H_ADSTB#1 ADSTB[1]# THERMDA
B25 H_THERMDC_R R53 1 2 100_0402_5% H_THERMDC L_THERM# 4 5
H_A20M# THERMDC THERM# GND
18 H_A20M# A6 A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP# R16

18 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 7,18
H_IGNNE# C4 +3VS 1 2 EMC1402-2-ACZL-TR MSOP 8P
18 H_IGNNE# IGNNE#
H_THERMDA, H_THERMDC routing together, 10K_0402_5%
H_STPCLK# D5 Address:100_1100
18 H_STPCLK# STPCLK# Trace width / Spacing = 10 / 10 mil
H_INTR C6 H CLK
18 H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK
18 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 15
H_SMI# A3 A21 CLK_CPU_BCLK#
18 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 15
C76
M4
N5
RSVD[01] FAN Control circuit 10U_1206_16V4Z~N
2 1
RSVD[02] +5VS
T2 RSVD[03]
B C88 B
V3 RSVD[04]
B2 1000P_0402_50V7K~N 1 2
RESERVED

RSVD[05] C77 10U_1206_16V4Z~N

D2 RSVD[06] 2 1
D22 RSVD[07]
D3 U3
RSVD[08]
F6 RSVD[09] 1 VEN GND 8
2 VIN GND 7
FAN1_POWER 3 6
EN_DFAN1 VO GND
26 EN_DFAN1 4 VSET GND 5

Penryn +3VS RT9027BPS SO 8P

1
JFAN1
R61
40mil
1 1
+VCCP 2.2K_0402_5% 2 2
3 3

2
26 FAN_SPEED1 4 GND
1

@ 1 5
R17 GND

2
56_0402_5% C94 ACES_85205-03001
4.7P_0402_50V8C D61
2 conn@
PJSOT24C_SOT23-3
2 2

For FAN Test Fail @ FAN1

B

1
E

H_PROCHOT# 3 1 OCP#
OCP# 19
C

@ Q2
MMBT3904_SOT23

+VCCP
A A
2

R18
56_0402_5%
1

H_IERR# Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(1/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 4 of 43
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE +CPU_CORE
7 H_D#[0..15] CONN@ CONN@
H_D#[32..47] 7
JCPU1B JCPU1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
D[2]# D[34]# VCC[003] VCC[070]

DATA GRP 0
H_D#3 G22 V26 H_D#35 A12 AC9
D[3]# D[35]# VCC[004] VCC[071]

DATA GRP 2
D H_D#4 H_D#36 D
F23 D[4]# D[36]# V23 A13 VCC[005] VCC[072] AC12
H_D#5 G25 T22 H_D#37 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 D[6]# D[38]# U25 A17 VCC[007] VCC[074] AC15
H_D#7 E23 U23 H_D#39 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 D[8]# D[40]# Y25 A20 VCC[009] VCC[076] AC18
H_D#9 G24 W22 H_D#41 B7 AD7
H_D#10 D[9]# D[41]# H_D#42 VCC[010] VCC[077]
J24 D[10]# D[42]# Y23 B9 VCC[011] VCC[078] AD9
H_D#11 J23 W24 H_D#43 B10 AD10
H_D#12 D[11]# D[43]# H_D#44 VCC[012] VCC[079]
H22 D[12]# D[44]# W25 B12 VCC[013] VCC[080] AD12
H_D#13 F26 AA23 H_D#45 B14 AD14
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
K22 D[14]# D[46]# AA24 B15 VCC[015] VCC[082] AD15
H_D#15 H23 AB25 H_D#47 B17 AD17
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VCC[016] VCC[083]
7 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 7 B18 VCC[017] VCC[084] AD18
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7 VCC[018] VCC[085]
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
7 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 7 VCC[019] VCC[086]
7 H_D#[16..31] H_D#[48..63] 7 C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10
D[21]# D[53]# VCC[027] VCC[094]

DATA GRP 3
H_D#22 L22 AD20 H_D#54 D12 AF12
H_D#23 D[22]# D[54]# H_D#55 VCC[028] VCC[095]
M23 D[23]# D[55]# AE22 D14 VCC[029] VCC[096] AF14
H_D#24 P25 AF23 H_D#56 D15 AF15
H_D#25 D[24]# D[56]# H_D#57 VCC[030] VCC[097]
P23 D[25]# D[57]# AC25 D17 VCC[031] VCC[098] AF17
H_D#26 P22 AE21 H_D#58 D18 AF18
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099] +VCCP
T24 D[27]# D[59]# AD21 E7 VCC[033] VCC[100] AF20
H_D#28 R24 AC22 H_D#60 E9
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
L25 D[29]# D[61]# AD23 E10 VCC[035] VCCP[01] G21
H_D#30 T25 AF22 H_D#62 E12 V6
C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP[02] C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
7 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 7 VCC[038] VCCP[04]

220U_D2_4VY_R15M
H_DSTBP#1 M26 AF24 H_DSTBP#3 E17 M6
7 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 7 VCC[039] VCCP[05] +
H_DINV#1 N24 AC20 H_DINV#3 E18 J21
7 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 7 VCC[040] VCCP[06]

C10
E20 VCC[041] VCCP[07] K21
+V_CPU_GTLREF AD26 R26 COMP0 F7 M21
@ R52 GTLREF COMP[0] VCC[042] VCCP[08] 2
1 2 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 F9 VCC[043] VCCP[09] N21
@ R22 1 2 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T2 C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
TEST4 AF26 F14 R6
T3 TEST4 VCC[046] VCCP[12]
TEST5 AF1 E5 H_DPRSTP# R23 R24 R25 R26 F15 T21
T4 TEST5 DPRSTP# H_DPRSTP# 7,18,39 VCC[047] VCCP[13]

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T5 TEST6 DPSLP# H_DPSLP# 18 VCC[048] VCCP[14]

1
TEST7 C3 D24 H_DPWR# F18 V21
T6 TEST7 DPWR# H_DPWR# 7 VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PW RGOOD F20 W21
15 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD 18 VCC[050] VCCP[16]
CPU_BSEL1 B23 D7 H_CPUSLP# AA7
15 CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 7 VCC[051]
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
15 CPU_BSEL2 BSEL[2] PSI# H_PSI# 39 VCC[052] VCCA[01] +1.5VS
AA10 C26

2
VCC[053] VCCA[02]

0.01U_0402_16V7K
10U_0805_6.3V6M
Penryn AA12 VCC[054]
AA13 VCC[055] VID[0] AD6 CPU_VID0 39
AA15 VCC[056] VID[1] AF5 CPU_VID1 39 1 1
AA17 VCC[057] VID[2] AE5 CPU_VID2 39
AA18 AF4 C12 C11
VCC[058] VID[3] CPU_VID3 39
layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU AA20 VCC[059] VID[4] AE3 CPU_VID4 39 2 2
Resistor placed within AB9 VCC[060] VID[5] AF3 CPU_VID5 39
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs 0.5" of CPU pin.Trace AC10 VCC[061] VID[6] AE2 CPU_VID6 39
AB10 VCC[062]
should be at least 25 AB12 VCC[063]
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 AB14 AF7 VCCSENSE VCCSENSE 39
mils away from any other AB15
VCC[064] VCCSENSE
Near pin B26
VCC[065]
toggling signal. AB17 VCC[066] No stuff 27.4 pull down near IMVP for testing
AB18 AE7 VSSSENSE VSSSENSE 39
166 0 1 1 COMP[0,2] trace width is VCC[067] VSSSENSE
B 18 mils. COMP[1,3] trace Penryn B

width is 4 For 8 layer condition

.

200 0 0
Length match within 25 mils.
1
The trace width/space/other is
20/7/25.
266 0 0 0
+VCCP
1

R27
For 6 layer
1K_0402_1% +CPU_CORE
Z=27.4 ohm
2

+V_CPU_GTLREF
VCCSENSE, VSSSENSE/ 14mils (MS), R28 1 2 100_0402_1% VCCSENSE
16mils (SL) width, 7mils space, 25mils
1

space to other signals Mismatch =25mils.

R29 R30 1 2 100_0402_1% VSSSENSE
2K_0402_1%
2

Close to CPU pin AD26

Close to CPU pin
within 500mils.
within 500mils.
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(2/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 5 of 43
5 4 3 2 1
 5 4 3 2 1

High Frequence Decoupling

10uF 0805 X5R -> 85 degree.

+CPU_CORE Place these caps inside

the CPU socket.
Place these caps inside 1 1 1 1 1 1 1 1 1 1 ( Left side on Top ).
the CPU socket cavity. C202 C204 C529 C232 C258 C505 C504 C257 C261 C214
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
( Left side on Top ). 2 2 2 2 2 2 2 2 2 2
D D
CONN@
JCPU1D
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14
A16
VSS[004] VSS[085] R2
R5
+CPU_CORE Place these caps inside
VSS[005] VSS[086]
A19 VSS[006] VSS[087] R22 the CPU socket.
A23 VSS[007] VSS[088] R25 Place these caps inside
AF2 VSS[008] VSS[089] T1 1 1 1 1 1 1 1 1 1 1 ( Right side on Top ).
B6 VSS[009] VSS[090] T4 the CPU socket cavity. C190 C197 C254 C193 C203 C200 C192 C199 C208 C226
B8 VSS[010] VSS[091] T23
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
B11 VSS[011] VSS[092] T26 ( Right side on Top side). 2 2 2 2 2 2 2 2 2 2
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5
C8 VSS[018] VSS[099] V22
+CPU_CORE
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
C16 VSS[021] VSS[102] W4
C19
C2
VSS[022] VSS[103] W23
W26
Place these caps inside 1 1 1 1 1 1
VSS[023] VSS[104]
C22 VSS[024] VSS[105] Y3 the CPU socket cavity. C501
10U_0805_6.3V6M
C508
10U_0805_6.3V6M
C514
10U_0805_6.3V6M
C519
10U_0805_6.3V6M
C522
10U_0805_6.3V6M
C533
10U_0805_6.3V6M
C25 VSS[025] VSS[106] Y6
2 2 2 2 2 2
D1 VSS[026] VSS[107] Y21 ( Left side on Bottom ).
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5
C C
D13 VSS[030] VSS[111] AA8
D16 VSS[031] VSS[112] AA11
D19 VSS[032] VSS[113] AA14
D23 VSS[033] VSS[114] AA16
+CPU_CORE
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
E8
E11
VSS[037] VSS[118] AB1
AB4
Place these caps inside 1 1 1 1 1 1
VSS[038] VSS[119]
E14 VSS[039] VSS[120] AB8 the CPU socket cavity. C502
10U_0805_6.3V6M
C510
10U_0805_6.3V6M
C515
10U_0805_6.3V6M
C520
10U_0805_6.3V6M
C526
10U_0805_6.3V6M
C532
10U_0805_6.3V6M
E16 VSS[040] VSS[121] AB11
2 2 2 2 2 2
E19 VSS[041] VSS[122] AB13 ( Right side on Bottom ).
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19
F5 VSS[044] VSS[125] AB23
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
F16 VSS[048] VSS[129] AC8
F19 VSS[049] VSS[130] AC11
+CPU_CORE
F2 VSS[050] VSS[131] AC14
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 AC21
VSS[053] VSS[134]
ESR <= 1.5m ohm
330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9
G1
G23
VSS[054] VSS[135] AC24
AD2
Place these caps inside 1 1 1 1
Place these caps inside
VSS[055] VSS[136]
G26 VSS[056] VSS[137] AD5 the CPU socket. the CPU socket.
C196

C198

C259

+ + + C255 +
H3 AD8
H6
H21
VSS[057]
VSS[058]
VSS[138]
VSS[139] AD11
AD13
( Left side on Top ). ( Right side on Top side). Capacitor > 880 uF
VSS[059] VSS[140] 2 2 2 2
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
B B
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21 Place these inside
P3 VSS[081] VSS[162] A25 socket cavity on L8
VSS[163] AF25 (North side
Penryn Secondary)
.
+VCCP

1 1 1 1 1 1
C213 C209 C212 C185 C183 C184

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

A 2 2 2 2 2 2 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(3/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 6 of 43
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] 4 U4B
5 H_D#[0..63] U4A
A14 H_A#3 M36
H_A#_3 T7 RSVD1

DDR CLK/ CONTROL/COMPENSATION

H_D#0 F2 C15 H_A#4 N36 AP24 M_CLK_DDR0 M_CLK_DDR0 13
H_D#_0 H_A#_4 T11 RSVD2 SA_CK_0

0.01U_0402_25V7K
2.2U_0603_6.3V4Z
H_D#1 G8 F16 H_A#5 R33 AT21 M_CLK_DDR1 M_CLK_DDR1 13
H_D#_1 H_A#_5 T12 RSVD3 SA_CK_1
H_D#2 F8 H13 H_A#6 T33 AV24 M_CLK_DDR2 M_CLK_DDR2 14
H_D#_2 H_A#_6 +1.8V T13 RSVD4 SB_CK_0
H_D#3 E6 C18 H_A#7 AH9 AU20 M_CLK_DDR3 M_CLK_DDR3 14
H_D#_3 H_A#_7 T14 RSVD5 SB_CK_1
H_D#4 G2 M16 H_A#8 AH10
H_D#_4 H_A#_8 T15 RSVD6
H_D#5 H6 J13 H_A#9 1 1 AH12 AR24 M_CLK_DDR#0
H_D#_5 H_A#_9 T16 RSVD7 SA_CK#_0 M_CLK_DDR#0 13

1
C398

C400
H_D#6 H2 P16 H_A#10 AH13 AR21 M_CLK_DDR#1
H_D#_6 H_A#_10 T17 RSVD8 SA_CK#_1 M_CLK_DDR#1 13
H_D#7 F6 R16 H_A#11 R331 K12 AU24 M_CLK_DDR#2
H_D#_7 H_A#_11 T18 RSVD9 SB_CK#_0 M_CLK_DDR#2 14
H_D#8 D4 N17 H_A#12 1K_0402_1% AL34 AV20 M_CLK_DDR#3
H_D#_8 H_A#_12 2 2 T19 RSVD10 SB_CK#_1 M_CLK_DDR#3 14
H_D#9 H3 M13 H_A#13 AK34
H_D#_9 H_A#_13 T20 RSVD11
H_D#10 M9 E17 H_A#14 AN35 BC28 DDR_CKE0_DIMMA
T21 DDR_CKE0_DIMMA 13

2
H_D#11 H_D#_10 H_A#_14 H_A#15 +SMRCOMP_VOH RSVD12 SA_CKE_0 DDR_CKE1_DIMMA
M11 H_D#_11 H_A#_15 P17 T22 AM35 RSVD13 SA_CKE_1 AY28 DDR_CKE1_DIMMA 13
D H_D#12 H_A#16 DDR_CKE2_DIMMB D
J1 H_D#_12 H_A#_16 F17 T24 T24 RSVD14 SB_CKE_0 AY36 DDR_CKE2_DIMMB 14

1
H_D#13 J2 G20 H_A#17 BB36 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SB_CKE_1 DDR_CKE3_DIMMB 14

RSVD
H_D#14 N12 B19 H_A#18 R332 B31
H_D#_14 H_A#_18 T25 RSVD15
H_D#15 J6 J16 H_A#19 3.01K_0402_1% B2 BA17 DDR_CS0_DIMMA#
H_D#_15 H_A#_19 T26 RSVD16 SA_CS#_0 DDR_CS0_DIMMA# 13
H_D#16 P2 E20 H_A#20 M1 AY16 DDR_CS1_DIMMA#
H_D#_16 H_A#_20 T27 RSVD17 SA_CS#_1 DDR_CS1_DIMMA# 13
H_D#17 L2 H16 H_A#21 NA lead free AV16 DDR_CS2_DIMMB#
DDR_CS2_DIMMB# 14

2
H_D#18 H_D#_17 H_A#_21 H_A#22 +SMRCOMP_VOL SB_CS#_0 DDR_CS3_DIMMB#
R2 H_D#_18 H_A#_22 J20 SB_CS#_1 AR13 DDR_CS3_DIMMB# 14
H_D#19 N9 L17 H_A#23 AY21
H_D#_19 H_A#_23 T28 RSVD20

1
0.01U_0402_25V7K
2.2U_0603_6.3V4Z
H_D#20 L6 A17 H_A#24 BD17 M_ODT0 M_ODT0 13
H_D#21 H_D#_20 H_A#_24 H_A#25 R333 SA_ODT_0 M_ODT1
M5 H_D#_21 H_A#_25 B17 1 1 SA_ODT_1 AY17 M_ODT1 13
H_D#22 H_A#26 1K_0402_1% M_ODT2 +1.8V
J3 H_D#_22 H_A#_26 L16 SB_ODT_0 BF15 M_ODT2 14

C403

C404
H_D#23 N2 C21 H_A#27 BG23 AY13 M_ODT3 M_ODT3 14
H_D#_23 H_A#_27 T41 RSVD22 SB_ODT_1
H_D#24 R1 J17 H_A#28 BF23
T44

2
H_D#25 H_D#_24 H_A#_28 H_A#29 2 2 RSVD23 SMRCOMP R328
N5 H_D#_25 H_A#_29 H20 T73 BH18 RSVD24 SM_RCOMP BG22 1 2 80.6_0402_1%
H_D#26 N6 B18 H_A#30 BF18 BH21 SMRCOMP# R329 1 2 80.6_0402_1%
H_D#_26 H_A#_30 T74 RSVD25 SM_RCOMP#
H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32 +SMRCOMP_VOH
N8 H_D#_28 H_A#_32 B20 SM_RCOMP_VOH BF28
H_D#29 L7 F21 H_A#33 BH28 +SMRCOMP_VOL
H_D#30 H_D#_29 H_A#_33 H_A#34 SM_RCOMP_VOL
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35 AV42 +V_DDR_MCH_REF
H_D#32 H_D#_31 H_A#_35 +3VS SM_VREF R39
Y3 H_D#_32 SM_PWROK AR36 1 2 10K_0402_1%
H_D#33 AD14 H12 H_ADS# R82 BF17 SM_REXT R40 1 2 499_0402_1%
H_D#_33 H_ADS# H_ADS# 4 SM_REXT
H_D#34 Y6 B16 H_ADSTB#0 PM_EXTTS#0 1 2 BC36 TP_SM_DRAMRST# T29 PAD
H_D#_34 H_ADSTB#_0 H_ADSTB#0 4 SM_DRAMRST#
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 4
H_D#36 Y12 A9 H_BNR# 10K_0402_5% B38 CLK_MCH_DREFCLK
H_D#_36 H_BNR# H_BNR# 4 DPLL_REF_CLK CLK_MCH_DREFCLK 15
H_D#37 Y14 F11 H_BPRI# A38 CLK_MCH_DREFCLK#
H_D#_37 H_BPRI# H_BPRI# 4 DPLL_REF_CLK# CLK_MCH_DREFCLK# 15
H_D#38 Y7 G12 H_BR0# R83 E41 MCH_SSCDREFCLK
HOST
H_D#_38 H_BREQ# H_BR0# 4 DPLL_REF_SSCLK MCH_SSCDREFCLK 15
H_D#39 W2 E9 H_DEFER# PM_EXTTS#1 1 2 F41 MCH_SSCDREFCLK#
H_D#_39 H_DEFER# H_DEFER# 4 DPLL_REF_SSCLK# MCH_SSCDREFCLK# 15
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# 4

CLK
H_D#41 Y9 AH7 CLK_MCH_BCLK 10K_0402_5% F43 CLK_MCH_3GPLL
H_D#_41 HPLL_CLK CLK_MCH_BCLK 15 PEG_CLK CLK_MCH_3GPLL 15
H_D#42 AA13 AH6 CLK_MCH_BCLK# E43 CLK_MCH_3GPLL#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 15 PEG_CLK# CLK_MCH_3GPLL# 15
H_D#43 AA9 J11 H_DPWR#
C H_D#_43 H_DPWR# H_DPWR# 5 C
H_D#44 AA11 F9 H_DRD Y#
H_D#_44 H_DRDY# H_DRDY# 4
H_D#45 AD11 H9 H_HIT#
H_D#_45 H_HIT# H_HIT# 4
H_D#46 AD10 E12 H_HITM# AE41 DMI_MRX_ITX_N0
H_D#_46 H_HITM# H_HITM# 4 DMI_RXN_0 DMI_MRX_ITX_N0 19
H_D#47 AD13 H11 H_LOCK# AE37 DMI_MRX_ITX_N1
H_D#_47 H_LOCK# H_LOCK# 4 DMI_RXN_1 DMI_MRX_ITX_N1 19
H_D#48 AE12 C9 H_TRDY# AE47 DMI_MRX_ITX_N2
H_D#_48 H_TRDY# H_TRDY# 4 DMI_RXN_2 DMI_MRX_ITX_N2 19
H_D#49 AE9 AH39 DMI_MRX_ITX_N3
H_D#_49 DMI_RXN_3 DMI_MRX_ITX_N3 19
H_D#50 AA2
H_D#51 H_D#_50 DMI_MRX_ITX_P0
AD8 H_D#_51 DMI_RXP_0 AE40 DMI_MRX_ITX_P0 19
H_D#52 AA3 MCH_CLKSEL0 T25 AE38 DMI_MRX_ITX_P1
H_D#_52 15 MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_MRX_ITX_P1 19
H_D#53 AD3 J8 H_DINV#0 MCH_CLKSEL1 R25 AE48 DMI_MRX_ITX_P2
H_D#_53 H_DINV#_0 H_DINV#0 5 15 MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_MRX_ITX_P2 19
H_D#54 AD7 L3 H_DINV#1 MCH_CLKSEL2 P25 AH40 DMI_MRX_ITX_P3
H_D#_54 H_DINV#_1 H_DINV#1 5 15 MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_MRX_ITX_P3 19
H_D#55 AE14 Y13 H_DINV#2 PAD T8 P20
H_D#_55 H_DINV#_2 H_DINV#2 5 CFG_3
H_D#56 AF3 Y1 H_DINV#3 PAD T9 P24 AE35 DMI_MTX_IRX_N0
H_D#_56 H_DINV#_3 H_DINV#3 5 CFG_4 DMI_TXN_0 DMI_MTX_IRX_N0 19
H_D#57 AC1 CFG5 C25 AE43 DMI_MTX_IRX_N1
H_D#_57 9 CFG5 CFG_5 DMI_TXN_1 DMI_MTX_IRX_N1 19
H_D#58 AE3 L10 H_DSTBN#0 CFG6 N24 AE46 DMI_MTX_IRX_N2
H_D#_58 H_DSTBN#_0 H_DSTBN#0 5 9 CFG6 CFG_6 DMI_TXN_2 DMI_MTX_IRX_N2 19
H_D#59 AC3 M7 H_DSTBN#1 CFG7 M24 AH42 DMI_MTX_IRX_N3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 5 9 CFG7 CFG_7 DMI_TXN_3 DMI_MTX_IRX_N3 19
H_D#60 AE11 AA5 H_DSTBN#2 PAD T37 E21
H_D#_60 H_DSTBN#_2 H_DSTBN#2 5 CFG_8

DMI
CFG
H_D#61 AE8 AE6 H_DSTBN#3 CFG9 C23 AD35 DMI_MTX_IRX_P0
H_D#_61 H_DSTBN#_3 H_DSTBN#3 5 9 CFG9 CFG_9 DMI_TXP_0 DMI_MTX_IRX_P0 19
H_D#62 AG2 PAD T65 C24 AE44 DMI_MTX_IRX_P1
H_D#_62 CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 19
H_D#63 AD6 L9 H_DSTBP#0 PAD T40 N21 AF46 DMI_MTX_IRX_P2
H_D#_63 H_DSTBP#_0 H_DSTBP#0 5 CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 19
M8 H_DSTBP#1 PAD T67 CFG12 P21 AH43 DMI_MTX_IRX_P3
H_DSTBP#_1 H_DSTBP#1 5 CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 19
AA6 H_DSTBP#2 PAD T47 CFG13 T21
H_DSTBP#_2 H_DSTBP#2 5 CFG_13
H_SWNG C5 AE5 H_DSTBP#3 PAD T10 R20
H_SWING H_DSTBP#_3 H_DSTBP#3 5 CFG_14
H_RCOMP E3 PAD T66 M20
H_RCOMP H_REQ#0 CFG16 CFG_15
H_REQ#_0 B15 H_REQ#0 4 9 CFG16 L21 CFG_16
K13 H_REQ#1 PAD T68 H21
H_REQ#_1 H_REQ#1 4 CFG_17

GRAPHICS VID
F13 H_REQ#2 PAD T39 P29
H_REQ#_2 H_REQ#2 4 CFG_18
B13 H_REQ#3 CFG19 R28
H_REQ#_3 H_REQ#3 4 9 CFG19 CFG_19
4 H_RESET# H_RESET# C12 B14 H_REQ#4 CFG20 T28 B33
H_CPURST# H_REQ#_4 H_REQ#4 4 9 CFG20 CFG_20 GFX_VID_0 T30
5 H_CPUSLP# H_CPUSLP# E11 B32
H_CPUSLP# GFX_VID_1 T31
B6 H_RS#0 H_RS#0 4 G33
H_RS#_0 GFX_VID_2 T32
F12 H_RS#1 H_RS#1 4 F33
B H_RS#_1 GFX_VID_3 T33 B
C8 H_RS#2 H_RS#2 4 19 PM_BMBUSY# PM_BMBUSY# R29 E33
H_RS#_2 PM_SYNC# GFX_VID_4 T34
+H_VREF A11 H_DPRSTP# B7
H_AVREF 5,18,39 H_DPRSTP# PM_DPRSTP#
B11 PM_EXTTS#0 N33
H_DVREF 13 PM_EXTTS#0 PM_EXT_TS#_0
PM_EXTTS#1 P32
14 PM_EXTTS#1 PM_EXT_TS#_1

PM
CANTIGA_1p0 PM_PWROK_R AT40 C34
PWROK GFX_VR_EN T35 +VCCP
PLT_RST# 1 2 PLT_RST#_NB AT11
17,26,29 PLT_RST# RSTIN#
4,18 H_THERMTRIP# 1 2 R523 100_0402_5% THERMTRIP# T20
R56 0_0402_5% DPRSLPVR THERMTRIP#
19,39 DPRSLPVR R32 DPRSLPVR

1
AH37 CL_CLK0 R100
CL_CLK CL_CLK0 19
1 2 PM_PWROK_R AH36 CL_DATA0 1K_0402_1%
19,26 ICH_PWROK CL_DATA CL_DATA0 19
R408 0_0402_5% BG48 AN36 M_PWROK
NC_1 CL_PWROK M_PWROK 19
1 2 BF48 AJ35 CL_RST#
19,26,39 VGATE CL_RST# 19

2
NC_2 CL_RST#

ME
@ R407 0_0402_5% BD48 AH34 +CL_VREF +CL_VREF
NC_3 CL_VREF
Layout Note: BC48 NC_4

1
BH47 1
H_RCOMP / H_VREF / H_SWNG BG47
NC_5 C181 R99
NC_6 0.1U_0402_16V4Z 511_0402_1%
trace width and spacing is 10/20 +1.8V
BE47 NC_7 DDPC_CTRLCLK N28 T36
Layout Note: BH46 NC_8 DDPC_CTRLDATA M28 T48 2
V_DDR_MCH_REF BF46 G36 T63

2
+VCCP NC_9 SDVO_CTRLCLK

NC
BG45 NC_10 SDVO_CTRLDATA E36 T64
1

+VCCP trace width and BH44 K36 CLKREQ#_7

NC_11 CLKREQ# CLKREQ#_7 15
spacing is 20/20. R42 BH43 H36 MCH_ICH_SYNC#
NC_12 ICH_SYNC# MCH_ICH_SYNC# 19
221_0603_1%
1K_0402_1%

1K_0402_1%

MISC
BH6 NC_13
1

BH5 R1430
R45 R322 NC_14
BG4 B12 1 2 +VCCP
2

+V_DDR_MCH_REF H_DPRSTP# NC_15 TSATN#

13,14 +V_DDR_MCH_REF BH3 NC_16 56_0402_5%
BF3 NC_17
1
0.1U_0402_16V4Z

BH2
2

NC_18
18P_0402_50V8J

+H_VREF H_RCOMP H_SWNG 1 R43 1 BG2 B28

NC_19 HDA_BCLK T99
@
24.9_0402_1%

C121 1K_0402_1% BE2 B30

NC_20 HDA_RST# T100
0.1U_0402_16V4Z

C1816 BG1 B29

NC_21 HDA_SDI T101
1

1
100_0402_1%
0.1U_0402_16V4Z

A A
1 1 BF1 C29 T102
2

2 2 NC_22 HDA_SDO
2K_0402_1%

HDA
R46 @ R324 R323 C386 BD1 A28
NC_23 HDA_SYNC T103
BC1 NC_24
C391 F1 0905 Add test point
2 2 NC_25
A47
2

NC_26
CANTIGA_1p0
Security Classification Compal Secret Data Compal Electronics, Inc.
within 100 mils from NB Near B3 pin Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(1/6)-AGTL/DMI/DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 7 of 43
5 4 3 2 1
 5 4 3 2 1

D D

13 DDR_A_D[0..63] 14 DDR_B_D[0..63]
U4D U4E
DDR_A_D0 AJ38 BD21 DDR_A_BS#0 DDR_B_D0 AK47 BC16 DDR_B_BS#0
SA_DQ_0 SA_BS_0 DDR_A_BS#0 13 SB_DQ_0 SB_BS_0 DDR_B_BS#0 14
DDR_A_D1 AJ41 BG18 DDR_A_BS#1 DDR_B_D1 AH46 BB17 DDR_B_BS#1
SA_DQ_1 SA_BS_1 DDR_A_BS#1 13 SB_DQ_1 SB_BS_1 DDR_B_BS#1 14
DDR_A_D2 AN38 AT25 DDR_A_BS#2 DDR_B_D2 AP47 BB33 DDR_B_BS#2
SA_DQ_2 SA_BS_2 DDR_A_BS#2 13 SB_DQ_2 SB_BS_2 DDR_B_BS#2 14
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# 13 AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_A_CAS# DDR_B_D5 AJ48 AU17 DDR_B_RAS#
SA_DQ_5 SA_CAS# DDR_A_CAS# 13 SB_DQ_5 SB_RAS# DDR_B_RAS# 14
DDR_A_D6 AM44 AY20 DDR_A_WE# DDR_A_WE# 13 DDR_B_D6 AM48 BG16 DDR_B_CAS#
SA_DQ_6 SA_WE# SB_DQ_6 SB_CAS# DDR_B_CAS# 14
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14 DDR_B_WE# DDR_B_WE# 14
DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
AN43 SA_DQ_8 AU47 SB_DQ_8
DDR_A_D9 AN44 DDR_B_D9 AU46
SA_DQ_9 DDR_A_DM[0..7] 13 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_A_DM0 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 SA_DM_0 AM37 AY48 SB_DQ_11 DDR_B_DM[0..7] 14
DDR_A_D12 AN41 AT41 DDR_A_DM1 DDR_B_D12 AT47 AM47 DDR_B_DM0
DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
AN39 SA_DQ_13 SA_DM_2 AY41 AR47 SB_DQ_13 SB_DM_1 AY47
DDR_A_D14 AU44 AU39 DDR_A_DM3 DDR_B_D14 BA47 BD40 DDR_B_DM2
DDR_A_D15 SA_DQ_14 SA_DM_3 DDR_A_DM4 DDR_B_D15 SB_DQ_14 SB_DM_2 DDR_B_DM3
AU42 SA_DQ_15 SA_DM_4 BB12 BC47 SB_DQ_15 SB_DM_3 BF35
DDR_A_D16 AV39 AY6 DDR_A_DM5 DDR_B_D16 BC46 BG11 DDR_B_DM4
DDR_A_D17 SA_DQ_16 SA_DM_5 DDR_A_DM6 DDR_B_D17 SB_DQ_16 SB_DM_4 DDR_B_DM5
AY44 SA_DQ_17 SA_DM_6 AT7 BC44 SB_DQ_17 SB_DM_5 BA3

A
DDR_A_D18 BA40 AJ5 DDR_A_DM7 DDR_B_D18 BG43 AP1 DDR_B_DM6
SA_DQ_18 SA_DM_7 SB_DQ_18 SB_DM_6

B
DDR_A_D19 BD43 DDR_A_DQS[0..7] 13 DDR_B_D19 BF43 AK2 DDR_B_DM7
DDR_A_D20 SA_DQ_19 DDR_A_DQS0 DDR_B_D20 SB_DQ_19 SB_DM_7
AV41 SA_DQ_20 SA_DQS_0 AJ44 BE45 SB_DQ_20 DDR_B_DQS[0..7] 14
DDR_A_D21 AY43 AT44 DDR_A_DQS1 DDR_B_D21 BC41 AL47 DDR_B_DQS0
DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
BB41 BA43 BF40 AV48
DDR_A_D23 BC40
SA_DQ_22
MEMORY SA_DQS_2
BC37 DDR_A_DQS3 DDR_B_D23 BF41
SB_DQ_22 SB_DQS_1
BG41 DDR_B_DQS2

MEMORY
DDR_A_D24 SA_DQ_23 SA_DQS_3 DDR_A_DQS4 DDR_B_D24 SB_DQ_23 SB_DQS_2 DDR_B_DQS3
AY37 SA_DQ_24 SA_DQS_4 AW12 BG38 SB_DQ_24 SB_DQS_3 BG37
DDR_A_D25 BD38 BC8 DDR_A_DQS5 DDR_B_D25 BF38 BH9 DDR_B_DQS4
DDR_A_D26 SA_DQ_25 SA_DQS_5 DDR_A_DQS6 DDR_B_D26 SB_DQ_25 SB_DQS_4 DDR_B_DQS5
AV37 SA_DQ_26 SA_DQS_6 AU8 BH35 SB_DQ_26 SB_DQS_5 BB2
DDR_A_D27 AT36 AM7 DDR_A_DQS7 DDR_B_D27 BG35 AU1 DDR_B_DQS6
SA_DQ_27 SA_DQS_7 DDR_A_DQS#[0..7] 13 SB_DQ_27 SB_DQS_6
DDR_A_D28 AY38 AJ43 DDR_A_DQS#0 DDR_B_D28 BH40 AN6 DDR_B_DQS7
C SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 DDR_B_DQS#[0..7] 14 C
DDR_A_D29 BB38 AT43 DDR_A_DQS#1 DDR_B_D29 BG39 AL46 DDR_B_DQS#0
DDR_A_D30 SA_DQ_29 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D30 SB_DQ_29 SB_DQS#_0 DDR_B_DQS#1
AV36 SA_DQ_30 SA_DQS#_2 BA44 BG34 SB_DQ_30 SB_DQS#_1 AV47
DDR_A_D31 AW36 BD37 DDR_A_DQS#3 DDR_B_D31 BH34 BH41 DDR_B_DQS#2
DDR_A_D32 SA_DQ_31 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D32 SB_DQ_31 SB_DQS#_2 DDR_B_DQS#3
BD13 SA_DQ_32 SA_DQS#_4 AY12 BH14 SB_DQ_32 SB_DQS#_3 BH37
DDR_A_D33 AU11 BD8 DDR_A_DQS#5 DDR_B_D33 BG12 BG9 DDR_B_DQS#4
DDR_A_D34 SA_DQ_33 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D34 SB_DQ_33 SB_DQS#_4 DDR_B_DQS#5
BC11 SA_DQ_34 SA_DQS#_6 AU9 BH11 SB_DQ_34 SB_DQS#_5 BC2
DDR_A_D35 BA12 AM8 DDR_A_DQS#7 DDR_B_D35 BG8 AT2 DDR_B_DQS#6
SYSTEM

SA_DQ_35 SA_DQS#_7 DDR_A_MA[0..14] 13 SB_DQ_35 SB_DQS#_6

DDR_A_D36 AU13 DDR_B_D36 BH12 AN5 DDR_B_DQS#7

SYSTEM
DDR_A_D37 SA_DQ_36 DDR_A_MA0 DDR_B_D37 SB_DQ_36 SB_DQS#_7
AV13 SA_DQ_37 SA_MA_0 BA21 BF11 SB_DQ_37 DDR_B_MA[0..14] 14
DDR_A_D38 BD12 BC24 DDR_A_MA1 DDR_B_D38 BF8 AV17 DDR_B_MA0
DDR_A_D39 SA_DQ_38 SA_MA_1 DDR_A_MA2 DDR_B_D39 SB_DQ_38 SB_MA_0 DDR_B_MA1
BC12 SA_DQ_39 SA_MA_2 BG24 BG7 SB_DQ_39 SB_MA_1 BA25
DDR_A_D40 BB9 BH24 DDR_A_MA3 DDR_B_D40 BC5 BC25 DDR_B_MA2
DDR_A_D41 SA_DQ_40 SA_MA_3 DDR_A_MA4 DDR_B_D41 SB_DQ_40 SB_MA_2 DDR_B_MA3
BA9 SA_DQ_41 SA_MA_4 BG25 BC6 SB_DQ_41 SB_MA_3 AU25
DDR_A_D42 AU10 BA24 DDR_A_MA5 DDR_B_D42 AY3 AW25 DDR_B_MA4
DDR_A_D43 SA_DQ_42 SA_MA_5 DDR_A_MA6 DDR_B_D43 SB_DQ_42 SB_MA_4 DDR_B_MA5
AV9 SA_DQ_43 SA_MA_6 BD24 AY1 SB_DQ_43 SB_MA_5 BB28
DDR_A_D44 BA11 BG27 DDR_A_MA7 DDR_B_D44 BF6 AU28 DDR_B_MA6
DDR_A_D45 SA_DQ_44 SA_MA_7 DDR_A_MA8 DDR_B_D45 SB_DQ_44 SB_MA_6 DDR_B_MA7
BD9 SA_DQ_45 SA_MA_8 BF25 BF5 SB_DQ_45 SB_MA_7 AW28
DDR_A_D46 AY8 AW24 DDR_A_MA9 DDR_B_D46 BA1 AT33 DDR_B_MA8
DDR_A_D47 SA_DQ_46 SA_MA_9 DDR_A_MA10 DDR_B_D47 SB_DQ_46 SB_MA_8 DDR_B_MA9
BA6 SA_DQ_47 SA_MA_10 BC21 BD3 SB_DQ_47 SB_MA_9 BD33
DDR_A_D48 DDR_A_MA11 DDR_B_D48 DDR_B_MA10
DDR

AV5 SA_DQ_48 SA_MA_11 BG26 AV2 SB_DQ_48 SB_MA_10 BB16

DDR_A_D49 DDR_A_MA12 DDR_B_D49 DDR_B_MA11

DDR
AV7 SA_DQ_49 SA_MA_12 BH26 AU3 SB_DQ_49 SB_MA_11 AW33
DDR_A_D50 AT9 BH17 DDR_A_MA13 DDR_B_D50 AR3 AY33 DDR_B_MA12
DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AN8 SA_DQ_51 SA_MA_14 AY25 AN2 SB_DQ_51 SB_MA_13 BH15
DDR_A_D52 AU5 DDR_B_D52 AY2 AU33 DDR_B_MA14
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
AU6 SA_DQ_53 AV1 SB_DQ_53
DDR_A_D54 AT5 DDR_B_D54 AP3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AN10 SA_DQ_55 AR1 SB_DQ_55
DDR_A_D56 AM11 DDR_B_D56 AL1
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AM5 SA_DQ_57 AL2 SB_DQ_57
DDR_A_D58 AJ9 DDR_B_D58 AJ1
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AJ8 SA_DQ_59 AH1 SB_DQ_59
DDR_A_D60 AN12 DDR_B_D60 AM2
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AM13 SA_DQ_61 AM3 SB_DQ_61
DDR_A_D62 AJ11 DDR_B_D62 AH3
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AJ12 SA_DQ_63 AJ3 SB_DQ_63
CANTIGA_1p0 CANTIGA_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(2/6)-DDR2 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 8 of 43
5 4 3 2 1
 5 4 3 2 1

U4C
R56 within 500 mils from
pin T37,T36 PEGCOMP trace width Strap Pin Table
R95 +VCC_PEG and spacing is 20/25 mils.
L32 L_BKLT_CTRL 000 = FSB 1066MHz
16,26 GMCH_ENBKL GMCH_ENBKL G32 T37 1 2 CFG[2:0] FSB Freq select
R81 1 L_BKLT_EN PEG_COMPI 010 = FSB 800MHz
+3VS 2 10K_0402_5% CTRL_CLK M32 L_CTRL_CLK PEG_COMPO T36 49.9_0402_1%

R80 1 2 10K_0402_5% CTRL_DATA M33

011 = FSB 667MHz
GMCH_EDID_CLK_LCD L_CTRL_DATA
16 GMCH_EDID_CLK_LCD K33 L_DDC_CLK PEG_RX#_0 H44 Others = Reserved
GMCH_EDID_DAT_LCD J33 J46
16 GMCH_EDID_DAT_LCD L_DDC_DATA PEG_RX#_1
PEG_RX#_2 L44
PEG_RX#_3 L40 CFG[4:3] Reserved
16 GMCH_LVDDEN GMCH_LVDDEN M29 N41
L_VDD_EN PEG_RX#_4
1 2 C44 LVDS_IBG PEG_RX#_5 P48 0 = DMI x 2
R94 2.4K_0402_1%~D B43 N44 CFG5 (DMI select)
LVDS_VBG PEG_RX#_6 1 = DMI x 4
E37
E38
LVDS_VREFH PEG_RX#_7 T43
U43
*
0 = The iTPM Host Interface is enable
D LVDS_VREFL PEG_RX#_8
* D

LVDS
16 GMCH_LVDSAC- GMCH_LVDSAC- C41 Y43 CFG6
GMCH_LVDSAC+ LVDSA_CLK# PEG_RX#_9
16 GMCH_LVDSAC+ C40 LVDSA_CLK PEG_RX#_10 Y48 1 = The iTPM Host Interface is disable
16 GMCH_LVDSBC- GMCH_LVDSBC- B37 Y36
GMCH_LVDSBC+ LVDSB_CLK# PEG_RX#_11
16 GMCH_LVDSBC+ A37 LVDSB_CLK PEG_RX#_12 AA43 0 =(TLS)chiper suite with no confidentiality
PEG_RX#_13 AD37 CFG7 (Intel Management
GMCH_LVDSA0- H47 AC47 1 =(TLS)chiper suite with confidentiality
16 GMCH_LVDSA0-
16 GMCH_LVDSA1-
16 GMCH_LVDSA2-
GMCH_LVDSA1-
GMCH_LVDSA2-
E46
G40
LVDSA_DATA#_0
LVDSA_DATA#_1
PEG_RX#_14
PEG_RX#_15 AD39 Engine Crypto strap) *
GMCH_LVDSA3- LVDSA_DATA#_2
T145 A40 LVDSA_DATA#_3 PEG_RX_0 H43
J44 CFG8 Reserved

GRAPHICS
GMCH_LVDSA0+ PEG_RX_1
16 GMCH_LVDSA0+ H48 LVDSA_DATA_0 PEG_RX_2 L43
16 GMCH_LVDSA1+ GMCH_LVDSA1+ D45 L41
GMCH_LVDSA2+ LVDSA_DATA_1 PEG_RX_3
16 GMCH_LVDSA2+ F40 LVDSA_DATA_2 PEG_RX_4 N40 CFG9 0 = Reverse Lane,15->0, 14->1
GMCH_LVDSA3+ B40 P47
T146 LVDSA_DATA_3 PEG_RX_5
PEG_RX_6 N43 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
GMCH_LVDSB0- A41 T42
16 GMCH_LVDSB0-
16 GMCH_LVDSB1-
16 GMCH_LVDSB2-
GMCH_LVDSB1-
GMCH_LVDSB2-
H38
G37
LVDSB_DATA#_0
LVDSB_DATA#_1
PEG_RX_7
PEG_RX_8 U42
Y42 0 = Enable
*
GMCH_LVDSB3- LVDSB_DATA#_2 PEG_RX_9
T147 J37 LVDSB_DATA#_3 PEG_RX_10 W47 CFG10 (PCIE Lookback enable)
Y37 1 = Disable
16 GMCH_LVDSB0+
16 GMCH_LVDSB1+
GMCH_LVDSB0+
GMCH_LVDSB1+
B42
G38
LVDSB_DATA_0
PEG_RX_11
PEG_RX_12 AA42
AD36 CFG11 Reserved
*
GMCH_LVDSB2+ LVDSB_DATA_1 PEG_RX_13
16 GMCH_LVDSB2+ F37 LVDSB_DATA_2 PEG_RX_14 AC48
GMCH_LVDSB3+ K37 AD40 CFG[13:12] (XOR/ALLZ) 00 = Reserved

PCI-EXPRESS
T148 LVDSB_DATA_3 PEG_RX_15
01 = XOR Mode Enabled
PEG_TX#_0 J41 10 = All Z Mode Enabled
M46 11 = Normal Operation(Default)
1
75_0402_1%
1
2
2 R1507
F25
H25
TVA_DAC
PEG_TX#_1
PEG_TX#_2 M47
M40 CFG[15:14] Reserved
*
75_0402_1% TVB_DAC PEG_TX#_3
1 2 R1508 K25 TVC_DAC PEG_TX#_4 M42

TV
75_0402_1% R1509 R48
PEG_TX#_5
H24 TV_RTN PEG_TX#_6 N38 CFG16 (FSB Dynamic ODT) 0 = Disabled
PEG_TX#_7 T40
U37 1 = Enabled
C31
PEG_TX#_8
PEG_TX#_9 U40
Y40
*
TV_DCONSEL_0 PEG_TX#_10
C E32 TV_DCONSEL_1 PEG_TX#_11 AA46 CFG[18:17] Reserved C
PEG_TX#_12 AA37
16 CRT_B CRT_B AA40
CRT_G PEG_TX#_13
AD43 CFG19 (DMI Lane Reversal) 0 = Normal Operation
16
16
CRT_G
CRT_R CRT_R PEG_TX#_14
PEG_TX#_15 AC46
(Lane number in Order)
*
2

2
150_0402_1%

150_0402_1%

150_0402_1%

E28 CRT_BLUE PEG_TX_0 J42

PEG_TX_1 L46 1 = Reverse Lane
R74

R76

R75

G28 CRT_GREEN PEG_TX_2 M48

M39
J28
PEG_TX_3
M43 CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational. *
1

CRT_RED PEG_TX_4
G29 CRT_IRTN
VGA PEG_TX_5
PEG_TX_6
R47
N37 1 = PCIE/SDVO are operating simu.
PEG_TX_7 T39
3VDDCCL H32 U36
16 3VDDCCL CRT_DDC_CLK PEG_TX_8
3VDDCDA J32 U39
16 3VDDCDA CRT_DDC_DATA PEG_TX_9
16 CRT_HSYNC CRT_HSYNC J29 Y39 @ R66 1 2 2.21K_0402_1%~D
CRT_HSYNC PEG_TX_10 7 CFG5
E29 CRT_TVO_IREF PEG_TX_11 Y46
16 CRT_VSYNC CRT_VSYNC L29 AA36 @ R58 1 2 2.21K_0402_1%~D
CRT_VSYNC PEG_TX_12 7 CFG6
PEG_TX_13 AA39
AD42 @ R59 1 2 2.21K_0402_1%~D
PEG_TX_14 7 CFG7
PEG_TX_15 AD46
@ R55 1 2 2.21K_0402_1%~D
7 CFG9
1

CANTIGA_1p0 @ R70 1 2 2.21K_0402_1%~D

7 CFG16
R334
1K_0402_1%
CFG[5:16] have internal pullup
2

+3VS

+3VS @ R72 1 2 4.02K_0402_1%~D

7 CFG19
R483 2.2K_0402_5%
1 2 GMCH_EDID_CLK_LCD 7 CFG20
@ R73 1 2 4.02K_0402_1%~D
B B
R484 2.2K_0402_5%
1 2 GMCH_EDID_DAT_LCD CFG[19:20] have internal pulldown

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(3/6)-VGA/LVDS/TV
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 9 of 43
5 4 3 2 1
 5 4 3 2 1

+3VS_DAC_CRT +3VS
L15 +1.05VS_DPLLA
1 2
47U_1206_6.3V6M 0_0603_5% +VCCP +VCCP
+VCCP

0.01U_0402_25V7K~N

0.1U_0402_10V4Z
1 L17 +V1.05VS_AXF
C1835

C407

C411
1 1 1 2 U4H 2 1 R101
COIL 2.2U +-20% IHLP-2525CZ-ER-2R2-M-01 8A 852mA 10UH_LB2012T100MR_20%_0805~D 1 2

0.1U_0402_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z
@ L114 U13 1 0_0603_5%
2 VTT_1

4.7U_0805_10V4Z

220U_D2_4VY_R15M

C173

C182
73mA T13 1 1 1
2 2 VTT_2

220U_D2_4VY_R15M
B27 U12 +
VCCA_CRT_DAC_1 VTT_3 1 1 1

C384

C191

C113

C69
A26 T12 +
+3VS_DAC_CRT VCCA_CRT_DAC_2 VTT_4

C370
VTT_5 U11
2.68mA 2 2 2
VTT_6 T11
2 2 2 2
A25 U10

CRT
+3VS_DAC_BG VCCA_DAC_BG VTT_7
D
SolveCRT Voltage ripple B25 VSSA_DAC_BG VTT_8 T10
U9 D
+3VS_DAC_BG +3VS_DAC_CRT VTT_9
VTT_10 T9
VTT_11 U8
R836 1 2 0_0402_5%~D +1.05VS_DPLLA 64.8mA F47 T8
VCCA_DPLLA VTT_12

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z
U7

VTT
VTT_13 +1.8V_SM_CK
0.01U_0402_25V7K~N

0.1U_0402_10V4Z

+1.05VS_DPLLB 64.8mA L48 T7 1 1 1 +1.8V

VCCA_DPLLB VTT_14 +1.05VS_DPLLB +VCCP
C405

C408

1 1 U6 R102
VTT_15

C56
C383

C373

0.1U_0402_16V4Z
24mA AD1 T6 L16 1 2

PLL
+1.05VS_HPLL VCCA_HPLL VTT_16

10U_0805_10V4Z
U5 2 1 0_0805_5%
139.2mA AE1 VTT_17 2 2 2 10UH_LB2012T100MR_20%_0805~D
+1.05VS_MPLL VCCA_MPLL VTT_18 T5 1 1
2 2

0.1U_0402_10V4Z

C178

10U_0805_10V4Z

C102
C96
VTT_19 V3

C174
VTT_20 U3 1 1
+1.8V_TXLVDS 13.2mA J48 V2
VCCA_LVDS VTT_21 2 2
1 U2

A LVDS
C413 VTT_22
J47 VSSA_LVDS VTT_23 T2
V1 2 2
1000P_0402_50V7K VTT_24
VTT_25 U1
2 414uA
AD48 VCCA_PEG_BG

A PEG
+1.5VS +1.05VS_HPLL +VCCP +1.5VS_TVDAC +1.5VS
50mA
1 +1.05VS_PEGPLL AA48 L29 R84
C175 VCCA_PEG_PLL
1 2 1 2

0.022U_0402_16V7K

0.1U_0402_10V4Z
MBK2012121YZF_0805 0_0805_5%

4.7U_0805_10V4Z
0.1U_0402_16V4Z 720mA AR20
2 VCCA_SM_1

0.1U_0402_16V4Z
AP20 VCCA_SM_2 1 1 1 1

C388

C1774
AN20 VCCA_SM_3
POWER

C161

C162
AR17 VCCA_SM_4
AP17 VCCA_SM_5
+VCCP AN17 2 2 2 2
+1.05VS_A_SM VCCA_SM_6
100U_D2E_6.3VM_R15M~D

AT16 VCCA_SM_7
R50 AR16

A SM
VCCA_SM_8
C
1 2 AP16 VCCA_SM_9 C
1 0_0805_5%
+1.05VS_MPLL +VCCP
22U_0805_6.3V6M~D

1 1 1
C82

+ C83 C72 L9
+VCC_PEG +VCCP
C68

1 2
4.7U_0805_10V4Z 1 PJP28

2
2 2 2 2 C63 LQH32CNR15M33L_1210~D @ JUMP_43X118

0_0603_5%
1U_0603_10V4Z 26mA AP28 321.35mA 1 1
VCCA_SM_CK_1 2 2

R1415
AN28 B22 +V1.05VS_AXF 0.1U_0402_16V4Z
VCCA_SM_CK_2 VCC_AXF_1 2

22U_0805_6.3V6M~D

4.7U_0805_10V4Z
AP25 B21 1

AXF
+1.05VS_A_SM_CK VCCA_SM_CK_3 VCC_AXF_2

C1775
R71 AN25 A21 1 1

1
VCCA_SM_CK_4 VCC_AXF_3

C1776
1 2 AN24 +
VCCA_SM_CK_5 1

C95

220U_D2_4VY_R15M
0_0603_5% AM28 124mA
VCCA_SM_CK_NCTF_1
22U_0805_6.3V6M~D

0.1U_0402_16V4Z

AM26 C62
A CK
VCCA_SM_CK_NCTF_2 22U_0805_6.3V6M~D 2 2 2
1 1 AM25 VCCA_SM_CK_NCTF_3 2
C104

C123

AL25 VCCA_SM_CK_NCTF_4 VCC_SM_CK_1 BF21 +1.8V_SM_CK

AM24 BH20

SM CK
VCCA_SM_CK_NCTF_5 VCC_SM_CK_2
AL24 VCCA_SM_CK_NCTF_6 VCC_SM_CK_3 BG20
2 2 +1.05VS_PEGPLL +VCCP
AM23 VCCA_SM_CK_NCTF_7 VCC_SM_CK_4 BF20 L12
AL23 VCCA_SM_CK_NCTF_8 118.8mA 1 2
TVA 24.15mA
+3VS_DAC_CRT +1.05VS_DMI

0.1U_0402_16V4Z
TVB 39.48mA K47 +1.8V_TXLVDS BLM21PG221SN1D_0805~D +VCC_PEG
VCC_TX_LVDS

R1416
TVX 24.15mA B24 1 R112
VCCA_TV_DAC_1 +3VS

C176
+3VS_DAC_CRT A24 VCCA_TV_DAC_2 VCC_HV_1 C35 1 2
TV

B35 105.3mA 0_0805_5%

VCC_HV_2

0.1U_0402_16V4Z
A35 1_0402_5%~D
HV

VCC_HV_3 2

0.1U_0402_16V4Z

10U_0805_10V4Z
HDMI disable connected to GND 50mA A32 1
VCC_HDA
HDA

C116
VCC_PEG_1 V48 1732mA +VCC_PEG 1 1

C410

C179
VCC_PEG_2 U48
V47
PEG

+1.05VS_HPLL VCC_PEG_3 2
VCC_PEG_4 U47
2 2
D TV/CRT

+1.5VS_TVDAC 58.67mA M25 U46

VCCD_TVDAC VCC_PEG_5
0.01U_0402_25V7K~N

0.1U_0402_10V4Z

B +1.5VS_QDAC 48.363mA L28 B

VCCD_QDAC
C401

C402

1 1 VCC_DMI_1 AH48 456mA +1.05VS_DMI

157.2mA AF1 AF48
VCCD_HPLL VCC_DMI_2 +1.5VS_QDAC +1.5VS
AH47
DMI

50mA VCC_DMI_3
+1.05VS_PEGPLL AA47 VCCD_PEG_PLL VCC_DMI_4 AG47
2 2 L113
C1780 0.1U_0402_16V4Z

2 1 2
60.31mA M38 20mils BLM18PG181SN1D_0603
VCCD_LVDS_1
C233 0.1U_0402_16V4Z

LVDS

0.01U_0402_25V7K~N

0.1U_0402_16V4Z
2 +1.8V_LVDS L37 VCCD_LVDS_2 VTTLF1 A8

C97

C98
VTTLF2 L1 1 1
1
VTTLF

VTTLF3 AB2
1
0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

2 2
1 1 1
C382

C385

C65

CANTIGA_1p0

2 2 2

+1.8V_LVDS +1.8V_TXLVDS
40 mils
R110 R350
1 2 +1.8V 1 2 +1.8V

10U_0805_10V4Z

1000P_0402_50V7K
0_0603_5% 0_0603_5%

10U_0805_10V4Z
1 1

C187

C186

1U_0603_10V4Z

C414
1 1

C418
2 2
A 2 2 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(4/6)-PWR
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 10 of 43
5 4 3 2 1
 5 4 3 2 1

U4G +VCCP
Extnal Graphic: 1210.34mA 3000mA
integrated Graphic: 1930.4mA AP33 W28
VCC_SM_1 VCC_AXG_NCTF_1
AN33 VCC_SM_2 VCC_AXG_NCTF_2 V28

330U_D2_2.5VY_R15M

330U_D2_2.5VY_R15M
+1.8V BH32 VCC_SM_3 VCC_AXG_NCTF_3 W26
U4F BG32 V26 1 1 Layout Note:
+VCCP VCC_SM_4 VCC_AXG_NCTF_4

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

0.1U_0402_10V7K~D

@ C86

@ C101
BF32 VCC_SM_5 VCC_AXG_NCTF_5 W25

330U_V_2.5VM
BD32 V25 + + Place close to GMCH
1 VCC_SM_6 VCC_AXG_NCTF_6
1 1 2 BC32 VCC_SM_7 VCC_AXG_NCTF_7 W24

C165

C147
C148
D
AG34 + BB32 V24 D
VCC_1 VCC_SM_8 VCC_AXG_NCTF_8 2 2

C164
AC34 VCC_2 BA32 VCC_SM_9 VCC_AXG_NCTF_9 W23
AB34 VCC_3 AY32 VCC_SM_10 VCC_AXG_NCTF_10 V23
2 2 2 1
AA34 VCC_4 AW32 VCC_SM_11 VCC_AXG_NCTF_11 AM21
Y34 VCC_5 AV32 VCC_SM_12 VCC_AXG_NCTF_12 AL21
V34 VCC_6 AU32 VCC_SM_13 VCC_AXG_NCTF_13 AK21
U34 VCC_7 AT32 VCC_SM_14 VCC_AXG_NCTF_14 W21
AM33 0317 change value AR32 V21
VCC_8 VCC_SM_15 VCC_AXG_NCTF_15

POWER
AK33 VCC_9 AP32 VCC_SM_16 VCC_AXG_NCTF_16 U21
AJ33 VCC_10 AN32 VCC_SM_17 VCC_AXG_NCTF_17 AM20
22U_0805_6.3V6M~D

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z
AG33 VCC_11 BH31 VCC_SM_18 VCC_AXG_NCTF_18 AK20
1 AF33 VCC_12 BG31 VCC_SM_19 VCC_AXG_NCTF_19 W20
220U_D2_4VY_R15M

1 1 1 1 BF31 VCC_SM_20 VCC_AXG_NCTF_20 U20

C118

C143

C119

+ C120
AE33 VCC_13 BG30 VCC_SM_21 VCC_AXG_NCTF_21 AM19
C374

VCC CORE
AC33 VCC_14 BH29 VCC_SM_22 VCC_AXG_NCTF_22 AL19
AA33 VCC_15 BG29 VCC_SM_23 VCC_AXG_NCTF_23 AK19
2 2 2 2 2
Y33 VCC_16 BF29 VCC_SM_24 VCC_AXG_NCTF_24 AJ19
W33 VCC_17 BD29 VCC_SM_25 VCC_AXG_NCTF_25 AH19

VCC SM
V33 VCC_18 BC29 VCC_SM_26 VCC_AXG_NCTF_26 AG19
U33 VCC_19 BB29 VCC_SM_27 VCC_AXG_NCTF_27 AF19
AH28 VCC_20 BA29 VCC_SM_28 VCC_AXG_NCTF_28 AE19
AF28 VCC_21 AY29 VCC_SM_29 VCC_AXG_NCTF_29 AB19
AC28 VCC_22 AW29 VCC_SM_30 VCC_AXG_NCTF_30 AA19
AA28 VCC_23 AV29 VCC_SM_31 VCC_AXG_NCTF_31 Y19
AJ26 VCC_24 AU29 VCC_SM_32 VCC_AXG_NCTF_32 W19
AG26 VCC_25 AT29 VCC_SM_33 VCC_AXG_NCTF_33 V19
AE26 VCC_26 AR29 VCC_SM_34 VCC_AXG_NCTF_34 U19
AC26 VCC_27 AP29 VCC_SM_35 VCC_AXG_NCTF_35 AM17
AH25 VCC_28 VCC_AXG_NCTF_36 AK17
AG25 VCC_29 BA36 VCC_SM_36/NC VCC_AXG_NCTF_37 AH17
AF25 VCC_30 BB24 VCC_SM_37/NC VCC_AXG_NCTF_38 AG17
AG24 VCC_31 BD16 VCC_SM_38/NC VCC_AXG_NCTF_39 AF17
+VCCP

0.47U_0402_6.3V4Z~D

1U_0603_10V4Z~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

10U_0805_10V4Z~D

22U_0805_6.3VAM~D
C C
AJ23 VCC_32 BB21 VCC_SM_39/NC VCC_AXG_NCTF_40 AE17
AH23 VCC_33 POWER AW16 VCC_SM_40/NC VCC_AXG_NCTF_41 AC17
AF23 VCC_34 AW13 VCC_SM_41/NC VCC_AXG_NCTF_42 AB17 1 1 1 1 1 1
VCC_NCTF_1 AM32 AT13 VCC_SM_42/NC VCC_AXG_NCTF_43 Y17

C100
C99

C78

C57

C79

C80
T32 VCC_35 VCC_NCTF_2 AL32 VCC_AXG_NCTF_44 W17
AK32 +VCCP 6326.84mA V17

VCC GFX NCTF

VCC_NCTF_3 VCC_AXG_NCTF_45 2 2 2 2 2 2
VCC_NCTF_4 AJ32 VCC_AXG_NCTF_46 AM16
VCC_NCTF_5 AH32 Y26 VCC_AXG_1 VCC_AXG_NCTF_47 AL16
VCC_NCTF_6 AG32 AE25 VCC_AXG_2 VCC_AXG_NCTF_48 AK16
VCC_NCTF_7 AE32 AB25 VCC_AXG_3 VCC_AXG_NCTF_49 AJ16
VCC_NCTF_8 AC32 AA25 VCC_AXG_4 VCC_AXG_NCTF_50 AH16
VCC_NCTF_9 AA32 AE24 VCC_AXG_5 VCC_AXG_NCTF_51 AG16
VCC_NCTF_10 Y32 AC24 VCC_AXG_6 VCC_AXG_NCTF_52 AF16
VCC_NCTF_11 W32 AA24 VCC_AXG_7 VCC_AXG_NCTF_53 AE16 Layout Note: Inside GMCH
VCC_NCTF_12 U32 Y24 VCC_AXG_8 VCC_AXG_NCTF_54 AC16 cavity for VCC_AXG.
VCC_NCTF_13 AM30 AE23 VCC_AXG_9 VCC_AXG_NCTF_55 AB16
VCC_NCTF_14 AL30 AC23 VCC_AXG_10 VCC_AXG_NCTF_56 AA16
VCC_NCTF_15 AK30 AB23 VCC_AXG_11 VCC_AXG_NCTF_57 Y16
VCC_NCTF_16 AH30 AA23 VCC_AXG_12 VCC_AXG_NCTF_58 W16
VCC_NCTF_17 AG30 AJ21 VCC_AXG_13 VCC_AXG_NCTF_59 V16
VCC_NCTF_18 AF30 AG21 VCC_AXG_14 VCC_AXG_NCTF_60 U16
VCC_NCTF_19 AE30 AE21 VCC_AXG_15
VCC_NCTF_20 AC30 AC21 VCC_AXG_16
VCC_NCTF_21 AB30 AA21 VCC_AXG_17
VCC_NCTF_22 AA30 Y21 VCC_AXG_18
VCC_NCTF_23 Y30 AH20 VCC_AXG_19
VCC_NCTF_24 W30 AF20 VCC_AXG_20
VCC NCTF

VCC_NCTF_25 V30 AE20 VCC_AXG_21

VCC_NCTF_26 U30 AC20 VCC_AXG_22
VCC_NCTF_27 AL29 AB20 VCC_AXG_23
VCC_NCTF_28 AK29 AA20 VCC_AXG_24
VCC_NCTF_29 AJ29 T17 VCC_AXG_25
B B
VCC_NCTF_30 AH29 T16 VCC_AXG_26
VCC_NCTF_31 AG29 AM15 VCC_AXG_27
VCC_NCTF_32 AE29 AL15 VCC_AXG_28
VCC_NCTF_33 AC29 AE15 VCC_AXG_29
VCC_NCTF_34 AA29 AJ15 VCC_AXG_30
VCC_NCTF_35 Y29 AH15 VCC_AXG_31
VCC_NCTF_36 W29 AG15 VCC_AXG_32
VCC_NCTF_37 V29 AF15 VCC_AXG_33
VCC_NCTF_38 AL28 AB15 VCC_AXG_34
VCC_NCTF_39 AK28 AA15 VCC_AXG_35

VCC GFX
VCC_NCTF_40 AL26 Y15 VCC_AXG_36
VCC_NCTF_41 AK26 V15 VCC_AXG_37
VCC_NCTF_42 AK25 U15 VCC_AXG_38
VCC_NCTF_43 AK24 AN14 VCC_AXG_39
VCC_NCTF_44 AK23 AM14 VCC_AXG_40
U14 VCC_AXG_41 VCC_SM_LF1 AV44 VCCSM_LF1

VCC SM LF
T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
VCC_SM_LF3 AM40 VCCSM_LF3
VCC_SM_LF4 AV21 VCCSM_LF4
VCC_SM_LF5 AY5 VCCSM_LF5
VCC_SM_LF6 AM10 VCCSM_LF6
CANTIGA_1p0
VCC_SM_LF7 BB13 VCCSM_LF7

C146

C145

C163
C70

C71

C67

C81
1 1 1 1 1 1 1

PAD T42 AJ14 VCC_AXG_SENSE

0.1U_0402_16V4Z

0.1U_0402_16V4Z
PAD T43 AH14 VSS_AXG_SENSE 2 2 2 2 2 2 2

0.47U_0402_6.3V6K
0.22U_0603_10V7K

0.22U_0603_10V7K

1U_0603_10V4Z

1U_0603_10V4Z
A A

CANTIGA_1p0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(5/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 11 of 43
5 4 3 2 1
 5 4 3 2 1

U4J
U4I BG21 AH8
VSS_199 VSS_297
L12 VSS_200 VSS_298 Y8
AU48 VSS_1 VSS_100 AM36 AW21 VSS_201 VSS_299 L8
AR48 VSS_2 VSS_101 AE36 AU21 VSS_202 VSS_300 E8
AL48 VSS_3 VSS_102 P36 AP21 VSS_203 VSS_301 B8
BB47 VSS_4 VSS_103 L36 AN21 VSS_204 VSS_302 AY7
AW47 VSS_5 VSS_104 J36 AH21 VSS_205 VSS_303 AU7
AN47 VSS_6 VSS_105 F36 AF21 VSS_206 VSS_304 AN7
AJ47 VSS_7 VSS_106 B36 AB21 VSS_207 VSS_305 AJ7
AF47 VSS_8 VSS_107 AH35 R21 VSS_208 VSS_306 AE7
D D
AD47 VSS_9 VSS_108 AA35 M21 VSS_209 VSS_307 AA7
AB47 VSS_10 VSS_109 Y35 J21 VSS_210 VSS_308 N7
Y47 VSS_11 VSS_110 U35 G21 VSS_211 VSS_309 J7
T47 VSS_12 VSS_111 T35 BC20 VSS_212 VSS_310 BG6
N47 VSS_13 VSS_112 BF34 BA20 VSS_213 VSS_311 BD6
L47 VSS_14 VSS_113 AM34 AW20 VSS_214 VSS_312 AV6
G47 VSS_15 VSS_114 AJ34 AT20 VSS_215 VSS_313 AT6
BD46 VSS_16 VSS_115 AF34 AJ20 VSS_216 VSS_314 AM6
BA46 VSS_17 VSS_116 AE34 AG20 VSS_217 VSS_315 M6
AY46 VSS_18 VSS_117 W34 Y20 VSS_218 VSS_316 C6
AV46 VSS_19 VSS_118 B34 N20 VSS_219 VSS_317 BA5
AR46 VSS_20 VSS_119 A34 K20 VSS_220 VSS_318 AH5
AM46 VSS_21 VSS_120 BG33 F20 VSS_221 VSS_319 AD5
V46 VSS_22 VSS_121 BC33 C20 VSS_222 VSS_320 Y5
R46 VSS_23 VSS_122 BA33 A20 VSS_223 VSS_321 L5
P46 VSS_24 VSS_123 AV33 BG19 VSS_224 VSS_322 J5
H46 VSS_25 VSS_124 AR33 A18 VSS_225 VSS_323 H5
F46 VSS_26 VSS_125 AL33 BG17 VSS_226 VSS_324 F5
BF44 VSS_27 VSS_126 AH33 BC17 VSS_227 VSS_325 BE4
AH44 VSS_28 VSS_127 AB33 AW17 VSS_228
AD44 P33 AT17 BC3
AA44
Y44
VSS_29
VSS_30
VSS_31
VSS_128
VSS_129
VSS_130
L33
H33
R17
M17
VSS_229
VSS_230
VSS_231
VSS VSS_327
VSS_328
VSS_329
AV3
AL3
U44 VSS_32 VSS_131 N32 H17 VSS_232 VSS_330 R3
T44 K32 C17 P3
M44
F44
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
F32
C32 BA16
VSS_233

VSS_235
VSS_331
VSS_332
VSS_333
F3
BA2
BC43 VSS_36 VSS_135 A31 VSS_334 AW2
AV43 VSS_37 VSS_136 AN29 AU16 VSS_237 VSS_335 AU2
AU43 VSS_38 VSS_137 T29 AN16 VSS_238 VSS_336 AR2
AM43 VSS_39 VSS_138 N29 N16 VSS_239 VSS_337 AP2
J43 VSS_40 VSS_139 K29 K16 VSS_240 VSS_338 AJ2
C C
C43 VSS_41 VSS_140 H29 G16 VSS_241 VSS_339 AH2
BG42 VSS_42 VSS_141 F29 E16 VSS_242 VSS_340 AF2
AY42 VSS_43 VSS_142 A29 BG15 VSS_243 VSS_341 AE2
AT42 VSS_44 VSS_143 BG28 AC15 VSS_244 VSS_342 AD2
AN42 VSS_45 VSS_144 BD28 W15 VSS_245 VSS_343 AC2
AJ42 VSS_46 VSS_145 BA28 A15 VSS_246 VSS_344 Y2
AE42 VSS_47 VSS_146 AV28 BG14 VSS_247 VSS_345 M2
N42 VSS_48 VSS_147 AT28 AA14 VSS_248 VSS_346 K2
L42 VSS_49 VSS_148 AR28 C14 VSS_249 VSS_347 AM1
BD41 VSS_50 VSS_149 AJ28 BG13 VSS_250 VSS_348 AA1
AU41 VSS_51 VSS_150 AG28 BC13 VSS_251 VSS_349 P1
AM41 VSS_52 VSS_151 AE28 BA13 VSS_252 VSS_350 H1
AH41 VSS_53 VSS_152 AB28
AD41 VSS_54 VSS_153 Y28 VSS_351 U24
AA41 VSS_55 VSS_154 P28 AN13 VSS_255 VSS_352 U28
Y41 VSS_56 VSS_155 K28 AJ13 VSS_256 VSS_353 U25
U41 VSS_57 VSS_156 H28 AE13 VSS_257 VSS_354 U29
T41 VSS_58 VSS_157 F28 N13 VSS_258
M41 VSS_59 VSS_158 C28 L13 VSS_259
G41 VSS_60 VSS_159 BF26 G13 VSS_260 VSS_NCTF_1 AF32
B41 VSS_61 VSS_160 AH26 E13 VSS_261 VSS_NCTF_2 AB32
BG40 VSS_62 VSS_161 AF26 BF12 VSS_262 VSS_NCTF_3 V32
BB40 VSS_63 VSS_162 AB26 AV12 VSS_263 VSS_NCTF_4 AJ30
AV40 VSS_64 VSS_163 AA26 AT12 VSS_264 VSS_NCTF_5 AM29
AN40 VSS_65 VSS_164 C26 AM12 VSS_265 VSS_NCTF_6 AF29
H40 B26 AA12 AB29

VSS NCTF
VSS_66 VSS_165 VSS_266 VSS_NCTF_7
E40 VSS_67 VSS_166 BH25 J12 VSS_267 VSS_NCTF_8 U26
AT39 VSS_68 VSS_167 BD25 A12 VSS_268 VSS_NCTF_9 U23
AM39 VSS_69 VSS_168 BB25 BD11 VSS_269 VSS_NCTF_10 AL20
AJ39 VSS_70 VSS_169 AV25 BB11 VSS_270 VSS_NCTF_11 V20
AE39 VSS_71 VSS_170 AR25 AY11 VSS_271 VSS_NCTF_12 AC19
N39 VSS_72 VSS_171 AJ25 AN11 VSS_272 VSS_NCTF_13 AL17
B B
L39 VSS_73 VSS_172 AC25 AH11 VSS_273 VSS_NCTF_14 AJ17
B39 VSS_74 VSS_173 Y25 VSS_NCTF_15 AA17
BH38 VSS_75 VSS_174 N25 Y11 VSS_275 VSS_NCTF_16 U17
BC38 VSS_76 VSS_175 L25 N11 VSS_276
BA38 VSS_77 VSS_176 J25 G11 VSS_277
AU38 G25 C11 BH48

VSS SCB
VSS_78 VSS_177 VSS_278 VSS_SCB_1
AH38 VSS_79 VSS_178 E25 BG10 VSS_279 VSS_SCB_2 BH1
AD38 VSS_80 VSS_179 BF24 AV10 VSS_280 VSS_SCB_3 A48
AA38 VSS_81 VSS_180 AD12 AT10 VSS_281 VSS_SCB_4 C1
Y38 VSS_82 VSS_181 AY24 AJ10 VSS_282 VSS_SCB_5 A3
U38 VSS_83 VSS_182 AT24 AE10 VSS_283
T38 VSS_84 VSS_183 AJ24 AA10 VSS_284 NC_26 E1
J38 VSS_85 VSS_184 AH24 M10 VSS_285 NC_27 D2
F38 VSS_86 VSS_185 AF24 BF9 VSS_286 NC_28 C3
C38 VSS_87 VSS_186 AB24 BC9 VSS_287 NC_29 B4
BF37 VSS_88 VSS_187 R24 AN9 VSS_288 NC_30 A5
BB37 VSS_89 VSS_188 L24 AM9 VSS_289 NC_31 A6
AW37 VSS_90 VSS_189 K24 AD9 VSS_290 NC_32 A43
AT37 VSS_91 VSS_190 J24 G9 VSS_291 NC_33 A44
AN37 G24 B9 B45

NC
VSS_92 VSS_191 VSS_292 NC_34
AJ37 VSS_93 VSS_192 F24 BH8 VSS_293 NC_35 C46
H37 VSS_94 VSS_193 E24 BB8 VSS_294 NC_36 D47
C37 VSS_95 VSS_194 BH23 AV8 VSS_295 NC_37 B47
BG36 VSS_96 VSS_195 AG23 AT8 VSS_296 NC_38 A46
BD36 VSS_97 VSS_196 Y23 NC_39 F48
AK15 VSS_98 VSS_197 B23 NC_40 E48
AU36 VSS_99 VSS_198 A23 NC_41 C48
VSS_199 AJ6 NC_42 B48

CANTIGA_1p0 CANTIGA_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(6/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 12 of 43
5 4 3 2 1
 5 4 3 2 1

Close to VREF pins of SO-DIMM

+1.8V
8 DDR_A_DQS#[0..7] +V_DDR_MCH_REF 7,14

8 DDR_A_D[0..63] JDIM2

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D5 1 1
8 DDR_A_DM[0..7] VSS DQ4

C201

C220
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
8 DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
DDR_A_DQS#0 VSS DM0 2 2
8 DDR_A_MA[0..13] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D6
DQS0 DQ6 DDR_A_D7
15 VSS DQ7 16
DDR_A_D2 17 18
DDR_A_D3 DQ2 VSS DDR_A_D13
19 DQ3 DQ12 20
D DDR_A_D12 D
21 VSS DQ13 22
DDR_A_D8 23 24
DDR_A_D9 DQ8 VSS DDR_A_DM1
Layout Note: 25 DQ9 DM1 26
27 VSS VSS 28
Place near JDIM1 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 7
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 DQS1 CK0# 32 M_CLK_DDR#0 7
33 VSS VSS 34
DDR_A_D14 35 36 DDR_A_D11
DDR_A_D15 DQ10 DQ14 DDR_A_D10
37 DQ11 DQ15 38
39 VSS VSS 40

+1.8V 41 42
DDR_A_D16 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21
DQ17 DQ21
47 VSS VSS 48
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

330U 2.5V Y D2
1 DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 7
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C105

C124

C149

C166

C169

C154

C131

C130

C108

C84
+ 53 54
DDR_A_D18 VSS VSS DDR_A_D23
55 DQ18 DQ22 56
@ DDR_A_D19 57 58 DDR_A_D22
2 2 2 2 2 2 2 2 2 2 DQ19 DQ23
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
Layout Note: DDR_CKE0_DIMMA
77 VSS VSS 78
DDR_CKE1_DIMMA
7 DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA 7
C Place one cap close to every 2 pullup 81 82 C
VDD VDD
resistors terminated to +0.9V 83 NC NC/A15 84
DDR_A_BS#2 85 86 DDR_A_MA14
8 DDR_A_BS#2 BA2 NC/A14 DDR_A_MA14 8
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 8
DDR_A_BS#0 107 108 DDR_A_RAS#
+0.9VS 8 DDR_A_BS#0 BA0 RAS# DDR_A_RAS# 8
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
8 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 7
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
8 DDR_A_CAS# CAS# ODT0 M_ODT0 7
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
7 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

7 M_ODT1 M_ODT1 119 120

NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D37 123 124 DDR_A_D32
DDR_A_D36 DQ32 DQ36 DDR_A_D33
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C106

C125

C126

C127

C150

C151

C167

C107

C128

C129

C152

C153

C168

C1779

133 134 DDR_A_D39

DDR_A_D35 VSS DQ38 DDR_A_D38
135 DQ34 DQ39 136
DDR_A_D34 137 138
DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D47
DDR_A_D44 DQ40 DQ45
143 DQ41 VSS 144
B DDR_A_DQS#5 B
145 VSS DQS5# 146
DDR_A_DM5 147 148 DDR_A_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D43
DDR_A_D46 DQ42 DQ46 DDR_A_D42
Layout Note: 153 DQ43 DQ47 154
Pla ce these resistor 155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D52
closely JP41,all DDR_A_D48 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
trace length Max=1.5" 161 VSS VSS 162
163 164 M_CLK_DDR1
NC,TEST CK1 M_CLK_DDR1 7
165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 7
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_A_D54 173 174 DDR_A_D51
+0.9VS DDR_A_D50 DQ50 DQ54 DDR_A_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_A_D61 179 180 DDR_A_D57
RP14 RP22 56_0404_4P2R_5% DDR_A_D60 DQ56 DQ60 DDR_A_D56
181 DQ57 DQ61 182
DDR_A_MA5 1 4 4 1 DDR_A_BS#2 183 184
DDR_A_MA8 VSS VSS
2 3 3 2 DDR_CKE0_DIMMA DDR_A_DM7 185 DM7 DQS7# 186 DDR_A_DQS#7
187 188 DDR_A_DQS7
RP13 56_0404_4P2R_5% RP17 56_0404_4P2R_5% DDR_A_D59 VSS DQS7
189 DQ58 VSS 190
DDR_A_MA1 1 4 4 1 DDR_A_MA6 DDR_A_D58 191 192 DDR_A_D62
DDR_A_MA3 DQ59 DQ62
2 3 3 2 DDR_A_MA7 193 VSS DQ63 194 DDR_A_D63
CLK_SMBDATA 195 196
14,15,19,23 ICH_SM_DA SDA VSS
RP7 56_0404_4P2R_5% RP15 56_0404_4P2R_5% CLK_SMBCLK 197 198
14,15,19,23 ICH_SM_CLK SCL SA0
DDR_CS0_DIMMA# 1 4 4 1 DDR_A_MA9 199 200
+3VS VDDSPD SA1
DDR_A_RAS# 2 3 3 2 DDR_A_MA12 1

1
10K_0402_5%

10K_0402_5%
1 1
RP6 56_0404_4P2R_5% RP16 56_0404_4P2R_5% C58 C59 FOX_ASOA426-M2RN-7F
R31

R32
DDR_A_MA10 1 4 4 1 DDR_A_MA4
A DDR_A_BS#0 2 3 3 2 DDR_A_MA2 0.1U_0402_16V4Z
2 2
2.2U_0603_6.3V6K SO-DIMM A A

REVERSE
2

RP5 56_0404_4P2R_5% RP8 56_0404_4P2R_5%

DDR_A_WE# 1 4 4 1 DDR_A_BS#1
DDR_A_CAS# 2 3 3 2 DDR_A_MA0
Bottom side
RP1 56_0404_4P2R_5% RP2 56_0404_4P2R_5%
DDR_CS1_DIMMA# 2 3 4 1 DDR_A_MA13
M_ODT1 1 4 3 2 M_ODT0
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title
56_0404_4P2R_5% RP23 56_0404_4P2R_5%
DDR_CKE1_DIMMA 1 2 4 1 DDR_A_MA11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR2 SO-DIMM I
R96 56_0402_5% 3 2 DDR_A_MA14 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 13 of 43
5 4 3 2 1
 5 4 3 2 1

8 DDR_B_DQS#[0..7] Close to VREF pins of SO-DIMM

+1.8V
8 DDR_B_D[0..63]
+V_DDR_MCH_REF 7,13
8 DDR_B_DM[0..7] JDIM1

2.2U_0805_16V4Z

0.1U_0402_16V4Z
8 DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D5 1 1
DDR_B_D0 VSS DQ4 DDR_B_D4
8 DDR_B_MA[0..13] 5 DQ0 DQ5 6

C221

C222
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
DDR_B_D2 17 18
D DDR_B_D3 DQ2 VSS DDR_B_D12 D
Layout Note: 19 DQ3 DQ12 20
DDR_B_D13
21 VSS DQ13 22
Place near JDIM2 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR2
DQS1# CK0 M_CLK_DDR2 7
DDR_B_DQS1 31 32 M_CLK_DDR#2
DQS1 CK0# M_CLK_DDR#2 7
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

330U 2.5V Y D2
1 DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C112

C139

C160

C138

C177

C109

C132

C133

C155

C189
+ 47 48
DDR_B_DQS#2 VSS VSS
49 DQS2# NC 50 PM_EXTTS#1 7
@ DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D29
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
Layout Note: DDR_B_D30
71 VSS VSS 72
DDR_B_D26
73 DQ26 DQ30 74
Place one cap close to every 2 pullup DDR_B_D31 75 76 DDR_B_D27
DQ27 DQ31
C
resistors terminated to +0.9VS DDR_CKE2_DIMMB
77 VSS VSS 78
DDR_CKE3_DIMMB C
7 DDR_CKE2_DIMMB 79 CKE0 NC/CKE1 80 DDR_CKE3_DIMMB 7
81 VDD VDD 82
83 NC NC/A15 84
DDR_B_BS#2 85 86 DDR_B_MA14
8 DDR_B_BS#2 BA2 NC/A14 DDR_B_MA14 8
87 VDD VDD 88
DDR_B_MA12 89 90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
+0.9VS A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
A10/AP BA1 DDR_B_BS#1 8
DDR_B_BS#0 107 108 DDR_B_RAS#
8 DDR_B_BS#0 BA0 RAS# DDR_B_RAS# 8
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
8 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 7
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
8 DDR_B_CAS# CAS# ODT0 M_ODT2 7
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13

7 DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
7 M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C110

C134

C135

C156

C157

C170

C171

C111

C136

C158

C137

C172

C159

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
DDR_B_D40 141 142 DDR_B_D45
B DDR_B_D41 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
Layout Note: 147 DM5 DQS5 148
Pla ce these resistor 149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
closely JP42,all DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
trace length Max=1.5" 155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR3
NC,TEST CK1 M_CLK_DDR3 7
165 166 M_CLK_DDR#3
+0.9VS DDR_B_DQS#6 VSS CK1# M_CLK_DDR#3 7
167 DQS6# VSS 168
DDR_B_DQS6 169 170 DDR_B_DM6
DQS6 DM6
171 VSS VSS 172
DDR_B_D51 173 174 DDR_B_D54
RP18 RP24 56_0404_4P2R_5% DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
DDR_B_MA1 1 4 4 1 DDR_B_MA9 177 178
DDR_B_MA3 DDR_B_MA12 DDR_B_D56 VSS VSS DDR_B_D60
2 3 3 2 179 DQ56 DQ60 180
DDR_B_D61 181 182 DDR_B_D57
RP10 56_0404_4P2R_5% RP26 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_BS#0 1 4 4 1 DDR_B_MA14 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_MA10 DDR_B_MA11 DM7 DQS7# DDR_B_DQS7
2 3 3 2 187 VSS DQS7 188
DDR_B_D59 189 190
RP12 56_0404_4P2R_5% RP19 56_0404_4P2R_5% DDR_B_D58 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
DDR_B_MA0 1 4 4 1 DDR_B_MA8 193 194 DDR_B_D63
DDR_B_BS#1 DDR_B_MA5 CLK_SMBDATA VSS DQ63
2 3 3 2 13,15,19,23 ICH_SM_DA 195 SDA VSS 196
CLK_SMBCLK 197 198 R33
13,15,19,23 ICH_SM_CLK SCL SAO
RP11 56_0404_4P2R_5% RP21 56_0404_4P2R_5% 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_B_RAS# 1 4 4 1 DDR_B_MA7

1
10K_0402_5%
DDR_CS2_DIMMB# 2 3 3 2 DDR_B_MA6 1 1 10K_0402_5%

R34
C61 C60 FOX_AS0A426-NARN-7F~N
A RP9 56_0404_4P2R_5% RP20 56_0404_4P2R_5% A
DDR_B_CAS#
DDR_B_WE#
1 4 4 1 DDR_B_MA4
DDR_B_MA2
0.1U_0402_16V4Z
2 2
2.2U_0603_6.3V6K SO-DIMM B
2 3 3 2
REVERSE
2

RP3
56_0404_4P2R_5% RP4 56_0404_4P2R_5%
DDR_CS3_DIMMB# 2 3 4 1 DDR_B_MA13 Bottom side
M_ODT3 1 4 3 2 M_ODT2

56_0404_4P2R_5% RP25 Security Classification Compal Secret Data Compal Electronics, Inc.
4 1 DDR_CKE2_DIMMB 2007/1/15 2008/1/15 Title
DDR_CKE3_DIMMB1 DDR_B_BS#2
Issued Date Deciphered Date
2 3 2
R335 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR2 SO-DIMM II
56_0404_4P2R_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 14 of 43
5 4 3 2 1
 5 4 3 2 1

+3VS_CK505
Routing the trace at least 10mil R971
FSC FSB FSA CPU SRC PCI REF DOT_96 USB 1 2
+3VS
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz CLK_XTAL_OUT 0_0805_5% 1
C1189
1
C1190
1
C1191
1
C1192
1
C1193
1
C1194
1
C1195
CLK_XTAL_IN

2
0_0402_5%
0 0 0 266 100 33.3 14.318 96.0 48.0 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2

R1417
0 0 1 133 100 33.3 14.318 96.0 48.0 14.31818MHZ_16P
Y7 0905 Connect to +VCCP

1
+VCCP +1.05VS_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0 2 1
Place close to U55
D R972 D
0 1 1 166 100 33.3 14.318 96.0 48.0 2 2
1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
C1196 C1197 0_0805_5% 1 1 1 1 1 1 1
1 0 0 333 100 33.3 14.318 96.0 48.0 22P_0402_50V8J 22P_0402_50V8J C1198 C1199 C1200 C1201 C1202 C1203 C1204
1 1

+1.05VS_CK505 2 2 2 2 2 2 2
1 0 1 100 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 0 400 100 33.3 14.318 96.0 48.0

+3VS_CK505
1 1 1 Reserved
MEDIA_REQ#32 29
CLK_PCIE_MEDIA 29 CardBus OZ888
CLK_PCIE_MEDIA# 29

R976 1 2 0_0402_5% R_MCH_BCLK# R_CLKREQ#_EXPCARD R977 1 2 0_0402_5%

7 CLK_MCH_BCLK# EXPCARD_REQ#16 25
NB R978 1 2 0_0402_5% R_MCH_BCLK R_PCIE_EXPR R979 1 2 0_0402_5% Express Card
7 CLK_MCH_BCLK CLK_PCIE_EXPR 25
R980 2 1 0_0402_5% R_CPU_BCLK# R_PCIE_EXPR# R981 1 2 0_0402_5%
4 CLK_CPU_BCLK# CLK_PCIE_EXPR# 25
R983 CPU R982 2 1 0_0402_5% R_CPU_BCLK
4 CLK_CPU_BCLK
FSA 1 2 1 2 +3VS_CK505
MCH_CLKSEL0 7
2.2K_0402_5% R985
1K_0402_5%

73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
5 CPU_BSEL0
U55
+3VS_CK505 +1.05VS_CK505

SRC_8/CPU_ITP
GND
VDD_CPU

VSS_CPU

VDD_CPU_IO

VDD_SRC_IO

VSS_SRC

VDD_SRC
CPU_0
CPU_0#

CPU_1
CPU_1#

CLKREQ_7#

SRC_7
SRC_7#

CLKREQ_6#
SRC_6
SRC_6#
SRC_8#/CPU_ITP#
C C
R987 1 2 0_0402_5% R_CKPWRGD 1 54 H_STP_PCI#
19 CK_PWRGD CKPWRGD/PD# PCI_STOP# H_STP_PCI# 19
CPU_BSEL1 2 53 H_STP_CPU# CPU_STP
FS_B/TEST_MODE CPU_STOP# H_STP_CPU# 19
3 VSS_REF VDD_SRC_IO 52
CLK_XTAL_OUT 4 51
CLK_XTAL_IN XTAL_OUT SRC_10#
5 XTAL_IN SRC_10 50
6 VDD_REF CLKREQ_10# 49
R991 1 2 33_0402_1% FSC 7 48 R_PCIE_SATA R992 1 2 0_0402_5%
19 CLK_14M_ICH REF_0/FS_C/TEST_ SRC_11 CLK_PCIE_SATA 18
PAD T120 8 47 R_PCIE_SATA# R994 1 2 0_0402_5% ICH_SATA
REF_1 SRC_11# CLK_PCIE_SATA# 18
13,14,19,23 ICH_SM_DA ICH_SM_DA 9 46 R_CLKSATAREQ# R995 1 2 0_0402_5%
SDA CLKREQ_11# CLKSATAREQ# 19
13,14,19,23 ICH_SM_CLK ICH_SM_CLK 10 45 R_CLK_PCIE_LAN# R996 1 2 0_0402_5%
SCL SRC_9# CLK_PCIE_LAN# 21
11 44 R_CLK_PCIE_LAN R997 1 2 0_0402_5% GLAN
NC SRC_9 CLK_PCIE_LAN 21
CPU_BSEL1 1 2 12 43 R_CLKREQ#_GLAN
MCH_CLKSEL1 7 VDD_PCI CLKREQ_9# GLAN_REQ#9 21
R998 13 42
1K_0402_5% R1001 33_0402_1% PCI2_TME PCI_1 VSS_SRC
1 2 14 PCI_2 CLKREQ_4# 41 WLAN_REQ#4 23
23 CLK_DEBUG_PORT R1004 33_0402_1% R_CLK_PCI_EC R_CLK_PCIE_MCARD# R1005 1
5 CPU_BSEL1 1 2 15 PCI_3 SRC_4# 40 2 0_0402_5% CLK_PCIE_MCARD# 23
26 CLK_PCI_EC R1006 33_0402_1% 27_SEL R_CLK_PCIE_MCARD R1007 1
27 CLK_PCI_TPM 1 2 16 PCI_4/SEL_LCDCL SRC_4 39 2 0_0402_5% CLK_PCIE_MCARD 23 MiniCard_WLAN

USB_1/CLKREQ_A#
R1008 1 2 33_0402_1% ITP_EN 17 38
17 PCI_CLK

LCDCLK#/27M_SS
PCIF_5/ITP_EN VDD_SRC_IO

SRC_0#/DOT_96#
18 VSS_PCI CLKREQ_3# 37

SRC_0/DOT_96
0905 Connect PCI_CLK

VDD_PLL3_IO
LCDCLK/27M
USB_0/FS_A

VDD_PLL3

VSS_PLL3

VSS_SRC
VDD_48

SRC_2#

SRC_3#
VDD_IO
VSS_48

VSS_IO

SRC_2

SRC_3
S IC ICS9LPRS397AKLFT MLF 72P CLK GEN

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
+3VS_CK505
R_PCIE_ICH# R1010 1 2 0_0402_5%
CLK_PCIE_ICH# 19
R_PCIE_ICH R1012 1 2 0_0402_5% ICH9
CLK_PCIE_ICH 19
R1013 1 2 33_0402_1% FSA
19 CLK_48M_ICH
B R1016 R1014 1 B
7 CLKREQ#_7 2 0_0402_5% R_CLKREQ#_7 R_MCH_3GPLL# R1015 1 2 0_0402_5%
CLK_MCH_3GPLL# 7
FSC 1 2 1 2 +1.05VS_CK505 R_MCH_3GPLL R1018 1 2 0_0402_5% NB_3GPLL
MCH_CLKSEL2 7 CLK_MCH_3GPLL 7
10K_0402_5% R1017 +1.05VS_CK505
1K_0402_5% R1019 2 1 0_0402_5% R_MCH_DREFCLK
7 CLK_MCH_DREFCLK
R1021 2 1 0_0402_5% R_MCH_DREFCLK# SSCDREFCLK# R1022 1 2 0_0402_5%
5 CPU_BSEL2 7 CLK_MCH_DREFCLK# MCH_SSCDREFCLK# 7
SSCDREFCLK R1023 1 2 0_0402_5% GMCH_27M (UMA)
MCH_SSCDREFCLK 7

+3VS

ITP_EN * 01 = SRC8/SRC8#
= ITP/ITP#

27_SEL * 01 = Enable DOT96 & SRC1(UMA)

= Enable SRC0 & 27MHz(DIS) EXPCARD_REQ#16 1 2
R90 10K_0402_5%
0 = Overclocking of CPU and SRC Allowed MEDIA_REQ#32 1 2
PCI2_TME R97 10K_0402_5%
CLKSATAREQ#
*1 = Overclocking of CPU and SRC NOT allowed
GLAN_REQ#9
R88
1

1
2
10K_0402_5%
2
+3VS_CK505 R87 10K_0402_5%
WLAN_REQ#4 1 2
R85 10K_0402_5%
2

CLKREQ#_7 1 2
R1031 R60 10K_0402_5%
A A
10K_0402_5%
1

ITP_EN 27_SEL PCI2_TME

1
1

R1033
R1032
10K_0402_5%
10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

Clock Generator CK505

2
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 15 of 43
5 4 2 1
 A B C D E

D11 D18 D20

DAN217_SC59-3DAN217_SC59-3DAN217_SC59-3
CRT +CRT_VCC +CRT_VCC +3VS +3VS +3VS

1
+5VS 4.7K

2
+CRT_VCC
W=40mils

2K_0402_5%

2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
For NVidia R7 R6 R77 R103
F1@ D14 W=40mils
+5VS 1 2 2 1

1
1.1A_6VDC_FUSE RB411DT146 SOT23
@ @ @ R1496 1 1

2
0.1U_0402_10V4Z

G
2 1

C44
C43 Q3
0_1206_5%~D 0.1U_0402_10V4Z VGA_DDC_DATA_C 1 3
2 2 3VDDCDA 9
SSM3K7002FU_SC70-3

2
@

G
1 1

26 MSEN# MSEN# VGA_DDC_CLK_C Q5 1 3 3VDDCCL 9

SSM3K7002FU_SC70-3

S
JCRT1
CRT_R 1 2 CRT_R_L 6
9 CRT_R
L8 11
BK1608LL121-T 0603 1 16
CRT_G 1 2 CRT_G_L 7 17
9 CRT_G
L10 12
BK1608LL121-T 0603 2
CRT_B 1 2 CRT_B_L 8
9 CRT_B
L14 13

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
150_0402_1%

150_0402_1%
1 1 1 BK1608LL121-T 0603 3

1
150_0402_1%

@ @ @ 1 1 1 DDC_MD2 9
1
R65

R63
C45 C46 C47 For EMI 14
R64

C48 C49 C50 4

2 2 2
10
2 2 2
15
2

2 1 5
2

100P_0402_50V8J
4.7P_0402_50V8C 4.7P_0402_50V8C 4.7P_0402_50V8C C51
SUYIN_070549FR015S208CR
+CRT_VCC HSYN C_L
1 2 CONN@
L11 0_0603_5% 2
1 2 2 1 1 VGA_DDC_DATA_C
C52 0.1U_0402_10V4Z R62 10K_0402_5% 1 2 V SYNC_L C53
L13 0_0603_5% 1
5
1

100P_0402_50V8J

100P_0402_50V8J
2
1 1
P
OE#

9 CRT_HSYNC 2 1 CRT_HSYNC_B 2 A Y 4 D_CRT_HSYNC C54 VGA_DDC_CLK_C

R631 0_0402_5% C55 C144 @ 2
G

15P_0402_50V8J

15P_0402_50V8J
U62 1
74AHCT1G125GW_SOT353-5 2 2
3

100P_0402_50V8J
+CRT_VCC C140
2 2
@ 2
1 2
C115 0.1U_0402_10V4Z
5
1
P
OE#

9 CRT_VSYNC 2 1 CRT_VSYNC_B 2 A Y 4 D_CRT_VSYNC

R632 0_0402_5%
G

U63
74AHCT1G125GW_SOT353-5
3

Close to VGA
+3VS

LCD

1
R21
+LCDVDD +5VALW D26 4.7K_0402_5%
W=60mils CH751H-40_SC76

2
+3VS BKOFF# DISPOFF#
26 BKOFF# 1 2
2

2
100_0603_1%

47K_0402_5%

D25
R49

R98

@ CH751H-40_SC76
9,26 GMCH_ENBKL GMCH_ENBKL 1 2
1 1

D S
SI2301BDS-T1-E3 1P SOT23 R652
3 G 3
Q7 2 2 1 2 Q6 100K_0402_5%
SSM3K7002FU_SC70-3 G R54 1K_0402_5% W=60mils @
S
3

Q9 1 +LCDVDD
D 7.3
1

SSM3K7002FU_SC70-3 C180 +LCDVDD

1

D9 D
2
9 GMCH_LVDDEN 2 1 2 1 1
G C188 C41 JLVDS1
100K_0402_5%

CH751H-40PT_SOD323-2 S 0.047U_0402_16V7K +LCDVDD 1 2 +LCDVDD

3

4.7U_0805_10V4Z 0.1U_0402_10V4Z 1 2
LCD_CBL_DET#
+3VS 3 3 4 4 LCD_CBL_DET# 26
2 2
R92

GMCH_EDID_CLK_LCD 5 6 LCD_TST
9 GMCH_EDID_CLK_LCD 5 6 LCD_TST 26
GMCH_LVDSA0- 7 8 GMCH_EDID_DAT_LCD
9 GMCH_LVDSA0- 7 8 GMCH_EDID_DAT_LCD 9
26 LCD_VCC_TEST_EN 2 R662 1 9 9 10 GMCH_LVDSA0+
10
0_0402_5% GMCH_LVDSA1+ GMCH_LVDSA1- GMCH_LVDSA0+ 9
9 GMCH_LVDSA1+ 11 11 12 12
GMCH_LVDSA2- 13 14 GMCH_LVDSA1- 9
9 GMCH_LVDSA2- 13 14
15 16 GMCH_LVDSA2+
EC_SMB_CK2_R GMCH_LVDSAC+ 15 16
GMCH_LVDSAC- GMCH_LVDSA2+ 9
4,26 EC_SMB_CK2 1 2 9 GMCH_LVDSAC+ 17 17 18 18
@ R1502 0_0402_5% GMCH_LVDSB0- 19 20 GMCH_LVDSAC- 9
9 GMCH_LVDSB0- 19 20
4,26 EC_SMB_DA2 1 2 EC_SMB_DA2_R 21 22 GMCH_LVDSB0+ GMCH_LVDSB0+ 9
@ R1503 0_0402_5% GMCH_LVDSB1+ 21 22
GMCH_LVDSB1-
9 GMCH_LVDSB1+ 23 23 24 24 GMCH_LVDSB1- 9
9 GMCH_LVDSB2- GMCH_LVDSB2- 25 26
25 26
GMCH_LVDSB2+
27 27 28 28 GMCH_LVDSB2+ 9
9 GMCH_LVDSBC+ GMCH_LVDSBC+ 29 30 GMCH_LVDSBC-
EC_SMB_CK2_R 29 30 GMCH_LVDSBC- 9
31 31 32 32
+B+ 33 34 EC_SMB_DA2_R
INVT_PWM 33 34
+B+
26 INVT_PWM 35 35 36 36 +B+
DAC_BRIG 37 38 DISPOFF#
D59 26 DAC_BRIG 37 38
39 39 40 40
3 DISPOFF# 41 42 2 2
INVT_PWM GND GND C32 C34
1
2 INVT_PWM DAC_BRIG ACES_88242-4001

0.1U_0603_50V4Z
0.1U_0603_50V4Z
+3VS 1 1
4 PJSOT24C_SOT23-3 4
@
100P_0402_25V8K C3

100P_0402_25V8K C4

C6
100P_0402_25V8K

2
C38
0.1U_0402_16V4Z
1
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

ESD EMI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT CONN/LCD CONN
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 16 of 43
A B D E
 5 4 3 2 1

+3VS

R1035 1 2 8.2K_0402_5% PCI_DEVSEL#

R1036 1 2 8.2K_0402_5% PCI_STOP#

R1037 1 2 8.2K_0402_5% PCI_TRDY#

R1038 1 2 8.2K_0402_5% PCI_FRAME# U56B

D11 F1 PCI_REQ0#
R1039 1 AD0 REQ0#
2 8.2K_0402_5% PCI_PLOCK# C8 AD1 PCI GNT0# G4 PCI_GNT0#
D PCI_REQ1# D
D9 AD2 REQ1#/GPIO50 B6
R1040 1 2 8.2K_0402_5% PCI _IRDY# E12 A7
AD3 GNT1#/GPIO51 PCI_REQ2#
E9 AD4 REQ2#/GPIO52 F13
R1041 1 2 8.2K_0402_5% PCI_SERR# C9 F12
AD5 GNT2#/GPIO53 PCI_REQ3#
E10 AD6 REQ3#/GPIO54 E6
R1042 1 2 8.2K_0402_5% PCI_PERR# B7 F6 PCI_GNT3#
AD7 GNT3#/GPIO55
C7 AD8
C5 AD9 C/BE0# D8
G11 AD10 C/BE1# B4
F8 AD11 C/BE2# D6
F11 AD12 C/BE3# A5
E7 AD13
A3 D3 PCI _IRDY#
+3VS AD14 IRDY#
D2 AD15 PAR E3
F10 R1 PCI_PCIRST#
AD16 PCIRST# PCI_DEVSEL#
D5 AD17 DEVSEL# C6
R1043 1 2 8.2K_0402_5% PCI_PIRQA# D10 E4 PCI_PERR#
AD18 PERR# PCI_PLOCK#
B3 AD19 PLOCK# C2
R1044 1 2 8.2K_0402_5% PCI_PIRQB# F7 J4 PCI_SERR#
AD20 SERR# PCI_STOP#
C3 AD21 STOP# A4
R1045 1 2 8.2K_0402_5% PCI_PIRQC# F3 F5 PCI_TRDY#
AD22 TRDY# PCI_FRAME#
F4 AD23 FRAME# D7
R1046 1 2 8.2K_0402_5% PCI_PIRQD# C1 AD24 PCI_PLTRST#
G7 AD25 PLTRST# C14
R1047 1 2 8.2K_0402_5% PCI_PIRQE# H7 D4 PCI_CLK
AD26 PCICLK PCI_CLK 15
D1 R2 EC_PME#
AD27 PME# EC_PME# 26
R1048 1 2 8.2K_0402_5% PCI_PIRQF# G5 AD28
H6 AD29
R1049 1 2 8.2K_0402_5% PCI_PIRQG# G1 AD30
H3 AD31
R1050 2 1 8.2K_0402_5% PCI_PIRQH#

C PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# C
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
E1 PIRQB# PIRQF#/GPIO3 K6
R1051 1 2 8.2K_0402_5% PCI_REQ0# PCI_PIRQC# J6 F2 PCI_PIRQG#
PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
C4 PIRQD# PIRQH#/GPIO5 G2
R1052 1 2 8.2K_0402_5% PCI_REQ1#
ICH9M REV 1.0
R1053 1 2 8.2K_0402_5% PCI_REQ2#
C2
R1054 1 2 8.2K_0402_5% PCI_REQ3#
2 1 1 2 PCI_CLK +3VALW
@ R10 @ 33_0402_5%
22P_0402_50V8J
1
@ C1810
0.1U_0402_10V4Z
2

5
@ U59
PCI_PCIRST# 2

P
B PCI_RST#
Y 4 PCI_RST# 21,23,25,27
1 A

G
MC74VHC1G08DFT2G SC70 5P

3
R1067
0_0402_5%
2 1

A16 swap override Strap Boot BIOS Strap

B B

Low= A16 swap override Enble

PCI_GNT0# SPI_CS#1 Boot BIOS Location
PCI_GNT3# High= Default *
+3VALW
0 1 SPI
@R1431
PCI_GNT3# 1 2
1K_0402_5%
1 0 PCI 1
@ C1808
0.1U_0402_10V4Z
2
1 1 LPC *

5
@ U58
PCI_PLTRST# 2

P
B PLT_RST#
Y 4 PLT_RST# 7,26,29
+3VALW 1 A

G
@ R1058 MC74VHC1G08DFT2G SC70 5P

3
SPI_CS1#_R 1 2
19 SPI_CS1#_R
1K_0402_5% R1061
@ R1060 0_0402_5%
PCI_GNT0# 1 2 2 1
1K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(1/4)-PCI/INT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4592P 0.2
PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 17 of 43
5 4 3 2 1
 5 4 3 2 1

+RTCVCC
+3VS

1 2 SM_INTRUDER# R1063
R1062 1M_0402_5% GATEA20 1 2
1 2 LAN100_SLP 8.2K_0402_5%
R1064 332K_0402_1%~D
1 2 ICH_INTVRMEN R1066
R1065 332K_0402_1%~D KB_RST# 1 2
10K_0402_5%

D D

+RTCVCC

U56A LPC_AD[0..3] 23,26,27

1 2
R1068 20K_0402_5% ICH_RTCX1 C23 K5 LPC_AD0
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1
1 2 C24 RTCX2 FWH1/LAD1 K4
R1109 20K_0402_5% L6 LPC_AD2
ICH_RTCRST# FWH2/LAD2 LPC_AD3
A25 RTCRST# FWH3/LAD3 K2

RTC
LPC
SRTCRST# F20
SM_INTRUDER# SRTCRST# LPC_FRAME#
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# 23,26,27
1 1 +VCCP

2
C1220 C1210 ICH_INTVRMEN B22 J3 LPC_DRQ0# T121 PAD
JOPEN2 JOPEN1 LAN100_SLP INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1 T122 PAD
1U_0603_10V4Z @ 1U_0603_10V4Z @

2
2 2 GATEA20
E25 GLAN_CLK A20GATE N7 GATEA20 26
AJ27 H_A20M# R1070
A20M# H_A20M# 4
C13 56_0402_5%
LAN_RSTSYNC H_DPRSTP#
DPRSTP# AJ25 H_DPRSTP# 5,7,39

LAN / GLAN
H_DPSLP#
Close JOPEN1 and JOPEN2 near JMINI1 F14 AE23 H_DPSLP# 5

1
LAN_RXD0 DPSLP#
G13 LAN_RXD1
D14 AJ26 R_H_FERR# R1072 1 2 H_FERR#
LAN_RXD2 FERR# H_FERR# 4
56_0402_5%
D13 AD22 H_PW RGOOD
LAN_TXD0 CPUPWRGD H_PWRGOOD 5
ICH_RTCX1 D12 LAN_TXD1 H_IGNNE#
E13 LAN_TXD2 IGNNE# AF25 H_IGNNE# 4

CPU
R1069 R1419
1 2 2 1 ICH_RTCX2 +1.5VS B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# 4 +VCCP
AG25 H_INTR
C INTR H_INTR 4 C
10M_0402_5% 0_0402_5% B28 L3 KB_RST#
GLAN_COMPI RCIN# KB_RST# 26
1 2 R1073 24.9_0402_1% 1 2 GLAN_COMP B27 GLAN_COMPO

1
C1211 AF23 H_NMI
NMI H_NMI 4
C1212 R1074 33_0402_5% 1 2 HDA_BITCLK AF6 AF24 H_SMI# R1075
24 ACZ_BITCLK HDA_BIT_CLK SMI# H_SMI# 4
12P_0402_50V8J 10P_0402_50V8J R1076 33_0402_5% 1 2 HDA_SYNC AH4 56_0402_5%
2 1 24 ACZ_SYNC HDA_SYNC
AH27 H_STPCLK#
STPCLK# H_STPCLK# 4
R1077 33_0402_5% 1 2 HDARST# AE7
24 ACZ_RST#

2
HDA_RST# THRMTRIP_ICH# R1078
THRMTRIP# AG26 1 2 54.9_0402_1% H_THERMTRIP# 4,7
HDA_SDIN0 AF4
24 ADC_ACZ_SDIN0 HDA_SDIN0
AG4 HDA_SDIN1 TP12 AG27

IHDA
AH3 HDA_SDIN2
AE5 HDA_SDIN3
SATA4RXN AH11
1

R1079 33_0402_5% 1 2 HDA_SDOUT AG5 AJ11

24 ACZ_SDOUT HDA_SDOUT SATA4RXP
AG12
IN

OUT

SATA4TXN
PAD T123 AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12
Y8 1 2 AE8
+3VS PAD T124 HDA_DOCK_RST#/GPIO34
32.768KHZ QTFM28-32768K125P10L R1080 10K_0402_5% AH9
SATA_LED# SATA5RXN
NC

NC

27 SATA_LED# AG8 SATALED# SATA5RXP AJ9

SATA5TXN AE10
22 PSATA_IRX_DTX_N0_C AJ16 AF10
2

SATA0RXN SATA5TXP
AH16

SATA
22 PSATA_IRX_DTX_P0_C SATA0RXP
PSATA_ITX_DRX_N0 CLK_PCIE_SATA#
HDD 22 PSATA_ITX_DRX_N0
PSATA_ITX_DRX_P0
AF17
AG17
SATA0TXN SATA_CLKN AH18
AJ18 CLK_PCIE_SATA
CLK_PCIE_SATA# 15
22 PSATA_ITX_DRX_P0 SATA0TXP SATA_CLKP CLK_PCIE_SATA 15

22 ODD_IRX_DTX_N0_C AH13 SATA1RXN SATARBIAS# AJ7

AJ13 AH7 R1081 1 2
22 ODD_IRX_DTX_P0_C SATA1RXP SATARBIAS
ODD_ITX_DRX_N0
ODD 22 ODD_ITX_DRX_N0
ODD_ITX_DRX_P0
AG14
AF14
SATA1TXN 24.9_0402_1%
22 ODD_ITX_DRX_P0 SATA1TXP
ICH9M REV 1.0
Within 500 mils
B B

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

@ R1082
1 2 ACZ_SDOUT
1K_0402_5%

@ R1083
1 2 ICH_RSVD
ICH_RSVD 19
1K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(2/4)_LAN,HD,IDE,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 18 of 43
5 4 3 2 1
 5 4 3 2 1

+3VS 1 2 SERIRQ Place closely pin AF3 Place closely pin H1

R1084 10K_0402_5% +3VALW R1085 1 2 2.2K_0402_5%
1 2 PCI_CLKRUN# R1087 1 2 2.2K_0402_5%
R1086 8.2K_0402_5% U56C CLK_48M_ICH CLK_14M_ICH
1 2 EC_THERM# ICH_SMBCLK G16 AH23 GPIO21 1 2 +3VS
25 ICH_SMBCLK SMBCLK SATA0GP/GPIO21
@ R1088 8.2K_0402_5% ICH_SMBDATA A13 AF19 GPIO19 R1089 8.2K_0402_5%
25 ICH_SMBDATA SMBDATA SATA1GP/GPIO19

1
1 2 OCP# CL_RST#1 E17 AE21 GPIO36 @ @
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

SATA
GPIO
SMB
R1090 10K_0402_5% ME_EC_CLK1 C17 AD20 GPIO37 R1091 R1092
PM_BMBUSY# ME_EC_DATA1 SMLINK0 SATA5GP/GPIO37
1 2 B18 SMLINK1
@ R1094 8.2K_0402_5% H1 CLK_14M_ICH 10_0402_5% 10_0402_5%
CLK14 CLK_14M_ICH 15
1 2 EC_SCI# I CH_RI# F19 AF3 CLK_48M_ICH
CLK_48M_ICH 15

2
RI# CLK48

Clocks
@ R1095 8.2K_0402_5%
ICH8 don't have PAD T125 SUS_STAT# R4 P1 ICH_SUSCLK T126 PAD 1 @ 1 @
XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK C1217 C1218
4 XDP_DBRESET# G19 SYS_RESET#
1 2 LAN_CABDT C16 SLP_S3#
D SLP_S3# SLP_S3# 26 D
R313 10K_0402_5% PM_BMBUSY# M6 E16 SLP_S4# 4.7P_0402_50V8C 4.7P_0402_50V8C
7 PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S4# 26 2 2
G17 SLP_S5#
SLP_S5# SLP_S5# 26
26 EC_LID_OUT# EC_LID_OUT# A17 SMBALERT#/GPIO11 R695 100_0402_5%
S4_STATE#/GPIO26 C10 T127 PAD
H_STP_PCI# A14 1 2 M_PWROK
15 H_STP_PCI# STP_PCI#

SYS GPIO
R_STP_CPU# E19 G20 ICH_PWROK
15 H_STP_CPU# STP_CPU# PWROK ICH_PWROK 7,26
1 2
PCI_CLKRUN# L4 M2 1 2 R1097 10K_0402_5%
26,27 PCI_CLKRUN# CLKRUN# DPRSLPVR/GPIO16 DPRSLPVR 7,39
0_0402_5% R1098

Power MGT
21,23,25,26 ICH_PCIE_WAKE# ICH_PCIE_WAKE# @ 2 R1505 1 ICH_PCIE_WAKE#_R E20 B13 ICH_LOW_BAT#
0_0402_5% SERIRQ WAKE# BATLOW#
26,27 SERIRQ M5 SERIRQ
EC_THERM# AJ23 R3 PWRBTN_OUT#
26 EC_THERM# THRM# PWRBTN# PBTN_OUT# 26
+3VS 1 2SB_SPKR
R1096 @ 10K_0402_5% 1 2 VRMPWRGD D21 D20 1 2
7,26,39 VGATE VRMPWRGD LAN_RST#
low-->default R1099 0_0402_5% R1100 0_0402_5%
1 2 PAD T128 A20 TP11 RSMRST# D22 R_EC_RSMRST# R1104
1 2 10K_0402_5%
High -->No boot R1102 100K_0402_5%
@ 4 OCP# OCP# AG19 R5 CK_PWRGD_R R1105 1 2 0_0402_5%
GPIO1 CK_PWRGD CK_PWRGD 15
LAN_LOPWEN AH21
21 LAN_LOPWEN GPIO6
AG21 R6 M_PWROK
GPIO7 CLPWROK M_PWROK 7
26 EC_SMI# EC_SMI# A21
EC_SCI# GPIO8 +3VS
26 EC_SCI# C12 GPIO12 SLP_M# B16 T129 PAD
+3VS 1 2 GPIO49 PAD T130 C21
R1101 @ 10K_0402_5% GPIO13 CL_CLK0 R1106
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 7
K1 B19 0.1U_0402_16V4Z 1 2
GPIO18 CL_CLK1 3.24K_0402_1%
PAD T149 AF8 GPIO20

1
checklist pull hi AJ22 F22 CL_DATA0 1
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 7

Controller Link
PAD T131 A9 C19 C1219 R1107

GPIO
GPIO27 CL_DATA1 453_0402_1%
PAD T132 D19 GPIO28
CLKSATAREQ# L1 C25 CL_VREF0_ICH
15 CLKSATAREQ# SATACLKREQ#/GPIO35 CL_VREF0 2 NA lead free
AE19 A19

2
SLOAD/GPIO38 CL_VREF1
AG22 SDATAOUT0/GPIO39
C CL_RST# C
AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST# 7
GPIO49 AH24 D18
CL_RST#1 GPIO49 CL_RST1#
+3VALW 1 2 A8 GPIO57/CLGPIO5
R1108 10K_0402_5% A16
ICH_LOW_BAT# SB_SPKR MEM_LED/GPIO24
1 2 24 SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18
R1110 8.2K_0402_5% MCH_ICH_SYNC# AJ24 C11
7 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT ACIN 26,32,33
1 2 ICH_PCIE_WAKE#_R ICH_RSVD B21 C20 LAN_CABDT
18 ICH_RSVD TP3 WOL_EN/GPIO9 LAN_CABDT 21

MISC
R1111 10K_0402_5% PAD T133 AH20
I CH_RI# TP8
1 2 PAD T134 AJ20 TP9
R1113 10K_0402_5% PAD T135 AJ21
XDP_DBRESET# TP10
1 2
R1114 10K_0402_5% ICH9M REV 1.0
1 2 ME_EC_CLK1 RSMRST circuit
R1115 10K_0402_5% U56D
1 2 ME_EC_DATA1 N29 V27 DMI_MTX_IRX_N0 DMI_MTX_IRX_N0 7 R1103 @ R656
PERN1 DMI0RXN

Direct Media Interface

R1116 10K_0402_5% N28 V26 DMI_MTX_IRX_P0 DMI_MTX_IRX_P0 7 0_0402_5% 0_0402_5%
EC_LID_OUT# PERP1 DMI0RXP DMI_MRX_ITX_N0
1 2 P27 PETN1 DMI0TXN U29 DMI_MRX_ITX_N0 7 1 2 1 2 POK 34
R1117 10K_0402_5% P26 U28 DMI_MRX_ITX_P0 DMI_MRX_ITX_P0 7
EC_SMI# PETP1 DMI0TXP
1 2
R1119 8.2K_0402_5% GLAN_RXN L29 Y27 DMI_MTX_IRX_N1 DMI_MTX_IRX_N1 7 R_EC_RSMRST#
21 GLAN_RXN PERN2 DMI1RXN 26 EC_RSMRST#
GLAN_RXP L28 Y26 DMI_MTX_IRX_P1 DMI_MTX_IRX_P1 7
21 GLAN_RXP PERP2 DMI1RXP
GLAN 0.1U_0402_16V7K~N2 1 C1221GLAN_TXN_C M27 W29 DMI_MRX_ITX_N1 DMI_MRX_ITX_N1 7
21 GLAN_TXN PETN2 DMI1TXN
0.1U_0402_16V7K~N2 1 C1222GLAN_TXP_C M26 W28 DMI_MRX_ITX_P1 DMI_MRX_ITX_P1 7
+3VALW 21 GLAN_TXP PETP2 DMI1TXP
PCIE_RXN3 J29 AB27 DMI_MTX_IRX_N2 DMI_MTX_IRX_N2 7
23 PCIE_RXN3 PERN3 DMI2RXN
EC_SWI# PCIE_RXP3 DMI_MTX_IRX_P2

PCI-Express
1 2 23 PCIE_RXP3 J28 PERP3 DMI2RXP AB26 DMI_MTX_IRX_P2 7
R1483 10K_0402_5% WLAN 23 PCIE_TXN3 0.1U_0402_16V7K~N2 1 C1223PCIE_C_TXN3 K27 AA29 DMI_MRX_ITX_N2 DMI_MRX_ITX_N2 7
USB_OC#1 0.1U_0402_16V7K~N2 PETN3 DMI2TXN
1 2 23 PCIE_TXP3 1 C1224PCIE_C_TXP3 K26 PETP3 DMI2TXP AA28 DMI_MRX_ITX_P2 DMI_MRX_ITX_P2 7
R1484 10K_0402_5%
1 2 USB_OC#2_8 PCIE_RXN4 G29 AD27 DMI_MTX_IRX_N3 DMI_MTX_IRX_N3 7
25 PCIE_RXN4 PERN4 DMI3RXN
R1485 10K_0402_5% Express Card PCIE_RXP4 G28 AD26 DMI_MTX_IRX_P3 DMI_MTX_IRX_P3 7
25 PCIE_RXP4 PERP4 DMI3RXP
1 2 USB_OC#4 25 PCIE_TXN4 0.1U_0402_16V7K~N2 1 C1225PCIE_C_TXN4 H27 PETN4 DMI3TXN AC29 DMI_MRX_ITX_N3 DMI_MRX_ITX_N3 7
B R1486 10K_0402_5% 0.1U_0402_16V7K~N2 1 C1226PCIE_C_TXP4 H26 AC28 DMI_MRX_ITX_P3 B
25 PCIE_TXP4 PETP4 DMI3TXP DMI_MRX_ITX_P3 7
1 2 USB_OC#7
R1487 10K_0402_5% PCIE_RXN5 E29 T26 CLK_PCIE_ICH#
29 PCIE_RXN5 PERN5 DMI_CLKN CLK_PCIE_ICH# 15
1 2 USB_OC#3 PCIE_RXP5 E28 T25 CLK_PCIE_ICH
29 PCIE_RXP5 PERP5 DMI_CLKP CLK_PCIE_ICH 15
R1488 10K_0402_5% CardBus 29 PCIE_TXN5
0.1U_0402_16V7K~N2 1 C1228PCIE_C_TXN5 F27 PETN5
1 2 USB_OC#9
29 PCIE_TXP5
0.1U_0402_16V7K~N2 1 C1227PCIE_C_TXP5 F26 PETP5 DMI_ZCOMP AF29 R1120 24.9_0402_1% Within 500 mils
R1489 10K_0402_5% AF28 DMI_IRCOMP 1 2 +1.5VS
USB_OC#0 DMI_IRCOMP
1 2 C29 PERN6/GLAN_RXN
R1490 10K_0402_5% C28 AC5 USB20_N0
PERP6/GLAN_RXP USBP0N USB20_N0 28
1 2 USB_OC#5 D27 AC4 USB20_P0 JUSBP1
PETN6/GLAN_TXN USBP0P USB20_P0 28
R1492 10K_0402_5% D26 AD3 USB20_N1
PETP6/GLAN_TXP USBP1N USB20_N1 28
1 2 USB_OC#10 AD2 USB20_P1 Camera
USBP1P USB20_P1 28
R1493 10K_0402_5% D23 AC1 USB20_N2
SPI_CLK USBP2N USB20_N2 28
1 2 USB_OC#11 D24 AC2 USB20_P2 JUSBP3
SPI_CS0# USBP2P USB20_P2 28
R1494 10K_0402_5% 17 SPI_CS1#_R SPI_CS1#_R F23 AA5 USB20_N3
SPI_CS1#/GPIO58/CLGPIO6 USBP3N USB20_N3 28
AA4 USB20_P3 Felica
USBP3P USB20_P3 28
D25 AB2 USB20_N4
SPI_MOSI USBP4N USB20_N4 28
SPI

E23 AB3 USB20_P4 BlueTooth

SPI_MISO USBP4P USB20_P4 28
AA1 USB20_N5
USBP5N USB20_N5 28
USB_OC#0 N4 AA2 USB20_P5 FingerPrinter
28 USB_OC#0 OC0#/GPIO59 USBP5P USB20_P5 28
USB_OC#1 N5 W5 USB20_N6
OC1#/GPIO40 USBP6N USB20_N6 23
USB_OC#2_8 USB20_P6
28 USB_OC#2_8
USB_OC#3
N6
P6
OC2#/GPIO41 USBP6P USB W4
Y3 USB20_N7
USB20_P6 23 Mini Card 2
OC3#/GPIO42 USBP7N USB20_N7 25
USB_OC#4 M1 Y2 USB20_P7 Express Card
OC4#/GPIO43 USBP7P USB20_P7 25
USB_OC#5 N2 W1 USB20_N8
+3VS OC5#/GPIO29 USBP8N USB20_N8 28
EC_SWI# M4 W2 USB20_P8 JUSBP3
26 EC_SWI# OC6#/GPIO30 USBP8P USB20_P8 28
USB_OC#7 M3 V2 USB20_N9
OC7#/GPIO31 USBP9N USB20_N9 28
USB_OC#2_8 N3 V3 USB20_P9 JUSBP4
OC8#/GPIO44 USBP9P USB20_P9 28
USB_OC#9 N1 U5
28 USB_OC#9 OC9#/GPIO45 USBP10N
1

2.2K_0402_5% USB_OC#10 P5 U4
2.2K_0402_5% R1123 R1124 USB_OC#11 OC10#/GPIO46 USBP10P
P3 OC11#/GPIO47 USBP11N U1
USBP11P U2
A Q106 USBRBIAS A
AG2 USBRBIAS
SSM3K7002FU_SC70-3 AG1
2

USBRBIAS#
1
S

3 1 ICH_SMBDATA Within 500 mils

13,14,15,23 ICH_SM_DA
ICH9M REV 1.0
R1125
22.6_0402_1%
G
2

13,14,15,23 ICH_SM_CLK 3 1ICH_SMBCLK

2

Q107
Security Classification Compal Secret Data Compal Electronics, Inc.
2006/02/13 2006/03/10 Title
G

+3VS Issued Date Deciphered Date

2

SSM3K7002FU_SC70-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(3/4)_DMI,USB,GPIO,PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 19 of 43
5 4 3 2 1
 5 4 3 2 1

+RTCVCC +VCCP U56E

20 mils G3: 6uA U56F 1634mA AA26 H5
VSS[1] VSS[107]
A23 VCCRTC VCC1_05[1] A15 AA27 VSS[2] VSS[108] J23

1U_0603_10V4Z~D
0.1U_0402_16V4Z

0.1U_0402_16V4Z
VCC1_05[2] B15 AA3 VSS[3] VSS[109] J26
1 1 1 +ICH_V5REF_RUN 2mA A6 C15 0.1U_0402_16V4Z 0.1U_0402_16V4Z AA6 J27
V5REF VCC1_05[3] VSS[4] VSS[110]

C1229

C1230
VCC1_05[4] D15 1 1 AB1 VSS[5] VSS[111] AC22

C1231
+ICH_V5REF_SUS 2mA AE1 E15 C1232 C1233 AA23 K28
V5REF_SUS VCC1_05[5] VSS[6] VSS[112]
VCC1_05[6] F15 AB28 VSS[7] VSS[113] K29
2 2 2
AA24 VCC1_5_B[1] VCC1_05[7] L11 AB29 VSS[8] VSS[114] L13
2 2
AA25 VCC1_5_B[2] VCC1_05[8] L12 AB4 VSS[9] VSS[115] L15
AB24 VCC1_5_B[3] VCC1_05[9] L14 AB5 VSS[10] VSS[116] L2
40 mils AB25 L16 L97 AC17 L26
L96 VCC1_5_B[4] VCC1_05[10] BLM18PG181SN1_0603~D VSS[11] VSS[117]
AC24 VCC1_5_B[5] VCC1_05[11] L17 AC26 VSS[12] VSS[118] L27
+1.5VS 1 2 +VCC1_5_B 22U_0805_6.3V6M~D 646mA AC25 L18 +VCCDMIPLL 1 2 +1.5VS AC27 L5
BLM21PG600SN1D_0805~D VCC1_5_B[6] VCC1_05[12] VSS[13] VSS[119]
1 AD24 VCC1_5_B[7] VCC1_05[13] M11 AC3 VSS[14] VSS[120] L7
D D
1 1 1 AD25 VCC1_5_B[8] VCC1_05[14] M18 1 1 AD1 VSS[15] VSS[121] M12

220U_D2_4VM
+ C1235 C1236 C1237 AE25 P11 C1238 C1239 AD10 M13
VCC1_5_B[9] VCC1_05[15] VSS[16] VSS[122]

C1234
AE26 P18 10U_0805_10V4Z AD12 M14
VCC1_5_B[10] VCC1_05[16] 0.01U_0402_16V7K VSS[17] VSS[123]
AE27 VCC1_5_B[11] VCC1_05[17] T11 AD13 VSS[18] VSS[124] M15
2 2 2 2 2 2
AE28 VCC1_5_B[12] VCC1_05[18] T18 AD14 VSS[19] VSS[125] M16
AE29 VCC1_5_B[13] VCC1_05[19] U11 AD17 VSS[20] VSS[126] M17

CORE
2.2U_0603_6.3V4Z F25 U18 AD18 M23
+5VS +3VS 22U_0805_6.3V6M~D VCC1_5_B[14] VCC1_05[20] VSS[21] VSS[127]
G25 VCC1_5_B[15] VCC1_05[21] V11 AD21 VSS[22] VSS[128] M28
H24 V12 5ohm@100MHz AD28 M29
VCC1_5_B[16] VCC1_05[22] +VCC_DMI VSS[23] VSS[129]
H25 VCC1_5_B[17] VCC1_05[23] V14 1 2 +VCCP AD29 VSS[24] VSS[130] N11
1

22U_0805_6.3VAM
J24 V16 L98 AD4 N12
R1127 D45 VCC1_5_B[18] VCC1_05[24] BLM18PG181SN1_0603~D VSS[25] VSS[131]
J25 VCC1_5_B[19] VCC1_05[25] V17 1 AD5 VSS[26] VSS[132] N13
100_0402_5%~D K24 V18 C1240 AD6 N14
CH751H-40PT_SOD323-2 VCC1_5_B[20] VCC1_05[26] VSS[27] VSS[133]
K25 VCC1_5_B[21] AD7 VSS[28] VSS[134] N15
L23 R29 AD9 N16
2

VCC1_5_B[22] VCCDMIPLL 2 VSS[29] VSS[135]

L24 VCC1_5_B[23] AE12 VSS[30] VSS[136] N17
+ICH_V5REF_RUN L25 W23 23mA AE13 N18
VCC1_5_B[24] VCC_DMI[1] +VCCP VSS[31] VSS[137]
1 20 mils M24 VCC1_5_B[25] VCC_DMI[2] Y23 AE14 VSS[32] VSS[138] N26
M25 VCC1_5_B[26] AE16 VSS[33] VSS[139] N27
C1241 N23 AB23 48mA AE17 P12
1U_0603_10V6K~D VCC1_5_B[27] V_CPU_IO[1] VSS[34] VSS[140]
N24 VCC1_5_B[28] V_CPU_IO[2] AC23 AE2 VSS[35] VSS[141] P13
2

4.7U_0603_6.3V6M

0.1U_0402_10V4Z

0.1U_0402_10V4Z
N25 VCC1_5_B[29] AE20 VSS[36] VSS[142] P14
0.1U Change to 1U P24 AG29 2mA 0.1U_0402_10V4Z +3VS 1 1 1 AE24 P15
VCC1_5_B[30] VCC3_3[1] VSS[37] VSS[143]

C1242

C1243

C1244
P25 VCC1_5_B[31] AE3 VSS[38] VSS[144] P16

VCCA3GP
R24 AJ6 0.1U_0402_10V4Z 1 +3VS 1 AE4 P17
+5VALW +3VALW VCC1_5_B[32] VCC3_3[2] VSS[39] VSS[145]
R25 VCC1_5_B[33] AE6 VSS[40] VSS[146] P2
2 2 2

C1245

C1246
R26 AC10 0.1U_0402_10V4Z 1 +3VS AE9 P23
VCC1_5_B[34] VCC3_3[7] VSS[41] VSS[147]
R27 VCC1_5_B[35] AF13 VSS[42] VSS[148] P28
1

2 2

C1247
D46 T24 AD19 AF16 P29
R1128 VCC1_5_B[36] VCC3_3[3] VSS[43] VSS[149]
T27 AF20 AF18 P4

VCCP_CORE
100_0402_5%~D VCC1_5_B[37] VCC3_3[4] 2 (DMI) VSS[44] VSS[150]
T28 VCC1_5_B[38] VCC3_3[5] AG24 AF22 VSS[45] VSS[151] P7
CH751H-40PT_SOD323-2 T29 AC20 +3VS AH26 R11
C VCC1_5_B[39] VCC3_3[6] VSS[46] VSS[152] C
U24 308mA AF26 R12
2

+ICH_V5REF_SUS VCC1_5_B[40] VSS[47] VSS[153]

U25 VCC1_5_B[41] VCC3_3[8] B9 AF27 VSS[48] VSS[154] R13

0.1U_0402_10V4Z

C1248

0.1U_0402_10V4Z

C1249

0.1U_0402_10V4Z

C1250
20 mils V24 VCC1_5_B[42] VCC3_3[9] F9 1 1 1 Add 0.1uF AF5 VSS[49] VSS[155] R14
1 V25 VCC1_5_B[43] VCC3_3[10] G3 AF7 VSS[50] VSS[156] R15
U23 VCC1_5_B[44] VCC3_3[11] G6 AF9 VSS[51] VSS[157] R16
C1306 W24 J2 AG13 R17
1U_0603_10V6K~D VCC1_5_B[45] VCC3_3[12] 2 2 2 VSS[52] VSS[158]
W25 J7 AG16 R18

PCI
2 VCC1_5_B[46] VCC3_3[13] VSS[53] VSS[159]
K23 VCC1_5_B[47] VCC3_3[14] K7 AG18 VSS[54] VSS[160] R28
Y24 VCC1_5_B[48] AG20 VSS[55] VSS[161] T12
L99 Y25 AJ4 0.1U_0402_16V4Z +3VS AG23 T13
10UH_LB2012T100MR_20%_0805~D VCC1_5_B[49] VCCHDA VSS[56] VSS[162]
47mA 1 AG3 VSS[57] VSS[163] T14
+1.5VS 1 2 +VCCSATAPLL AJ19 AJ3 11mA 0.1U_0402_16V4Z +3VALW C1252 AG6 T15
VCCSATAPLL VCCSUSHDA VSS[58] VSS[164]
1 AG9 VSS[59] VSS[165] T16
1U_0603_10V4Z

10U_0805_10V4Z

AC16 AC8 11mA C1253 AH12 T17

+1.5VS VCC1_5_A[1] VCCSUS1_05[1] T140 2 VSS[60] VSS[166]
1 AD15 VCC1_5_A[2] VCCSUS1_05[2] F17 AH14 VSS[61] VSS[167] T23
T141
C1254

1 1 AD16 VCC1_5_A[3] AH17 VSS[62] VSS[168] B26

2
ARX
C1255

C1256 AE15 AD8 +VCCSUS1_5_ICH_1 AH19 U12

VCC1_5_A[4] VCCSUS1_5[1] T142 VSS[63] VSS[169]
AF15 VCC1_5_A[5] AH2 VSS[64] VSS[170] U13
2 1U_0603_10V4Z +VCCSUS1_5_ICH_2
AG15 VCC1_5_A[6] VCCSUS1_5[2] F18 AH22 VSS[65] VSS[171] U14
2 2 T143
AH15 VCC1_5_A[7] 1 AH25 VSS[66] VSS[172] U15
AJ15 C1257 AH28 U16
VCC1_5_A[8] VSS[67] VSS[173]
A18 +3VALW AH5 U17
VCCPSUS

VCCSUS3_3[1] 0.1U_0402_10V4Z VSS[68] VSS[174]

+1.5VS AC11 VCC1_5_A[9] VCCSUS3_3[2] D16 AH8 VSS[69] VSS[175] AD23
2
1 AD11 VCC1_5_A[10] VCCSUS3_3[3] D17 AJ12 VSS[70] VSS[176] U26
C1258 AE11 E22 AJ14 U27
VCC1_5_A[11] VCCSUS3_3[4] VSS[71] VSS[177]
ATX

AF11 VCC1_5_A[12] AJ17 VSS[72] VSS[178] U3

1U_0603_10V4Z AG10 AJ8 V1
2 VCC1_5_A[13] VSS[73] VSS[179]
AG11 VCC1_5_A[14] VCCSUS3_3[5] AF1 B11 VSS[74] VSS[180] V13
AH10 VCC1_5_A[15] 212mA B14 VSS[75] VSS[181] V15
AJ10 VCC1_5_A[16] VCCSUS3_3[6] T1 B17 VSS[76] VSS[182] V23
VCCSUS3_3[7] T2 B2 VSS[77] VSS[183] V28
AC9 VCC1_5_A[17] VCCSUS3_3[8] T3 B20 VSS[78] VSS[184] V29
B
T4 +3VALW B23 V4 B
VCCSUS3_3[9] VSS[79] VSS[185]

0.1U_0402_16V4Z~D

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D
1342mA AC18 VCC1_5_A[18] VCCSUS3_3[10] T5 B5 VSS[80] VSS[186] V5
AC19 VCC1_5_A[19] VCCSUS3_3[11] T6 B8 VSS[81] VSS[187] W26
+1.5VS VCCSUS3_3[12] U6 1 1 1 C26 VSS[82] VSS[188] W27
VCCPUSB

AC21 VCC1_5_A[20] VCCSUS3_3[13] U7 C27 VSS[83] VSS[189] W3

C1259

C1260

C1261
1 VCCSUS3_3[14] V6 E11 VSS[84] VSS[190] Y1
C1262 G10 V7 E14 Y28
VCC1_5_A[21] VCCSUS3_3[15] 2 2 2 VSS[85] VSS[191]
G9 VCC1_5_A[22] VCCSUS3_3[16] W6 E18 VSS[86] VSS[192] Y29
0.1U_0402_16V4Z W7 E2 Y4
2 VCCSUS3_3[17] VSS[87] VSS[193]
AC12 VCC1_5_A[23] VCCSUS3_3[18] Y6 E21 VSS[88] VSS[194] Y5
AC13 VCC1_5_A[24] VCCSUS3_3[19] Y7 E24 VSS[89] VSS[195] AG28
+1.5VS AC14 VCC1_5_A[25] VCCSUS3_3[20] T7 E5 VSS[90] VSS[196] AH6
1 11mA E8 AF2
C1263 +VCCCL1_05_ICH_1 VSS[91] VSS[197]
AJ5 VCCUSBPLL VCCCL1_05 G22 F16 VSS[92] VSS[198] B25
11mA T144
1 F28 VSS[93]
0.1U_0402_16V4Z AA7 G23 +VCCCL1_5 C1264 F29 A1
2 VCC1_5_A[26] VCCCL1_5 VSS[94] VSS_NCTF[1]
USB CORE

AB6 VCC1_5_A[27]
19/73/73mA G12 VSS[95] VSS_NCTF[2] A2
AB7 A24 +3VS 1 1 0.1U_0402_10V4Z G14 A28
VCC1_5_A[28] VCCCL3_3[1] 2 VSS[96] VSS_NCTF[3]
AC6 VCC1_5_A[29] VCCCL3_3[2] B24 G18 VSS[97] VSS_NCTF[4] A29
C1265 1U_0603_10V4Z

C1266 0.1U_0402_16V4Z~D

AC7 VCC1_5_A[30] G21 VSS[98] VSS_NCTF[5] AH1

G24 VSS[99] VSS_NCTF[6] AH29
VCC_LAN1_05_INT_ICH_1 A10 2 2
1 2 VCCLAN1_05[1] G26 VSS[100] VSS_NCTF[7] AJ1
+3VS C1267 A11 G27 AJ2
0.1U_0402_16V4Z~D VCCLAN1_05[2] VSS[101] VSS_NCTF[8]
G8 VSS[102] VSS_NCTF[9] AJ28
1 2 +VCCLAN3_3 19/78/78mA A12 H2 AJ29
VCCLAN3_3[1] VSS[103] VSS_NCTF[10]
0.1U_0402_16V4Z

1 R1129 0_0603_5% B12 H23 B1

C1268 VCCLAN3_3[2] VSS[104] VSS_NCTF[11]
23mA H28 VSS[105] VSS_NCTF[12] B29
+1.5VS 1 2 +VCCGLANPLL A27 H29
L100 80mA VCCGLANPLL VSS[106]
2
GLAN POWER
10U_0805_10V4Z

2.2U_0603_6.3V4Z

1UH_20%_0805~D D28 ICH9M REV 1.0

+1.5VS VCCGLAN1_5[1]
D29 VCCGLAN1_5[2]
1 1 1 E26 VCCGLAN1_5[3]
A C1269 C1270 C1271 A
E27 VCCGLAN1_5[4]
1mA
+3VS A26VCCGLAN3_3
2 2 2
ICH9M REV 1.0
4.7U_0603_6.3V6M~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(4/4)_POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 20 of 43
5 4 3 2 1
 5 4 3 2 1

W=60mils W=60mils
+3VALW +LAN_IO
Q128 +LAN_VDD
1.5A

D
6 1 2 +LAN_VDD12

S
1 5 4 +LAN_IO

0.1U_0402_10V7K~N C1463

0.1U_0402_10V7K~N C1464

0.1U_0402_10V7K~N C1465

0.1U_0402_10V7K~N C1466

0.1U_0402_10V7K~N C1467

0.1U_0402_10V7K~N C1468
C1455 2 1 1 1 1 1 R1238 1 1 1 1 1 1
1U_0603_10V6K 1 C1456 C1457 C1458 C1459 C1460 0_0603_5%
SI3456BDV-T1-E3 1N TSOP6 @

G
2

3
2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N
22U_1206_6.3V6M

22U_1206_6.3V6M
+B+_BIAS

2
D D
R1239
470K_0402_5%

1
EN_WOL
These caps close to U64: Pin 4,10,13, 30, 36,39
1

2
D
Q58 R1240
These caps close to U64: Pin 44, 45
26 EN_WOL# 2
G SSM3K7002FU_SC70-3 1.5M_0402_5%
S @
3

1
+LAN_IO

1 1
C1474 C1475

0.1U_0402_10V7K~N
22U_1206_6.3V6M
2 2

These caps close to U64: Pin 4

U64 +LAN_IO +LAN_VDD

2 1 GLAN_RXP_C 20 33 LAN_LED3 R1241 3.6K_0402_5%

19 GLAN_RXP HSOP LED3/EEDO
C1473 0.1U_0402_16V7K~N 34 LAN_LED2 1 2
LED2/EEDI/AUX

0.1U_0402_10V7K

0.01U_0402_16V7K
2 1 GLAN_RXN_C 21 35 LAN_LED1 1 2 These caps close to U64: Pin 44,45
19 GLAN_RXN HSON LED1/EESK
C1476 0.1U_0402_16V7K~N 32
EECS

C1743

C1744
GLAN_TXP 15 ( Should be place within 200 mils )
19 GLAN_TXP HSIP
38 LAN_LED0
C GLAN_TXN LED0 2 1 C
19 GLAN_TXN 16 HSIN
RTL8111DL 2 LAN_MDIP0 W=60mils +LAN_VDD @
MDIP0 LAN_MDIN0
15 CLK_PCIE_LAN 17 REFCLK_P MDIN0 3
18 5 LAN_MDIP1 L107
15 CLK_PCIE_LAN# REFCLK_M MDIP1
6 LAN_MDIN1 1 2
MDIN1 LAN_MDIP2
15 GLAN_REQ#9 25 CLKREQB MDI P2 8
9 LAN_MDIN2 4.7UH_1008HC-472EJFS-A_5%_1008
1 1
PCI_RST# MDI N2 LAN_MDIP3 C1478 C1479
17,23,25,27 PCI_RST# 27 PERSTB MDI P3 11

0.1U_0402_10V7K~N

22U_1206_6.3V6M
12 LAN_MDIN3 These components close to U64: Pin 48
MDI N3
2 2
1
R1244
2
2.49K_0402_1%
46 RSET FB12 4 +LAN_VDD12 ( Should be place within 200 mils )
R1245
19,23,25,26 ICH_PCIE_WAKE# ICH_PCIE_WAKE# 26 48 +LAN_SROUT12 W=60mils W=30mils L110 W=30mils
ISOLATEB LANWAKEB SROUT12 0_0603_5%
+3VS 1 2 28 ISOLATEB
19 +LAN_EVDD12 2 1 +LAN_VDD
1K_0402_5% EVDD12
41 CKTAL1 DVDD12 30 +LAN_VDD12
2

42 CKTAL2 DVDD12 36 2 1
R1246 13 C1484 1U_0402_6.3V
DVDD12
15K_0402_5% AVDD12 10 2 1
2

C1485 1U_0402_6.3V
R1420 39
1

AVDD12
0_0402_5%
19 LAN_CABDT LAN_CABDT 23 44 +LAN_IO These caps close to U64: Pin 19
NC VDDSR
24 45
1

NC VDDSR
7 GND VDD33 29
Y9 14 GND VDD33 37
27P_0402_50V8J

27P_0402_50V8J

31 0_0603_5% L108
GND +LAN_AVDD33
1 2 47 GND AVDD33 1 2 1 +LAN_IO
2 2 AVDD33 40
C1488

C1489

25MHZ_20P_1BX25000CK1A 22 43 +LAN_IO 1 2
EGND ENSR C1486 0.1U_0402_16V7K~N
B B
1 2
1 1 RTL8111DL-GR_LQFP48 C1487 0.1U_0402_16V7K~N
1 2
C1495 0.1U_0402_16V7K~N JLAN1
1 2
C1496 0.1U_0402_16V7K~N LAN_LED0 1 R953 2 LAN_ACTIVITY# 13
220_0402_5% Yellow LED-
+LAN_IO
1 12 Yellow LED+
0_0402_5% @ 1
LAN_LOPWEN 1 2 ISOLATEB These caps close to U64: Pin 1, 29,37,40 C1817 @ RJ45_TX3- 8
19 LAN_LOPWEN PR4-
@ R1374 C1818
220P_0402_50V7K 2 220P_0402_50V7K RJ45_TX3+ 7
TS1 2 PR4+
RP42
D54 RJ45_RX1- 6
C1490 1 PR2-
2 0.01U_0402_16V7K +V_DAC 1 TCT1 MCT1 24 5 4 LAN_LED21 2 LED2_LED3 for EMI
LAN_MDIN3 2 23 RJ45_TX3- 6 3 RJ45_TX2- 5
LAN_MDIP3 TD1+ MX1+ RJ45_TX3+ CH751H-40PT_SOD323-2 PR3-
3 TD1- MX1- 22 7 2 These caps close to JLAN1: Pin 13, 12 RJ45_TX2+
8 1 4 PR3+
C1491 1 2 0.01U_0402_16V7K +V_DAC 4 21 D55
LAN_MDIN2 TCT2 MCT2 RJ45_TX2- LAN_LED31 RJ45_RX1+
5 TD2+ MX2+ 20 75_1206_8P4R_5% 2 3 PR2+
LAN_MDIP2 6 19 RJ45_TX2+ 2
TD2- MX2- C1493 CH751H-40PT_SOD323-2 RJ45_TX0- 2 PR1-
C1492 1 2 0.01U_0402_16V7K +V_DAC 7 18 1000P_1206_2KV7K 15
LAN_MDIN1 TCT3 MCT3 RJ45_RX1- RJ45_TX0+ GND
8 TD3+ MX3+ 17 1 PR1+
LAN_MDIP1 RJ45_RX1+ 1
9 TD3- MX3- 16 GND 14
D56 LED2_LED3 1 R1251 2 LINK_10_1000# 11
C1494 1 +V_DAC LAN_LED11 LED1_LED3 Green LED-
2 0.01U_0402_16V7K 10 TCT4 MCT4 15 2 220_0402_5%
LAN_MDIN0 11 14 RJ45_TX0- LED1_LED3 1 R1252 2 LINK_100_1000# 9
LAN_MDIP0 TD4+ MX4+ RJ45_TX0+ CH751H-40PT_SOD323-2 220_0402_5% Orange LED-
12 TD4- MX4- 13
1 1 +LAN_IO 10 Green-Orange LED+
D57
LAN_LED31 2 C1819 C1820 1
A BOTH_GST5009-LF 220P_0402_50V7K C-1775553 A
CH751H-40PT_SOD323-2 220P_0402_50V7K 2 2 C1821 CONN@
CM1293-04SO_SOT23-6 CM1293-04SO_SOT23-6 220P_0402_50V7K
2
LAN_MDIN1 LAN_MDIP0 LAN_MDIN2 LAN_MDIP3
for EMI
1 CH1 CH4 4 1 CH1 CH4 4
These caps close to JLAN1: Pin 9, 11

2 Vn Vp 5 +3VS 2 Vn Vp 5 +3VS
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/21 Deciphered Date 2009/03/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Gigabit LAN_RTL8111C
LAN_MDIP1 3 6 LAN_MDIN0 LAN_MDIP2 3 6 LAN_MDIN3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
CH2 CH3 CH2 CH3 Custom 0.2
@ D29 @ D28
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4592P
Date: Thursday, February 19, 2009 Sheet 21 of 43
5 4 3 2 1
 5 4 3 2 1

SATA HDD CONN

JSATA1
0.01U_0402_50V7K 1
PSATA_ITX_DRX_P0 C1214 1 PSATA_ITX_DRX_P0_C GND
2 2
D 18 PSATA_ITX_DRX_P0
18 PSATA_ITX_DRX_N0
PSATA_ITX_DRX_N0C1213 1
C393 3900P_0402_50V7K
2 PSATA_ITX_DRX_N0_C
0.01U_0402_50V7K
3
4
A+
A- SATA ODD CONN D

PSATA_IRX_DTX_N0 GND
18 PSATA_IRX_DTX_N0_C 2 1 5 B-
6 B+
2 1 PSATA_IRX_DTX_P0 7
18 PSATA_IRX_DTX_P0_C GND
C392 3900P_0402_50V7K
JODD2
8 V33 close JSATA2
9 C1216 0.01U_0402_50V7K 1
V33 ODD_ITX_DRX_P0 GND
10 V33 18 ODD_ITX_DRX_P0 1 2 ODD_ITX_DRX_P0_C 2 RX+
11 ODD_ITX_DRX_N0 1 2 ODD_ITX_DRX_N0_C 3
GND 18 ODD_ITX_DRX_N0 RX-
12 C1215 0.01U_0402_50V7K 4
GND ODD_IRX_DTX_N0 GND
13 GND 18 ODD_IRX_DTX_N0_C 1 2 5 TX-
14 C327 1 2 0.01U_0402_50V7K ODD_IRX_DTX_P0 6
V5 18 ODD_IRX_DTX_P0_C TX+
15 C326 0.01U_0402_50V7K 7
+5VS V5 GND
16 V5
17 GND GND 23
18 Reserved
19 GND GND 24
20 V12 8 DP
21 V12 +5VS 9 5V
22 V12 10 5V GND 14
11 MD GND 15
SUYIN_127043FR022G226ZL_NR 12 GND
13 GND
+5VS CONN@
+5VS SUYIN_127382FR013S52_NR

10U_0805_10V4Z~N 0.1U_0402_16V7K~N
1 10U_0805_10V4Z 0.1U_0402_16V4Z
1 1 1 1
+
1 1 1 1
C @C1777 C574 C296 C377 C376 C499 C
C498 C506 C503
2 2 2 2 2
2 2 2 2
150U_B2_6.3VM_R45M 0.1U_0402_16V7K~N 1000P_0402_50V7K~N
1U_0603_10V4Z 1000P_0402_50V7K~N

Close to SATA HDD

Close to ODD Conn

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 22 of 43
5 4 3 2 1
 A B C D E

Debug Board +1.5VS

+3VS

JMINI1
1 1 2 2
3 3 4 4
5 5 6 6
7 8 LPC_FRAME# LPC_FRAME# 18,26,27
R1425 0_0402_5% 7 8 LPC_AD3
9 9 10 10
PCI_RST# 1 2 11 12 LPC_AD2
11 12 LPC_AD1
26 EC_RX_P80_DATA 1 2 13 13 14 14
1 @ R1427 0_0402_5% R1424 10_0402_5%2 LPC_AD0 1
15 15 16 16 LPC_AD[0..3] 18,26,27
17 18 @ R1426 10_0402_5%2 EC_TX_P80_DATA 26
CLK_DEBUG_PORT 17 18
19 19 20 20
21 22 PCI_RST#
21 22 R14142
23 23 24 24 1 +3VALW
25 26 0_0402_5%
25 26
27 27 28 28
29 29 30 30
31 31 32 32
33 33 34 34
35 35 36 36
37 37 38 38
39 39 40 40
+3VS 41 41 42 42
43 43 44 44
45 45 46 46
47 47 48 48
49 49 50 50
51 51 52 52

53 GND1 GND2 54

FOX_AS0B226-S52N-7F~N

2 2

Power status(Left)
LED1
12-21-BHC-ZL1M2RY-2C BLUE +5VALW

PWR_BLUE_LED# 2 1 1 R472 2
26,27 PWR_BLUE_LED#
200_0603_5%

Mini-Express Card---WLAN
LED2 +5VALW
BATT_LOW_LED# 3 Y
26 BATT_LOW_LED#
1 1 R471 2
3 +3V_WLAN BATT_CHG_LED# 2 3
26 BATT_CHG_LED#
@ B 200_0603_5%
R411 1 2 +1.5VS 12-22/Y2BHC-A30/2C_Y/B~D
+3VALW
0_0805_5%
+1.5VS 0.01U_0402_16V7K~N

1 1
C488
JMINI2
9,21,25,26 ICH_PCIE_WAKE# ICH_PCIE_WAKE# 1 2 C485 W=60mils W=60mils
CH_DATA @ R380 1 0_0402_5% 1 2 2 2
28 CH_DATA 2 MINI_PIN3 3 3 4 4
CH_CLK @ R381 1 0_0402_5%
2 MINI_PIN4 5 6 +3VALW
28 CH_CLK 5 6 +3V_WLAN
15 WLAN_REQ#4 WLAN_REQ#4 7 8 LPC_FRAME# 0.01U_0402_16V7K~N Q131
7 8 LPC_AD3
9 9 10 10

D
11 12 LPC_AD2 6

S
15 CLK_PCIE_MCARD# 11 12
13 14 LPC_AD1 1 5 4
15 CLK_PCIE_MCARD 13 14
15 16 LPC_AD0 C1822 2
PCI_RST# 1 15 16 1U_0603_10V6K
2 17 17 18 18 1
R445 0_0402_5% 19 20 WL_OFF# 0.01U_0402_16V7K~N 4.7U_0805_10V4Z~N

G
15 CLK_DEBUG_PORT 19 20 WL_OFF# 26 2
21 22 PCI_RST#

3
PCIE_RXN3 PCIE_C_RXN3 23 21 22 PCI_RST# 17,21,25,27 +B+_BIAS SI3456BDV-T1-E3 1N TSOP6
19 PCIE_RXN3 1 2 23 24 24 +3V_WLAN 1 1 1
19 PCIE_RXP3 PCIE_RXP3 R4031 20_0402_5% PCIE_C_RXP3 25 26 C500 C489 C456
R404 0_0402_5% 25 26
27 27 28 28 +1.5VS

2
29 30 ICH_SM_CLK ICH_SM_CLK 13,14,15,19
PCIE_TXN3 29 30 ICH_SM_DA R1512 2 2 2
19 PCIE_TXN3 31 31 32 32 ICH_SM_DA 13,14,15,19
PCIE_TXP3 33 34 470K_0402_5%
19 PCIE_TXP3 33 34
35 36 USB20_N6 0.1U_0402_16V4Z~N
35 36 USB20_N6 19
37 38 USB20_P6
USB20_P6 19

1
37 38 WLANPW
+3V_WLAN 39 39 40 40
41 42 LED_WWAN# T61 PAD
41 42

2
LED_WLAN# D
43 43 44 44 LED_WLAN# 27
45 46 2 1 +3V_WLAN 2 Q132 R1513
4 45 46 26 WLANPW_EN# 4
47 48 100K_0402_5% R86 +1.5VS G SSM3K7002FU_SC70-3 1.5M_0402_5%
47 48
49 50 S
3
49 50
51 52 +3V_WLAN

1
51 52
53 GND1 GND2 54

ACES_88910-5204
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 23 of 43
A B C D E
 5 4 3 2 1

+3VS
+5VS
L6
1 2
40mil +3VS_DVDD 40mil +AVDD_HD 1 2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
R128 0_0603_5% 0_0805_5%

1U_0402_6.3V

10U_0603_6.3V

1U_0402_6.3V

10U_0603_6.3V

1U_0402_6.3V
1 1 1 1 1 1 1 1 1

C796
C1399

C1398

C1397

C1403

C1404

C1405

C1406

C1407
2 2 2 2 2 2 2 2 2 +AVDD_HD

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
27
38

39
45
HEADPHONE OUT JACK

1
U60

DVDD_CORE
DVDD_IO

DVDD

AVDD
AVDD

PVDD
PVDD
D D
C23 @ 10P_0402_50V8JR41 @ 10_0402_5% FOX_JA6333L-B3S0-7F~N
1 2 2 1 5

2
HP_ JD 4 10
L23

R1519

R1520

R1521

R1522
18 ACZ_BITCLK ACZ_BITCLK 6 28 AMP_LEFT 9
HDA_BITCLK HP0_PORT_A_L AMP_RIGHT HP_RIGHT HP _R HPR
HP0_PORT_A_R 29 1 2 1 2 3 8
18 ADC_ACZ_SDIN0 2 R8 1 33_0402_5% 8 HDA_SDI VREFOUT_A_or_F 23 R360 56_0402_5% BLM18BD601SN1D_0603~D 6 7

0.01U_0402_16V7K

0.01U_0402_16V7K
@ @ @ @ HP_LEFT 1 2 HP_L 1 2 H PL 2

PACDN042Y3R_SOT23-3
18 ACZ_SDOUT 5 31 HP_LEFT SPR_L1 R361 56_0402_5% L22 1
HDA_SDO HP1_PORT_B_L HP_RIGHT SPR_L2 BLM18BD601SN1D_0603~D
HP1_PORT_B_R 32 1 1

1000P_0402_50V7K~N

1000P_0402_50V7K~N
10 +MIC1_VREFO SPR_R1
18 ACZ_SYNC HDA_SYNC

3
19 MIC_LEFT SPR_R2 1 1 @ JHP1
PORT_C_L

C1836

C1837
11 20 MIC_RIGHT D16
18 ACZ_RST# HDA_RST# PORT_C_R 2 2
VREFOUT_C 24

C260

C252
28 MIC_CLK 1 2 2 DMIC_CLK/GPIO1
R126 0_0603_5% SPR_L1 @ R1532 1 INTSPK_L1 2 2
SPKR_PORT_D_L+ 40 2
28 MIC_SIG 1 2 4 41 SPR_L2 @ R1533 1 0_0603_5%
2 INTSPK_L2 @ @ @ @ For IDT @ @

1
DMIC0/GPIO2 SPKR_PORT_D_L-

10K_0402_5% R696

10K_0402_5% R697

10K_0402_5% R699

10K_0402_5% R698
R127 0_0603_5% 0_0603_5%

1
46 DMIC1/GPIO0/SPDIF_OUT_1
43 SPR_R1 @ R1534 1 2 INTSPK_R2
SPKR_PORT_D_R- SPR_R2 @ R1535 1 0_0603_5% INTSPK_R1
For IDT 48 SPDIF_OUT_0 SPKR_PORT_D_R+ 44 2

HPL
0_0603_5%

HPR
1@ R1539 2 0_0402_5% 47 15

2
26 EC_MUTE EAPD PORT_E_L @ @
C1421 2 35
PORT_E_R 16 Memo control
CAP-
PORT_F_L 17
2.2U_0603_6.3V6K 36 18
CAP+ PORT_F_R

1
D D D D
+AVDD_HD
2 1 14 12 1 2 MONO_IN Q138 2 Q133 2 2 Q134 2 Q139
100K_0402_5% R1495 SENSE_B PC_BEEP R1189 0_0402_5% 2N7002_SOT23-3 G G G G 2N7002_SOT23-3
+AVDD_HD 25 @S SSM3K131TU_UFM-3
S S SSM3K131TU_UFM-3 S @

3
MONO_OUT +5VALW
1 2 13 SENSE_A
R915 2.49K_0402_1% 22 SSM3K131TU_UFM-3
CAP2 @ @

3
S S S S
HP_ JD 1 2 7 Q136
DVSS

2
R13 20K_0402_1% 42 21 2N7002_SOT23-3SSM3K131TU_UFM-3
2
G G
2 2
G
2
G 2N7002_SOT23-3
M IC_JD 1 PVSS VREFFILT R1537 Q140 Q135 Q141
2 26 AVSS
C R892 10K_0402_1% 30 34 10K_0402_1% D D D D C

1
AVSS V-
2 1 33 AVSS
C114 1000P_0402_50V7K~N 49 37

1
GND VREG

2.2U_0603_6.3V6K

10U_0603_6.3V

1U_0402_6.3V
92HD81B1X5NLGXA1X8 48P 1 1 1 1

C66
C1414

C1413
C141

1
D
C1826 15P_0402_50V8J @ 4.7U_0603_6.3V EC_MUTE 2 R1538@
1 2 ACZ_SDOUT
GNDA 2 2 2 2 G Q137 100K_0402_5%
S SSM3K7002FU_SC70-3

2
For SED TEST For pop/click noise from S3/S4/cold boot/warm boot
W=40mil R1523
1 2 +5VS
1 1
0_0603_5%
+5VS
+MIC1_VREFO MICROPHONE IN JACK
C1827 C1828
0.1U_0402_16V4Z 10U_0805_10V4Z
2 2
16
15
6

1U_0402_6.3V
U18 R1524 1 2 10K_0402_5% 1

C7
VDD
PVDD1
PVDD2

@ R1525 1 2 10K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
@

2
2
C1829 1 2 7 2 R1526 1 2 10K_0402_5%
0.47U_0603_10V7K RIN+ GAIN0 FOX_JA6333L-B3S0-7F
3 @ R1527 1 2 10K_0402_5% 5
GAIN1

R3481

R3491
AMP_RIGHT C1830 1 2 AMP_R 17 M IC_JD 4 10
0.47U_0603_10V7K RIN- SPK_R1 INTSPK_R1
ROUT+ 18 1 2 9
R1528 0_0603_5% MIC_RIGHT 1 2 3 8
C24 2.2U_0402_6.3V6 L34 BLM18BD601SN1D_0603~D 6 7
14 SPK_R2 1 2 INTSPK_R2 MIC_LEFT 1 2 2
C1831 1 ROUT- R1529 0_0603_5% C25 2.2U_0402_6.3V6 L35 BLM18BD601SN1D_0603~D
2 9 LIN+ 1
0.47U_0603_10V7K
B B

PACDN042Y3R_SOT23-3
4 SPK_L1 1 2 INTSPK_L1 @ C525 @ C524
LOUT+ R1530 0_0603_5% JMIC1

100P_0402_25V8K

100P_0402_25V8K
AMP_LEFT C1832 1 2 AMP_L 5 LIN-

3
0.47U_0603_10V7K 8 SPK_L2 1 2 INTSPK_L2
LOUT- R1531 0_0603_5% D23

@
R14 1 2
12 0_0805_5%

1
NC
10 R115 1 2
EC_MUTE BYPASS 0_0805_5%
19 SHUTDOWN
1
C1833 R116 1 2
@
EC Beep R1183
GND1
GND2
GND3
GND4

0_0805_5% C1412 0.1U_0402_16V4Z

GND

1 2 MONO_IN
2 1U_0603_10V4Z 26 BEEP
R117 1 2
@
P3017THF TSSOP 20P 0_0805_5% 499K_0402_1%~D
21

20
13
11
1

R118 1 2
@
0_0805_5%
ICH Beep C1416 0.1U_0402_16V4Z
R1188

GND GNDA 19 SB_SPKR 1 2

499K_0402_1%~D

GAIN0 GAIN1 GAIN

Speaker Connector

INTSPK_R1

INTSPK_R2

INTSPK_L1

INTSPK_L2
0 0 6dB PACDN042Y3R_SOT23-3 D12
2 ACES_88266-04001

@
1 INTSPK_L2 4 6
PACDN042Y3R_SOT23-3 D17 INTSPK_L1 4 G2
3 3 3 G1 5

100P_0402_25V8K

100P_0402_25V8K

100P_0402_25V8K

100P_0402_25V8K
0 1 10dB INTSPK_R2
* 2 2 2

C15

C16
C8

C9
1 INTSPK_R1 1 1
A 3 A
JSPK1
1 0 15.6dB

1 1 21.6dB
Compal Electronics, Inc.
Change to 100p from 0.01u for EMI
-1012
Security Classification Compal Secret Data
Issued Date 2008/05/07 Deciphered Date 2009/05/07 Title

Buzzer need to support ICH/PCM_SPK/Battery_low and WL_on/off HD CODEC 92HD81B1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4596P
Date: Thursday, February 19, 2009 Sheet 24 of 43
5 4 3 2 1
 5 4 3 2 1

Express card

D JEXP1 D
+1.5VS_PEC
Express Card Power Switch 4.7U_0805_10V4Z~N 1 GND
USB20_N7 2
+1.5VS_PEC 19 USB20_N7 USB_D-
+1.5VS 1 1 USB20_P7 3
U11 19 USB20_P7 USB_D+
EXPR_CPUSB# 4
C90 C89 CPUSB#
2 1 12 1.5Vin 1.5Vout 11 5 RSV
C91 0.1U_0402_16V4Z~N 14 13 0.1U_0402_16V4Z~N 6
1.5Vin 1.5Vout +3VS_PEC 2 2 ICH_SMBCLK RSV
+3VS 19 ICH_SMBCLK 7 SMB_CLK
ICH_SMBDATA 8
19 ICH_SMBDATA SMB_DATA
2 1 2 3.3Vin 3.3Vout 3 +1.5VS_PEC 9 +1.5V
C74 0.1U_0402_16V4Z~N 4 5 +3V_PEC 10
3.3Vin 3.3Vout +1.5VS_PEC +1.5V
+3VALW 19,21,23,26 ICH_PCIE_WAKE# ICH_PCIE_WAKE# 11 WAKE#
2 1 17 AUX_IN AUX_OUT 15 +3V_PEC 12 +3.3VAUX
C85 0.1U_0402_16V4Z~N +3V_PEC PERST# 13
PCI_RST# 4.7U_0805_10V4Z~N PERST#
17,21,23,27 PCI_RST# 6 SYSRST# OC# 19 +3VS_PEC 14 +3.3V
15 +3.3V
SYSON 20 8 PERST# 15 EXPCARD_REQ#16 EXPCARD_REQ#16 16
26,30,36 SYSON SHDN# PERST# CLKREQ#
1 1 CPPE# 17
SUSP# CLK_PCIE_EXPR# CPPE#
26,29,30,35,37 SUSP# 1 STBY# NC 16 15 CLK_PCIE_EXPR# 18 REFCLK-
C92 C93 CLK_PCIE_EXPR 19
15 CLK_PCIE_EXPR REFCLK+
CPPE# 10 7 0.1U_0402_16V4Z~N 20
CPPE# GND 2 2 PCIE_RXN4 GND
19 PCIE_RXN4 21 PERn0
EXPR_CPUSB# 9 19 PCIE_RXP4 PCIE_RXP4 22
CPUSB# PERp0
23 GND
18 PCIE_TXN4 24
RCLKEN +3VS_PEC 19 PCIE_TXN4 PETn0
PCIE_TXP4 25
19 PCIE_TXP4 PETp0
P2231NF_QFN20 4.7U_0805_10V4Z~N 26 GND
C +1.5V_CARD Max. 650mA, Average 500mA 27 C
GND
1 1 28 GND
+3V_CARD Max. 1300mA, Average 1000mA 29 GND GND 31
C75 C73 30 32
0.1U_0402_16V4Z~N GND GND
2 2 FOX_1CX41202-KH_26P
conn@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXPRESS CARD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 25 of 43
5 4 3 2 1
 L18
+3VALW +EC_AVCC 2 1
+EC_AVCC
1
+3VALW
2 FBM-11-160808-601-T_0603
Board ID +3VALW
C481
+3VALW C482
1 1 1 1 1 1 1000P_0402_50V7K~N 0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N
C281

0.1U_0402_16V4Z~N
C285

0.1U_0402_16V4Z~N
C277

0.1U_0402_16V4Z~N
C493

1000P_0402_50V7K~N
C269

1000P_0402_50V7K~N
C291

1
ECAGND2 1
2 1 2008-08-05 change Brd ID

2
FBM-11-160808-601-T_0603 L19 R232
2 2 2 2 2 2 100K_0402_5%
R405
Ra
10K_0402_5%

2
AD_BID

1
1

111
125

2
EC_PME#

22
33
96

67
9
R1506 U29 R231 C272
71.5K_0402_1% 0.1U_0402_16V4Z
2 1 Rb

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
19,21,23,25 ICH_PCIE_WAKE# 2
0_0402_5%

1
R266 0_0402_5%
GATEA20 1 21 1 2
18 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 16
KB_RST# 2 23 BEEP M/B rev:0.1; 0.2; 0.3; 1.0
18 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP 24
SERIRQ 3 26 W_DISABLE# W_DISABLE# 27
19,27 SERIRQ SERIRQ# FANPWM1/GPIO12 Voltage:0.0; 0.4; 0.8; 1.0
LPC_FRAME# 4 27 ACOFF
18,23,27 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 33
LPC_AD3 5
18,23,27 LPC_AD3 LAD3
CLK_PCI_EC LPC_AD2 7 PWM Output C273 1 2 0.01U_0402_16V7K ECAGND
18,23,27 LPC_AD2 LAD2 VCC 3.3V+/-5% 0.6V~1.6V
LPC_AD1 8 63 BATT_TEMP
18,23,27 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 40
1

LPC_AD0 BATT_OVP Ra 100k

R272
18,23,27 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP 40
ADP_I/AD2/GPIO3A 65 ADP_I 33 Board ID Rb
CLK_PCI_EC AD_BID 26.1K +/-1%
15 CLK_PCI_EC 12 PCICLK AD Input AD3/GPIO3B 66 0
34.8K +/-1%
0.683
@ 10_0402_5% R228 PLT_RST# 13 75 MIC_DIAG BATT_OVP C1825 1 2 0.01U_0402_16V7K ECAGND 1 0.8519
7,17,29 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 MIC_DIAG 28 46.4K +/-1%
1 2 EC_RST# 37 76 POW_MON 2 1.0459
+3VALW POW_MON 39
2

EC_SCI# ECRST# SELIO2#/AD5/GPIO43 56.2K +/-1%

1 19 EC_SCI# 20 SCI#/GPIO0E
3 1.1873
@ C282 47K_0402_5% PCI_CLKRUN# 71.5K +/-1%
19,27 PCI_CLKRUN# 38 CLKRUN#/GPIO1D
4 1.3758
DAC_BRIG 91K +/-1%
2 DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG 16 5 1.5723
15P_0402_50V8J C268 70 EN_DFAN1
2 KSI[0..7] EN_DFAN1/DA1/GPIO3D EN_DFAN1 4
0.1U_0402_16V4Z DA Output 71 IR EF
27 KSI[0..7] IREF/DA2/GPIO3E IREF 33
KSI0 55 72 M_PWROK_EC 1 2
1 KSO[0..15] KSI0/GPIO30 DA3/GPIO3F CHGVADJ 33
KSI1 56 R256 0_0402_5%
27 KSO[0..15] KSI1/GPIO31
KSI2 57
KSI3 KSI2/GPIO32 EC_MUTE
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE 24
KSI4 59 84 LCD_TST
KSI4/GPIO34 PSDAT1/GPIO4B LCD_TST 16
KSI5 60 85
+5VALW KSI6 KSI5/GPIO35 PSCLK2/GPIO4C LCD_CBL_DET#
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 LCD_CBL_DET# 16
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 27
EC_SMB_DA1 R263 2 1 4.7K_0402_5% KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 27
KSO1 40
EC_SMB_CK1 R262 2 1 4.7K_0402_5% KSO2
KSO3
KSO4
41
42
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23 SDICS#/GPXOA00 97 SPI_PULLDOWN 2 R274
EN_WOL#
1 4.7K_0402_5%
SPI Flash (8Mb*1)
@ C507
@ R419
43 KSO4/GPIO24 SDICLK/GPXOA01 98 EN_WOL# 21
+3VS KSO5 BT_OFF# 2 SPI_CLK_R
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
VGATE
BT_OFF# 28 1 2 1
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 VGATE 7,19,39 22P_0402_50V8J 0_0402_5%
EC_SMB_DA2 R264 2 1 4.7K_0402_5% KSO7 46 SPI Device Interface
KSO8 KSO7/GPIO27 +3VALW
47 KSO8/GPIO28
EC_SMB_CK2 R265 2 1 4.7K_0402_5% KSO9 48 119 FRD#SPI_SO C314
KSO10 KSO9/GPIO29 SPIDI/RD# FWR#SPI_SI 20mils
49 KSO10/GPIO2A SPIDO/WR# 120 1 2
LCD_TST @ R269 2 1 4.7K_0402_5% KSO11 50 SPI Flash ROM SPICLK/GPIO58 126 SPI_CLK 2 R437 1
KSO12 KSO11/GPIO2B FSEL#SPICS# 0.1U_0402_16V4Z~N 10K_0402_5%
51 KSO12/GPIO2C SPICS# 128
LCD_CBL_DET# R276 2 1 4.7K_0402_5% KSO13 52 U37
KSO14 KSO13/GPIO2D FSEL#SPICS# 2
53 KSO14/GPIO2E 1SPI_CS# 1 CS# VCC 8
MIC_DIAG R308 1 2 10K_0402_5% KSO15 54 73 WLANPW_EN# WLANPW_EN# 23 R439 15_0402_5% 2 7
KSO15/GPIO2F CIR_RX/GPIO40 MSEN# FRD#SPI_SO 1 SO HOLD#
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 MSEN# 16 2SPI_SO 3 WP# SCLK
SPI_CLK_R 1
6 2 SPI_CLK
EC_FB_SDATA R303 2 1 4.7K_0402_5% 82 89 FSTCHG 15_0402_5% R275 4 15_0402_5%
5 R420
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 33 GND SI
90 BATT_CHG_LED# SPI_SI1 2 FWR#SPI_SI
BATT_CHGI_LED#/GPIO52 BATT_CHG_LED# 23
EC_FB_SCLK R304 2 1 4.7K_0402_5% 91 CAPSLED# W25X16-VSSIG SOIC_SO8 15_0402_5% R438
CAPS_LED#/GPIO53 CAPSLED# 27
EC_SMB_CK1 77 GPIO BATT_LOW_LED#/GPIO54 92 BATT_LOW_LED#
40 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED# 23
MSEN# R309 1 2 10K_0402_5% EC_SMB_DA1 78 93 SCRLED#
40 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 SCRLED# 27
EC_SMB_CK2 79 SM Bus 95 SYSON
4,16 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 25,30,36
4,16 EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 39
127 ACIN
AC_IN/GPIO59 ACIN 19,32,33

6SLP_S3# 100 EC_RSMRST#

19 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 19
14SLP_S5# 101 EC_LID_OUT#
19 SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 19
15EC_SMI# 102 EC_ON
19 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 27
16LID_SW# 103 EC_SWI#
LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# 19
EC_FB_SCLK 17 104 ICH_PWROK
27 EC_FB_SCLK SUSP#/GPIO0B ICH_PWROK/GPXO06 ICH_PWROK 7,19
27 EC_FB_SDATA EC_FB_SDATA 18 GPO 105 BKOFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 16
EC_PME# 19 GPIO 106 WL_OFF#
17 EC_PME# EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# 23
25 107 LCD_VCC_TEST_EN
FAN_SPEED1 28 EC_THERM#/GPIO11 GPXO10 PSID_DISABLE# LCD_VCC_TEST_EN 16
4 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 PSID_DISABLE# 32 U10
27 TOUCHKEY_TINT TOUCHKEY_TINT 29 @
EC_TX_P80_DATA 30 FANFB2/GPIO15 APX9132ATI-TRL_SOT23-3
23 EC_TX_P80_DATA EC_TX/GPIO16
EC_RX_P80_DATA 31 110 SLP_S4# SLP_S4# 19
23 EC_RX_P80_DATA EC_RX/GPIO17 PM_SLP_S4#/GPXID1
ON_OFF 32 112 GMCH_ENBKL GMCH_ENBKL 9,16 LID_SW# 3 2

GND
27 ON_OFF ON_OFF/GPIO18 ENBKL/GPXID2 VOUT VDD +3VALW
PWR_BLUE_LED# 34 114 USB_EN USB_EN 28
23,27 PWR_BLUE_LED# PWR_LED#/GPIO19 GPXID3
NUMLED# 36 GPI 115 EC_THERM# 1
+5VS 27 NUMLED# NUMLED#/GPIO1A GPXID4 EC_THERM# 19
116 SUSP#
SUSP# 25,29,30,35,37

1
R271 GPXID5 PBTN_OUT# C1815
GPXID6 117 PBTN_OUT# 19
4.7K_0402_5% 118 PS_ID 0.1U_0402_16V4Z
TP_DATA XCLKI GPXID7 PS_ID 32 2
1 2 122 XCLK1
TP_CLK 1 2 XCLKO 123 124 +V18_R 1 2 1U_0603_10V4Z
R270 XCLK0 V18R C322
AGND

4.7K_0402_5%
GND
GND
GND
GND
GND

C270 2 1 0.1U_0402_16V4Z
XCLKO 1 R278 2 XCLKI
@ 20M_0603_5% KB926QFA1_LQFP128
11
24
35
94
113

69
2

R1421
ECAGND U9
0_0402_5%
APX9132ATI-TRL_SOT23-3
+3VALW
1

LID_SW# 3 2

GND
VOUT VDD +3VALW
EC_MUTE R312 1 2 1
10K_0402_5%

1
KSO1 @R1428 2 1 C1809
47K_0402_5% 1 1 0.1U_0402_16V4Z
KSO2 @R1429 2 C292 C297 2
1
1

47K_0402_5%
18P_0402_50V8J

18P_0402_50V8J

WL_OFF# @R1536 2 1
IN

OUT

47K_0402_5% 2 2
0.5A per each pin
NC

NC
2

32.768KHZ_12.5P_1TJS125BJ2A251
X2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 26 of 43
 A B C D E

+3VALW
INT_KBD CONN. JKB1
KSO8 @ C449 100P_0402_25V8K KSI7 @ C235 100P_0402_25V8K

KSI0 1 KSI3 @ C239 100P_0402_25V8K KSI6 @ C236 100P_0402_25V8K

Power Button 26 KSI[0..7]
KSI[0..7] KSI1 2
1
2

100K_0402_5%
KSI2 3 KSO9 @ C249 100P_0402_25V8K KSI5 @ C237 100P_0402_25V8K
KSO[0..15] KSI3 3
26 KSO[0..15] 4 4

R297
KSI4 5 KSI2 @ C240 100P_0402_25V8K KSO0 @ C441 100P_0402_25V8K
KSI5 5
6 6
KSI6 7 KSI1 @ C241 100P_0402_25V8K KSO1 @ C442 100P_0402_25V8K

1
D15 KSI7 7
8 8
2 KSO0 9 KSO10 @ C248 100P_0402_25V8K KSO2 @ C443 100P_0402_25V8K
ON_OFF 26 9
PWR_ON-OFF_BTN# 1 KSO1 10
51ON# KSO2 10 KSO11 @ C247 100P_0402_25V8K KSI4 @ C238 100P_0402_25V8K
3 51ON# 32 11 11
KSO3 12
1 CHN202UPT SC-70 KSO4 12 KSI0 @ C242 100P_0402_25V8K KSO3 @ C444 100P_0402_25V8K 1
13 13
KSO5 14
+3VALW KSO6 14 KSO12 @ C246 100P_0402_25V8K KSO4 @ C445 100P_0402_25V8K
15 15

1
2 KSO7 16
KSO8 16 KSO13 @ C245 100P_0402_25V8K KSO5 @ C446 100P_0402_25V8K
17 17
2

C313 D13 KSO9 18

R296 1000P_0402_50V7K~N RLZ20A_LL34 KSO10 18 KSO14 @ C244 100P_0402_25V8K KSO6 @ C447 100P_0402_25V8K
19 19
4.7K_0402_5% 1 KSO11 20

2
@ KSO12 20 KSO15 @ C243 100P_0402_25V8K KSO7 @ C448 100P_0402_25V8K
21 21

1
D KSO13 22
1

EC_ON KSO14 22
26 EC_ON 1 2 2 23 23
R291 G Q26 KSO15 24
0_0402_5% 3 S SSM3K7002FU_SC70-3 25
24
25
For EMI
26 26
27 G1
28 G2
ACES_88514-2601_26P
CONN@

@ SW3
SW_1BT002-0121L_4P

PWR_ON-OFF_BTN# 3 1 POWER SWITCH Function/B CONN.

4 2
5
6

JFN1
2 BTOP_BTN# 2
1 1
SCRLED# 2
Regulator for ENE sensor 26
26
SCRLED#
CAPSLED#
CAPSLED#
NUMLED#
3
4
2
3
Wireless_BTN 26
26
NUMLED#
TOUCHKEY_TINT TOUCHKEY_TINT1
PWR_BLUE_LED#
2 R606
0_0402_5%
5
6
4
5
23,26 PWR_BLUE_LED# 6
+5VS SW1 +5VS
Adjustable Output 7 7
BLUETOOTH_LED# 8
1BS003-1211L_3P R901 RT9198-33PBR SOT-23 5P 28 BLUETOOTH_LED# 8
KC FBMA-11-100505-301T 0402 9
EC_FB_SCLK L7 2 EC_FN_SCLK 9
1 2 3 SHDN# BP 4 26 EC_FB_SCLK 1 10 10
+3VS_FUN For ENE ( Close to JFN1 ). 26 EC_FB_SDATA EC_FB_SDATA L21 2 1 EC_FN_SDATA 11 11
1

10K_0603_1% 2 KC FBMA-11-100505-301T 0402 LED_WLAN# 12

1U_0402_6.3V4Z

GND +3VS_FUN 23 LED_WLAN# PWR_ON-OFF_BTN# 12

13
1

+3VS @ R880 13
1 1 VIN VOUT 5 +3VALW 14 14
C250

0_0603_5% R622 1 2R_SATA_LED# 15

18 SATA_LED# 15
U54 1 2 0_0402_5% 16 16
W_DISABLE#

17 GND
2

10U_0603_6.3V
1 18 GND

C1834
ACES_88512-1641_16P
D60
CONN@
2
2
26 W_DISABLE# 1
3
EC_FN_SCLK
PJSOT24C_SOT23-3 EC_FN_SDATA
@
D58
PWR_ON-OFF_BTN# 2
1 1 1
BTOP_BTN# 3 C37 C39
3 33P_0402_50V J NPO 33P_0402_50V J NPO 3
@ @
TPM 1.2 18,23,26 LPC_FRAME#
LPC_FRAME#
PCI_RST#
PJSOT24C_SOT23-3
@
2 2

17,21,23,25 PCI_RST#
SERIRQ
19,26 SERIRQ
CLK_PCI_TPM
15 CLK_PCI_TPM
PCI_CLKRUN#
19,26 PCI_CLKRUN#

Touch PAD/B CONN.

TP/B TO M/B CONN@
ACES_88514-0441_4P
+5VS
6 G2
5 G1
4 4
JTPM1 1 TP_CLK 3
26 TP_CLK 3
TP_DATA 2
26 TP_DATA 2
LPC_FRAME# 1 2 LPC_AD0 LPC_AD0 18,23,26 C300 1
PCI_RST# GND1 RES0 LPC_AD1 0.01U_0402_16V7K 1
3 IAC_SDATA_OUT RES1 4 LPC_AD1 18,23,26 1 1
SERIRQ LPC_AD2 2 @ @ JP1
5 GND2 3.3V 6 LPC_AD2 18,23,26

C309
PCI_CLKRUN# 7 8 LPC_AD3
IAC_SYNC GND3 LPC_AD3 18,23,26

100P_0402_25V8K C310
+3VS 12mA 9 10 CLK_PCI_TPM
IAC_SDATA_IN GND4

3
2 2
+3VALW 11 IAC_RESET# IAC_BITCLK 12
D24

100P_0402_25V8K
SM05T1G_SOT23-3~D
GND
GND
GND
GND
GND
GND

1
ACES_88018-124L
13
14
15
16
17
18

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_OK/BTN/TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 27 of 43
A B C D E
 +5VALW +USB_AS CM1293-04SO_SOT23-6
0.1U_0402_16V4Z
1 1 4 USB_P0
U12 CH1 CH4
80 mils

2
1 8 + C434 C223
GND OUT
2 IN OUT 7
3 6 150U_B2_6.3VM_R45M R155 2 5 +USB_AS
USB_EN# IN OUT 2 470_0603_5% Vn Vp
1 4 EN# OC# 5
C228

1 1
RT9711PS SO 8P
0.1U_0402_16V4Z D USB_N0
3 CH2 CH3 6
2 USB_EN# Q14
2
G SSM3K7002FU_SC70-3 @ D19

1
USB_OC#0 19 S

3
R154
100K_0402_5%
@

2
+USB_AS

+USB_CS W=60mils JUSBP1

+5VALW 1
USB20_N0 USB_N0 VCC
19 USB20_N0 2 1 2 USB_N
USB20_P0 R1 2 0_0402_5%
1 USB_P0 3
19 USB20_P0 USB_P
U14 R3 0_0402_5% 4
80 mils 1 GND OUT 8 5
GND
GND
2 IN OUT 7 6 GND
3 IN OUT 6 7 GND

2
1 USB_EN# 4 5 8
C253 EN# OC# GND
RT9711PS SO 8P R38 SUYIN_020133MR004S536ZL
0.1U_0402_16V4Z 470_0603_5% CONN@
2

1
CM1293-04SO_SOT23-6
USB_OC#2_8 19
1 4 USB_P9
CH1 CH4

1
D
USB_EN# 2 Q13 2 5 +USB_BS
G SSM3K7002FU_SC70-3 Vn Vp
S

3
3 6 USB_N9
+USB_BS CH2 CH3
+5VALW @ D21

U13 0.1U_0402_16V4Z
80 mils 1 GND OUT 8 1 W=60mils +USB_BS
2 IN OUT 7
3 6 + C1811 C1812
USB_EN# IN OUT
1 4 EN# OC# 5
C64 150U_B2_6.3VM_R45M JUSBP4

2
RT9711PS SO 8P 2
1 VCC
0.1U_0402_16V4Z USB20_N9 2 1 USB_N9 2
2 19 USB20_N9 USB_N
R36 USB20_P9 R1410 2 0_0402_5%
1 USB_P9 3
19 USB20_P9 USB_P
470_0603_5% R1411 0_0402_5% 4 GND
5

1
GND
6 GND
7 GND
8 GND
USB_OC#9 19
SUYIN_020133MR004S536ZL

1
D CONN@
USB_EN# 2 Q8
G SSM3K7002FU_SC70-3
S

3
Felica Conn
+5VS

1
1
USB20_N3 2
19 USB20_N3 2
Check Module pin define USB20_P3
Camera Conn 19 USB20_P3 3
3
4
TP1 LEC 4
5
5 G2 8
JCA1 6
6 G1 7
1 1 @ 1
2 JFE1
USB20_P1 2 CONN@
CM1293-04SO_SOT23-6 19 USB20_P1 3 3 C315 @ ACES_88512-0641_6P
4 4
1 4 USB20_P5 USB20_N1 5 10U_0805_10V4Z 2
CH1 CH4 19 USB20_N1 5 +USB_CS
+5VS 2 1 6 6
L111 MBK1608221YZF 0603
24 MIC_SIG MIC_SIG 7 W=80mils
7
+3VS 2 1 8 8
2 5 +3VS L112 MBK1608221YZF 0603
24 MIC_CLK MIC_CLK 1 2 9
Vn Vp MIC_DIAG L41 0_0603_5% 9 JUSBP3
26 MIC_DIAG 10 10
11 GND 1 1
1 1 12 GND 2 2
3 6 USB20_N5 L42, L43 AS CLOSE JCA1 AS POSSIBLE @ C1770 @ C1771 3
CH2 CH3 29 IEEE1394_TPBN0 3
ACES_88460-1001 4
AS CLOSE AS JCA1 29 IEEE1394_TPBP0 4
D27
2 2 L41 AS CLOSE JCA1 AS POSSIBLE Bluetooth 29 IEEE1394_TPAN0 5
6
5
29 IEEE1394_TPAP0 6
7 7
JBT1 8
19 USB20_P2 8
100P_0402_50V 100P_0402_50V 1 19 USB20_N2 9
1 9
19
USB20_P4 2 2 10 10
19
USB20_N4 3 3 19 USB20_P8 11 11
PAD T62 BT_ACTIVE 4 12
4 19 USB20_N8 12
CH_CLK
Fingerprint 23 CH_CLK
BT_OFF#
5
6
5
26 BT_OFF# 6
JFP1 7 13
+5VALW 23 CH_DATA 7 GND1
19 USB20_N5 6 6 G1 7 +3VS 8 8 14 GND2
19 USB20_P5 5 5 G2 8 27 BLUETOOTH_LED# 9 9
4 10 ACES_87213-1200G
4 10
2

+3VS 3 3 11 GND CONN@

2 R222 12
2 10K_0402_5% GND
1 1 ACES_88460-1001
1

ACES_88512-0641_6P USB_EN#
CONN@
1

D
USB_EN 2 Q4
26 USB_EN
G SSM3K7002FU_SC70-3
Security Classification Compal Secret Data Compal Electronics, Inc.
S Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB/BlueTooth/FP/Felcia
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 28 of 43
 5 4 3 2 1

+1.8VS_CB
R1432 +1.8VS_CB
300mA
1 2 +1.8PE_VCCA
0_0402_5% U65

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N
4.7U_0603_6.3V6K
+3VALW 1 VIN VOUT 5
1 2 2 2 2 GND

C1781
SUSP# 3 4
25,26,30,35,37 SUSP# EN FB

C1782

C1783

C1784

2
0_0402_5%
@ RT9043-GB_SOT23-5~D
2 1 1 1

R1433

1U_0402_6.3V6K~D
R1514

2
1 61.9K +-1% 0402

C1823
1

1
R1515 @ C1824
2 10K_0402_5%

1
D @ Q130 2 D
AO3413_SOT23 +1.8VS_CB 22U_0805_6.3V6M~D

1
300mA

+VCCA_OUT
+1.8V 3 1 R1516
100K_0402_1%

4.7U_0805_10V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
@ R1434

G
1 1 1

2
30,38 SUSP 1 2

0.01U_0402_16V7K

C1785

C1786

C1787

C1788
100K_0402_5% 1 U46
R1435 @
@ 2 2 2
1 2
0_0402_5% IEEE1394_TPBN0
C1789

7 PE_VCCA 1394_TPBN 33
2 IEEE1394_TPBP0
14 PE_VCCA 1394_TPBP 34
17 PE_VCCA
+3VS IEEE1394_TPAN0

+VCCD_OUT
O2 recommend 1394_TPAN 36
IEEE1394_TPAP0
Layout Note: Place close to
100mA 1 VCCA_OUT 1394_TPAP 37
OZ888 and Shield GND.
+3.3VCCD POWER
4 38 IEEE1394_TPBIAS0
CORE_VCCD 1394_TPBIAS

0.1U_0402_10V6K

0.1U_0402_10V6K

4.7U_0805_10V4Z
18 C1790
+3VS_PHY CORE_VCCD OZ888XI OZ888XI
1 1 24 CORE_VCCD
IEEE1394 1394_XI 42 1 2
0_0603_5% 41 43 OZ888XO
CORE_VCCD 1394_XO

C1791

C1792

C1793
1 2 64 R1437 5.9K_0402_1% 10P_0402_50V8J~D
+3VS CORE_VCCD

2
R1436 39 1 2 +3VS_CR
2 2 1394_REF X3
20 VCCD_OUT 200mA
0.1U_0402_10V6K

0.1U_0402_10V6K

4.7U_0805_10V4Z

28 VCCD_OUT MMI_VCC 26 24.576MHz_16P_X5H024576FG1H-H

4.7U_0603_6.3V6K
1 1

1
+3VS_PHY 44 1 C1797
3.3VCCD
C1794

C1795

C1796

27 25 XD_CD# 1 2 1 R1438 2 OZ888XO

3.3VCCD MMI_XD_CD# MS_CD# C1798 0_0402_5%
19 3.3VCCD MMI_MS_CD# 29
2 2 SD_CD# 10P_0402_50V8J~D
100mA MMI_SD_MMC_CD# 30
2
2 FOR DELL TEST
3.3VCCA MSCLK_XDCE#
40 3.3VCCA MS_CLK/XD_CE# 45
C 35 46 SD_CLK_R 1 2 SD_CLK C
3.3VCCA SD_MMC_CLK MMI_WPI# R1501 0_0402_5%
R1439 MMI_WPI# 61
1 2 +PE_3.3VCCA 3 63 MMI_XD_WPO
0_0603_5% C1799 4.7U_0805_10V4Z PE_3.3VCCA MMI_XD_WPO XD_RE#
MMI_XD_RE# 62
1@R1517 2 0_0402_5% MMI_XD_RB# 23 XD_RB#
C1800 0.1U_0402_10V6K 22 XD_CLE
MMI_XD_CLE
1 2 1R1518 2 11 PLL_REF_RETURN SD_MMC_CMD 48 SD_CMD
0_0402_5% 21 XD_WE#
1.2K_0402_1% 2 R1440 1 MMI_XD_WE# MSBS_XDALE SD_CLK XDCE_MSCLK
9 PE_RTERM2 MS_BS/XD_ALE 47
+3VS_CR
Add GND For O2 5.1K_0402_1% 2 R1441 1 10 49 MMC_XD_D7
PE_RTERM1 MMC_MS_XD_D7

2
50 MMC_XD_D6
MMC_MS_XD_D6 MMC_XD_D5 R1498 R1499
19 PCIE_TXP5 12 PE_RXP MMC_MS_XD_D5 51
13 52 MMC_XD_D4 1 1 1 0_0402_5% 0_0402_5%
19 PCIE_TXN5 PE_RXN MMC_MS_XD_D4
PCIe @ @
C1801 2 1 PCIE_C_RXP5 15 CardReader C1803 C1804 C1805
19 PCIE_RXP5

1
+3VS C1802 PE_TXP
19 PCIE_RXN5 2 0.1U_0402_10V6K
1 PCIE_C_RXN5 16
PE_TXN MS_XD_D3 53 MS_XD_D3 1U 10V Z Y5V 0603 1U 10V Z Y5V 0603 1U 10V Z Y5V 0603
0.1U_0402_10V6K MMC_SD_D3 2 2 2
SD_MMC_D3 54 1 1
1 R1442 2 5 55 MS_XD_D2
15 CLK_PCIE_MEDIA PE_REFCLKP MS_XD_D2
10K_0402_5% 6 56 MMC_SD_D2 C1813 @ C1814 @
15 CLK_PCIE_MEDIA# PE_REFCLKN SD_MMC_D2
57 MS_XD_D1 1U 10V Z Y5V 0603 1U 10V Z Y5V 0603
MS_XD_D1 MMC_SD_D1 2 2
15 MEDIA_REQ#32 32 PE_CLKREQ# SD_MMC_D1 58
59 MS_XD_D0
MS_XD_D0 MMC_SD_D0
7,17,26 PLT_RST# 31 PE_RST# SD_MMC_D0 60

65 DGND AGND 8 Layout Note: Place close to

GND J8IN1
OZ888GS0L1N_QFN64_8X8

B +3VS_CR +3VS_CR B

JSD1
3 XD-VCC SD-VCC 21
MS-VCC 28
MS_XD_D0 R1443 1 2 0_0402_5% XDD0_MSD0 32
MS_XD_D1 R1444 1 0_0402_5% XDD1_MSD1 XD-D0 SDCLK R1445 1 33_0402_5%~D SD_CLK
2 10 XD-D1 7 IN 1 CONN SD_CLK 20 2
IEEE1394_TPBIAS0 MS_XD_D2 R1446 1 2 0_0402_5% XDD2_MSD2 9 14 SDDAT0 R1447 1 2 0_0402_5% MMC_SD_D0
MS_XD_D3 R1448 1 0_0402_5% XDD3_MSD3 XD-D2 SD-DAT0 SDDAT1 R1449 1 0_0402_5% MMC_SD_D1
2 8 XD-D3 SD-DAT1 12 2
1U_0402_6.3V6K

MMC_XD_D4 R1450 1 2 0_0402_5% XDD4_MMCD4 7 30 SDDAT2 R1451 1 2 0_0402_5% MMC_SD_D2

XD-D4 SD-DAT2
1

1
56.2_0402_1%

56.2_0402_1%

1 MMC_XD_D5 R1452 1 2 0_0402_5% XDD5_MMCD5 6 29 SDDAT3 R1453 1 2 0_0402_5% MMC_SD_D3

MMC_XD_D6 R1456 1 0_0402_5% XDD6_MMCD6 XD-D5 SD-DAT3 XDD4_MMCD4
2 5 XD-D6 SD-DAT4 27
R1454 R1455 C1806 MMC_XD_D7 R1458 1 2 0_0402_5% XDD7_MMCD7 4 23 XDD5_MMCD5
XD-D7 SD-DAT5 XDD6_MMCD6
SD-DAT6 18
2 XD_WE# R1461 1 0_0402_5% XDWE XDD7_MMCD7
2 34 16
2

MMI_XD_WPO R1463 1 0_0402_5% XDWP XD-WE SD-DAT7

2 33 XD-WP
MSBS_XDALE R1464 1 2 0_0402_5% XDALE_MSBS 35 1 SDCD R1465 1 2 0_0402_5% SD_CD#
XD_CD# R1466 1 0_0402_5% XDCD XD-ALE SD-CD SDW P R1467 1
2 40 XD-CD SD-WP 2 2 0_0402_5% MMI_WPI#
IEEE1394_TPAP0 XD_RB# R1468 1 2 0_0402_5% XDRB 39 25 SDCMD R1469 1 2 0_0402_5% SD_CMD
IEEE1394_TPAP0 28 XD-R/B SD-CMD
XD_RE# R1470 1 2 0_0402_5% XDRE 38
IEEE1394_TPAN0 MSCLK_XDCE# R1471 1 33_0402_5%~D XDCE_MSCLK XD-RE XDCE_MSCLK
IEEE1394_TPAN0 28 2 37 XD-CE MS-SCLK 26
XD_CLE R1473 1 2 0_0402_5% XDCLE 36 13 XDALE_MSBS
IEEE1394_TPBP0 XD-CLE MS-BS MSINS R1475 1
IEEE1394_TPBP0 28 MS-INS 22 2 0_0402_5% MS_CD#

IEEE1394_TPBN0 11 17 XDD0_MSD0
IEEE1394_TPBN0 28 7in1-GND MS-DATA0
31 15 XDD1_MSD1
7in1-GND MS-DATA1 XDD2_MSD2
41 7in1-GND MS-DATA2 19
1

1
56.2_0402_1%

56.2_0402_1%

42 24 XDD3_MSD3
7in1-GND MS-DATA3
R1480 R1481

TAITW_R015-A10-LM
2

A A
All DATA spacing=8mil, CLK spacing=15mil
5.1K_0402_1%

270P_0402_50V7K
2

2
R1482

C1807

1 Security Classification Compal Secret Data

1

Issued Date 2008/1/3 Deciphered Date 2009/01/3 Title

OZ888 Card Reader /1394
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Layout Note: Place close to OZ888 Chipset. Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 29 of 43
5 4 3 2 1
 A B C D E

+3VALW to +3VS Transfer +5VALW to +5VS Transfer

+3VALW +3VS
+B+_BIAS +5VALW +5VS
U40
8 1 10U_0805_10V4Z~N U39
1 D S
7 D S 2 8 D S 1
R198 1 6 3 7 2
D S D S
5 D G 4 1 1 1 6 D S 3
330K_0402_5% C271 C465 C256 C278 5 4 1 1
SI4800DY_SO8 D G C284 C283
2

1 2 10U_0805_10V4Z~N SI4800DY_SO8 1
2 2 2 10U_0805_10V4Z~N 10U_0805_10V4Z~N
RUNON 3VS_GATE 2 2
1 2
R197 1 RUNON 1 2 1 5VS_GATE 0.1U_0402_16V4Z~N
100K_0402_5% 0.1U_0402_16V4Z~N R267 C279
C264 47K_0402_5%
1

D 0.01U_0402_25V7K~N 0.01U_0402_25V7K~N
SUSP 2 2
2
G Q18
S SSM3K7002FU_SC70-3
3

+CPU_CORE 1 2 +VCCP
C211 0.1U_0402_16V4Z~N

2 +3VALW 2
1

R409

100K_0402_5%
2

SYSON#
1

D
SYSON 2 Q42
25,26,36 SYSON
G SSM3K7002FU_SC70-3
S
3
2

R365
10K_0402_5%
1

+5VALW
1

R340
3 3
100K_0402_5%
2

SUSP
29,38 SUSP
VGA Discharge circuit
1

D
SUSP# 2 Q32
25,26,29,35,37 SUSP#
G SSM3K7002FU_SC70-3
2

S
3

R338
10K_0402_5%
1

Discharge circuit-1 +1.8V +0.9VS +5VS +3VS +1.5VS

+1.8VS_CB
2

2
2

R133 @ R351 @ R391 @ R383 R382 @

R536 @ 470_0603_5% 470_0603_5% 470_0603_5% 39_0603_5% 470_0603_5%
470_0603_5%
1

1
1

1
D D D D D
1

D SYSON# 2 SUSP SUSP SUSP SUSP

2 2 2 2
SUSP 2 Q50 @ G G G G G
4 G SSM3K7002FU_SC70-3 S Q12 @ S Q33 @ S Q39 @ S Q38 S Q37 @ 4
3

3
S SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 30 of 43
A B C E
 5 4 3 2 1

FD1 FD2 FD3 FD4 FD5 FD6

FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL
@ @ @ @ @ @

1
D D
H7 H8 H9 H10 H11 H12 H29 H15 H16 H20 H21 H23 H22
H_3P0 @ HOLEA
1 @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA

1
H17 H18 H25 H27
@ HOLEA @ HOLEA @ HOLEA @ HOLEA
H_3P2
1

1
H30
@ HOLEA
H_3P1
1

H26
@ HOLEA
H_3P7
C C
1

H3 H4 H5 H6
@ HOLEA @ HOLEA @ HOLEA @ HOLEA
H_4P2
1

H1 H2
@ HOLEA @ HOLEA
H_4P5
1

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Screws
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4592P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 31 of 43
5 4 3 2 1
 5 4 3 2 1

PL16
PJPDC1 FBM-L11-160808-601LMT 0603~D
TYCO_1566065-2~D 2 1 DOCK_PSID ADPIN VIN
Low_PWR 1
9 PL17
GND_4 SMB3025500YA_2P
DC+_1 2
8 GND_3
DC+_2 3 1 2

7 4 PR189
GND_2 DC-_1 @ 1M_0402_1%~D
D D
6 GND_1 DC-_2 5 1 2

0.1U_0603_25V7K~D
1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D
MH1 VIN
MH2 VS VIN

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D
0.01U_0402_25V7K~D
1

1
PC157

PC159

0.01U_0402_25V7K~D
PC313

PC311

PC312

PC314

PC158

PC160
@

1
PR191 @ PR192

1
PC161
@ PR190 @ 10K_0402_5%~D 1K_0402_5%~D
82.5K_0402_1%~D 1 2
@ ACIN 19,26,33

2
PR193 @

2
8
@ 22K_0402_1%~D
N41 1 2 N40 3 PU12A

P
+
O 1

.1U_0402_16V7K~D

19.6K_0402_1%~D
@ @ N35 2 -

1
@

1
PC162

PR194
@ LM393DR_SO8 @ PR195

4
PC163 PD1 10K_0402_5%~D
1000P_0402_50V7K~D RLZ4.3B_LL34

2
2

2
@ PR198
VIN 10K_0402_5%~D
2 1
RTCVREF

2
3.3V

8
PD3 @
5 PU12B

P
PJP1 +
PD4 @ JUMP_43X118 RLS4148_LL34-2 O 7
6

1 1
-

G
BATT+ 2 1 1 1 2 2 LM393DR_SO8
Vin Detector

4
1
C CH751H-40PT_SOD323-2 C
PR203 PR204
68_1206_5% 68_1206_5%
Max. typ. Min.
2

PQ50
L-->H 18.234 17.841 17.449
2
0.22U_1206_25V7K~D

CHGRTCP 3 TP0610K-T1-E3_SOT23-3
1 VS
H-->L 17.597 17.210 16.813
32.8
1

PR205
PC164

100K_0402_5%~D PC165
0.1U_0603_25V7K~D
2

PR206
2

22K_0402_1%~D
27 51ON# 1 2
1

RTCVREF PR207
200_0805_5%
3.3V APL5156-33DI-TRL_SOT89-3
PU14 +5VALWP +3VALWP
2

3 VOUT VIN 2
1
4.7U_0805_6.3V6K~D

DA204U_SOT323
B B
1

GND
PC166

PC167
1U_0805_25V4Z~D
2

2
1

PD5

2.2K_0402_5%~D
@ PR208
2

1 2

2
0_0402_5%~D

PR209
PR212

1
PQ53 33_0402_5%~D

1
DOCK_PSID

S
1 3 1 2 PS_ID 26
FDV301N_NL_SOT23-3~D

G
2
15K_0402_1%~D 100K_0402_1%~D
+5VALWP

2
+5VALWP

PR213

DA204U_SOT323
PJP4
@ JUMP_43X118

10K_0402_1%~D
1 1 2 2 +1.5VS

2
PD6
+1.5VSP

1
2

PR214
C
PJP3 PJP6 2 PQ54
@ JUMP_43X118 @ JUMP_43X118 B MMST3904-7-F_SOT323-3 @

2
1 1 E
+5VALWP 2 2 +0.9VSP 1 1 2 2 +0.9VS

2
+5VALW
PR215

1
@
1

PJP5 PJP8 PD7 PR216

@ JUMP_43X118 @ JUMP_43X118 SM24_SOT23 1 2 PSID_DISABLE# 26
1

1 1 2 2 +VCCPP 1 1 2 2 +VCCP @ 10K_0402_1%~D

PJP7 PJP10
A @ JUMP_43X118 @ JUMP_43X118 A

+3VALWP 1 1 2 2 +3VALW 1 1 2 2

PJP9
@ JUMP_43X118
+1.8VP 1 1 2 2 +1.8V
Security Classification Compal Secret Data
PJP11 2006/10/1 2007/5/01 Title
@ JUMP_43X118
Issued Date Deciphered Date
1 1
DCIN / Vin Detector
2 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4596P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 32 of 43
5 4 3 2 1
 A B C D E

PQ55 PQ56 +B+

VIN FDS4435BZ_SO8 FDS4435BZ_SO8
PR217
8 1 1 8 0.015_2512_1%
D S S D

0.01U_0402_25V7K~D
7 2 2 7 PJP15
D S S D CHG_B+
6 D S 3 3 S D 6 1 4 2 2 1 1

1
5 D G 4 4 G D 5

2
3.3_1210_5%~D 3.3_1210_5%~D

PC171

PC315

PC172

PC316

PC173
2 3 @ JUMP_43X118 PC168 PR218

1
100K_0402_1%~D

2
PR339

0.01U_0402_25V7K~D

1
2

CHGEN#
100K_0402_1%~D

2
1

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1000P_0402_50V7K~D

1000P_0402_50V7K~D
PC170 PC175 PC177

1
2

5
6
7
8

1
PC174

PR219
0.01U_0603_50V7K~D .1U_0402_16V7K~D PU15 0.1U_0805_25V7K

1 2

1
1
1 2 1 28 1 2 /BATDRV 1
CHGEN PVCC PQ57

2
1

4
3
2
1
PR272
PR220 FDS8884_SO8

2
PC178 PC176 2.2_0603_5%~D PQ58

S
S
S
G
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D 27 1 2 4 FDS4435BZ_SO8

2
BTST

2
2

PR221

D
D
D
D
340K_0402_1%~D 2 26 DH_CHG
ACN HIDRV
3

3
2
1

5
6
7
8
ACP PR222

1
2

4 25 LX_CHG PL18 0.02_2512_1%

PC169 ACDET ACDRV PH PD8 10UH_SIL1045RA-100PF_4.5A_30% BATT+
5 ACDET
2.2U_0805_25V6K 2 1 1 2 1 2 1 4
1

4.7_1206_5%~D

10U_1206_25V6M~D

10U_1206_25V6M~D
REGN
RLS4148_LL34-2 PC179 2 3

2
PR224 0.1U_0603_25V7K~D

10U_1206_25V6M~D
5
6
7
8

1
PR394

PC181

PC223
PR223 115K_0402_1%~D ACSET @

PC180
1

2
54.9K_0402_1% 1 2 6
+3VALW ACSET
24 PQ59

2
REGN

1
FDS6690AS_NL_SO8
1

1
1

1
PR225 PC183
PC182 100K_0402_1%~D 4

1 2

680P_0603_50V7K~D
0.01U_0402_25V7K~D 1U_0603_10V6K~D

2
2

@ @

PC361
90W adapter 1 2 7 ACOP
PR226 PC184 23 DL_CHG @

3
2
1

2
340K_0402_1%~D 0.47U_0603_16V7K~N LODRV
Icharge=(Vsrset/Vvdac)*(0.1/PR34)=3.34A CP setting
1

Iadapter=(Vacset/Vvdac)*(0.1/PR217)=3.1A PGND 22
OVPSET 8 PC185
OVPSET .1U_0402_16V7K~D
Input OVP : 22.3V
1 2
2 2
Input UVP : 16.98V 9 AGND LEARN 21 ACOFF 26
2

1
Fsw : 300KHz PR227
54.9K_0402_1% VREF PC186 PC187
20 CELLS 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D

2
CELLS
1

10 VREF

1
PQ60 3

1
SI2301BDS-T1-E3_SOT23-3 PC188
1U_0603_10V6K~D PR370
VREF PR228 @ 0_0402_5%~D 19

2
100K_0402_1%~D SRP
CELLS GND 3 Cell

2
1 2GATE 2 11 VDAC SRN 18
2

VREF 4 Cell
PR229 1 2 17
+3VALW BAT
1

47K_0402_1%~D PR371

1
PC189 0_0402_5%~D VADJ 12
0.1U_0603_25V7K~D VADJ PC190
1

ACSET 0.1U_0603_25V7K~D

2
CELLS 29
ACGOOD# TP RTCVREF
13 ACGOOD ICHG setting
1

D VREF
2 3cell/4cell# 40 PR231
G REGN 16 2 1 IREF 26
SRSET

2
S PQ61 /BATDRV 14 49.9K_0402_1%~D
3

BATDRV

1
SSM3K7002F_SC59-3 PR232

1
PR234 PR230 100K_0402_1%~D
1

PC191
Cells selector PR51 IADAPT 15 1 2 100K_0402_1%~D
@0.01U_0402_25V7K~D 100K_0402_1%~D

1
@ 0_0402_5%~D BQ24751ARHDR_QFN28_5X5 PR233

2
PR53 10_0603_5%~D ACIN 19,26,32
210K_0402_1%~D
2

1
3 VADJ D 3
26 CHGVADJ 1 2
26 ADP_I ACGOOD# 2 PQ62
1

G SSM3K7002F_SC59-3

1
PR54 S

3
499K_0402_1%~D PC192 IREF Current
100P_0402_50V8J~D

2
2

2.968V 3A
+COINCELL
PR235
PQ63
+B+ 1 2 3 TP0610K-T1-E3_SOT23-3
1 +B+_BIAS
1
470K_0402_5%~D

100_0805_5%~D 32.8 VREF

0.1U_0805_25V7M~D

VREF PR1
2

+5VALW 1K_0402_5%~D
COIN RTC Battery
PR236

PC193 VREF
1

2
GATE RTCVREF
1

PR395 PJP24 PR237

2

200K_0402_1%~D
Z4012

100K_0402_1%~D
1
1

1
220K_0402_5%

1SS355_SOD323-2

PD9
2

D
2

1
PR238

PR396 2 PQ89
2

100K_0402_1%~D G SSM3K7002F_SC59-3 CHGEN#

S +COINCELL 1 2
2

+ -
1

1
D +RTCVCC D
32.8
1

PQ64 D ACOFF 1 PQ90 PQ65

2 2 26 FSTCHG 2
2 G SSM3K7002F_SC59-3 G SSM3K7002F_SC59-3
1
0.1U_0603_25V7K~D

G RHU002N06_SOT323 PC362 S PD2 S

3

3
220K_0402_5%

S .1U_0402_16V7K~D BAT54CW_SOT323~D
3
2

PR397
SUYIN_060003FA002G201NL~D
1
PC194

PR239

340K_0402_1%~D 1
4 PC1 @ 4
27.4
2

1U_0603_10V4Z~D
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title
Charger/RTC BATTERY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KML50 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 33 of 43
A B C D E
 5 4 3 2 1

TPS51427_B+
TPS51427_B+
+B+
PJP20 PR240
@ JUMP_43X118 0_0805_5%~D
1 1 2 2 1 2

0.1U_0603_25V7K~D

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

2200P_0402_50V7K~D

2200P_0402_50V7K~D

0.1U_0603_25V7K~D
4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
VL

5
6
7
8
PC215

PC195

PC196

PC197

8
7
6
5

1
PC200

PC216
D D

PC198

PC199
PQ67

1U_0603_10V6K~D
PQ66 AO4466_SO8

2
2

4.7U_0805_6.3V6K~D
AO4466_SO8 PC201

2
0.1U_0603_25V7K~D 4

1
PC202
4

PC203
1
+5VALWP

3
2
1
1
2
3
PL21

7
PL20 PU16 PC207 2 1
1 2 1U_0603_10V6K~D 3.3UH_1164AY-3R3N-P3_7.5A_30%

V5FILT

LDO
VIN
+3VALWP 3.3UH_1164AY-3R3N-P3_7.5A_30% 33 19 1 2
TP V5DRV

8
7
6
5

5
6
7
8

1
680P_0603_50V8J~D 4.7_1206_5%~D
1
680P_0603_50V8J~D 4.7_1206_5%~D

PR242
DH3 26 15 DH5
DRVH2 DRVH1

PR241
PQ68 PR243 PR245 PQ69
0_0402_5%~D

AO4712_SO8 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8

VBST2 VBST1
2

1 2.2_0603_5%~D

2
2

2
PR244

61.9K_0402_1%~D
4 2.2_0603_5%~D PC208 4

2
PC204 + PC205

2
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D

1
1

PC209

PR246
330U_D3L_6.3VM_R25M LX3 25 16 LX5 1
1

2 LL2 LL1

PC206

1
2
3

3
2
1

2
+ PC210

2
DL3 23 18 DL5 330U_D3L_6.3VM_R25M

1
DRVL2 DRVL1
10K_0402_1%~D

2
2

PGND 22

2
PR247

C FB3 30 C
VOUT2

PR248
10K_0402_1%~D
VOUT1 10
VL 32
1

REFIN2

1
@ 11 FB5
2VREF_TPS51427 FB1

1 2 1 VREF2
PC211 0.22U_0603_10V7K~D
VSW 9
8 LDOREFIN @ PR249 0_0402_5%~D
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical) SKIPSEL 29 2 1 VL
PR250 0_0402_5%~D
1 2
3.3VALWP PD10 PR251
20 NC PGOOD2 28

Imax=6A VS RLZ5.1B_LL34 100K_0402_1%~D

POK 19
1 2 1 2 4 EN_LDO PGOOD1 13 PR253
2
200K_0402_5%~D

309K_0402_1%
Iocp=8.94A
2
PR252

PC212 14 12 TRIP1 2 1
0.22U_0603_25V7K~D EN1 TRIP1
PR255

TONSE
VREF3
1

27 31 TRIP2 2 1

GND
1

EN2 TRIP2

2
B 309K_0402_1% B

0_0402_5%~D
@ PR254 SN0806081RHBR_QFN32_5X5

21
VL
806K_0603_1%~D

0_0402_5%~D

PR256
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)
2

1
PR257

2VREF_TPS514271

PR260

1
@ 47K_0402_5%~D PR258
PR259 PC308 @
5VALWP
1

2 1 1 2 1U_0603_10V6K~D Imax=6A
2

2VREF_TPS514272
40 MAINPWON 0_0402_5%~D
0.047U_0402_16V7K~D

0_0402_5%~D

Iocp=8.81A
1

PC213
2

0.047U_0603_16V7K~D

PC214
2

PQ74
TP0610K-T1-E3_SOT23-3
@
1 3

PD16
1 2

1SS355TE-17_SOD323-2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/1 Deciphered Date 2007/05/30 Title
+3VALWP, + 5VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4596P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 34 of 43
5 4 3 2 1
 5 4 3 2 1

D D

PJP25
VCCPP_B++ 2 1 +B+

JUMP_43X118
@

2200P_0402_50V7K~D

10U_1206_25V6M~D

10U_1206_25V6M~D

0.1U_0603_25V7K~D
1

PC218
PC217

PC317

PC318
2

2
C C

PR340
FDS6676AS
267K_0402_1%~D Rds(on)=5.9mohm~7.25mohm
1 2
VCCPP

5
6
7
8
PR341
0_0402_5%~D PR342 PC319 Imax=9A
2 1 EN_VCCP BST_VCCP1 2 1 2
25,26,29,30,37 SUSP#
1

PC320 2.2_0603_5%~D 0.1U_0603_25V7K~D PQ79

PR343 .1U_0402_16V7K~D 4 FDS8884_SO8 Iocp=14.04A
30.1K_0402_1%~D @
Fsw=298KHz
2

15 +5VALW

14
2

PU23

3
2
1
PL29
EN_PSV

TP

VBST
1UH_FDUE1040D-1R0M-P3_21.3A_20%
TON_VCCP 2 13 UG_VCCP 1 2
TON DRVH +VCCPP

2
PR344 3 12 LX_VCCP 1
VOUT LL

4.7U_0805_6.3V6K~D
300_0603_5%~D PR347 PR345 PR346 PC321 PC322

5
6
7
8

1
1 2 V5FILT_VCCP 4 11 TRIP_VCCP
1 2 0_0603_5%~D 4.7_1206_5%~D +
+5VALW V5FILT TRIP

220U_D2_4VM
10.2K_0402_1%~D

D
D
D
D
FB_VCCP 5 10 V5DRV_VCCP PQ80

2 1

2
VFB V5DRV
1

B FDS6676AS_SO8 2 B
PC324 6 9 LG_VCCP PC323
PGOOD DRVL

G
PGND

S
S
S
1U_0603_10V6K~D 680P_0603_50V8J~D
GND
2

4
3
2
1

1
1
TPS51117RGYR_QFN14_3.5x3.5 PC325
7

PC326 4.7U_0805_10V6K~D

2
47P_0402_50V8J~D
2 1

2 1

PR348
8.66K_0402_1%~D
1

PR349
21.5K_0402_1%~D
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/2/5 Deciphered Date 2009/2/5 Title
+VCCPP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4596P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 35 of 43
5 4 3 2 1
 5 4 3 2 1

D D

PJP26
+1.8VP_B++ 2 1 +B+

JUMP_43X118
@

2200P_0402_50V7K~D

10U_1206_25V6M~D

10U_1206_25V6M~D

0.1U_0603_25V7K~D
1

PC220
PC219

PC327

PC328
2

2
C C

PR350
FDS6670AS
267K_0402_1%~D Rds(on)=9mohm~11.5mohm
1 2
1.8VP

5
6
7
8
PR351

25,26,30 SYSON
0_0402_5%~D PR352 PC329 Imax=9A
2 1 EN_1.8 BST_1.8 1 2 1 2
<BOM Structure>
1

PC330 2.2_0603_5%~D 0.1U_0603_25V7K~D PQ81

PR353 .1U_0402_16V7K~D 4 FDS8884_SO8 Iocp=10.95A
30.1K_0402_1%~D @
Fsw=297KHz
2

+5VALW
15

14
2

PU24

3
2
1
PL30
EN_PSV

TP

VBST
1.8UH_SIL104R-1R8PF_9.5A_30%
TON_1.8 2 13 UG_1.8 1 2
TON DRVH +1.8VP

2
PR354 3 12 LX_1.8 1
VOUT LL

5
6
7
8

4.7U_0805_6.3V6K~D
300_0603_5%~D PR357 PR355 PR356 PC331 PC332

1
1 2 V5FILT_1.8 4 11 TRIP_1.81 2 0_0603_5%~D 4.7_1206_5%~D +

D
D
D
D
+5VALW V5FILT TRIP

220U_D2_4VM
12.1K_0402_1%~D PQ82
B FB_1.8 V5DRV_1.8 FDS6670AS_NL_SO8 B
5 10

2 1

2
VFB V5DRV
1

2
PC333 6 9 LG_1.8 4 PC334
PGOOD DRVL G
PGND

1U_0603_10V6K~D 680P_0603_50V8J~D
GND
2

1
1

S
S
S
TPS51117RGYR_QFN14_3.5x3.5 PC335
7

3
2
1
PC336 4.7U_0805_10V6K~D

2
47P_0402_50V8J~D
2 1

2 1
PR358
30.1K_0402_1%~D
1

PR359
21.5K_0402_1%~D
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/1 Deciphered Date 2007/05/30 Title
+1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4596P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 36 of 43
5 4 3 2 1
 5 4 3 2 1

D D

PJP27
+1.5VSP_B++ 2 1 +B+

JUMP_43X118
@

2200P_0402_50V7K~D

10U_1206_25V6M~D

10U_1206_25V6M~D

0.1U_0603_25V7K~D
1

PC222
PC221

PC337

PC338
2

2
C C

PR360
AO4712
267K_0402_1%~D Rds(on)=15mohm~18mohm
1 2
1.5VSP

5
6
7
8
PR361
0_0402_5%~D PR362 PC339 Imax=3.5A
2 1 EN_1.5 BST_1.5 1 2 1 2
25,26,29,30,35 SUSP#
1

PC340 2.2_0603_5%~D 0.1U_0603_25V7K~D PQ83

PR363 .1U_0402_16V7K~D 4 AO4466_SO8 Iocp=6.87A
30.1K_0402_1%~D @
Fsw=298KHz
2

+5VALW

15

14
2

1
PU25

3
2
1
PL31
EN_PSV

TP

VBST
2.2UH_PCMC063T-2R2MN_8A_20%
TON_1.5 2 13 UG_1.5 1 2
TON DRVH +1.5VSP

2
PR364 3 12 LX_1.5 1
VOUT LL

5
6
7
8

4.7U_0805_6.3V6K~D
300_0603_5%~D PR365 PR366 PR367 PC341 PC342

1
1 2 V5FILT_1.5 4 11 TRIP_1.51 2 0_0603_5%~D 4.7_1206_5%~D +
+5VALW V5FILT TRIP

220U_D2_4VM
12K_0402_1%~D
FB_1.5 5 10 V5DRV_1.5 PQ84

2 1

2
VFB V5DRV
1

AO4712_SO8 2
PC343 6 9 LG_1.5 4 PC344
PGOOD DRVL
PGND

B 1U_0603_10V6K~D 680P_0603_50V8J~D B
GND
2

1
1
TPS51117RGYR_QFN14_3.5x3.5 PC345
7

3
2
1
PC346 4.7U_0805_10V6K~D

2
47P_0402_50V8J~D
2 1

2 1
PR368
22.1K_0402_1%~D
1

PR369
22.1K_0402_1%~D
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/2/5 Deciphered Date 2009/2/5 Title
+1.5VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4596P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 37 of 43
5 4 3 2 1
 5 4 3 2 1

D +1.8V D

1
PJP17

1
@ JUMP_43X118

2 2
PU20

4.7U_0805_6.3V6K~D
1 VIN VCNTL 6 +3VALW

1
PC267

4.7U_0805_6.3V6K~D
2 GND NC 5

1
PC268
1
3 7

2
VREF NC

2
PR317 4 8
1K_0402_1%~D VOUT NC
9

2
TP
APL5331KAC-TRL_SO8~N
PR318
+0.9VSP

1
0_0402_5%~D D

1U_0603_10V6K~D
1 2 2

1
29,30 SUSP

PC271
G PR320 PC270
S

2
1
PQ78

2
PC272
@

2
C .1U_0402_16V7K~D C
RHU002N06_SOT323 .1U_0402_16V7K~D
1K_0402_1%~D

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/1 Deciphered Date 2007/05/30 Title
+0.9VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4596P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 38 of 43
5 4 3 2 1
 5 4 3 2 1

+5VS

2
CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
5

5
PC112 +CPU_B+
PR142
PL13

VR_ON

26
2 1 1_0603_5%~D
FBMA-L18-453215-900LMA90T_1812
@ 1 2 +B+

1
5600P_0402_25V7K
1 1

1U_0603_10V6K~D

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

2200P_0402_50V7K~D

0.1U_0603_25V7K~D
100U_25V_M

100U_25V_M
D D

1
0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

PC114

PC115

PC116

PC113

PC155

PC225

PC226
PR143 499_0402_1%~D + +

1
PC118
1U_0603_10V6K~D

PC119
7,19 DPRSLPVR 1 2

1
PC117

PC120

2
PR144 0_0402_5%~D @ 2 2

2
5,7,18 H_DPRSTP# 1 2

5
PR1460_0402_5%~D

PR1470_0402_5%~D

PR1480_0402_5%~D

PR1490_0402_5%~D

PR1500_0402_5%~D

PR1510_0402_5%~D

PR1520_0402_5%~D
PR145 0_0402_5%~D

1
CLK_EN# 1 2

1
0_0402_5%~D
+3VS PR154 0_0402_5%~D PQ43

PR153
1 2 4 SI7686DP-T1-E3_SO8

2
+3VS

1U_0603_10V6K~D
PC122

2
1.91K_0402_1%~D

1
PC121
PR155 0.22U_0603_10V7K~D P_0.36H_ETQP4LR36WFC_24A_20%

3
2
1
1 BOOT_CPU1 1 2 1 2 2 1 +CPU_CORE
2

4.7_1206_5%~D
PR156

PR157

1
10K_0402_1%~D
3.65K_1206_1%
2.2_0603_5%~D PQ44 @ PQ45 PL14

1
PR158

PR160
499_0402_1%~D

SI7636DP-T1-E3_SO8
49

48

47

46

45

44

43

42

41

40

39

38

37

PR159
PR161

SI7636DP-T1-E3_SO8
2

1_0402_5%~D

GND

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
DPRSLPVR

VR_ON
1

680P_0603_50V8J~D
1 2

2
7,19,26 VGATE 1 36 4 4 PR162 @ 0_0402_5%~D

2
PGOOD BOOT1 G G

PC123
5 H_PSI# 1 2
2 35 UGATE_CPU1 VSUM PC124
PSI# UGATE1

S
S
S

S
S
S
POW_MON 26 PC147 PR181 10K_0402_1%~D 1 2

2
1U_0603_10V6K~D
1 2 1 2 3 34 PHASE_CPU1 VCC_PRM

3
2
1

3
2
1
PMON PHASE1 ISEN1
C PR164 147K_0402_1%~D 4 33 0.22U_0603_16V7K~D C
RBIAS PGND1
1 2

2200P_0402_50V7K~D

0.1U_0603_25V7K~D
VR_TT# 5 32 LGATE_CPU1 +CPU_B+
VR_TT# LGATE1

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
PR165 @ 4.22K_0402_1% PH2

1
1 2 1 2 6 NTC PVCC 31

PC125

PC126

PC127

PC227

PC228
@ 100K_0603_1%_TH11-4H104FT 7 30 LGATE_CPU2 PQ46

2
SOFT LGATE2 SI7686DP-T1-E3_SO8
1 2
@ 0.015U_0402_16V7K PC128 8 29 @
0.068U_0603_50V7K~N PC129 OCSET ISL6266ACRZ-T_QFN48_7X7 PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2
PR166 11.5K_0402_1%~D 10 27 UGATE_CPU2 P_0.36H_ETQP4LR36WFC_24A_20%
COMP UGATE2 PR167 PC130
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 2 1
PC131 FB BOOT2 PL15
1 2

1
DROOP

1000P_0402_50V7K~D 12 25 2.2_0603_5%~D
0.22U_0603_10V7K~D PQ48
FB2 NC

1
VSUM
VDIFF

ISEN2

ISEN1

10K_0402_1%~D
VSEN

PR169 8.25K_0402_1%~D PQ47 PR168

GND

D
VDD
RTN

DFB

1
VIN

SI7636DP-T1-E3_SO8

PR170
3.65K_1206_1%
4.7_1206_5%~D PR172
VO

1 2

SI7636DP-T1-E3_SO8

PR171
1 2 PU11 1_0402_5%~D
13

14

15

16

17

18

19

20

21

22

23

24

1 2
4

2
PC132 1000P_0402_50V7K~D G
4

2
29.1
ISEN1 G PC133 PR173 @ 0_0402_5%~D

S
S
S
ISEN2 680P_0603_50V8J~D 1 2

2
S
S
S
PR175 97.6K_0402_1%~D PC134 270P_0402_50V7K~D 1 2 +5VS

3
2
1
1

1 2 2 1 VSUM PC135

3
2
1
1

PR174 1_0603_5%~D 1 2
PR176 PC136 @
B 1K_0402_1%~D 1U_0603_10V6K~D 0.22U_0603_16V7K~D B
1 2
2
2

PC137 100P_0402_50V8J~D VCC_PRM

1

ISEN2
PR178
PR184 PR177 PC138 2200P_0402_50V7K~D
100K_0402_1%~D 1 2 1 2 1 2 +CPU_B+
1

@ 100_0402_1%~D
1 2 PC139 10_0603_5%~D
2

0.1U_0603_25V7K~D
2

PR179 1K_0402_1%~D
PC140 330P_0402_50V7K~D
5 VCCSENSE 1 2 1 2
VSUM
1

PR180 0_0402_5%~D
1

2.61K_0402_1%~D

PC141 PC142
PR182

@330P_0402_50V7K~D 0.01U_0603_25V7K~D
2

1 2
5 VSSSENSE PR183 0_0402_5%~D
2
1

11K_0402_1%~D

PC143 180P_0402_50V8J~D
PR185

1 2
2

1 2 1 2 PH3
2

PR186 1K_0402_1%~D PR187 3.57K_0402_1%~D 10KB_0603_ERTJ1VR103J

PC144 0.068U_0603_50V7K~N
1

VCC_PRM 1 2

PC146 0.22U_0603_10V7K~D
A A
PC145 2 1 2 1
0.22U_0603_16V7K~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4596P
Date: Thursday, February 19, 2009 Sheet 39 of 43
5 4 3 2 1
 5 4 3 2 1

1
PD12 PD13
BATT+ PJSOT24C_SOT23-3 PJSOT24C_SOT23-3
D BATT++ D

3
PL28
Battery Connect/OTP
BATT+

SMB3025500YA_2P

1 2 BATT++
+3VALWP

1
100P_0402_50V8J~D

100P_0402_50V8J~D
1000P_0402_50V7K~D
1

1
PC279
PC309

PC310
PC278 2

2
0.01U_0402_25V7K~D
2

2
PR324 Place clsoe to EC pin
47K_0402_5%~D
1 2 BATT_TEMP
BATT_TEMP 26

1
PR325

2
1K_0402_5%~D
PC280
PJPB1 battery connector .1U_0402_16V7K~D

1
SMART PJP19

@
1 PR326
Batte ry: 1
2 2
3 3cell/4cell# 1K_0402_5%~D
3 3cell/4cell# 33
4 2 1
1 . B AT +
4
5 5 1 2 +3VALWP
2 . B AT + 6 6
7 PR327
7
3.ID 10 GND 8 8 6.49K_0402_1%~D
11 9
4 .B/I GND 9

5. TS SUYIN_200275MR009G186ZL 1 2 EC_SMB_DA1 26
C
6.SMD @ PR328 C
100_0402_5%~D
7.S MC
8.GND CPU
9.GND 1 2 EC_SMB_CK1 26
PR329
PH1 under CPU botten side :
100_0402_5%~D
CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

VL VS
BATT+
1

2
PR330

1
453K_0402_1%~D PC281
0.1U_0603_25V7K~D
CPU

1
VS
2

PR331
0.01U_0402_25V7K~D

10.7K_0402_1%~D VL

2
1

PR333
PR332 147K_0402_1%~D

2
499K_0402_1%~D 1 2
1

PC282

PR334
B 205K_0402_1%~D B
2
2

PR335

1
8
61.9K_0402_1%~D
PR398 1 2 3 PD11

P
+
8

PU22B LM358ADR_SO8 1 1 2
10K_0402_1%~D 5 1 2 2
0 MAINPWON 34
P

+ VL -

G
2 1 7 1SS355_SOD323-2
0 PR336 PU22A
6

4
-
G

1
26 BATT_OVP 150K_0402_1%~D LM358ADR_SO8
1

PH4
4

1
100K_0603_1%_TH11-4H104FT

1
PR337
86.6K_0402_1% PC283 PR338

2
1000P_0402_50V7K~D 150K_0402_1%~D
2

2
2
PC284
1U_0603_10V6K~D

LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/1 Deciphered Date 2007/05/30 Title
BATTERY CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4596P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 40 of 43
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1/1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 32 DCIN /Vin Detector 08/12/08 COMPAL common circuit design modify change PR203 from 33 to 68 and add PR204 to 68 0.3

D 2 08/12/08 COMPAL design modify change PL17 from SM010018880 to SM010008E10 0.3 D

3 33 Charger 08/12/08 COMPAL vendor FAE suggest change PR272 PR339 from 1 to 3.3 0.3

4 40 BATTERY CONN 08/12/08 COMPAL design modify change PL28 from SM010018210 to SM010008E10 0.3

5 32 DCIN /Vin Detector 08/12/12 COMPAL increase capacitor for EMI request add PC313 at 0.01uf and PC314 at 0.1uf 0.3

6 35 VCCPP 08/12/12 COMPAL change resister for EMI request change PR342 from 0 to 2.2 0.3

7 36 1.8VP 08/12/12 COMPAL change resister for EMI request change PR352 from 0 to 2.2 0.3

8 37 1.5VSP 08/12/12 COMPAL change resister for EMI request change PR362 from 0 to 2.2 0.3

9 35 VCCPP 08/12/18 COMPAL add resister and capacitor for EMI request add PR346 at 4.7and pc323 at 680p 0.3

10 36 1.8VP 08/12/18 COMPAL add resister and capacitor for EMI request add PR356 at 4.7and pc334 at 680p 0.3

11 37 1.5VSP 08/12/18 COMPAL add resister and capacitor for EMI request add PR367 at 4.7and pc344 at 680p 0.3

12
C C
13

14

15

16

17

18

19

20

21

22

23
B B

24

25

26

27

28

29

30

31

32

33

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PW PIR-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4596P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 41 of 43
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1/1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 28 USB/BT/ FP/ Felica/Camera 2008/12/02 Compal_HW Small USB board no function Modify Pin definition of JUSBP3 0.2

D 2 24 HDA-IDT_92HD81 2008/12/02 Compal_HW R voice and L voice fail Modify Pin definition of JSPK1 0.2 D

3 27 PWR_OK/ BTN/ KB / TP/TPM1.2 2008/12/02 Compal_HW Switch function fail Modify Pin definition of SW1 0.2

4 21 LAN-8111D 2008/12/16 Compal_HW EMI LAN test fail Add C1817-C1820 for LAN connector 0.2

5 23 Mini-Card/WWAN/Roboson 2008/12/16 Compal_HW S5 wake on Wirlesslan fail Add U89 to control wirless lan voltage 0.2

10

11

12
C C
13

14

15

16

17

18

19

20

21

22

B 23 B

24

25

26

27

28

29

30

31

32

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/03/21 Deciphered Date 2009/03/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EE_PIR-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4592P
Date: Thursday, February 19, 2009 Sheet 42 of 43
5 4 3 2 1
 5 4 3 2 1

ACIN/BATT-IN

+5VALW/+3VALW

EC_ON

D D

ON/OFF

STB_SB (Control +3V_SB)

+3V_SB

RSMRST# T1>20ms

WOL_EN(Control +3VLAN)

+3VLAN

SYSON(Control +3V/+1.8V)

+3V/1.8V
C C

T2=40ms

PWRBTN_OUT#

T3<110ms
SLP_S5#

SLP_S4#

SLP_S3#

SUSP# T4=20ms

+5VS>3VS>1.5VS>1.25VS>+1.2VS>VCCP>0.9VS

VR_ON#/VGA_ON T5>30ms

B
+CPU_CORE B

T6= ~7ms
VGATE(IMVP to SB for VRMPWRGD/to EC for CPUCORE PWRGD)

CK_PWRGD(SB to CLK-GEN; Local AND of VRMPWRGD and S3 ) 100ns>T7>0ns

T8>99ms
T9>3ms
PM_PWROK(EC to SB/NB) T10>70ms

H_PWRGOOD(SB to CPU; Local AND of VRMPWRGD and PWROK)

PLTRST#(SB to NB/Device) 41RTCCLK>T11>34RTCCLK

H_RESET#(NB to CPU) T12>1ms

VGA_ON T13>30ms
A A

+VGA_CORE

VGA_PWGOD(Turn on 1.8VS for VRAM/VGA) T14= ~7ms

+1.8VS

Security Classification Compal Electronics, Inc.

Issued Date 2008/03/21 2009/03/21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power On Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4592P
Date: Thursday, February 19, 2009 Sheet 43 of 43
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