Layout Interview: (Analog Layout) Mode of Interview: F2F

Company: Invecas Contact Person: Anil

Person no 1

1. Tell me about yourself?

2. What all projects you have worked on?
3. What all blocks are there in LDO, explain with input and output voltage? How much is the
dropout voltage? How much is the reference voltage(from where it is coming)? Where output
is connected? How much is the output voltage? What is the voltage value for vdd1p8 and vdd
What is the voltage value for vdd1p8 and vdd_int
4. What is the spacing rule for different Nwell? If i place the two Nwell with different potential
side by side what will happen?? (hint related to reliability) it will form the npn BJT
5. What is the W/L for the input pairs?
6. Why we go for matching? If a=6, n=3 and b=6,n=3 how will you do the matching?
7. What kind of VCO you have worked on? What is the current of that VCO? How many stages
were there? How you placed and how you did the routing? how did you taken care of
parasitic?
8. How did you solve max density in your layout? How did you solve PC max density in your
layout?
9. What other antenna error will come other that gate related antenna? How did you solve that?
how you place diode? He asked in depth.
10. What are HVT,LVT,RVT and SVT devices, what are thick and thin oxide devices? What
about egnfet and egpfet?
11. List out the different layers in Samsung 10lpe and TSMC28

Person no 2

1. Tell me about yourself?

2. What is latch up? How you will prevent latch up? How exactly taps reduces the resistances?
Can you please write what all layers will be there in ntap?
3. What verification checks you have done? Suppose I am getting short between two nets how
you will you track in lvs caliber?
4. Did you work on Min and max density? how did you solve min density, suppose in 50*50
window the min metal density is 40% but I am getting 38% how do you solve this? I want
you to calculate and clear this error in single attempt no trial and error method.
5. What kind of VCO you have worked on? How many stages? How you placed the each stage?
How you reduced the parasitic? Can you please write draw the floorplan of VCO?
6. What is Sa and Sb? Match the device A=4 and B=4 w.r.t LOD? I matched the device in two
axes he told to match in single axes?
7. How you will reduce the resistance of the particular wire?(decrease the length of the wire if
possible, add more contacts, metal stacking, parallel connection, if it is critical net then route
with higher metal so thickness of the metal increases)
8. How you will reduce the capacitance of the metal?(increase the width of the net, and try to
avoid routing near to critical net, try to route with higher metal)
Person : Anil

1. What all blocks you have worked on?

2. What kind of PFD you have worked on? What kind of charge pump you have worked on?
3. For how many months you worked on the digital blocks, ESD, analog blocks and currently
what project you are working?